A solar cell and its preparation method and application

Abstract

The present invention provides a solar cell, a preparation method thereof, and an application thereof. The solar cell includes an N-type silicon wafer layer, wherein a boron junction layer, an aluminum oxide layer, and a first silicon nitride layer are sequentially stacked on the front side of the N-type silicon wafer layer, and a silicon oxide layer, a Poly-Si layer, and a second silicon nitride layer are sequentially stacked on the back side of the N-type silicon wafer layer; a first gate line passes through the first silicon nitride layer, the aluminum oxide layer, and the boron junction layer and contacts the front surface of the N-type silicon wafer layer, and the first gate line includes a first seed layer and a first metal layer stacked in sequence; a second gate line passes through the silicon oxide layer, the Poly-Si layer, and the second silicon nitride layer and contacts the negative surface of the N-type silicon wafer layer, and the second gate line includes a second seed layer and a second metal layer stacked in sequence. The preparation method of the present invention can effectively improve the bonding strength between the gate line and the silicon wafer, and meet the pull-off force and reliability requirements of the component.

Description

Technical Field

[0001] The present invention relates to the photovoltaic field, and in particular to a solar cell and a preparation method and application thereof. Background Art

[0002] Silver paste costs are the largest component of the non-silicon costs of photovoltaic cells. For example, in PERC cells, paste accounts for over 40%. With the recent gradual rise in international silver prices, with the silver point rising from 17.15 in May 2020 to 25.37, silver paste costs have also increased accordingly. The photovoltaic market has entered the high-power era, increasing demand for next-generation, high-efficiency solar cells. High-efficiency cell technologies, such as TOPCon and HJT, require double-sided silver paste printing, increasing silver paste usage by over 60% compared to PERC cells. Coupled with the rapid expansion of photovoltaic installations, the proportion of silver paste in the total silver supply is expected to rise rapidly, driving up silver prices and costs. Electroplating technology allows the use of base metals such as nickel, copper, and tin instead of silver, effectively reducing cell metallization costs. This reduces the cost difference between TOPCon and HJT cells and PERC cells, accelerating the adoption of new high-efficiency cells.

[0003] CN111826692A discloses a method for light-induced or light-assisted electroplating of photovoltaic cells, in which the negative electrode of the photovoltaic cell is contacted with the electroplating solution, the positive electrode or the negative electrode is connected to the anode placed in the electroplating solution, and the light source passes through the electroplating solution of a certain depth to reach the electroplating cathode to achieve light-induced electroplating. The electroplating solution includes one or more of nickel, copper, tin, silver, steel, and bismuth, but there is no description of the need to prepare a seed layer to increase the pull-off force, so the electroplating effect is not good.

[0004] CN112701192A discloses a method for preparing a selectively doped structure for a solar cell. The method involves pre-treating a silicon wafer and then depositing a poly layer containing a doping layer. Laser treatment is then performed on the poly layer to produce a heavily doped region. The poly layer is then oxidized to a BSG / PSG layer after de-doping. Finally, the BSG and PSG layers are cleaned to produce the selectively doped structure for the solar cell. This method is primarily intended to precisely control the doping levels in the lightly and heavily doped regions of the selectively doped structure. However, the gate line preparation process is not disclosed, and the beneficial effect of preparing the gate lines on the solar cell of the invention in improving the bonding strength between the gate lines and the silicon wafer is not demonstrated.

[0005] Therefore, how to prepare a solar cell with strong bonding between the gate line and the silicon wafer is an important research direction in this field. Summary of the Invention

[0006] The purpose of the present invention is to provide a solar cell and a preparation method and application thereof.

[0007] In order to achieve the purpose of the invention, the present invention adopts the following technical solutions:

[0008] One of the objects of the present invention is to provide a solar cell, which includes an N-type silicon wafer layer, wherein a boron junction layer, an aluminum oxide layer, and a first silicon nitride layer are stacked in sequence on the front side of the N-type silicon wafer layer, and a silicon oxide layer, a Poly-Si layer, and a second silicon nitride layer are stacked in sequence on the back side of the N-type silicon wafer layer.

[0009] The first gate line passes through the first silicon nitride layer, the aluminum oxide layer and the boron junction layer and contacts the front surface of the N-type silicon layer. The first gate line includes a first seed layer and a first metal layer stacked in sequence.

[0010] The second gate line passes through the silicon oxide layer, the Poly-Si layer and the second silicon nitride layer and contacts the negative surface of the N-type silicon layer. The second gate line includes a second seed layer and a second metal layer stacked in sequence.

[0011] The solar cell prepared by the present invention can effectively improve the bonding strength between the gate line and the silicon wafer. Platinum is used as the seed layer. Due to its higher work function, platinum can effectively match the silicon wafer. During the annealing process, a platinum-silicon alloy layer can be formed to enhance the bonding strength between the gate line and the silicon wafer.

[0012] As a preferred technical solution of the present invention, the thickness of the N-type silicon wafer layer is 120 to 180 μm, wherein the thickness can be 120 μm, 125 μm, 130 μm, 135 μm, 140 μm, 145 μm, 150 μm, 155 μm, 160 μm, 165 μm, 170 μm, 175 μm or 180 μm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0013] Preferably, the thickness of the boron junction layer is 0.5 to 1.2 μm, wherein the thickness may be 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm or 1.2 μm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0014] Preferably, the thickness of the aluminum oxide layer is 2 to 15 nm, wherein the thickness can be 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 11 nm, 12 nm, 13 nm, 14 nm or 15 nm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0015] Preferably, the thickness of the first silicon nitride layer is 70 to 90 nm, wherein the thickness can be 70 nm, 72 nm, 74 nm, 76 nm, 78 nm, 80 nm, 82 nm, 84 nm, 86 nm, 88 nm or 90 nm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0016] Preferably, the thickness of the silicon oxide layer is 1 to 2 nm, wherein the thickness can be 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm or 2 nm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0017] Preferably, the thickness of the Poly-Si layer is 30 to 250 nm, wherein the thickness may be 30 nm, 50 nm, 100 nm, 150 nm, 200 nm or 250 nm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0018] Preferably, the thickness of the second silicon nitride layer is 70 to 90 nm, wherein the thickness can be 70 nm, 72 nm, 74 nm, 76 nm, 78 nm, 80 nm, 82 nm, 84 nm, 86 nm, 88 nm or 90 nm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0019] As a preferred technical solution of the present invention, the first gate line includes a first seed layer and a first metal layer stacked in sequence.

[0020] Preferably, the first seed layer comprises a first metal platinum layer.

[0021] Preferably, the first metal layer includes a first metal nickel layer, a first metal copper layer and a first metal silver layer sequentially stacked on the first seed layer.

[0022] Preferably, the first seed layer contacts the front surface of the N-type silicon layer.

[0023] Preferably, the thickness of the first metal platinum layer is 1 to 100 nm, wherein the thickness can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0024] Preferably, the thickness of the first metal nickel layer is 0.5 to 5 μm, wherein the thickness can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0025] Preferably, the thickness of the first metal copper layer is 1 to 20 μm, wherein the thickness can be 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm or 20 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0026] Preferably, the thickness of the first metal silver layer is 0.2 to 2 μm, wherein the thickness can be 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm or 2 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0027] Preferably, the second gate line includes a second seed layer and a second metal layer stacked in sequence.

[0028] Preferably, the second seed layer comprises a second metal platinum layer.

[0029] Preferably, the second metal layer includes a second metal nickel layer, a second metal copper layer, and a second metal silver layer sequentially stacked on the second seed layer.

[0030] Preferably, the second seed layer contacts the negative surface of the N-type silicon layer;

[0031] Preferably, the thickness of the second metal platinum layer is 1 to 100 nm, wherein the thickness can be 1 nm, 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm or 100 nm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0032] Preferably, the thickness of the second metal nickel layer is 0.5 to 5 μm, wherein the thickness can be 0.5 μm, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm or 5 μm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0033] Preferably, the thickness of the second metal copper layer is 1 to 20 μm, wherein the thickness can be 1 μm, 2 μm, 4 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 16 μm, 18 μm or 20 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0034] Preferably, the thickness of the second metallic silver layer is 0.2 to 2 μm, wherein the thickness may be 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1.0 μm, 1.2 μm, 1.4 μm, 1.6 μm, 1.8 μm or 2 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0035] As a preferred technical solution of the present invention, the number of the first gate lines is ≥1, where the number can be 1, 2, 3, 4, 5, 6, 7 or 8, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0036] Preferably, the number of the second gate lines is ≥1, wherein the number can be 1, 2, 3, 4, 5, 6, 7 or 8, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0037] A second object of the present invention is to provide a method for preparing a solar cell as described in the first object, the method comprising the following steps:

[0038] After texturing on the N-type silicon wafer layer, boron is diffused to form a boron junction layer. After removing the boron junction layer on the back side of the N-type silicon wafer layer, oxidation and Poly-Si deposition are sequentially performed on the back side of the N-type silicon wafer layer to obtain a silicon oxide layer and a Poly-Si layer. After phosphorus diffusion, a first pre-processed cell is obtained.

[0039] Removing the PSG and Poly plating on the front of the first pre-processed cell, depositing an aluminum oxide layer and a first silicon nitride layer on the boron junction layer in sequence, and depositing a second silicon nitride layer on the Poly-Si layer to obtain a second pre-processed cell;

[0040] A laser is used to groove the front and back surfaces of the second pretreated cell, and a first seed layer and a second seed layer are independently electroplated on the surface of the silicon wafer in the grooved area, and a first metal layer and a second metal layer are independently deposited on the first seed layer and the second seed layer to obtain the solar cell.

[0041] As a preferred technical solution of the present invention, the texturing is to remove the mechanical damage layer on the surface of the N-type silicon layer with a first alkaline solution, and then continue to perform surface corrosion treatment with a second alkaline solution to obtain a pyramid structure on the surface of the N-type silicon layer.

[0042] Preferably, the first alkaline solution comprises sodium hydroxide solution and / or potassium hydroxide solution.

[0043] Preferably, the mass concentration of the first alkaline solution is 1.5-2.5%, wherein the mass concentration can be 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2.0%, 2.1%, 2.2%, 2.3%, 2.4% or 2.5%, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0044] Preferably, the thickness of the mechanical damage layer is 1.2 to 1.8 μm, wherein the thickness may be 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm or 1.8 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0045] Preferably, the second alkaline solution comprises sodium hydroxide solution and / or potassium hydroxide solution.

[0046] Preferably, the mass concentration of the second alkaline solution is 2.5-3.5%, wherein the mass concentration can be 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3.0%, 3.1%, 3.2%, 3.3%, 3.4% or 3.5%, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0047] Preferably, the base width of the pyramid structure is 1.2 to 1.8 μm, wherein the size may be 1.2 μm, 1.3 μm, 1.4 μm, 1.5 μm, 1.6 μm, 1.7 μm or 1.8 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0048] As a preferred technical solution of the present invention, the boron diffusion is BCl3 gaseous diffusion.

[0049] Preferably, the temperature of the gaseous diffusion is 900-920°C, wherein the temperature may be 900°C, 902°C, 904°C, 906°C, 908°C, 910°C, 912°C, 914°C, 916°C, 918°C or 920°C, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0050] Preferably, the time for gaseous diffusion is 150 to 200 min, wherein the time can be 150 min, 155 min, 160 min, 165 min, 170 min, 175 min, 180 min, 185 min, 190 min, 195 min or 200 min, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0051] Preferably, the method for removing the boron junction layer on the back side of the N-type silicon wafer layer is chain cleaning and polishing.

[0052] Preferably, the polishing thickness is 3 to 4 μm, wherein the thickness may be 3 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm or 4 μm, etc., but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0053] Preferably, the silicon oxide layer is prepared by a thermal oxidation method.

[0054] Preferably, the Poly-Si deposition method includes LPCVD deposition of a Poly-Si layer of 120 to 170 nm, wherein the deposited thickness can be 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, 150 nm, 155 nm, 160 nm, 165 nm or 170 nm, etc., but is not limited to the listed values, and other unlisted values ​​within this numerical range are also applicable.

[0055] As a preferred technical solution of the present invention, the PSG is removed by HF solution.

[0056] Preferably, the mass concentration of the HF solution is 1-10%, wherein the mass concentration can be 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9% or 10%, etc., but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0057] Preferably, the Poly plating is removed by a third alkaline solution.

[0058] Preferably, the third alkaline solution comprises sodium hydroxide solution and / or potassium hydroxide solution.

[0059] Preferably, the mass concentration of the third alkaline solution is 5-30%, wherein the mass concentration can be 5%, 10%, 15%, 20%, 25% or 30%, etc., but is not limited to the listed values. Other values ​​not listed within this numerical range are also applicable.

[0060] As a preferred technical solution of the present invention, the grooving exposes the silicon wafer.

[0061] Preferably, an oxygen-free annealing treatment is performed after the deposition is completed.

[0062] A third object of the present invention is to provide an application of the solar cell as described in the first object, wherein the solar cell is applied in the photovoltaic field.

[0063] Compared with the prior art, the present invention has the following beneficial effects:

[0064] The solar cells prepared by the present invention can effectively enhance the bonding strength between the grid lines and the silicon wafer, thereby increasing the main grid pull-off strength of the cell, ensuring that the power attenuation of the module during reliability testing complies with IEC standards, and further guaranteeing the power generation capacity of the module throughout its life cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] Figure 1 This is the structure of the solar cell in Examples 1-2 of the present invention and Comparative Example 1.

[0066] In the figure: 1-N-type silicon wafer layer; 2-boron junction layer; 3-aluminum oxide layer; 4-first silicon nitride layer; 5-silicon oxide layer; 6-Poly-Si layer; 7-second silicon nitride layer; 8-first metal platinum layer; 9-first metal nickel layer; 10-first metal copper layer; 11-first metal silver layer; 12-second metal platinum layer; 13-second metal nickel layer; 14-second metal copper layer; 15-second metal silver layer. DETAILED DESCRIPTION

[0067] The technical solution of the present invention is further described below by way of specific embodiments. It should be understood by those skilled in the art that the embodiments are merely to help understand the present invention and should not be regarded as specific limitations of the present invention.

[0068] Example 1

[0069] This embodiment provides a Figure 1 The structure of the solar cell shown:

[0070] The solar cell includes an N-type silicon wafer layer 1, on the front side of which a boron junction layer 2, an aluminum oxide layer 3 and a first silicon nitride layer 4 are sequentially stacked, and on the back side of which a silicon oxide layer 5, a Poly-Si layer 6 and a second silicon nitride layer 7 are sequentially stacked.

[0071] The first gate line passes through the first silicon nitride layer 4, the aluminum oxide layer 3 and the boron junction layer 2 and contacts the front surface of the N-type silicon layer 1, and the first gate line includes a first seed layer and a first metal layer stacked in sequence;

[0072] The second gate line passes through the silicon oxide layer 5 , the Poly-Si layer 6 and the second silicon nitride layer 7 and contacts the negative surface of the N-type silicon layer 1 . The second gate line includes a second seed layer and a second metal layer stacked in sequence.

[0073] The thickness of the N-type silicon layer is 170 nm.

[0074] The thickness of the boron junction layer 2 is 0.9 μm.

[0075] The thickness of the aluminum oxide layer 3 is 10 nm.

[0076] The thickness of the first silicon nitride layer 4 is 80 nm.

[0077] The thickness of the silicon oxide layer 5 is 1.5 nm.

[0078] The thickness of the Poly-Si layer 6 is 200 nm.

[0079] The thickness of the second silicon nitride layer 7 is 80 nm.

[0080] The first gate line includes a first seed layer and a first metal layer stacked in sequence.

[0081] The first seed layer includes a first metal platinum layer 8 .

[0082] The first metal layer includes a first metal nickel layer 9, a first metal copper layer 10 and a first metal silver layer 11 sequentially stacked on the first seed layer.

[0083] The first seed layer contacts the front surface of the N-type silicon layer 1 .

[0084] The thickness of the first metal platinum layer 8 is 10 nm.

[0085] The thickness of the first metal nickel layer 9 is 1 μm

[0086] The thickness of the first metal copper layer 10 is 10 μm.

[0087] The thickness of the first metal silver layer 11 is 1 μm.

[0088] The second gate line includes a second seed layer and a second metal layer stacked in sequence.

[0089] The second seed layer includes a second metal platinum layer 12 .

[0090] The second metal layer includes a second metal nickel layer 13, a second metal copper layer 14, and a second metal silver layer 15 sequentially stacked on the second seed layer.

[0091] The second seed layer contacts the negative surface of the N-type silicon layer 1;

[0092] The thickness of the second metal platinum layer 12 is 10 nm.

[0093] The thickness of the second metal nickel layer 13 is 1 μm.

[0094] The thickness of the second metal copper layer 14 is 10 μm.

[0095] The thickness of the second metal silver layer 15 is 1 μm.

[0096] As a preferred technical solution of the present invention, the number of the first gate lines is 2.

[0097] The number of the second gate lines is 2.

[0098] Example 2

[0099] This embodiment provides a method for preparing a solar cell as in embodiment 1, comprising the following steps:

[0100] (1) An N-type silicon substrate is subjected to a KOH solution with a mass concentration of 2% to remove a 1.5 μm mechanical damage layer, and then subjected to surface etching with a KOH solution with a mass concentration of 3% to form a pyramid structure with a size of 1.5 μm. The N-type silicon substrate having the pyramid structure is subjected to BCl3 gas diffusion at a gaseous diffusion temperature of 910°C and a gaseous diffusion time of 180 minutes to form a boron junction. The back junction is removed by a chain cleaning machine, and the back side of the N-type silicon substrate is polished by 3.5 μm to remove the peripheral boron junction layer. A 1.5 nm silicon oxide film is grown on the back side of the N-type silicon substrate by thermal oxidation, and then a 150 nm poly-Si layer is deposited by LPCVD. After phosphorus diffusion, n-type poly silicon is formed.

[0101] (2) Use a chain machine to remove PSG on the front side, then use a KOH solution in a tank machine to remove polysilicon on the front side, use HF to remove BSG on the silicon wafer, and clean the silicon wafer. Deposit aluminum oxide and silicon nitride on the front side of the silicon wafer, and silicon nitride on the back side.

[0102] (3) Using laser, the aluminum oxide and silicon nitride films on the metallized areas on the front and back of the silicon wafer are removed to expose the silicon wafer. Using electroplating, platinum is deposited on the exposed areas of the silicon wafer to form a seed layer. Then, nickel, copper, silver and other metals are deposited in sequence to form grid lines. After that, oxygen-free annealing is performed to form a solar cell.

[0103] Comparative Example 1

[0104] In this comparative example, except that the electroplating method in step (3) is replaced by the spraying method, other conditions are the same as those in Example 2.

[0105] Comparative Example 2

[0106] In this comparative example, except that step (3) of depositing metal platinum on the exposed part of the silicon wafer to form a seed layer is not performed, other conditions are the same as those in Example 2.

[0107] The pull-off force test of the solar cells in Example 2 and Comparative Examples 1-2 was performed. The test results are shown in Table 1.

[0108] Among them, the test method for pull-off force is: align the battery cell with the bottom plate groove of the tensile tester, clamp the interconnection bar, keep the test direction and the clamping jaws at 180°, the test tensile speed is 200mm / min, and the equipment records the tensile value.

[0109] Table 1

[0110] Pull-off force test Example 2 1.0N Comparative Example 1 0.2N Comparative Example 2 0.4N

[0111] From the above results, it can be seen that the pull-off force of Example 2 is better than that of Comparative Examples 1-2, indicating that platinum plating to form a seed layer can effectively improve the bonding strength between the gate line and the silicon wafer, meet the pull-off force and reliability requirements of the component, and the electroplating effect is the best.

[0112] The applicant declares that the above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Those skilled in the art should understand that any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention fall within the scope of protection and disclosure of the present invention.

Claims

1. A solar cell, characterized in that: The solar cell comprises an N-type silicon layer, wherein a boron junction layer, an aluminum oxide layer and a first silicon nitride layer are sequentially stacked on the front side of the N-type silicon layer, and a silicon oxide layer, a Poly-Si layer and a second silicon nitride layer are sequentially stacked on the back side of the N-type silicon layer; A first gate line passes through the first silicon nitride layer, the aluminum oxide layer, and the boron junction layer and contacts the front surface of the N-type silicon layer, the first gate line comprising a first seed layer and a first metal layer stacked in sequence; the first seed layer comprises a first metal platinum layer; the first seed layer contacts the front surface of the N-type silicon layer; The second gate line passes through the silicon oxide layer, the Poly-Si layer and the second silicon nitride layer and contacts the negative surface of the N-type silicon wafer layer. The second gate line includes a second seed layer and a second metal layer stacked in sequence; the second seed layer includes a second metal platinum layer; and the second seed layer contacts the negative surface of the N-type silicon wafer layer.

2. The solar cell according to claim 1, wherein The thickness of the N-type silicon layer is 120-180 μm.

3. The solar cell according to claim 1, wherein The thickness of the boron junction layer is 0.5-1.2 μm.

4. The solar cell according to claim 1, wherein The thickness of the aluminum oxide layer is 2 to 15 nm.

5. The solar cell according to claim 1, wherein The thickness of the first silicon nitride layer is 70-90 nm.

6. The solar cell according to claim 1, wherein The thickness of the silicon oxide layer is 1-2 nm.

7. The solar cell according to claim 1, wherein The thickness of the Poly-Si layer is 30 to 250 nm.

8. The solar cell according to claim 1, wherein The thickness of the second silicon nitride layer is 70-90 nm.

9. The solar cell according to claim 1, wherein The first metal layer includes a first metal nickel layer, a first metal copper layer, and a first metal silver layer sequentially stacked on the first seed layer.

10. The solar cell according to claim 9, characterized in that The thickness of the first metal platinum layer is 1-100 nm.

11. The solar cell according to claim 9, wherein The thickness of the first metal nickel layer is 0.5-5 μm.

12. The solar cell according to claim 9, wherein The thickness of the first metal copper layer is 1 to 20 μm.

13. The solar cell according to claim 9, characterized in that The thickness of the first metal silver layer is 0.2-2 μm.

14. The solar cell according to claim 1, wherein The second metal layer includes a second metal nickel layer, a second metal copper layer, and a second metal silver layer sequentially stacked on the second seed layer.

15. The solar cell according to claim 14, characterized in that The thickness of the second metal platinum layer is 1-100 nm.

16. The solar cell according to claim 14, wherein The thickness of the second metal nickel layer is 0.5-5 μm.

17. The solar cell according to claim 14, wherein: The thickness of the second metal copper layer is 1 to 20 μm.

18. The solar cell according to claim 14, wherein The thickness of the second metal silver layer is 0.2-2 μm.

19. The solar cell according to claim 1, wherein The number of the first gate lines is ≥1.

20. The solar cell according to claim 1, wherein The number of the second gate lines is ≥1.

21. A method for preparing a solar cell according to any one of claims 1 to 20, characterized in that: The preparation method comprises the following steps: After texturing on the N-type silicon wafer layer, boron is diffused to form a boron junction layer. After removing the boron junction layer on the back side of the N-type silicon wafer layer, oxidation and Poly-Si deposition are sequentially performed on the back side of the N-type silicon wafer layer to obtain a silicon oxide layer and a Poly-Si layer. After phosphorus diffusion, a first pre-processed cell is obtained. Removing the PSG and Poly plating on the front of the first pre-processed cell, depositing an aluminum oxide layer and a first silicon nitride layer on the boron junction layer in sequence, and depositing a second silicon nitride layer on the Poly-Si layer to obtain a second pre-processed cell; A laser is used to groove the front and back surfaces of the second pretreated cell, and a first seed layer and a second seed layer are independently electroplated on the surface of the silicon wafer in the grooved area, and a first metal layer and a second metal layer are independently deposited on the first seed layer and the second seed layer to obtain the solar cell.

22. The preparation method according to claim 21, characterized in that The texturing is to remove the mechanical damage layer on the surface of the N-type silicon layer with a first alkaline solution, and then perform surface etching with a second alkaline solution to obtain a pyramid structure on the surface of the N-type silicon layer.

23. The preparation method according to claim 22, characterized in that The first alkaline solution includes sodium hydroxide solution and / or potassium hydroxide solution.

24. The preparation method according to claim 22, characterized in that The mass concentration of the first alkaline solution is 1.5-2.5%.

25. The preparation method according to claim 22, characterized in that The thickness of the mechanical damage layer is 1.2-1.8 μm.

26. The preparation method according to claim 22, characterized in that The second alkaline solution includes sodium hydroxide solution and / or potassium hydroxide solution.

27. The preparation method according to claim 22, characterized in that The mass concentration of the second alkaline solution is 2.5-3.5%.

28. The preparation method according to claim 22, characterized in that The base width of the pyramid structure is 1.2 to 1.8 μm.

29. The preparation method according to claim 21, characterized in that The boron diffusion is BCl3 gaseous diffusion.

30. The preparation method according to claim 29, characterized in that The temperature of the gaseous diffusion is 900-920°C.

31. The preparation method according to claim 29, characterized in that The gaseous diffusion time is 150 to 200 minutes.

32. The preparation method according to claim 21, characterized in that The method for removing the boron junction layer on the back side of the N-type silicon slice layer is chain cleaning and polishing.

33. The preparation method according to claim 32, characterized in that The polishing thickness is 3-4 μm.

34. The preparation method according to claim 21, characterized in that The silicon oxide layer is prepared by a thermal oxidation method.

35. The preparation method according to claim 21, characterized in that The poly-Si deposition method includes depositing a poly-Si layer of 120 to 170 nm by LPCVD.

36. The preparation method according to claim 21, characterized in that The PSG is removed by HF solution.

37. The preparation method according to claim 36, characterized in that The mass concentration of the HF solution is 1-10%.

38. The preparation method according to claim 21, characterized in that The poly plating is removed by a third alkaline solution.

39. The preparation method according to claim 38, characterized in that The third alkaline solution includes sodium hydroxide solution and / or potassium hydroxide solution.

40. The preparation method according to claim 38, characterized in that The mass concentration of the third alkaline solution is 5-30%.

41. The preparation method according to claim 21, characterized in that The grooves expose the silicon wafer.

42. The preparation method according to claim 21, characterized in that After the deposition is completed, an oxygen-free annealing treatment is performed.

43. Use of the solar cell according to any one of claims 1 to 20, characterized in that: The solar cell is used in the photovoltaic field.

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