Signal processing circuit and signal processing method thereof and Hall sensor circuit

Abstract

The present invention proposes a signal processing circuit, a signal processing method thereof and a Hall sensor circuit. The signal processing circuit includes a Hall signal acquisition circuit, a signal amplification circuit, an offset elimination circuit and a comparison circuit. The Hall signal acquisition circuit is used to acquire at least two Hall signals. The signal amplification circuit is coupled to the Hall signal acquisition circuit, and the signal amplification circuit is used to perform signal amplification processing according to at least two Hall signals to obtain an amplified signal. The offset elimination circuit is used to perform calculation processing according to the amplified signal in a first state and the amplified signal in a second state to obtain an offset correction signal. The comparison circuit is coupled to the offset elimination circuit, and the comparison circuit is used to output a comparison result indication signal according to the offset correction signal and the comparison threshold. The signal processing circuit, the signal processing method thereof and the Hall sensor circuit proposed in the present invention can eliminate or reduce the offset effect introduced by the signal processing circuit, and effectively improve the Hall sensing accuracy and detection speed.

Description

Technical Field

[0001] The invention belongs to the field of power electronics, relates to a Hall sensor technology, and in particular to a signal processing circuit and a signal processing method thereof, and a Hall sensor circuit. Background Art

[0002] When a powered semiconductor Hall disk is in a vertical magnetic field, the electron holes will be deflected by the Lorentz force, thereby generating a potential difference perpendicular to the direction of the current. The potential difference generates an electric field force on the electron holes in the opposite direction to the Lorentz force. When the two forces are balanced, the potential difference is stable, and the generated potential difference is the Hall voltage.

[0003] Hall sensors based on the Hall effect have developed into a diverse family of magnetic sensors, which are increasingly used in various fields such as consumption, industrial control, and automobiles. Hall switches are one of the applications. They use an integrated Hall chip with power on to detect the external magnetic field and convert the changing parameters of the magnetic field into a digital voltage output, so that it has the function of a switch. For example, the input end of the Hall switch is characterized by the magnetic induction intensity B. When the value of the magnetic induction intensity B reaches a certain level (such as B1), the trigger inside the Hall switch flips, and the output level state of the Hall switch also flips. An important application of the Hall switch is the brushless DC motor. The Hall switch is used to give the motor's commutation signal so that the magnetic field generated by the stator generates a positive torque on the rotor, thereby driving the motor to rotate. The operation of the motor requires an inverter to convert electrical energy into kinetic energy. Generally, the device used for energy conversion is realized through a power switch. The change in the switching state of the power switch will cause great interference in the integrated Hall signal processing, resulting in malfunction of the switch.

[0004] like Figure 1As shown, a Hall sensor circuit of the prior art includes a voltage stabilizing circuit, a Hall film, a voltage amplifier, a hysteresis comparator, an output latch circuit, and a clock signal and logic control circuit. The prior art uses a rotating current technology to reduce the offset caused by the non-ideality of the Hall device. The rotating current technology controls the current applied to the Hall effect device and the Hall voltage generated thereby to rotate or switch between two pairs of connectors. The offset of the Hall device itself in the CMOS Hall sensor comes from the uneven concentration of doping, the anisotropy of the substrate material, and the asymmetry of the lithography. In general CMOS processes, the Hall effective signal is in the order of 0.1mV to 1mV, while the Hall offset is 1mV to 10mV. The Hall signal processing circuit also has an offset, which is manifested in the input offset of the op amp and comparator (generally the input offset is 1mV to 10mV), the leakage of the capacitor, and the noise interference of other modules on the power line and the ground line, such as the switching instantaneous interference coupling of the power switch tube on the motor driver chip. Therefore, improving the accuracy of the Hall sensor signal processing circuit needs to start from reducing the offset of the Hall element and the offset of the subsequent Hall signal processing circuit, as well as improving resistance to common-mode noise interference.

[0005] In view of this, it is necessary to provide a new structure or control method to solve at least part of the above problems. Summary of the invention

[0006] In order to solve at least part of the above problems, the present invention proposes a signal processing circuit and a signal processing method thereof and a Hall sensor circuit.

[0007] An embodiment of the present invention discloses a signal processing circuit, the signal processing circuit comprising:

[0008] A Hall signal acquisition circuit, used for acquiring at least two Hall signals;

[0009] A signal amplifying circuit, whose input end is coupled to the Hall signal acquiring circuit, is used for performing signal amplification processing according to at least two Hall signals to obtain an amplified signal;

[0010] An offset cancellation circuit, whose input end is coupled to the output end of the signal amplification circuit, is used to perform calculation processing according to the amplified signal in the first state and the amplified signal in the second state to obtain an offset correction signal; and

[0011] The comparison circuit has an input terminal coupled to the output terminal of the offset elimination circuit and is used for outputting a comparison result indication signal according to the offset correction signal and the comparison threshold.

[0012] As an embodiment of the present invention, the amplified signal includes a first amplified signal and a second amplified signal, and the signal amplification circuit includes:

[0013] A first amplifier circuit, whose input end is coupled to the output end of the Hall signal acquisition circuit, and is used to generate a first amplified signal according to the first Hall signal; and

[0014] The second amplifier circuit has an input end coupled to the output end of the Hall signal acquisition circuit and is used to generate a second amplified signal according to the second Hall signal.

[0015] As an embodiment of the present invention, the offset cancellation circuit includes:

[0016] A third amplifying circuit, comprising a third amplifier, an output terminal of which outputs a third amplified signal; and

[0017] The switch circuit has an input terminal respectively coupled to the first amplifier circuit and the second amplifier circuit, and is used to transmit the first amplified signal and the second amplified signal to the non-inverting input terminal and the inverting input terminal of the third amplifier respectively.

[0018] As an embodiment of the present invention, the offset cancellation circuit further includes:

[0019] The signal superposition circuit has an input end coupled to the output end of the third amplifier circuit and is used for performing calculation processing according to the third amplified signal in the first state and the third amplified signal in the second state to obtain an offset correction signal.

[0020] As an embodiment of the present invention, the signal superposition circuit is used to superimpose the third amplified signal in the first state on the inverted third amplified signal in the second state, so as to obtain the offset correction signal.

[0021] As an embodiment of the present invention, the comparison circuit includes:

[0022] a fourth amplifier circuit, a first input terminal of which is coupled to the first output terminal of the offset cancellation circuit, and a second input terminal of which is coupled to the second output terminal of the offset cancellation circuit;

[0023] a latch comparison circuit, wherein a first input terminal of the latch comparison circuit is coupled to the second output terminal of the fourth amplifier circuit, a second input terminal of the latch comparison circuit is coupled to the first output terminal of the fourth amplifier circuit, a latch control terminal of the latch comparison circuit is coupled to the seventh switch signal, and an output terminal of the latch comparison circuit outputs a comparison result indication signal;

[0024] a fifth fourth switch coupled between the first input terminal and the second output terminal of the fourth amplifier circuit; and

[0025] The sixth fourth switch is coupled between the second input terminal and the first output terminal of the fourth amplifier circuit.

[0026] As an embodiment of the present invention, the Hall signal acquisition circuit includes at least two Hall elements; wherein the direction of the Hall signal output by the first Hall element is opposite to the direction of the Hall signal output by the second Hall element.

[0027] As one embodiment of the present invention, the Hall signal acquisition circuit includes four Hall elements; wherein the direction of the Hall signal output by the first Hall element is the same as the direction of the Hall signal output by the third Hall element, and is opposite to the direction of the Hall signals output by the second Hall element and the fourth Hall element respectively.

[0028] As one embodiment of the present invention, the first non-inverting input terminal and the first inverting input terminal of the first amplifier circuit are respectively coupled to the first output terminal and the second output terminal of the first Hall element; and the first non-inverting input terminal and the first inverting input terminal of the second amplifier circuit are respectively coupled to the first output terminal and the second output terminal of the second Hall element.

[0029] As an embodiment of the present invention, the switch switching circuit includes:

[0030] A first switch, a first end of which is coupled to the output end of the first amplifier circuit;

[0031] A first second switch, a first end of which is coupled to the output end of the second amplifier circuit;

[0032] A first third switch, a first end of which is respectively coupled to the second end of the first first switch and the second end of the first second switch;

[0033] A second switch, a first end of which is coupled to the output end of the second amplifier circuit;

[0034] A second switch, a first end of which is coupled to the output end of the first amplifier circuit;

[0035] A second third switch, a first end of which is respectively coupled to the second end of the second first switch and the second end of the second second switch;

[0036] A first fifth switch, a first end of which is coupled to the second end of the first third switch;

[0037] A second fifth switch, a first end of which is coupled to the second end of the first fifth switch, and a second end of which is coupled to the second end of the second third switch;

[0038] A first capacitor, a first end of which is coupled to the second end of the first third switch;

[0039] A second-first capacitor, a first end of which is coupled to the second end of the second-third switch;

[0040] A third switch, a first end of which is coupled to the second end of the first capacitor;

[0041] a fourth-third switch, a first end of which is coupled to the second end of the third-third switch, and a second end of which is coupled to the second end of the second-first capacitor;

[0042] A third fifth switch, a first end of which is coupled to the second end of the first first capacitor; and

[0043] A first terminal of the fourth-fifth switch is coupled to the second terminal of the second-first capacitor.

[0044] As an embodiment of the present invention, the third amplifier circuit includes:

[0045] A third switch, a first end of which is coupled to the first output end of the switch switching circuit;

[0046] A third second switch, a first end of which is coupled to the first end of the third first switch;

[0047] a fourth switch, a first end of which is coupled to the second output end of the switch switching circuit;

[0048] a fourth second switch, a first end of which is coupled to the first end of the fourth first switch;

[0049] A third amplifier, a non-inverting input terminal of which is respectively coupled to the second terminal of the third-first switch and the second terminal of the fourth-second switch, and an inverting input terminal of which is respectively coupled to the second terminal of the fourth-first switch and the second terminal of the third-second switch;

[0050] a fifth switch, a first terminal of which is coupled to the second output terminal of the third amplifier;

[0051] a fifth second switch, a first terminal of which is coupled to the first output terminal of the third amplifier;

[0052] a sixth switch, a first terminal of which is coupled to the first output terminal of the third amplifier; and

[0053] A first terminal of the sixth second switch is coupled to the second output terminal of the third amplifier.

[0054] As an embodiment of the present invention, the signal superposition circuit includes:

[0055] A third fourth switch, a first end of which is coupled to the output end of the third amplifier circuit;

[0056] A first six-switch, a first end of which is coupled to a first end of a third four-switch;

[0057] a fourth switch, a first end of which is coupled to the output end of the third amplifier circuit;

[0058] A second sixth switch, a first end of which is coupled to the first end of the fourth fourth switch;

[0059] The first three capacitors have their first ends coupled to the second ends of the third four switches and the second ends of the second six switches respectively; and the second three capacitors have their first ends coupled to the second ends of the fourth four switches and the second ends of the first six switches respectively.

[0060] As one embodiment of the present invention, the latched comparison circuit is a hysteresis comparator.

[0061] As an embodiment of the present invention, the fourth amplifier circuit includes:

[0062] A first level conversion circuit, an input terminal of which is coupled to a first output terminal of the offset cancellation circuit;

[0063] A second level conversion circuit, an input terminal of which is coupled to the second output terminal of the offset elimination circuit;

[0064] an eighth switch coupled between the input terminal and the output terminal of the first level conversion circuit;

[0065] a ninth switch coupled between the input terminal and the output terminal of the second level conversion circuit;

[0066] a fifth amplifier, a non-inverting input terminal of which is coupled to the output terminal of the first level conversion circuit, and an inverting input terminal of which is coupled to the output terminal of the second level conversion circuit; and

[0067] The sixth amplifier has its non-inverting input terminal coupled to the first output terminal of the fifth amplifier, its inverting input terminal coupled to the second output terminal of the fifth amplifier, its first output terminal coupled to the second terminal of the latched comparator circuit, and its second output terminal coupled to the first terminal of the latched comparator circuit.

[0068] As an embodiment of the present invention, the offset cancellation circuit further includes:

[0069] A first second capacitor, a first end of which is coupled to the first end of the third first switch, and a second end of which is coupled to the second end of the fifth first switch;

[0070] A second second capacitor, a first end of which is coupled to the first end of the fourth first switch, and a second end of which is coupled to the second end of the sixth first switch;

[0071] A first four switches connected in parallel with the first two capacitors; and

[0072] The second fourth switch is connected in parallel with the second second capacitor.

[0073] Another embodiment of the present invention discloses a Hall sensor circuit, which includes the signal processing circuit as described in any one of the above items.

[0074] Another embodiment of the present invention further discloses a signal processing method, the signal processing method comprising:

[0075] Obtain at least two Hall signals;

[0076] Performing signal amplification processing according to at least two Hall signals to obtain an amplified signal;

[0077] Performing calculation processing on the amplified signal in the first state and the amplified signal in the second state to obtain an offset correction signal; and

[0078] A comparison result indication signal is output according to the offset correction signal and the comparison threshold.

[0079] As an embodiment of the present invention, the amplified signal includes a first amplified signal and a second amplified signal; the at least two Hall signals include a first Hall signal and a second Hall signal, the first amplified signal is generated according to the first Hall signal, and the second amplified signal is generated according to the second Hall signal.

[0080] As one embodiment of the present invention, a direction of the first Hall signal is opposite to a direction of the second Hall signal.

[0081] As one embodiment of the present invention, the first amplified signal and the second amplified signal are respectively transmitted to the non-inverting input terminal and the inverting input terminal of the third amplifier in the third amplifier circuit; the third amplifier circuit outputs the third amplified signal, and the third amplified signal in the first state is superimposed on the inverted third amplified signal in the second state, so as to obtain the offset correction signal.

[0082] The present invention proposes a signal processing circuit and a signal processing method thereof and a Hall sensing circuit, wherein the signal processing circuit includes a Hall signal acquisition circuit, a signal amplification circuit, an offset elimination circuit and a comparison circuit. The Hall signal acquisition circuit is used to acquire at least two Hall signals. The input end of the signal amplification circuit is coupled to the Hall signal acquisition circuit, and the signal amplification circuit is used to perform signal amplification processing according to at least two Hall signals to obtain an amplified signal. The input end of the offset elimination circuit is coupled to the output end of the signal amplification circuit, and the offset elimination circuit is used to perform calculation processing according to the amplified signal in a first state and the amplified signal in a second state to obtain an offset correction signal. The input end of the comparison circuit is coupled to the output end of the offset elimination circuit, and the comparison circuit is used to output a comparison result indication signal according to the offset correction signal and the comparison threshold. The signal processing circuit and the signal processing method thereof and the Hall sensing circuit proposed by the present invention can eliminate or reduce the offset effect introduced by the signal processing circuit, and effectively improve the Hall sensing accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0083] Figure 1 A schematic diagram of the circuit structure of a Hall sensor circuit in the prior art is shown;

[0084] Figure 2 A circuit structure schematic diagram of a signal processing circuit according to an embodiment of the present invention is shown;

[0085] Figure 3 A circuit structure schematic diagram of a Hall signal acquisition circuit according to an embodiment of the present invention is shown;

[0086] Figure 4 A circuit structure schematic diagram of a Hall signal acquisition circuit according to another embodiment of the present invention is shown;

[0087] Figure 5A schematic diagram of the circuit structure of a comparison circuit according to an embodiment of the present invention is shown;

[0088] Figure 6 FIG. 4 shows a timing diagram of various switch control signals of a signal processing circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0089] The preferred embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0090] In order to further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, rather than limiting the claims of the present invention.

[0091] The description in this section is only for several typical embodiments, and the present invention is not limited to the scope of the embodiments. The same or similar prior art means and some technical features in the embodiments are mutually replaced within the scope of the present invention.

[0092] "Coupled" or "connected" in the specification includes both direct connection and indirect connection. Indirect connection is a connection through an intermediate medium, such as a connection through an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connection may also include connection through other active or passive devices on the basis of achieving the same or similar functional purpose, such as connection through circuits or components such as switches and follower circuits. In addition, in the present invention, words such as "first" and "second" are mainly used to distinguish one technical feature from another technical feature, and do not necessarily require or imply that there is a certain actual relationship or order between these technical features.

[0093] An embodiment of the present invention discloses a signal processing circuit, which includes a Hall signal acquisition circuit, a signal amplification circuit, an offset elimination circuit and a comparison circuit. The Hall signal acquisition circuit is used to acquire two Hall signals. In one embodiment, the Hall signal acquisition circuit may include a Hall element. In another embodiment, the Hall signal acquisition circuit does not include a Hall element. In addition, in other embodiments, the Hall signal acquisition circuit is used to acquire more than two Hall signals, for example, four Hall signals or six Hall signals. In this embodiment, the input end of the signal amplification circuit is coupled to the Hall signal acquisition circuit, and the signal amplification circuit is used to perform signal amplification processing according to the two Hall signals to obtain an amplified signal. The input end of the offset elimination circuit is coupled to the output end of the signal amplification circuit, and the offset elimination circuit is used to perform calculation processing according to the amplified signal in the first state and the amplified signal in the second state to obtain an offset correction signal. The input end of the comparison circuit is coupled to the output end of the offset elimination circuit, and the comparison circuit is used to output a comparison result indication signal according to the offset correction signal and the comparison threshold. The comparison result indication signal can be used to determine the position of the motor rotor, thereby determining whether to change phases, so as to prevent the rotating magnetic field generated by the motor stator from applying torque in the opposite direction to the rotor of the permanent magnet, thereby causing the motor to stall. The invention proposes a signal processing circuit that can eliminate or reduce the offset effect introduced by the signal processing circuit, effectively improving the Hall sensing accuracy and detection speed. The Hall sensing speed of the prior art is relatively slow, responding in about a few hundred microseconds, while the Hall sensing device based on the invention has a faster detection speed, responding in about 10 microseconds.

[0094] In one embodiment of the present invention, Figure 2As shown, the signal processing circuit includes a Hall signal acquisition circuit (not shown in the figure), a signal amplifying circuit 20, an offset elimination circuit 30 and a comparison circuit 40. The signal amplifying circuit 20 includes a first amplifying circuit A1 and a second amplifying circuit A2. The input end of the first amplifying circuit A1 is coupled to the output end of the Hall signal acquisition circuit, and the first amplifying circuit A1 is used to generate a first amplified signal according to the first Hall signal. The input end of the second amplifying circuit A2 is coupled to the output end of the Hall signal acquisition circuit, and the second amplifying circuit A2 is used to generate a second amplified signal according to the second Hall signal. In a specific embodiment, the input end of the first amplifying circuit A1 includes a first non-inverting input end and a first inverting input end, and the output end of the Hall signal acquisition circuit includes a first output end and a second output end of the first Hall element and a first output end and a second output end of the second Hall element. The first non-inverting input end of the first amplifying circuit A1 is coupled to the first output end of the first Hall element to obtain a voltage Vha_1, and the inverting input end of the first amplifying circuit A1 is coupled to the second output end of the first Hall element to obtain a voltage Vha_2. The difference between the voltage Vha_1 and the voltage Vha_2 is the first Hall signal output by the first Hall element, that is, the first Hall voltage. The input end of the second amplifier circuit A2 includes a first non-inverting input end and a first inverting input end. The first non-inverting input end of the second amplifier circuit A2 is coupled to the first output end of the second Hall element to obtain the voltage Vhb_1, and the first inverting input end of the second amplifier circuit A2 is coupled to the second output end of the second Hall element to obtain the voltage Vhb_2. The difference between the voltage Vhb_1 and the voltage Vhb_2 is the second Hall signal output by the second Hall element, that is, the second Hall voltage.

[0095] In one embodiment of the present invention, the Hall signal acquisition circuit includes at least two Hall elements. Figure 3In the illustrated embodiment, the Hall signal acquisition circuit 10 includes a first Hall element 101 and a second Hall element 102. The first Hall element 101 includes a switch cka1, a switch cka2, a switch ckb1, a switch ckb2, a switch ckc1, a switch ckc2, a switch ckd1, a switch ckd2, a first Hall thin film, and a current source Ia. The first end of the switch cka1 is coupled to the first voltage, and the second end of the switch cka1 is coupled to the first end of the first Hall thin film. The first end of the switch cka2 is coupled to the first voltage, and the second end of the switch cka2 is coupled to the second end of the first Hall thin film. The first end of the switch ckb2 is coupled to the third end of the first Hall thin film, and the second end of the switch ckb2 is coupled to the current source Ia. The first end of the switch ckb1 is coupled to the fourth end of the first Hall thin film, and the second end of the switch ckb1 is coupled to the current source Ia. The output end of the current source is coupled to ground. The first end of the switch ckc1 is coupled to the second end of the switch cka2. The first end of the switch ckc2 is coupled to the second end of the switch cka1, and the second end of the switch ckc2 is coupled to the second end of the switch ckc1. The second end of the switch ckc1 serves as the first output end of the first Hall element 101, and the output signal of the second end of the switch ckc1 is the voltage Vha_1. The first end of the switch ckd1 is coupled to the first end of the switch ckb2. The first end of the switch ckd2 is coupled to the first end of the switch ckb1, and the second end of the switch ckd2 is coupled to the second end of the switch ckd1. The second end of the switch ckd1 serves as the second output end of the first Hall element 101, and the output signal of the second end of the switch ckd1 is the voltage Vha_2. The difference between the voltage Vha_1 and the voltage Vha_2 is the first Hall signal output by the first Hall element 101, that is, the first Hall voltage.

[0096] like Figure 3In the illustrated embodiment, the second Hall element 102 includes a switch cke1, a switch cke2, a switch ckf1, a switch ckf2, a switch ckg1, a switch ckg2, a switch ckh1, a switch ckh2, a second Hall plate, and a current source Ib. A first end of the switch cke2 is coupled to a first voltage, and a second end of the switch cke2 is coupled to a fourth end of the second Hall plate. A first end of the switch cke1 is coupled to a first voltage, and a second end of the switch cke1 is coupled to a third end of the second Hall plate. A first end of the switch ckf1 is coupled to a second end of the second Hall plate, and a second end of the switch ckf1 is coupled to the current source Ib. A first end of the switch ckf2 is coupled to a first end of the second Hall plate, and a second end of the switch ckf2 is coupled to the current source Ib. An output end of the current source Ib is coupled to ground. A first end of the switch ckg2 is coupled to a second end of the switch cke1. A first end of the switch ckg1 is coupled to a second end of the switch cke2, and a second end of the switch ckg1 is coupled to a second end of the switch ckg2. The second end of the switch ckg2 serves as the first output end of the second Hall element 102, and the output signal of the second end of the switch ckg2 is the voltage Vhb_1. The first end of the switch ckh2 is coupled to the first end of the switch ckf1. The first end of the switch ckh1 is coupled to the first end of the switch ckf2, and the second end of the switch ckh1 is coupled to the second end of the switch ckh2. The second end of the switch ckh2 serves as the second output end of the second Hall element 102, and the output signal of the second end of the switch ckh2 is the voltage Vhb_2. The difference between the voltage Vhb_1 and the voltage Vhb_2 is the second Hall signal output by the second Hall element 102, that is, the second Hall voltage.

[0097] In one embodiment of the present invention, Figure 3 and Figure 6, when the first switch control signal ck1 is at a first level (e.g., a high level), the control switches cka1, ckb1, ckc1, ckd1, cke1, ckf1, ckg1, and ckh1 are all turned on. When the first switch control signal ck1 is at a second level (e.g., a low level), the control switches cka1, ckb1, ckc1, ckd1, cke1, ckf1, ckg1, and ckh1 are all turned off. When the second switch control signal ck2 is at a first level (e.g., a high level), the control switches cka2, ckb2, ckc2, ckd2, cke2, ckf2, ckg2, and ckh2 are all turned on. When the second switch control signal ck2 is at a second level (e.g., a low level), the control switches cka2, ckb2, ckc2, ckd2, cke2, ckf2, ckg2, and ckh2 are all turned off. Exemplarily, the first switch control signal ck1 being at the first level and the second switch control signal ck2 being at the second level may be regarded as the first state, and the first switch control signal ck1 being at the second level and the second switch control signal ck2 being at the first level may be regarded as the second state. Figure 3 and Figure 6 It can be seen that under the same magnetic field direction, no matter in the first state or the second state, the direction of the Hall signal output by the first Hall element is opposite to the direction of the Hall signal output by the second Hall element.

[0098] In another embodiment of the present invention, Figure 4As shown, the Hall signal acquisition circuit includes four Hall elements, namely, a first Hall element 111, a second Hall element 112, a third Hall element 113 and a fourth Hall element 114. The second end of the switch ckc1 serves as the first output end of the first Hall element 111, and the output signal of the second end of the switch ckc1 is a voltage Vha_1. The second end of the switch ckd1 serves as the second output end of the first Hall element 111, and the output signal of the second end of the switch ckd1 is a voltage Vha_2. The difference between the voltage Vha_1 and the voltage Vha_2 is the first Hall signal output by the first Hall element 111, that is, the first Hall voltage. The second end of the switch ckg2 serves as the first output end of the second Hall element 112, and the output signal of the second end of the switch ckg2 is a voltage Vhb_1. The second end of the switch ckh2 serves as the second output end of the second Hall element 112, and the output signal of the second end of the switch ckh2 is a voltage Vhb_2. The difference between the voltage Vhb_1 and the voltage Vhb_2 is the second Hall signal output by the second Hall element 112, that is, the second Hall voltage. The second end of the switch ckk2 serves as the first output end of the third Hall element 113, and the output signal of the second end of the switch ckk2 is a voltage Vhc_1. The second end of the switch ckl2 serves as the second output end of the third Hall element 113, and the output signal of the second end of the switch ckl2 is a voltage Vhc_2. The difference between the voltage Vhc_2 and the voltage Vhc_1 is the third Hall signal output by the third Hall element 113, that is, the third Hall voltage. The second end of the switch cko1 serves as the first output end of the fourth Hall element 114, and the output signal of the second end of the switch cko1 is a voltage Vhd_1. The second end of the switch ckp1 serves as the second output end of the fourth Hall element 114, and the output signal of the second end of the switch ckp1 is a voltage Vhd_2. The difference between the voltage Vhd_2 and the voltage Vhd_1 is the fourth Hall signal output by the fourth Hall element 114, that is, the fourth Hall voltage. Figure 4 and Figure 6 It can be seen that under the same magnetic field direction, whether in the first state or the second state, the direction of the Hall signal output by the first Hall element 111 is the same as the direction of the Hall signal output by the third Hall element 113, and the direction of the Hall signal output by the first Hall element 111 is opposite to the directions of the Hall signals output by the second Hall element 112 and the fourth Hall element 114 respectively.

[0099] In another embodiment, if Figure 2As shown, the input end of the first amplifier circuit A1 includes a first non-inverting input end, a first inverting input end, a second non-inverting input end, a second inverting input end, a third non-inverting input end and a third inverting input end. The first non-inverting input end of the first amplifier circuit A1 is coupled to the first output end of the first Hall element to obtain the voltage Vha_1, and the first inverting input end of the first amplifier circuit A1 is coupled to the second output end of the first Hall element to obtain the voltage Vha_2. The second non-inverting input end of the first amplifier circuit A1 is coupled to the second output end of the third Hall element to obtain the voltage Vhc_2, and the second inverting input end of the first amplifier circuit A1 is coupled to the first output end of the third Hall element to obtain the voltage Vhc_1. The third non-inverting input end of the first amplifier circuit A1 is coupled to the second end of the first resistor R1, and the third inverting input end of the first amplifier circuit A1 is respectively coupled to the first end of the first resistor R1 and the second end of the second resistor R2, and the first end of the second resistor R2 is coupled to the output end of the first amplifier circuit A1. The first non-inverting input terminal of the second amplifier circuit A2 is coupled to the first output terminal of the second Hall element to obtain the voltage Vhb_1, and the first inverting input terminal of the second amplifier circuit A2 is coupled to the second output terminal of the second Hall element to obtain the voltage Vhb_2. The second non-inverting input terminal of the second amplifier circuit A2 is coupled to the second output terminal of the fourth Hall element to obtain the voltage Vhd_2, and the second inverting input terminal of the second amplifier circuit A2 is coupled to the first output terminal of the fourth Hall element to obtain the voltage Vhd_1. The third non-inverting input terminal of the second amplifier circuit A2 is coupled to the second end of the third resistor R3, and the third inverting input terminal of the second amplifier circuit A2 is respectively coupled to the first end of the third resistor R3 and the second end of the fourth resistor R4, and the first end of the fourth resistor R4 is coupled to the output terminal of the second amplifier circuit A2. The difference between the voltage Vhc_2 and the voltage Vhc_1 is the third Hall signal output by the third Hall element, that is, the third Hall voltage. The difference between the voltage Vhd_2 and the voltage Vhd_1 is the fourth Hall signal output by the fourth Hall element, that is, the fourth Hall voltage. The first amplifier circuit A1 is used to generate a first amplified signal according to the first Hall signal and the third Hall signal. The second amplifier circuit A2 is used to generate a second amplified signal according to the second Hall signal and the fourth Hall signal.

[0100] In one embodiment of the present invention, Figure 2As shown, the offset elimination circuit 30 includes a third amplifier circuit and a switch switching circuit. The third amplifier circuit 30 includes a third amplifier, and the output end of the third amplifier circuit 30 outputs a third amplified signal. The input end of the switch switching circuit is coupled to the first amplifier circuit A1 and the second amplifier circuit A2 respectively, and the switch switching circuit is used to transmit the first amplified signal to the in-phase input end of the third amplifier, and transmit the second amplified signal to the inverting input end of the third amplifier. It can be understood that the signal received by the in-phase input end of the third amplifier can be equal to the first amplified signal, or a signal that is proportional to or correlated with the first amplified signal. The signal received by the inverting input end of the third amplifier can be equal to the second amplified signal, or a signal that is proportional to or correlated with the second amplified signal. The third amplified signal in the first state is obtained by the amplified signal in the first state, and the third amplified signal in the second state is obtained by the amplified signal in the second state. The offset elimination circuit generates an offset correction signal according to the third amplified signal in the first state and the third amplified signal in the second state. In a specific embodiment, the switch switching circuit includes an energy storage circuit, and the switch switching circuit is used to transmit the first amplified signal to the first end of the energy storage circuit and the second amplified signal to the second end of the energy storage circuit in a first state, and transmit the second amplified signal to the first end of the energy storage circuit and the first amplified signal to the second end of the energy storage circuit in a second state. Specifically, the energy storage circuit includes a first capacitor and a second capacitor. The first end of the first capacitor serves as the first end of the energy storage circuit, and the first end of the second capacitor serves as the second end of the energy storage circuit.

[0101] In a specific embodiment of the present invention, the switch switching circuit includes a first switch ck11, a first second switch ck12, a first third switch ck13, a second first switch ck21, a second second switch ck22, a second third switch ck23, a first fifth switch ck15, a second fifth switch ck25, a first first capacitor C11, a second first capacitor C21, a third third switch ck33, a fourth third switch ck43, a third fifth switch ck35, and a fourth fifth switch ck45. A first end of the first first switch ck11 is coupled to an output end of the first amplifier circuit A1. A first end of the first second switch ck12 is coupled to an output end of the second amplifier circuit A2. A first end of the first third switch ck13 is respectively coupled to a second end of the first first switch ck11 and a second end of the first second switch ck12. A first end of the second first switch ck21 is coupled to an output end of the second amplifier circuit A2. A first end of the second second switch ck22 is coupled to an output end of the first amplifier circuit A1. A first end of the second third switch ck23 is respectively coupled to a second end of the second first switch ck21 and a second end of the second second switch ck22. The first end of the first five switches ck15 is coupled to the second end of the first three switches ck13. The first end of the second five switches ck25 is coupled to the second end of the first five switches ck15, and the second end of the second five switches ck25 is coupled to the second end of the second three switches ck23. The first end of the first capacitor C11 is coupled to the second end of the first three switches ck13. The first end of the second capacitor C21 is coupled to the second end of the second three switches ck23. The first end of the third three switches ck33 is coupled to the second end of the first capacitor C11. The first end of the fourth three switches ck43 is coupled to the second end of the third three switches ck33, and the second end of the fourth three switches ck43 is coupled to the second end of the second three capacitors C21. The first end of the third five switches ck35 is coupled to the second end of the first one capacitor C11, and the second end of the third five switches ck35 serves as the first output end of the switch switching circuit. The first end of the fourth five switches ck45 is coupled to the second end of the second one capacitor C21, and the second end of the fourth five switches ck45 serves as the second output end of the switch switching circuit.

[0102] In a specific embodiment of the present invention, the third amplifier circuit includes a third-first switch ck31, a third-second switch ck32, a fourth-first switch ck41, a fourth-second switch ck42, a third amplifier A3, a fifth-first switch ck51, a fifth-second switch ck52, a sixth-first switch ck61, and a sixth-second switch ck62. A first end of the third-first switch ck31 is coupled to a first output end of the switch switching circuit. A first end of the third-second switch ck32 is coupled to a first end of the third-first switch ck31. A first end of the fourth-first switch ck41 is coupled to a second output end of the switch switching circuit. A first end of the fourth-second switch ck42 is coupled to a first end of the fourth-first switch ck41. A non-inverting input end of the third amplifier A3 is coupled to a second end of the third-first switch ck31 and a second end of the fourth-second switch ck42, and an inverting input end of the third amplifier A3 is coupled to a second end of the fourth-first switch ck41 and a second end of the third-second switch ck32. A first end of the fifth-first switch ck51 is coupled to a second output end of the third amplifier A3. A first end of the fifth-second switch ck52 is coupled to a first output end of the third amplifier A3. The second end of the fifth-first switch ck51 is coupled to the second end of the fifth-second switch ck52, and the second end of the fifth-first switch ck51 serves as the second output end of the third amplifier circuit. The first end of the sixth-first switch ck61 is coupled to the first output end of the third amplifier A3. The first end of the sixth-second switch ck62 is coupled to the second output end of the third amplifier A3. The second end of the sixth-first switch ck61 is coupled to the second end of the sixth-second switch ck62, and the second end of the sixth-first switch ck61 serves as the first output end of the third amplifier circuit.

[0103] In another specific embodiment of the present invention, Figure 2 As shown, the offset cancellation circuit 30 further includes a first second capacitor C12, a second second capacitor C22, a first fourth switch ck14, and a second fourth switch ck24. The first end of the first second capacitor C12 is coupled to the first end of the third first switch ck31, and the second end of the first second capacitor C12 is coupled to the second end of the fifth first switch ck51. The first end of the second second capacitor C22 is coupled to the first end of the fourth first switch ck41, and the second end of the second second capacitor C22 is coupled to the second end of the sixth first switch ck61. The first fourth switch ck14 is connected in parallel with the first second capacitor C12. The second fourth switch ck24 is connected in parallel with the second second capacitor C22.

[0104] In one embodiment of the present invention, the offset elimination circuit further includes a signal superposition circuit. The input end of the signal superposition circuit is coupled to the output end of the third amplifier circuit, and the signal superposition circuit is used to perform operation processing according to the third amplified signal in the first state and the third amplified signal in the second state to obtain an offset correction signal. The operation processing may be a subtraction operation or a superposition operation. In one embodiment, the offset correction signal is obtained by subtracting the third amplified signal in the second state from the third amplified signal in the first state. In another embodiment, the offset correction signal is obtained by superimposing the third amplified signal in the first state on the inverted third amplified signal in the second state, that is, realizing the operation effect of subtracting the third amplified signal in the second state from the third amplified signal in the first state. The specific operation processing rules can be selected according to the needs of the specific circuit, which will not be repeated here.

[0105] In one embodiment of the present invention, Figure 2 As shown, the signal superposition circuit includes a third four-switch ck34, a first six-switch ck16, a fourth four-switch ck44, a second six-switch ck26, a first three-capacitor C13, and a second three-capacitor C23. The first end of the third four-switch ck34 is coupled to the output end of the third amplifier circuit. The first end of the first six-switch ck16 is coupled to the first end of the third four-switch ck34. The first end of the fourth four-switch ck44 is coupled to the output end of the third amplifier circuit. The first end of the second six-switch ck26 is coupled to the first end of the fourth four-switch ck44. The first end of the first three-capacitor C13 is respectively coupled to the second end of the third four-switch ck34 and the second end of the second six-switch ck26. The first end of the second three-capacitor C23 is respectively coupled to the second end of the fourth four-switch ck44 and the second end of the first six-switch ck16. In a specific embodiment, the output end of the third amplifier circuit includes a first output end and a second output end, the third four-switch ck34 is coupled to the second output end of the third amplifier circuit through the fifth one-switch ck51, and the fourth four-switch ck44 is coupled to the first output end of the third amplifier circuit through the sixth one-switch ck61.

[0106] In one embodiment of the present invention, Figure 2As shown, the comparison circuit 40 includes a fourth amplifier circuit A4, a latch comparison circuit, a fifth fourth switch ck54 and a sixth fourth switch ck64. The first input terminal of the fourth amplifier circuit A4 is coupled to the first output terminal of the offset cancellation circuit 30, and the second input terminal of the fourth amplifier circuit A4 is coupled to the second output terminal of the offset cancellation circuit 30. The first input terminal of the latch comparison circuit is coupled to the second output terminal of the fourth amplifier circuit A4, the second input terminal of the latch comparison circuit is coupled to the first output terminal of the fourth amplifier circuit A4, the latch control terminal of the latch comparison circuit is coupled to the seventh switch signal ck7, and the output terminal of the latch comparison circuit outputs a comparison result indication signal, and the comparison result indication signal includes a signal Y and a signal Y_N. The position of the motor rotor can be judged according to the signal Y and the signal Y_N, so as to determine whether to perform phase switching. The fifth fourth switch ck54 is coupled between the first input terminal and the second output terminal of the fourth amplifier circuit A4. The sixth fourth switch ck64 is coupled between the second input terminal and the first output terminal of the fourth amplifier circuit A4. In a specific embodiment of the present invention, the latch comparison circuit is a hysteresis comparator.

[0107] In one embodiment of the present invention, Figure 5 As shown, the fourth amplifier circuit includes a first level conversion circuit, a second level conversion circuit, an eighth switch ck8, a ninth switch ck9, a fifth amplifier A5 and a sixth amplifier A6. The input end of the first level conversion circuit is coupled to the first output end of the offset cancellation circuit. The input end of the second level conversion circuit is coupled to the second output end of the offset cancellation circuit. The eighth switch ck8 is coupled between the input end and the output end of the first level conversion circuit. The switching state of the eighth switch ck8 can be controlled by the output signal of the first OR gate. The first input end of the first OR gate receives the fourth switch control signal ck4, and the second input end of the first OR gate receives the signal Y. The ninth switch ck9 is coupled between the input end and the output end of the second level conversion circuit. The switching state of the ninth switch ck9 can be controlled by the output signal of the second OR gate. The first input end of the second OR gate receives the fourth switch control signal ck4, and the second input end of the second OR gate receives the signal Y_N. The non-inverting input end of the fifth amplifier A5 is coupled to the output end of the first level conversion circuit, and the inverting input end of the fifth amplifier A5 is coupled to the output end of the second level conversion circuit. The non-inverting input terminal of the sixth amplifier A6 is coupled to the first output terminal of the fifth amplifier A5, the inverting input terminal of the sixth amplifier A6 is coupled to the second output terminal of the fifth amplifier, the first output terminal of the sixth amplifier A6 is coupled to the second terminal of the latch comparator circuit, and the second output terminal of the sixth amplifier A6 is coupled to the first terminal of the latch comparator circuit.

[0108] In one embodiment, the first amplifier circuit and the second amplifier circuit are respectively fully differential amplifiers. Preferably, the third amplifier circuit includes a fully differential amplifier, which can perfectly eliminate common mode noise and improve the anti-interference ability of the system.

[0109] like Figure 6 As shown, it is a timing diagram of each switch control signal in the signal processing circuit, which are the first switch control signal ck1, the second switch control signal ck2, the third switch control signal ck3, the fourth switch control signal ck4, the fifth switch control signal ck5, the sixth switch control signal ck6, and the seventh switch control signal ck7. Among them, except for the dead time (near the area where ck3 switches between high and low levels), when the third switch control signal ck3 is at the first level, the fifth switch control signal ck5 is at the second level; when the third switch control signal ck3 is at the second level, the fifth switch control signal ck5 is at the first level. Similarly, except for the dead time (near the area where ck4 switches between high and low levels), when the fourth switch control signal ck4 is at the first level, the sixth switch control signal ck6 is at the second level; when the fourth switch control signal ck4 is at the second level, the sixth switch control signal ck6 is at the first level. Figures 2 to 5 In the embodiment, the first switch control signal ck1 is used to control the switch with the switch symbol suffix (the last digit) being 1, for example: switch cka1, switch ckb1, switch ck11, switch ck21, etc. The second switch control signal ck2 is used to control the switch with the switch symbol suffix being 2, for example: switch cka2, switch ckb2, switch ck12, switch ck22, etc. The third switch control signal ck3 is used to control the switch with the switch symbol suffix being 3, for example: switch ck13, switch ck23, switch ck33, etc. The fourth switch control signal ck4 is used to control the switch with the switch symbol suffix being 4, for example: switch ck14, switch ck24, switch ck34, etc. The fifth switch control signal ck5 is used to control the switch with the switch symbol suffix being 5, for example: switch ck15, switch ck25, switch ck35, etc. The sixth switch control signal ck6 is used to control the switch with the switch symbol suffix being 6, for example: switch ck16, switch ck26, etc. The seventh switch control signal ck7 is used to perform latch control.

[0110] In one embodiment of the present invention, Figure 2 and Figure 6, at time t1, the fourth switch control signal is at a first level (for example, a high level), the first second capacitor C12 and the second second capacitor C22 are reset, and the signal processing circuit restarts a cycle of signal processing. The first third capacitor C13 and the second third capacitor C23 store the offset Vos4 of the comparison circuit 40 and the offset Vos3 of the third amplifier circuit. In the stage where the first switch control signal ck1 is at a first level and the second switch control signal ck2 is at a second level, and through the control of the third switch control signal ck3 and the fourth switch control signal ck4, the third amplifier circuit includes a third amplifier, the signal received at the in-phase input terminal of the third amplifier is 2Vhall*R2 / R1+Vos1, and the signal received at the inverting input terminal of the third amplifier is -2Vhall*R4 / R3+Vos2. Considering the offset Vos3 of the third amplifier circuit, the third amplified signal at this time is

[0111] (2Vhall*R2 / R1+Vos1)-(-2Vhall*R4 / R3+Vos2)+Vos3.

[0112] Set the ratio of R2 / R1 to be equal to R4 / R3, so the third amplified signal is

[0113] 4Vhall*R2 / R1+Vos1-Vos2+Vos3.

[0114] Among them, Vhall is the Hall voltage; R1 is the resistance of the first resistor, R2 is the resistance of the second resistor; R2 / R1 is the amplification factor of the first amplifier circuit, R4 / R3 is the amplification factor of the second amplifier circuit, Vos1 is the offset value of the first amplifier circuit, Vos2 is the offset value of the second amplifier circuit, and Vos3 is the offset value of the third amplifier circuit.

[0115] In the stage where the first switch control signal ck1 is at the second level and the second switch control signal ck2 is at the first level, and through the control of the third switch control signal ck3 and the fourth switch control signal ck4, the signal received by the in-phase input terminal of the third amplifier is -2Vhall*R2 / R1+Vos1, and the signal received by the inverting input terminal of the third amplifier is 2Vhall*R4 / R3+Vos2. Considering the offset Vos3 of the third amplifier circuit, the third amplified signal at this time is

[0116] (-2Vhall*R2 / R1+Vos1)-(2Vhall*R4 / R3+Vos2)+Vos3=-4Vhall*R2 / R1+Vos1-Vos2+Vos3.

[0117] When the first switch control signal ck1 is at the second level, the second switch control signal ck2 is at the first level, and the fifth switch control signal ck5 is at the first level, the offset correction signal output by the offset cancellation circuit is

[0118] ((Vout+)-(Vout-))=(4Vhall*R2 / R1+Vos1-Vos2+Vos3)-(-4Vhall*R2 / R1+Vos1-Vos2+Vos3)-Vos4=8Vhall*R2 / R1-Vos4.

[0119] Wherein, Vout+ is the voltage at the second end of the first third capacitor C13, and Vout- is the voltage at the second end of the second third capacitor C23.

[0120] After time t6, the fourth switch control signal will be at the first level again, and the next cycle will begin.

[0121] From the above, it can be seen that the offset values ​​in the first amplifier circuit, the second amplifier circuit and the third amplifier circuit have been eliminated, which can eliminate or reduce the offset effect introduced by the signal processing circuit, and effectively improve the Hall sensing accuracy.

[0122] See also Figure 2 , Figure 5 and Figure 6 It can be seen that the first terminal voltage of the first level conversion circuit is equal to Vout+, and the second terminal voltage Vp of the first level conversion circuit obtained by the first level conversion circuit is (Vout+)+Y*Vls, where Y is a signal in the comparison result indication signal, and Vls is the voltage difference transferred by the first level conversion circuit.

[0123] The voltage at the first terminal of the second level conversion circuit is equal to Vout-. After being processed by the second level conversion circuit, the voltage at the second terminal of the second level conversion circuit Vn is (Vout+)+Y_N*Vls, where Y_N is another signal in the comparison result indication signal, and Vls is the voltage difference transferred by the second level conversion circuit. Without considering the amplifier circuit in the comparison circuit, the voltage difference Va between the voltage at the first input terminal and the voltage at the second input terminal of the comparison circuit is

[0124] Va=8Vhall*R2 / R1-Vos4+Vos4+Y*Vls-Y_N*Vls.

[0125] When the fourth switch control signal ck4 is at a first level (eg, a high level), the comparison circuit 40 is connected to form a unit gain negative feedback circuit. At this time, the offset of the comparison circuit 40 will appear Figure 2The right side of the first three capacitors C13 and the second three capacitors C23 is equivalent to existing in Vout = (Vout + -Vout -). Because it is a negative feedback, the offset stored at Vout is -Vos4. When the comparison circuit 40 outputs, that is, when the seventh switch control signal ck7 is at the first level (such as a high level), at this time, there is a fixed offset +Vos4 at the input end of the comparison circuit 40, and the two will cancel each other, thereby canceling the offset of the comparison circuit 40.

[0126] When 8Vhall*R2 / R1+Y*Vls-Y_N*Vls=0, the comparison circuit is at the flip point and will control the commutation process. Since the Hall voltage Vhall is a sinusoidal signal, Vhall will undergo positive and negative sinusoidal changes. When Va>0, Y=1, Y_N=0. When Va<0, Y=0, Y_N=1. When the seventh switch control signal ck7 is at the second level, the comparison circuit is in the latching stage, and the comparison result indication signal output by the comparison circuit maintains the state when the seventh switch control signal ck7 is at the first level. When the seventh switch control signal ck7 is at the first level, the output signal of the offset elimination circuit is sent to the latching comparison circuit for comparison after being pre-amplified by the fourth amplifier circuit, and the latching comparison circuit outputs the comparison result indication signals Y and Y_N. The commutation can be controlled according to the signal Y and the signal Y_N in the comparison result indication signal, so that the rotating magnetic field generated by the motor stator applies a torque in the corresponding direction to the rotor of the permanent magnet, so that the motor can work normally. By eliminating or reducing the offset in the signal processing circuit and improving the sensing accuracy of the Hall voltage, the anti-interference ability of the system can be effectively improved.

[0127] An embodiment of the present invention further discloses a Hall sensor circuit, which includes any of the above signal processing circuits. The signal processing circuit of the present invention can improve the anti-interference ability and sensor accuracy of the Hall sensor circuit.

[0128] An embodiment of the present invention further discloses a signal processing method, the signal processing method comprising:

[0129] Obtain at least two Hall signals;

[0130] Performing signal amplification processing according to at least two Hall signals to obtain an amplified signal;

[0131] Performing calculation processing on the amplified signal in the first state and the amplified signal in the second state to obtain an offset correction signal; and

[0132] A comparison result indication signal is output according to the offset correction signal and the comparison threshold.

[0133] In one embodiment of the present invention, the amplified signal includes a first amplified signal and a second amplified signal; the at least two Hall signals include a first Hall signal and a second Hall signal, the first amplified signal is generated according to the first Hall signal, and the second amplified signal is generated according to the second Hall signal.

[0134] In one embodiment of the present invention, the direction of the first Hall signal is opposite to the direction of the second Hall signal.

[0135] In one embodiment of the present invention, the first amplified signal and the second amplified signal are output to the non-inverting input terminal and the inverting input terminal of the third amplifier in the third amplifier circuit, respectively. In one embodiment of the present invention, the third amplifier circuit outputs the third amplified signal, and the third amplified signal in the first state is superimposed on the inverted third amplified signal in the second state, thereby obtaining an offset correction signal. The specific implementation of the signal processing method can refer to the implementation of the circuit and will not be further expanded.

[0136] An embodiment of the present invention proposes a Hall sensor composed of at least two Hall elements, which uses a rotating current method to offset the offset voltage introduced by the non-ideality of the Hall element, and eliminates the offset of the operational amplifier circuit, etc. through signal processing, thereby effectively reducing the offset effect of the Hall sensor.

[0137] The above description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above embodiments. The relevant descriptions of the effects or advantages involved in the embodiments may not be reflected in the experimental examples due to the uncertainty of the specific condition parameters, and are not used to limit the embodiments. The deformation and changes of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent components are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential characteristics of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. A signal processing circuit, characterized in that: The signal processing circuit comprises: A Hall signal acquisition circuit, used for acquiring at least two Hall signals; A signal amplifying circuit, whose input end is coupled to the Hall signal acquiring circuit, is used for performing signal amplification processing according to at least two Hall signals to obtain an amplified signal, wherein the amplified signal includes a first amplified signal and a second amplified signal; An offset cancellation circuit, whose input end is coupled to the output end of the signal amplification circuit, comprises a third amplification circuit, a switch circuit and a signal superposition circuit, and is used to perform operation processing according to the amplified signal in the first state and the amplified signal in the second state to obtain an offset correction signal; the third amplification circuit comprises a third amplifier, and the output end of the third amplification circuit outputs a third amplified signal; the input end of the switch circuit is coupled to the signal amplification circuit, and the switch circuit is used to transmit the first amplified signal and the second amplified signal to the in-phase input end and the inverting input end of the third amplifier respectively; the input end of the signal superposition circuit is coupled to the output end of the third amplification circuit, and the signal superposition circuit is used to superimpose the third amplified signal in the first state on the inverted third amplified signal in the second state to obtain an offset correction signal; and The comparison circuit has an input terminal coupled to the output terminal of the offset elimination circuit and is used for outputting a comparison result indication signal according to the offset correction signal and the comparison threshold.

2. The signal processing circuit according to claim 1, characterized in that The signal amplification circuit comprises: A first amplifier circuit, whose input end is coupled to the output end of the Hall signal acquisition circuit, and is used to generate a first amplified signal according to the first Hall signal; and The second amplifier circuit has an input end coupled to the output end of the Hall signal acquisition circuit and is used to generate a second amplified signal according to the second Hall signal.

3. The signal processing circuit according to claim 2, characterized in that: The input end of the switch circuit is respectively coupled to the first amplifier circuit and the second amplifier circuit.

4. The signal processing circuit according to claim 1, characterized in that: The comparison circuit comprises: a fourth amplifier circuit, a first input terminal of which is coupled to the first output terminal of the offset cancellation circuit, and a second input terminal of which is coupled to the second output terminal of the offset cancellation circuit; a latch comparison circuit, wherein a first input terminal of the latch comparison circuit is coupled to the second output terminal of the fourth amplifier circuit, a second input terminal of the latch comparison circuit is coupled to the first output terminal of the fourth amplifier circuit, a latch control terminal of the latch comparison circuit is coupled to the seventh switch signal, and an output terminal of the latch comparison circuit outputs a comparison result indication signal; a fifth fourth switch coupled between the first input terminal and the second output terminal of the fourth amplifier circuit; and The sixth fourth switch is coupled between the second input terminal and the first output terminal of the fourth amplifier circuit.

5. The signal processing circuit according to claim 1, characterized in that: The Hall signal acquisition circuit includes at least two Hall elements; wherein the direction of the Hall signal output by the first Hall element is opposite to the direction of the Hall signal output by the second Hall element.

6. The signal processing circuit according to claim 1, characterized in that: The Hall signal acquisition circuit includes four Hall elements; wherein the direction of the Hall signal output by the first Hall element is the same as the direction of the Hall signal output by the third Hall element, and is opposite to the directions of the Hall signals output by the second Hall element and the fourth Hall element respectively.

7. The signal processing circuit according to claim 2, characterized in that: A first non-inverting input terminal and a first inverting input terminal of the first amplifier circuit are respectively coupled to a first output terminal and a second output terminal of the first Hall element; as well as, The first non-inverting input terminal and the first inverting input terminal of the second amplifier circuit are respectively coupled to the first output terminal and the second output terminal of the second Hall element.

8. The signal processing circuit according to claim 3, characterized in that: The switch switching circuit includes: A first switch, a first end of which is coupled to the output end of the first amplifier circuit; A first second switch, a first end of which is coupled to the output end of the second amplifier circuit; A first third switch, a first end of which is respectively coupled to the second end of the first first switch and the second end of the first second switch; A second switch, a first end of which is coupled to the output end of the second amplifier circuit; A second switch, a first end of which is coupled to the output end of the first amplifier circuit; A second third switch, a first end of which is respectively coupled to the second end of the second first switch and the second end of the second second switch; A first fifth switch, a first end of which is coupled to the second end of the first third switch; A second fifth switch, a first end of which is coupled to the second end of the first fifth switch, and a second end of which is coupled to the second end of the second third switch; A first capacitor, a first end of which is coupled to the second end of the first third switch; A second-first capacitor, a first end of which is coupled to the second end of the second-third switch; A third switch, a first end of which is coupled to the second end of the first capacitor; a fourth-third switch, a first end of which is coupled to the second end of the third-third switch, and a second end of which is coupled to the second end of the second-first capacitor; A third fifth switch, a first end of which is coupled to the second end of the first first capacitor; and A first terminal of the fourth-fifth switch is coupled to the second terminal of the second-first capacitor.

9. The signal processing circuit according to claim 3, characterized in that: The third amplifying circuit comprises: A third switch, a first end of which is coupled to the first output end of the switch switching circuit; A third second switch, a first end of which is coupled to the first end of the third first switch; a fourth switch, a first end of which is coupled to the second output end of the switch switching circuit; a fourth second switch, a first end of which is coupled to the first end of the fourth first switch; A third amplifier, a non-inverting input terminal of which is respectively coupled to the second terminal of the third-first switch and the second terminal of the fourth-second switch, and an inverting input terminal of which is respectively coupled to the second terminal of the fourth-first switch and the second terminal of the third-second switch; a fifth switch, a first terminal of which is coupled to the second output terminal of the third amplifier; a fifth second switch, a first terminal of which is coupled to the first output terminal of the third amplifier; a sixth switch, a first terminal of which is coupled to the first output terminal of the third amplifier; and A first terminal of the sixth second switch is coupled to the second output terminal of the third amplifier.

10. The signal processing circuit according to claim 1, characterized in that: The signal superposition circuit comprises: A third fourth switch, a first end of which is coupled to the output end of the third amplifier circuit; A first six-switch, a first end of which is coupled to a first end of a third four-switch; a fourth switch, a first end of which is coupled to the output end of the third amplifier circuit; A second sixth switch, a first end of which is coupled to the first end of the fourth fourth switch; The first three capacitors have first terminals respectively coupled to the second terminals of the third four switches and the second terminals of the second six switches; and The first end of the second third capacitor is respectively coupled to the second end of the fourth fourth switch and the second end of the first sixth switch.

11. The signal processing circuit according to claim 4, characterized in that: The latch comparison circuit is a hysteresis comparator.

12. The signal processing circuit according to claim 4, characterized in that: The fourth amplifying circuit comprises: A first level conversion circuit, an input terminal of which is coupled to a first output terminal of the offset cancellation circuit; A second level conversion circuit, an input terminal of which is coupled to the second output terminal of the offset elimination circuit; an eighth switch coupled between the input terminal and the output terminal of the first level conversion circuit; a ninth switch coupled between the input terminal and the output terminal of the second level conversion circuit; a fifth amplifier, a non-inverting input terminal of which is coupled to the output terminal of the first level conversion circuit, and an inverting input terminal of which is coupled to the output terminal of the second level conversion circuit; and The sixth amplifier has its non-inverting input terminal coupled to the first output terminal of the fifth amplifier, its inverting input terminal coupled to the second output terminal of the fifth amplifier, its first output terminal coupled to the second terminal of the latched comparator circuit, and its second output terminal coupled to the first terminal of the latched comparator circuit.

13. The signal processing circuit according to claim 9, characterized in that: The offset cancellation circuit further includes: A first second capacitor, a first end of which is coupled to the first end of the third first switch, and a second end of which is coupled to the second end of the fifth first switch; A second second capacitor, a first end of which is coupled to the first end of the fourth first switch, and a second end of which is coupled to the second end of the sixth first switch; A first four switches connected in parallel with the first two capacitors; and The second fourth switch is connected in parallel with the second second capacitor.

14. A Hall sensor circuit, characterized in that: The Hall sensor circuit comprises a signal processing circuit as described in any one of claims 1-13.

15. A signal processing method, characterized in that: The signal processing method comprises: Obtain at least two Hall signals; Performing signal amplification processing according to at least two Hall signals to obtain an amplified signal, wherein the amplified signal includes a first amplified signal and a second amplified signal; The offset correction signal is obtained by performing calculation processing on the amplified signal in the first state and the amplified signal in the second state, wherein the steps include: transmitting the first amplified signal and the second amplified signal to the in-phase input terminal and the inverting input terminal of the third amplifier in the third amplifier circuit respectively; the third amplifier circuit outputs the third amplified signal, and the third amplified signal in the first state is superimposed on the inverted third amplified signal in the second state, thereby obtaining the offset correction signal; and A comparison result indication signal is output according to the offset correction signal and the comparison threshold.

16. The signal processing method according to claim 15, characterized in that: The at least two Hall signals include a first Hall signal and a second Hall signal, a first amplified signal is generated according to the first Hall signal, and a second amplified signal is generated according to the second Hall signal.

17. The signal processing method according to claim 16, characterized in that: The direction of the first Hall signal is opposite to the direction of the second Hall signal.

Images