Joint scheduling load in data processing apparatus

Abstract

Data processing apparatus and methods of operating such data processing apparatus are disclosed. An issue circuit buffers operations until operands required by the operations are available in a set of registers before execution. When a first load operation and a second load operation both depend on a common operand, and when the common operand is available in the set of registers, the first load operation and the second load operation are identified in the issue circuit. A load circuit has a first address generation unit to generate a first address for the first load operation and a second address generation unit to generate a second address for the second load operation. An address comparison unit compares the first address and the second address. The load circuit is arranged to cause a merged lookup to be performed in a local scratchpad storing copies of data values from a memory when the address comparison unit determines that the first address and the second address differ by less than a predetermined address range characteristic of the local scratchpad.

Description

[0001] This technology relates to data processing. Specifically, this technology relates to the performance of loading operations in a data processing apparatus.

[0002] Data processing units arranged to execute data processing instructions can be provided in a pipelined manner, where instructions fetched from memory are first decoded and then issued for execution. An instruction can only be executed if the operand specified by the instruction is available in a local register of the data processing unit accessible to the execution unit. Therefore, before being issued for execution, an instruction can be temporarily held in a issuance queue after decoding, awaiting the availability of its operand. One class of instructions that can be defined is the load instruction, which causes a specified data item to be retrieved from the memory system of the data processing unit and stored in a local register. Such load instructions can specify the data item to be retrieved from the memory system indirectly, such as via a pointer to a memory location or via a base pointer to a memory location where an offset needs to be applied, and may actually require retrieval and / or determination even if the offset itself is not specified as an immediate value in the instruction.

[0003] In one exemplary embodiment, a data processing apparatus includes: an execution circuit for performing a data processing operation in response to a sequence of instructions; a release circuit for buffering operations generated by the sequence of instructions prior to execution until operands required for the operation are available in a set of registers, wherein the release circuit is arranged to identify the first load operation and the second load operation based on the dependence of a first load operation and a second load operation on a common operand and the availability of the common operand in the set of registers; and a load circuit for loading at least one operand into the set of registers in response to a load instruction in the sequence of instructions, wherein the load circuit further includes: a first address generation unit, wherein... A first address generation unit is configured to generate a first address in response to the first load operation identified by the publishing circuit; a second address generation unit is configured to generate a second address in response to the second load operation identified by the publishing circuit; an address comparison unit is configured to compare the first address and the second address; and a local temporary storage device is configured to store a copy of a data value from a memory, wherein the loading circuit is configured to cause a merge lookup to be performed in the local temporary storage device based on the first address and the second address when the address comparison unit determines that the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device.

[0004] In another exemplary embodiment, a method for performing data processing includes the following steps: identifying a first load operation and a second load operation in a sequence of operations held in a release queue, based on the fact that a first load operation and a second load operation depend on a common operand and the availability of the common operand in a set of registers; generating a first address in response to the first load operation; generating a second address in response to the second load operation identified in the sequence of instructions in the release queue; comparing the first address and the second address in a load unit; and causing a merge lookup to be performed in the local temporary storage device of the load unit based on the first address and the second address when the difference between the first address and the second address is less than a predetermined address range characteristic of a local temporary storage device.

[0005] In another exemplary embodiment, a data processing apparatus includes: means for identifying a first load operation and a second load operation in a sequence of operations held in a release queue, based on the first load operation and the second load operation depending on a common operand and the availability of the common operand in a set of registers; means for generating a first address in response to the first load operation; means for generating a second address in response to the second load operation; means for comparing the first address and the second address in a load unit; and means for causing a merge lookup to be performed in the local temporary storage of the load unit based on the first address and the second address when the difference between the first address and the second address is less than a predetermined address range characteristic of a local temporary storage.

[0006] The present invention will be further described by way of example only, with reference to embodiments shown in the accompanying drawings, wherein:

[0007] Figure 1 The data processing apparatus is illustrated schematically with various examples that may embody the present technology;

[0008] Figure 2A The data processing apparatus, including a publishing queue and a loading unit, is illustrated schematically according to various examples of the present technology;

[0009] Figure 2B The release queue, along with associated operand comparison circuitry and identification control circuitry, is schematically illustrated according to various examples of the present technology.

[0010] Figures 3A to 3D The illustrations schematically depict the publish queue, two address generation units, address comparison unit, L1 data cache, and micro TLB in various configurations according to various examples of this technology;

[0011] Figure 4 The process of performing a merge lookup according to some embodiments of this technology is illustrated schematically;

[0012] Figure 5A The illustration schematically shows some implementation schemes. Figure 4 Further details of the operation of the address comparison circuit shown;

[0013] Figure 5B A load / store unit according to some implementation schemes is illustrated in more detail;

[0014] Figure 6A and Figure 6B Further details of some embodiments of this technology are illustrated schematically;

[0015] Figure 7 The function of a loading unit according to some embodiments of the present technology is schematically illustrated;

[0016] Figure 8 This diagram illustrates a sequence of steps performed by some embodiments of the present technology to determine whether a merge lookup should be performed; and

[0017] Figure 9 A sequence of steps performed in some embodiments of this technology is shown.

[0018] At least some embodiments provide a data processing apparatus comprising: an execution circuit for performing a data processing operation in response to a sequence of instructions; a release circuit for buffering operations generated by the sequence of instructions prior to execution until operands required by the operations are available in a set of registers, wherein the release circuit is arranged to identify the first load operation and the second load operation based on the dependence of a common operand and the availability of the common operand in the set of registers; and a load circuit for loading at least one operand into the set of registers in response to a load instruction in the sequence of instructions, wherein the load circuit further comprises: a first address generation unit. The unit comprises: a first address generation unit configured to generate a first address in response to a first load operation identified by the publishing circuit; a second address generation unit configured to generate a second address in response to a second load operation identified by the publishing circuit; an address comparison unit configured to compare the first address and the second address; and a local temporary storage device for storing copies of data values ​​from the memory, wherein the loading circuit is configured to cause a merge lookup in the local temporary storage device based on the first address and the second address when the address comparison unit determines that the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device.

[0019] This technology recognizes that a common pattern in programs running on data processing devices is loading multiple indexed values ​​from the same base address pointer that is relatively very close to each other in the program. For example, a load could be accessing different components of a structure after dereferencing the pointer, or reading a stack frame after a function call. In a standard configuration, multiple load operations are handled by one or more load units, each configured to handle a single load. This technology recognizes that advantages can be gained by reducing the number of independent lookups generated (e.g., translation back buffer lookups and cache lookups), thereby increasing load throughput without requiring a full additional load unit (and thus improving power performance per unit area). This is achieved by detecting loads and jointly scheduling them to adjacent addresses based on speculative grouping of loads in merge lookups that share dependencies of source operands. In this technology, this identification of loads capable of performing such merge lookups is performed relative to the release queue. Therefore, where the release queue can contain combinations of instructions, micro-operations (split instructions), and macro-operations (fusion instructions), identification can be performed for any of these types of "operations," particularly for "load operations" that can be temporarily held in the release queue. The term "load operation" used here for the content of the release queue refers to any of the following: (hierarchical) load instructions, load micro-operations, and load macro-operations. This approach, based on hardware-based shared dependency detection of load groups, therefore implies that no software burden is imposed on the programmer (or compiler) to seek and identify such first and second load instructions. Furthermore, this technique is to distinguish it from techniques associated with multi-threaded instruction execution, which attempt to identify loads in a parallel execution stream that can benefit from some form of cooperative processing. Here, the technique involves a sequential instruction stream in a single-threaded context. It should also be noted that this technique does not propose merging first and second load instructions. Instead, first and second load instructions are jointly scheduled, combining accesses to local memory devices (such as TLBs or caches) if their addresses sufficiently overlap.

[0020] Loads to be co-scheduled or combined are not limited to a specific size or data type. The only requirement for co-scheduled loading is that the loads share a dependency on the source operands. A non-limiting exemplary code sequence that can employ this technique could be:

[0021] 1. LDRx15, [sp, #0x140]; Loads a base pointer to a structure from a stack variable.

[0022] 2.LDRx10,[x15]; Load the next pointer field.

[0023] 3.LDRHx11,[x15,#0x10]; Load half-word data field

[0024] 4.LDRBx12,[x15,#0x14]; Load byte data field

[0025] Instruction #1 loads a pointer from a memory location—in this specific example, from a variable currently overflowing the stack—and stores the value in register x15. The result of instruction #1, held in register x15, is fed into instructions #2 through #4, which use the value stored in x15 as a base pointer for relative addressing and retrieve individual fields from a reference structure in memory. This technique is based on the observation that instructions #2 through #4 share the same source register dependency on register x15, meaning that all three are ready to execute simultaneously because the same source operands become available. This knowledge is used to speculatively issue at least two of the three load instructions #2, #3, and #4 to a specially adapted load unit containing at least two address generation units. If the result of the address generation phase shows that all virtual addresses differ by less than a predetermined address range, these virtual addresses can be combined into a single merge lookup within a local temporary storage unit.

[0026] The type of local temporary storage is not limited; for example, it can be a translation backup buffer used to store data for translation between virtual addresses used locally by the processing circuitry and physical addresses associated with physical locations in the memory hierarchy of the stored data elements. In other embodiments, the local temporary storage can be, for example, a data cache, in which temporary copies of data items are stored locally by the processing circuitry.

[0027] For a merge lookup to be performed, two requirements must be met. First, the publishing circuit detects that the first and second load operations must be based on a common operand. Once this condition is met, the first and second load operations are passed to the same load unit. This load unit contains multiple address generation units, each for each load operation passed to the load unit by the publishing circuit. The first address generation unit generates a first address based on the first load operation, and the second address generation unit generates a second address based on the second load operation. Since each address generation process is performed by a separate address generation unit, this step can be performed in parallel. However, it should be noted that a single address generation unit can also generate multiple addresses consecutively. Once an address is generated, the second requirement is that the address falls within a predetermined range. The predetermined range is a characteristic of the local temporary storage unit. In some embodiments, when the local temporary storage unit is a data cache, the predetermined address range may correspond to the size of a cache line within the data cache. In other embodiments, when the local temporary storage unit is a translation back buffer, the local temporary storage unit can be the smallest page size associated with the granularity at which the address translation data is stored in the translation back buffer. Once an address is generated, the address comparison unit compares the addresses to determine whether the address falls within the predetermined address range. If the second condition is met, a merge lookup can be performed in the local temporary storage device. Further details regarding merge lookups are provided below.

[0028] The address generation unit and address comparison unit can be implemented in various ways. In some implementations, multiple address generation units are provided, and the address comparison unit compares a set of most significant bits of the generated address bit by bit. Alternatively, a single address generation unit can be provided, and the generated first address can be temporarily stored by the address comparison unit. Once the address generation unit generates a second address, the address comparison unit can compare the second address with the temporarily stored first address. If the address corresponds to an address within a predetermined address range, a merge lookup can be performed.

[0029] In some implementations, when the address comparison unit determines that the difference between the first address and the second address is greater than a predetermined address range, the loading circuit is arranged to cause a first lookup to be performed on one of the first loading operation and the second loading operation, and to cause a second lookup to be performed on the other of the first loading operation and the second loading operation.

[0030] The manner in which the first and second lookups are performed is unrestricted and will depend on the nature of the local temporary storage. In some implementations, when the local temporary storage is a data cache and a predetermined address range corresponds to the size of a cache line in the data cache, the first and second lookups can be performed sequentially in the data cache. However, as will be discussed in more detail later, if the difference between the first and second addresses is greater than the predetermined address range associated with the data cache, a merge lookup can still be performed in the translation back buffer when the difference between the first and second addresses is less than the granularity size or minimum page size associated with address translation in the translation back buffer.

[0031] In some implementations, the merge lookup involves using either the first address or the second address. Local temporary storage stores data based on addresses. In some implementations where the local temporary storage is a data cache, data is stored in cache lines, and the identifier used to identify the contents of a given cache line corresponds to the most significant portion of the address. In some implementations, the cache line size is 64 bytes, and the address portion required to identify the contents of a given cache line is the most significant portion of the address. Therefore, a specific data item within a cache line is specified by the least significant portion of the address. For a 64-byte cache line size, where each unique memory address specifies a specific byte, the cache line specifier is thus given by excluding the six least significant bits from the address. Therefore, if the first address and the second address are within 64 bytes, they will share the same cache line, and the cache line can be specified using either the first address or the second address, which are identical once the six least significant bits of the address line are omitted. In some implementations, when the local temporary storage is a translation back buffer (TLB) and the predetermined address range corresponds to the minimum page size of 4kB used by the TLB, a merge lookup is performed using either the first address or the second address, which are identical when the least significant 12 bits of either the first address or the second address are ignored.

[0032] In some embodiments, the local temporary storage device is a first local temporary storage device, and the data processing circuitry further includes a second local temporary storage device, wherein one of the first and second local temporary storage devices is a translation backup buffer used to store translated data for translating input virtual addresses into output physical addresses. The first and second local temporary storage devices can be arranged such that they can be accessed in parallel. In some embodiments, this is achieved by performing a merge lookup on both the first and second local temporary storage devices. This is only possible if the address range difference between the first and second addresses is less than the smaller of the characteristic address range associated with the first and the characteristic address range associated with the second local temporary storage device. However, this technology is not limited to this particular configuration, and as will be discussed in detail later, when the difference between the first address and the second address is greater than the smaller of the feature address range associated with the first local temporary storage device and the feature address range associated with the second local temporary storage device, but the address difference is less than the larger of the feature address range associated with the first local temporary storage device and the feature address range associated with the second local temporary storage device, a merged lookup can be performed in the local temporary storage device with the larger feature address range, and a pair of lookups can be performed in the local temporary storage device with the smaller feature address range. As will be described in more detail later, this pair of lookups can be performed in parallel in some embodiments and sequentially in other embodiments.

[0033] In some implementations, the other of the first and second local temporary storage devices is a data cache. As previously mentioned, the data cache can be a virtual-addressed data cache or a physically-addressed data cache. When the data cache is a physically-addressed data cache, it should be understood that in order to perform a merge lookup or standard lookup, the virtual address provided to the load circuitry must first be translated to a physical address using a translation lookup buffer or otherwise.

[0034] As discussed earlier, in some implementations, the predetermined address range corresponds to the cache line size of the data cache. Therefore, a merge lookup corresponds to a merge lookup within the cache, where the merge lookup specifies the cache line to be looked up and read from the data cache. Once data is read from the data cache based on the most significant portion of the address line, the specific data item requested by the first and second lookups is retrieved from the data cache based on the least significant portion of the address. As a specific example, the address could be a 32-bit address that specifies a byte-addressable region of memory. The first 26 bits of this address can be used to identify the cache line, and once 64 bytes of cache line have been retrieved from the data cache, the six least significant bits can then be used to specify the specific byte within that line. Through this mechanism, only a single cache lookup is performed to provide the data associated with the first address and the data associated with the second address.

[0035] In some implementations where the predetermined address range corresponds to the cache line size of the data cache, the data cache is a virtual indexed cache, and the data processing means is arranged to perform a merge lookup in the data cache in parallel with a further merge lookup in the translation lookup buffer. The feature address range associated with the data cache can be, for example, a cache line size of 64 bytes. This is typically smaller than the minimum page size associated with the translation lookup buffer, which, as mentioned above, can be, for example, 4 KB. Therefore, in this case, if the difference between the first address and the second address is less than the feature size associated with the data cache, a merge lookup can be performed in the data cache, and a further merge lookup can be performed in the translation lookup buffer. Since the data cache is a virtual addressing cache, it is not necessary to translate the address from the virtual address to the physical address before looking up in the data cache. Therefore, lookups in the data cache can be performed in parallel with lookups in the translation lookup buffer.

[0036] In some implementations where the predetermined address range corresponds to the cache line size of the data cache, the data cache is a physical index cache, and the data processing means is arranged to perform a merge lookup in the data cache using the physical address obtained from a previous merge lookup in the translation lookup buffer. The feature address range associated with the data cache can be, for example, a cache line size of 64 bytes. This is typically smaller than the minimum page size associated with the translation lookup buffer. Therefore, if the difference between the first address and the second address is less than the feature size associated with the data cache, a single translation lookup buffer lookup may be performed in this case to translate the virtual address associated with the merge lookup into the physical address associated with the merge lookup. In particular, for a 32-bit physical address specifying a byte-addressable region of memory, if the translation lookup buffer stores the address translation of the 20-bit portion of the virtual address to a physical address of a 4kB page size, and the data cache stores a 64B cache line, the translation lookup buffer translates the 20 most significant bits of the virtual address into the 20 most significant bits of the physical address, thereby generating a 32-bit physical address. The data cache uses the 26 most significant bits of the physical address to identify the cache line to be read from the physically addressed cache. This method requires only a single lookup in the translation back buffer and a single lookup in the physically addressed cache. However, because the address needs to be translated from virtual to physical before being looked up in the data cache, these two steps are performed sequentially.

[0037] In some implementations, the predetermined address range corresponds to the minimum range of the address space where the translation back buffer stores the translated data. As discussed above, the characteristic address range associated with the translation back buffer is typically larger than the characteristic address range associated with the data cache. Therefore, in this case, it may not be possible to perform a merge lookup also in the data cache.

[0038] In some implementations where the predetermined address range corresponds to the minimum range of the address space where the translated data is stored in the translation back buffer, the data cache is a virtual indexed cache, and the data processing means is arranged to perform a pair of further lookups in parallel in the data cache and a merge lookup in the translation back buffer. Because the data cache is a virtual indexed data cache, it is possible to perform at least the first of a pair of further lookups in the data cache in parallel with the merge lookup in the translation back buffer.

[0039] In some implementations where the predetermined address range corresponds to the minimum range of the address space where the translated data is stored in the translation back buffer, the data cache is a physical index cache, and the data processing means is arranged to perform a pair of further lookups in the data cache using the output of the merge lookup in the translation back buffer. As discussed above, for example, if the translation back buffer stores the translated address in a 4kB page and the data cache stores a 64B cache line, the translation back buffer generates the 20 most significant bits of the physical address. The load circuitry is also configured to generate a pair of physical addresses, comprising a first physical address consisting of the 20 most significant bits of the physical address and the 12 least significant bits of the first virtual address, and a second physical address consisting of the 20 most significant bits of the physical address and the 12 least significant bits of the second virtual address. A pair of virtual lookups can then be performed in the data cache corresponding to the first and second physical addresses.

[0040] In some embodiments where the predetermined address range corresponds to the minimum range of the address space where the translated data is stored in the translation back buffer, the data cache includes a first port and a second port, and the data processing apparatus is arranged such that a pair of further lookups are performed in parallel via the first port and the second port. For embodiments where the data cache is a virtual addressing cache, both the merge lookup in the translation back buffer and the pair of lookups in the data cache can be performed in parallel. However, for embodiments where the data cache is a physical addressing cache, the merge lookup is first performed in the translation back buffer. A pair of physical addresses is generated using the resulting physical addresses, which can be used to perform a pair of lookups in parallel in the data cache.

[0041] In some embodiments, where the predetermined address range corresponds to the minimum range of the address space where the translation backup buffer stores translated data, the data cache includes buffering circuitry associated with buffered data lookup requests, and the data processing apparatus is arranged to cause a pair of further lookups to be performed sequentially as a first lookup and a second lookup, with the second lookup buffered in the buffering circuitry while the first lookup is being performed. The buffering circuitry can take many forms, but its simplest form may include a memory large enough to buffer the address associated with the second lookup. After the first lookup is performed, the address associated with the second lookup can be forwarded to the data cache.

[0042] In some implementations, in response to a merge lookup result being a miss in at least one of the data cache and translation back buffer, the load circuitry is arranged to forward the merge lookup to the next level of the memory hierarchy. Data is transferred to the cache in blocks the size of cache lines. Therefore, if a merge lookup miss is detected in the data cache, forwarding the merge lookup to the next level of the memory hierarchy will cause the required cache line associated with the merge lookup to be returned. Similarly, in cases where a miss is detected in the translation back buffer where the entry corresponds to the minimum page size, forwarding the merge lookup to the next level of the memory hierarchy will cause the required page translation to be returned for the merge lookup. However, in some implementations, in response to a merge lookup result being a miss in at least one of the data cache and translation back buffer, the load circuitry is arranged to forward the address of the earlier of a first load operation and a second load operation to the next level of the memory hierarchy.

[0043] In some embodiments, the data processing apparatus is an ordered data processing apparatus, and the first load operation and the second load instruction correspond to load operations from the same release group. By considering only load operations corresponding to load operations from the same release group, it is ensured that any dependencies among the load operations to be merged have been resolved. In other embodiments, the data processing apparatus is an out-of-order data processing apparatus. In these embodiments, any pair of load operations can be considered as potential candidates to be merged, provided their data dependencies have been resolved, and as previously discussed, the first load operation and the second load operation depend on a common operand.

[0044] In some implementations, the publishing circuit is further arranged to identify a third load operation based on a common operand, and the load circuit further includes a third address generation unit for generating a third address in response to the third load operation identified by the publishing circuit. The address comparison unit is arranged to compare a set of addresses including a first address, a second address, and a third address, and the load circuit is arranged to cause a merge lookup to be performed based on at least two addresses in the set of addresses when the address comparison unit determines that at least two addresses in the set of addresses differ from each other by less than a predetermined address range characteristic of the temporary storage device.

[0045] By arranging the publishing circuitry to identify more than two load operations, the chance of finding cases where a merge lookup can be determined is increased. As an illustrative, non-limiting example, there may be a first load operation, a second load operation, and a third load operation, all dependent on a common operand. When three address generation units have generated addresses for the three load operations, it can be determined that only the first address corresponding to the first load operation and the third address corresponding to the third load operation are within a predetermined address range; therefore, only the first and third load operations can be merged into a merge lookup. Alternatively, all three load operations may be within the predetermined address range, and a single merge lookup may be performed on all three load operations. It should be understood that these embodiments are not limited to three load operations, and in principle, any number of load operations dependent on a common operand can be identified and passed to the address generation units. Furthermore, the number of load operations passed to the loading circuitry need not be related to the number of address generation units. For example, if a first number of load operations are identified as dependent on a common operand and a second number of address generation units are provided (where the first number is greater than the second number), the load operations can be passed to the address generation units in batches, and the resulting addresses can be cached within the loading units to generate a merge load based on a subset of the first number of load operations. To give a concrete example, if six load operations are identified as depending on a common operand and three address generation units are provided, then the six load operations can be passed to the three address generation units in two sets of three load operations. The addresses generated by the three address generation units from the first set of three load operations can then be buffered until a second set of three addresses has been generated from the second set of three load operations.

[0046] In some implementations, the publishing circuit is further arranged to identify a fourth load operation based on a common operand. The load circuit also includes a fourth address generation unit for generating a fourth address in response to the fourth load operation identified by the publishing circuit. The set of addresses also includes the fourth address. The merge lookup is a first merge lookup. At least two addresses in the set of addresses are a first subset of the at least two addresses in the set of addresses. The load circuit is arranged to cause a second merge lookup to be performed based on the second subset of the at least two addresses in the set of addresses when the address comparison unit determines that the difference between the second subset of the at least two addresses in the set of addresses is less than a predetermined address range characteristic of the temporary storage device.

[0047] By arranging the loading circuitry to identify multiple merge lookups from a set of merged addresses, a flexible and efficient way of generating merge lookups is provided. It should be understood that these implementations are not limited to four load operations and four address generation units; in fact, as discussed above, any number of load operations can be considered regardless of the number of address generation units. Furthermore, it should be understood that the publishing circuitry is not limited to generating two merge lookups, and the publishing circuitry can be arranged to generate any number of merge lookups depending on the number of determinable lookup groups. Therefore, a second number of merge lookups can be generated from a first number of generated addresses, and assuming that each merge lookup requires combining at least two addresses, the maximum number of merge lookups expected will be half the number of generated addresses in the first number. Based on the previous example, if six load operations are identified as depending on a common operand and six addresses are generated using the techniques described herein, up to three merge lookups can be generated. For example, in the exemplary load addresses #1 to #6, a first merge lookup can be generated based on the determination that addresses #1 and #4 fall within a predetermined address range; a second merge lookup can be generated based on the determination that addresses #2 and #6 fall within a predetermined address range; and a third merge lookup can be generated based on the determination that addresses #3 and #5 fall within a predetermined address range. Alternatively, a first merge lookup can be generated based on the determination that addresses #1, #2, #3, and #6 all fall within a predetermined address range, and a second merge lookup can be generated based on the determination that addresses #4 and #5 fall within a predetermined address range. These specific examples are given for illustrative purposes only, and it should be understood that any combination of addresses generated based on any number of load operations can also be considered in the generation of merge lookups.

[0048] In some implementations, in response to the detection of an anomaly during a merge lookup, the data processing apparatus is arranged to signal the anomaly on the earliest load operation associated with the merge lookup. Thus, for example, when a micro-hierarchical anomaly occurs in a group of one or more merge looksups, the anomaly is reported on the earliest load where the anomaly is observed. If only a subset of merge loads in a group is affected by an anomaly (e.g., a fine-grained memory tag mismatch), the earliest load in the affected group will observe the anomaly.

[0049] In some embodiments, the data processing apparatus further includes a data multiplexing circuit for: retrieving a first data item corresponding to a first address from a first output cache line resulting from a cache access; and retrieving a second data item corresponding to a second address from a second output cache line. Once a merge lookup is performed in the data cache, the multiplexing circuit is used to retrieve the data item from the cache line. For example, if the merge lookup corresponds to two addresses falling within a single cache line of the data cache, the cache line is retrieved from the data cache and passed to the multiplexing circuit. The multiplexing circuit then retrieves the specified data item from the cache line based on the first and second addresses and passes the data item to a set of data registers specified by the corresponding first and second load operations. In some embodiments, in response to an anomaly detected during the retrieval of the first and second data items, the data processing apparatus is arranged to signal an anomaly on the earliest load operation affected by the anomaly.

[0050] At least some implementations provide a method for performing data processing, the method comprising the steps of: identifying a first load operation and a second load operation in a sequence of operations held in a release queue, based on the fact that a first load operation and a second load operation depend on a common operand and the availability of the common operand in a set of registers; generating a first address in response to the first load operation; generating a second address in response to the second load operation identified in the sequence of operations in the release queue; comparing the first address and the second address in a load unit; and causing a merge lookup to be performed in the local temporary storage of the load unit based on the first address and the second address when the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage.

[0051] At least some embodiments provide a data processing apparatus comprising: means for identifying a first load operation and a second load operation in a sequence of operations held in a release queue based on the first load operation and the second load operation depending on a common operand and the availability of the common operand in a set of registers; means for generating a first address in response to the first load operation; means for generating a second address in response to the second load operation; means for comparing the first address and the second address in a load unit; and means for causing a merge lookup to be performed in the local temporary storage of the load unit based on the first address and the second address when the difference between the first address and the second address is less than a predetermined address range characteristic of a local temporary storage.

[0052] Some specific implementation schemes will now be described with reference to the accompanying drawings.

[0053] Figure 1 A data processing apparatus 10, illustrating various examples of the present technology, is schematically shown. Provided Figure 1 The apparatus shown is intended to illustrate an exemplary context for performing the techniques disclosed herein. The apparatus includes data processing circuitry 12 that performs data processing operations on data items in response to a sequence of instructions executed thereon. These instructions are retrieved from memory 14 via an instruction cache 26 accessible to the data processing apparatus, and for this purpose, fetch circuitry 16 is provided in a manner familiar to those skilled in the art. Furthermore, the instructions retrieved by fetch circuitry 16 are passed to instruction decoder circuitry 18, which generates control signals arranged to control various aspects of the configuration and operation of the processing circuitry 12, register set 20, and load / store unit 22. Generally, the data processing circuitry 12 may be arranged in a pipelined manner, but its details are irrelevant to this technique. Those skilled in the art will recognize... Figure 1 This represents a general configuration, and for the sake of brevity only, further detailed descriptions are omitted here. (As in...) Figure 1 As can be seen, each of registers 20 includes a storage device for multiple data elements, allowing the processing circuitry to apply data processing operations to a specific data element within a specified register, or to a specified group of data elements (“vectors”) within a specified register. Data values ​​required by the data processing circuitry 12 during instruction execution, and data values ​​generated as a result of these data processing instructions, are written to and read from memory 14 via load / store unit 22, as will be described in further detail with reference to specific embodiments disclosed herein. It should also be noted that... Figure 1 The memory 14 in the document can generally be considered as an example of a computer-readable storage medium on which instructions of the present technology can be stored, typically as part of a predefined sequence of instructions (“program”) subsequently executed by processing circuitry. However, such programs can be accessed by processing circuitry from various sources, such as in RAM or ROM, via a network interface. This disclosure describes a new technique by which specific load instructions are jointly scheduled, and lookups that would otherwise be performed separately for each load instruction can be combined (or merged) to be performed as a single merged lookup if the addresses of the load instructions are sufficiently close. Further details relating to specific embodiments of the technology disclosed herein will be described below.

[0054] Figure 2AThe circuitry associated with the generation of merge lookups in some embodiments is illustrated schematically. The circuitry associated with the generation of merge lookups includes publishing circuitry 28, where decoded instructions are queued before being published for execution. As described above, the publishing queue can hold combinations of instructions, micro-operations (split instructions), and macro-operations (merge instructions). Generally, these are referred to herein as “operations” held in the publishing queue. In particular, publishing circuitry 28 needs to identify load operations that depend on common operands. Figure 2B Some components of the publishing circuit 28 are schematically shown, namely circuit 38 that performs operand comparisons and identification control circuit 42. Operand comparison circuit 38 compares operands associated with load operations in the publishing queue 40. Figure 2B In the example shown, load operations A and B are compared to determine whether they depend on a common operand. For example, such a comparison is determined based on the load operation's dependence on a common register value. In other words, if both operands A and B depend on a common register, and the value of the data stored in the common register is unaffected by other operations that may appear between A and B in the program sequence, then operands A and B will share a common operand. Once a pair of load operations within the release queue 40 has been identified based on their dependence on a common operand, the identification control circuit 42 determines when the operands on which these operations depend become available, and then allows these load operations to be sent to the load unit 22.

[0055] like Figure 2A As schematically shown, the loading unit includes a first address generation unit (AGU) 30, a second address generation unit (AGU) 32, and an address comparison unit 34. Address generation units 30 and 32 are each configured to generate an address based on an operand passed to the loading circuit. The specific implementation of the address generation unit can be any implementation known to those skilled in the art. The identification control circuit 42 within the publishing circuit 28 is configured to pass a first loading operation to the first address generation unit 30 and a second loading operation to the second address generation unit 32. The first address generation unit 30 generates a first address, which is passed to the address comparison unit 34, and the second address generation unit 32 generates a second address, which is passed to the address comparison unit 34. The address comparison unit 34 is arranged to compare the first address and the second address and determine whether the first address and the second address are within a predetermined address range. If the address comparison unit 34 determines that the first address and the second address are within the predetermined address range, a merge lookup is performed by passing one of the first address or the second address to the data storage device 36, which is a local temporary storage device. If the address does not fall within the predetermined address range, the loading circuit 22 is configured to perform a first lookup based on the earlier of the first loading operation and the second loading operation, and to perform a second lookup based on the later of the first loading operation and the second loading operation.

[0056] Figures 3A to 3D Various embodiments of the invention disclosed herein are illustrated schematically. In particular, Figure 3A The diagram shows: a release queue 40, in which operations are temporarily queued before release; a first address generation unit 30; a second address generation unit 32; an address comparison unit 340; a virtual addressing L1 data cache 360; a micro-translation back buffer (uTLB) 362; and a result multiplexing circuit 44. The operation of the release queue 40 and address generation units 30 and 32 has been described with reference to Figure 2 and is omitted here for brevity. The address comparison unit 340 is arranged to compare a first address and a second address and determine whether the difference between the first address and the second address is less than a predetermined size. In this embodiment, the predetermined size is the size of the cache line associated with the L1 data cache 360. In the illustrated example, the cache line size is 64B; however, this should be understood as an example and is not limiting. In particular, it will be apparent to those skilled in the art that the same technique can be applied to caches with 32B cache lines, 128B cache lines, or virtually any other size of cache line. If the address comparison circuit 340 determines that the difference between the first address and the second address is less than a predetermined size, the loading circuit causes a merge lookup to be performed in parallel in the virtual addressing L1 data cache 360 ​​and the uTLB 362. If a hit occurs in the L1 data cache or the micro-translation back buffer, the corresponding data is read out to the result multiplexing circuit 44.

[0057] Figure 3B Alternative embodiments of the invention disclosed herein are illustrated schematically. In particular, Figure 3BThe diagram shows: a release queue 40, in which operations are temporarily queued before release; a first address generation unit 30; a second address generation unit 32; an address comparison unit 342; a virtual addressing dual-port L1 data cache 364; a micro-translation backup buffer (uTLB) 362; and a result multiplexing circuit 44. The operation of the release queue 40 and address generation units 30 and 32 has been described with reference to Figure 2 and is omitted here for brevity. The address comparison unit 342 is arranged to compare a first address and a second address and determine whether the difference between the first address and the second address is less than a predetermined size. In this embodiment, the predetermined size is the granularity size of the translated data stored in the micro-translation backup buffer (uTLB) 362. In the illustrated example, the minimum page size is 4kB; however, this should be understood as an example and is not limiting. In particular, it will be apparent to those skilled in the art that the same technique can be applied regardless of the page size. If the address comparison circuit 342 determines that the difference between the first address and the second address is less than a predetermined size, the loading circuit causes a merge lookup to be performed in the uTLB 362. Additionally, the loading circuit is configured to perform the first lookup using the first port of the virtual addressing dual-port L1 data cache 364, and to perform a second lookup in parallel using the second port of the virtual addressing dual-port L1 data cache. It should be noted that the virtual addressing dual-port data cache can be replaced by a virtual addressing single-port data cache, such as... Figure 3A As shown. However, in this case, the first and second lookups will be performed sequentially in the L1 data cache, with the second lookup buffered in the buffer circuit while the first lookup is being performed. If a hit is found in the L1 data cache or the micro-translation backup buffer, the corresponding data is read out to the result multiplexing circuit 44. It should also be noted that although described separately, Figure 3A and 3B Examples may refer to a single implementation. That is, the address comparison circuit (described in these figures as a combination of 340 and 342) can be arranged to determine the difference between the first and second addresses, and trigger an event when the address is within the size of the L1 data cache line (e.g., 64B). Figure 3A The lookup process (i.e., merged parallel lookup in L1 cache and uTLB) is triggered when the address difference exceeds the L1 cache line size but is still within the minimum uTLB page size (e.g., 4kB). Figure 3B The lookup process (i.e., merge lookup in uTLB and two lookups in L1 data cache).

[0058] Figure 3C Another embodiment of the invention disclosed herein is illustrated schematically. In particular, Figure 3CThe diagram shows: a release queue 40, in which operations are temporarily queued before release; a first address generation unit 30; a second address generation unit 32; an address comparison unit 340; a physical index L1 data cache 366; a micro-translation back buffer (uTLB) 362; and a result multiplexing circuit 44. The operation of the release queue 40 and address generation units 30 and 32 has been described with reference to Figure 2 and is omitted here for brevity. The comparison unit 340 is arranged to compare a first address and a second address and determine whether the difference between the first address and the second address is less than a predetermined size. In this embodiment, the predetermined size is the size of the cache line associated with the physical index L1 data cache 366. In the illustrated example, the cache line size is 64B; however, this should be understood as an example and is not limiting. In particular, it will be apparent to those skilled in the art that the same technique can be applied to caches with 32B cache lines, 128B cache lines, or virtually any other size of cache line. If the address comparison circuit 340 determines that the difference between the first address and the second address is less than a predetermined size, the loading circuit causes a merge lookup to be performed in the micro-translation lookup buffer, and then performs a merge lookup in the physical index data cache 366 using the physical address obtained from the previous merge lookup in the micro-translation lookup buffer. If a hit exists in the L1 data cache or the micro-translation lookup buffer, the corresponding data is read out to the result multiplexing circuit 44.

[0059] Figure 3D Another embodiment of the invention disclosed herein is illustrated schematically. In particular, Figure 3DThe diagram shows: a release queue 40, in which operations are temporarily queued before release; a first address generation unit 30; a second address generation unit 32; an address comparison unit 342; a physical index dual-port L1 data cache 368; a micro-translation backup buffer (uTLB) 362; and a result multiplexing circuit 44. The operation of the release queue 40 and address generation units 30 and 32 has been described with reference to FIG2 and is omitted here for brevity. The comparison unit 342 is arranged to compare the first address and the second address and determine whether the difference between the first address and the second address is less than a predetermined size. In this embodiment, the predetermined size is the granularity size of the translated data stored in the micro-translation backup buffer (uTLB) 362. In the illustrated example, the minimum page size is 4kB; however, this should be understood as an example and is not limiting. In particular, it will be apparent to those skilled in the art that the same technique can be applied regardless of the page size. If the address comparison circuit 342 determines that the difference between the first address and the second address is less than a predetermined size, the loading circuit is arranged to cause a merged lookup to be performed in the uTLB 362 and a pair of further lookups to be performed in parallel in the physical index dual-port L1 data cache 368. Specifically, using the translated output from the uTLB 362 and the first address generated by the first address generation unit, a first lookup is performed using the first port of the physical index dual-port L1 data cache 368. Using the translated output from the uTLB 362 and the second address generated by the second address generation unit, a second lookup is performed using the second port of the physical index dual-port L1 data cache. It should be noted that the illustrated physical index dual-port data cache can be replaced by a physical index single-port data cache, such as... Figure 3C As shown. However, in this case, the first and second lookups will be performed sequentially in the L1 data cache, with the second lookup buffered in the buffer circuit while the first lookup is being performed. If a hit is found in the L1 data cache or the micro-translation backup buffer, the corresponding data is read out to the result multiplexing circuit 44. It should also be noted here that, although described separately, Figure 3C and Figure 3D Examples may refer to a single implementation. That is, the address comparison circuit (described in these figures as a combination of 340 and 342) can be arranged to determine the difference between the first and second addresses, and trigger an event when the address is within the size of the L1 data cache line (e.g., 64B). Figure 3C The lookup process (i.e., merging in the uTLB, followed by merge lookup in the L1 data cache) is triggered when the address difference exceeds the L1 data cache line size but is still within the minimum uTLB page size (e.g., 4kB). Figure 3D The lookup process (i.e., merge lookup in uTLB and two lookups in L1 data cache).

[0060] Figure 4 The process of performing a merge lookup according to some embodiments of the present technology is illustrated schematically. The process begins with a release queue 40, where operations 40(B) and 40(C) are identified as dependent on the result of operation 40(A). As shown with reference to FIG. 2, the release circuit 28 determines that operations 40(B) and 40(C) depend on a common operand (in this case, the contents of register x15), which is filled in response to operation 40(A). When register x15 in a set of registers 20 has been filled with the required operand, the release circuit 28 passes the first load operation 40(B) and the second load operation 40(C) to the first address generation unit 30 and the second address generation unit 32, respectively.

[0061] Address generation units 30 and 32 retrieve data values ​​from register x15 in register group 20 and the additional operands specified in the first load operation 40(B) and the second load operation 40(C). Address generation units 30 and 32 then generate a first address for the first load operation 40(B) and a second address for the second load operation 40(C). The first address and the second address are then forwarded to address comparison unit 34.

[0062] Address comparison unit 34 compares the most significant portion 400(A) of the first address with the most significant portion 402(A) of the second address. For the difference between the two addresses to be within a predefined range, the most significant portions of the addresses must be the same. Therefore, the comparison is performed by comparing these portions of the two addresses using comparator 404, which is provided here as a logical XNOR. The output of comparator 404, along with the two addresses 400 and 402, is passed to control logic unit 406. If comparator 404 indicates a match (i.e., determines that a merge lookup should be performed), control logic unit 406 retrieves either the most significant portion 400(A) of the first address or the most significant portion 402(A) of the second address and passes this information to cache 360 ​​to perform the merge lookup. However, if the control logic unit 406 determines that the difference between the two addresses is greater than a predetermined amount, that is, the most significant portion 400(A) of the first address is not equal to the most significant portion 402(A) of the second address, then the first lookup is performed using one of the first address 400 and the second address 402, while the second lookup based on the other of the first address 400 and the second address 402 is buffered so that it can be performed after the first lookup is completed.

[0063] Address comparison circuit 34 also passes the least significant portion 400(B) of the first address and the least significant portion 402(B) of the second address to multiplexing circuit 44 so that the required data item can be retrieved and returned when a merge lookup is performed. Once a merge lookup has been performed in data cache 360 ​​and the required data has been returned, the data is passed to multiplexing circuit 44. Multiplexing circuit uses the least significant portion 400(B) of the first address and the least significant portion of the second address to retrieve the data item specified in the merge lookup. Finally, multiplexing circuit passes the output data to the registers in the set of registers 20 specified in the first load operation 40(B) and the second load operation 40(C). Note that when control logic unit 406 determines that separate first and second lookups must be performed, the normal cache lookup and data return mechanism (not in...) is used. Figure 4 (As explicitly shown in A) Return the individual results of these first and second lookups.

[0064] Figure 4 An exception circuit 45 is also shown, which can be associated with the multiplexing circuit 44 and is configured such that if an exception is triggered during the extraction of data items required by the first and second loading operations, the exception is signaled as being associated with the later of the two operations.

[0065] Figure 5A Further details of the operation of an address comparison circuit 34 according to some embodiments are schematically shown. The comparison circuit 34 determines whether a first address 410 and a second address 412 correspond to addresses that differ by less than two different predetermined amounts. Comparator 404(A) compares the most significant portion 410(A) of the first address with the most significant portion 412(A) of the second address. If the two portions 410(A) and 412(A) are the same, then the two addresses are determined to be within a first predetermined range. Comparator 404(B) compares the first and second most significant portions 410(A) and 410(B) of the first address with the first and second most significant portions 412(A) and 412(B) of the second address. If the compared portions are the same, then the two addresses are determined to be within a second predetermined range. The method of comparing addresses is non-limiting, and it will be apparent to those skilled in the art that alternative comparison methods can yield the same results. For example, a second comparator 404(B) may simply compare the second most significant portion 410(B) of the first address with the second most significant portion 412(B) of the second address. The address within the second address range can then be determined, for example, by performing a logical AND operation on the outputs of two comparators, 404(A) and 404(B).

[0066] As a specific example, each of addresses 410 and 412 is assumed to be a 32-bit address, and the first predetermined range is the size of the page table (assumed to be 4kB for illustrative purposes), and the second predetermined range is the size of the cache line (assumed to be 64B for illustrative purposes). It should be understood that these sizes are for illustrative purposes only, and any address size, page table size, and cache line size can be used in the techniques described herein. To determine whether the first address 410 is within the same page as the second address 412, the first 20 bits of the address are compared by a first comparator 404(A). It should be noted that if the comparison unit operates on virtual addresses, the number of bits in the most significant portion of the address space may be reduced accordingly. To determine whether the first address 410 is within the same cache line as the second address 412, the 26 most significant bits are subsequently compared by comparator 404(B) or a combination of comparators 404(A) and 404(B).

[0067] The comparator output, along with the least significant portion 410(C) of the first address and the least significant portion 412(C) of the second address, is passed to control logic unit 406, which includes a first-in-first-out (FIFO) buffer 408. If it is determined that a merge lookup will be performed in the data cache, a merge lookup is generated in parallel with or after the lookup in the microtranslation lookup buffer 362 and passed to the data cache. If it is determined that a merge lookup will not be performed in the data cache (360) and / or will not be performed in the microtranslation lookup buffer 362, a first lookup is performed using one of the first address 410 and the second address 412, and a second lookup is performed using the other of the first address 410 and the second address 412, and the second lookup is buffered in FIFO 408.

[0068] Figure 5B Another feature that may be provided in loading unit 22 is shown, in which a lookup control circuit 50 is provided to control the generated lookups (i.e., individual lookups when the first and second addresses generated by address generation units 30 and 32 differ too much, and merged lookups when they are sufficiently close). The lookup control circuit 50 maintains information 52 relating to the operations for which lookups have been generated (whether merged or not), and when an exception is triggered during a merged lookup, the lookup control circuit 50 signals the exception as being associated with the earliest of the operations served by the merged lookup.

[0069] Figure 6A and Figure 6B Further details of some embodiments of the invention are illustrated schematically. In particular, Figure 6AThe illustration shows a case where the data cache is a dual-port physical index cache 368. A first address 400 includes a most significant portion 400(A) and a least significant portion 400(B). A second address 402 includes a most significant portion 402(A) and a least significant portion 402(B). A comparator 404 determines whether the first and second addresses correspond to addresses within a predetermined address range. In this case, the predetermined address range corresponds to the size of the page table in the uTLB 362. The comparator can function in any form, such as as described herein. Similarly, the size of the page table is unrestricted and can correspond to the size of any implemented page table. The output of comparator 404, along with addresses 400 and 402, is input to control logic unit 406, which determines whether to perform a merge lookup. When the difference between the first and second addresses is found to be within the size range of the page table in the uTLB 362, a virtual most significant portion of one of the addresses (here, the most significant portion 400(A) of the first address) is forwarded to the uTLB 362 to perform a single (merged) lookup. Therefore, the corresponding highest valid portion 600(A) generated applies to both the first address and the second address. Thus, the first address translated via uTLB includes the highest valid portion 600(A) and the least valid portion 400(B), and the translated second address includes the same highest valid portion 600(A) and least valid portion 402(B). Figure 6A In the example, with the L1 data cache 368 being a dual-port, the two generated physical addresses can be received in parallel by the data cache 368 and a parallel lookup can be performed.

[0070] Figure 6B It shows Figure 6A A variant of the implementation scheme, in which the data cache is a single-port physical index cache 620. Figure 6B In the example, the construction and operation of the initial component, as well as the structure of the first and second input addresses, are consistent with the above reference. Figure 6A The same applies to the discussion. Therefore, the first address (400(A) and 400(B)), the second address (402(A) and 402(B)), comparator 404, control logic unit 406, and uTLB 362 will not be described again here. Thus, as shown in Figure 6, the virtual most significant portion of one of the addresses (here, the most significant portion 400(A) of the first address) is forwarded to uTLB 362 to perform a single (merged) lookup. Therefore, the corresponding physical most significant portion 600(A) generated applies to both the first address and the second address. Therefore, the first address translated by uTLB includes the most significant portion 600(A) and the least significant portion 400(B), and the translated second address includes the same most significant portion 600(A) and the least significant portion 402(B). Figure 6B In the example, L1 data cache 368 is a single port, so the two generated physical addresses must be processed sequentially. For this purpose, a FIFO buffer 610 is provided, such that while the first of the two generated physical addresses is the first lookup object in data cache 620, the second of the two generated physical addresses is buffered and subsequently becomes the second lookup object in data cache 620.

[0071] Figure 7 The functionality of a loading unit according to some embodiments is schematically illustrated. The loading unit includes multiple address generation units 700, 702, 704, and 706 to generate addresses for a first loading operation, a second loading operation, a third loading operation, and a fourth loading operation. The generated addresses are compared by a series of comparators 710, 712, 714, 716, 718, and 720, which are schematically shown as logic XNOR gates. However, it will be apparent to those skilled in the art that any method capable of comparing addresses can be used to generate a set of outputs determining which addresses are within a predetermined range. For example, one could use... Figure 4 and / or Figure 5A The comparator circuit shown.

[0072] Comparator 710 determines whether the third and fourth addresses are within a predetermined range. Comparator 712 determines whether the second and fourth addresses are within a predetermined range. Comparator 714 determines whether the second and third addresses are within a predetermined range. Comparator 716 determines whether the first and fourth addresses are within a predetermined range. Comparator 718 determines whether the first and third addresses are within a predetermined range. Finally, comparator 720 determines whether the first and second addresses are within a predetermined range. The outputs of this set of comparators, along with the addresses generated by the first address generation unit 700, the second address generation unit 702, the third address generation unit 704, and the fourth address generation unit 706, are fed to the control logic unit 722. The control logic unit 722 determines which addresses (if any) can be merged into a merge lookup and can generate and store merge lookups according to the requirements in FIFO 708. For example, if the first and second addresses are within a predetermined address range, a first merge lookup (ML1) 708(A) can be generated. If the third and fourth addresses are within a predetermined address range, a second merge lookup (ML2) 408(B) can be generated. Merge lookups can be dispatched to the micro-translation back buffer and / or L1 data cache, or they can be stored in a FIFO while further merge lookups occur.

[0073] It should be understood that, regarding Figure 7The described logic is not limited to four address generation units, and any number of address generation units can be provided. The number of addresses included in the merge lookup can also be any number greater than one. For example, if eight address generation units are provided, up to four merge looksup can be generated via control logic unit 722. Similarly, if a single merge lookup is generated only based on the addresses generated by the address generation units, a FIFO buffer can be used to store corresponding looksup that do not form part of the merge lookup. Figure 7 In a specific example, if the first and fourth addresses are determined to be within a predetermined address range, a first merge lookup will be generated. However, if the second and third addresses are not found to be within the predetermined address range of any other addresses, a corresponding first lookup will be generated and stored in FIFO 708 corresponding to the second address, and a second lookup will be generated and stored in FIFO 708 corresponding to the third address. Therefore, in this example, a first merge lookup corresponding to the first and fourth addresses is generated, and two non-merge lookups corresponding to the second and third addresses are also generated.

[0074] Figure 8 A series of steps, performed according to some embodiments of the present invention, are shown to determine whether a merge lookup should be performed. The process begins at step S800, where it is determined whether a first operation is a load operation dependent on operands. If yes, the process proceeds to step S802; if no, the process proceeds to step S818, where a new pair of operations is selected before the process returns to step S800. In step S802, it is determined whether a second operation is a load operation dependent on the same operands as the first load operation. If yes, the process proceeds to step S804; if no, the process proceeds to step S818, where a new pair of operations is selected before the process returns to step S800.

[0075] In step S804, the first load operation and the second load operation are forwarded to the first address generation unit and the second address generation unit. In step S806, the first address generation unit generates a first address based on the first load operation, and the second address generation unit generates a second address based on the second load operation. In step S808, the comparison unit compares the first address and the second address. In step S810, it is determined whether the first address and the second address are sufficiently close. In other words, it is determined whether the first address and the second address correspond to addresses within a predetermined address range. If not, the process proceeds to step S814. If yes, the process proceeds to step S812, where a merge lookup is performed in the micro-TLB and / or cache. Based on the above description of the foregoing figures, it will be understood that whether a merge lookup is performed on both the micro-TLB and / or the cache depends on the difference between the first address and the second address, the relative cache line size in the cache, and the minimum page size used in the micro-TLB. Finally, the process returns to step S818, where a new pair of operations is selected before the process returns to step S800. Reconsider step S814, which is reached when it was determined in step S810 that the first address and the second address are not within a predetermined range of the address space. In step S814, a first lookup is performed based on one of the first address and the second address. In step S816, a second lookup is performed based on the other of the first address and the second address. The process then proceeds to step S818, where a new pair of operations is selected before the process returns to step S800.

[0076] Figure 9 A sequence of steps according to some embodiments is shown. In step S900, a first address is generated in response to a first load operation identified in the operation sequence retained in the release queue. In step S902, a second address is generated in response to a second load operation identified in the operation sequence retained in the release queue. In step S904, the first address and the second address are compared in the load unit. In step S906, when the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device, a merge lookup is performed in the local temporary storage device based on the first address and the second address.

[0077] In summary, a data processing apparatus and a method for operating such a data processing apparatus are disclosed. The publishing circuit buffers an operation before execution until the operand required for the operation is available in a set of registers. The first load operation and the second load operation are identified in the publishing circuit when both a first load operation and a second load operation depend on a common operand, and when that common operand is available in a set of registers. The loading circuit has a first address generation unit for generating a first address for the first load operation and a second address generation unit for generating a second address for the second load operation. An address comparison unit compares the first address and the second address. The loading circuit is arranged such that when the address comparison unit determines that the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device, a merge lookup is performed in the local temporary storage device storing copies of data values ​​from the memory.

[0078] In this application, the phrase "configured as..." is used to mean that the elements of the device have a configuration capable of performing the defined operations. In this context, "configuration" means the arrangement or manner of interconnection of hardware or software. For example, the device may have dedicated hardware that provides the defined operations, or a processor or other processing device may be programmed to perform the function. "Configured as" does not mean that the elements of the device need to be changed in any way to provide the defined operations.

[0079] While exemplary embodiments have been described in detail herein with reference to the accompanying drawings, it should be understood that the invention is not limited to those precise embodiments, and various changes, additions, and modifications can be made therein by those skilled in the art without departing from the scope of the invention as defined by the appended claims. For example, features of dependent claims may be combined with features of independent claims in various ways without departing from the scope of the invention.

Claims

1. A data processing apparatus, the data processing apparatus comprising: Execution circuitry, the execution circuitry being configured to perform data processing operations in response to a sequence of instructions; A release circuit is configured to buffer operations generated by the instruction sequence prior to execution until the operands required by the operations are available in a set of registers, wherein the release circuit is arranged to identify the first load operation and the second load operation based on the first load operation and the second load operation depending on a common operand and the availability of the common operand in the set of registers; Loading circuitry, the loading circuitry being configured to load at least one operand into the set of registers in response to a load instruction in the instruction sequence, wherein the loading circuitry further comprises: A first address generation unit is configured to generate a first address in response to the first load operation recognized by the publishing circuit. A second address generation unit, configured to generate a second address in response to the second load operation recognized by the publishing circuit; and An address comparison unit, configured to compare the first address and the second address; and A local temporary storage device for storing copies of data values ​​from a memory, wherein the loading circuit is arranged to cause a merge lookup to be performed in the local temporary storage device based on the first address and the second address when the address comparison unit determines that the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device.

2. The data processing apparatus according to claim 1, wherein when the address comparison unit determines that the difference between the first address and the second address is greater than the predetermined address range, the loading circuit is arranged to cause a first lookup to be performed on one of the first loading operation and the second loading operation, and to cause a second lookup to be performed on the other of the first loading operation and the second loading operation.

3. The data processing apparatus according to claim 1 or 2, wherein the merge lookup includes using one of the first address and the second address.

4. The data processing apparatus according to claim 1, wherein the local temporary storage device is a first local temporary storage device and the data processing circuit further includes a second local temporary storage device. One of the first local temporary storage device and the second local temporary storage device is a translation backup buffer, which is used to store translation data to translate the input virtual address into the output physical address.

5. The data processing apparatus according to claim 4, wherein the other of the first local temporary storage device and the second local temporary storage device is a data cache.

6. The data processing apparatus according to claim 5, wherein the predetermined address range corresponds to the cache line size of the data cache.

7. The data processing apparatus according to claim 6, wherein the data cache is a virtual index cache, and The data processing device is configured to perform the merge lookup in parallel with the translation backup buffer, in the data cache.

8. The data processing apparatus according to claim 6, wherein the data cache is a physical index cache, and The data processing device is configured to perform the merge lookup in the data cache using the physical address obtained from a previous merge lookup in the translation backup buffer.

9. The data processing apparatus according to claim 5, wherein the predetermined address range corresponds to the minimum range of the address space in which the translation backup buffer stores the translated data.

10. The data processing apparatus according to claim 9, wherein the data cache is a virtual index cache, and The data processing device is configured to perform a pair of further lookups in parallel within the data cache, and a merge lookup is performed in the translation backup buffer.

11. The data processing apparatus of claim 9, wherein the data cache is a physical index cache, and The data cache is configured to use the output of the merge lookup in the translation back buffer to perform a pair of further lookups in the data cache.

12. The data processing apparatus according to claim 10 or claim 11, wherein the data cache includes a first port and a second port, and The data processing device is configured to perform the pair of further lookups in parallel via the first port and the second port.

13. The data processing apparatus of claim 10 or claim 11, wherein the data cache includes buffering circuitry associated with a buffered data lookup request, and the data processing apparatus is arranged to cause the pair of further lookups to be performed sequentially as a first lookup and a second lookup, and to buffer the second lookup in the buffering circuitry while the first lookup is being performed.

14. The data processing apparatus according to any one of claims 5 to 11, wherein in response to a miss in at least one of the data cache and the translation backup buffer, the loading circuit is arranged to forward the merge lookup to the next level of the memory hierarchy.

15. The data processing apparatus according to any one of claims 5 to 11, wherein in response to a miss in at least one of the data cache and the translation back buffer, the loading circuit is arranged to forward the address of the earlier of the first loading operation and the second loading operation to the next level of the memory hierarchy.

16. The data processing apparatus according to claim 1 or 2, wherein the data processing apparatus is an ordered data processing apparatus, and The first loading operation and the second loading operation correspond to loading operations from the same release group.

17. The data processing apparatus according to claim 1 or 2, wherein the data processing apparatus is an out-of-order data processing apparatus.

18. The data processing apparatus of claim 1 or 2, wherein the publishing circuit is further arranged to identify a third load operation based on the common operand, and the load circuit further includes a third address generation unit for generating a third address in response to the third load operation identified by the publishing circuit. The address comparison unit is configured to compare a set of addresses including the first address, the second address, and the third address. Furthermore, the loading circuit is arranged such that when the address comparison unit determines that at least two addresses in the set of addresses differ by less than the predetermined address range characteristic of the temporary storage device, it causes the merge lookup to be performed based on at least two addresses in the set of addresses.

19. The data processing apparatus according to claim 18, wherein The publishing circuit is also configured to identify the fourth loading operation based on the common operand. The loading circuit further includes a fourth address generation unit, which generates a fourth address in response to the fourth loading operation identified by the publishing circuit. The set of addresses also includes the fourth address. The merge lookup is the first merge lookup. At least two addresses in the set of addresses are a first subset of at least two addresses in the set of addresses, and The loading circuit is arranged such that when the address comparison unit determines that the difference between a second subset of at least two addresses in the set of addresses is less than the predetermined address range characteristic of the temporary storage device, a second merge lookup is performed based on the second subset of at least two addresses in the set of addresses.

20. The data processing apparatus of claim 1 or 2, wherein in response to an anomaly detected during a merge lookup, the data processing apparatus is configured to signal the anomaly on the earliest load operation associated with the merge lookup.

21. The data processing apparatus according to claim 1 or 2, further comprising a data multiplexing circuit, the data multiplexing circuit being used for: Extract the first data item corresponding to the first address from the first output cache line obtained from the cache access; and Extract the second data item corresponding to the second address from the second output cache line.

22. The data processing apparatus of claim 21, wherein in response to an anomaly detected during the extraction of the first data item and the second data item, the data processing apparatus is arranged to signal the anomaly on the earliest loading operation affected by the anomaly.

23. A method for performing data processing, the method comprising the following steps: The first load operation and the second load operation are identified from the sequence of operations retained in the release queue, based on the fact that the first load operation and the second load operation depend on a common operand and the availability of the common operand in a set of registers; A first address is generated in response to the first loading operation; In response to the second load operation identified in the operation sequence in the release queue, a second address is generated; Compare the first address and the second address in the loading unit; as well as When the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device, a merge lookup is performed in the local temporary storage device of the loading unit based on the first address and the second address.

24. A data processing apparatus, the data processing apparatus comprising: A means for identifying the first load operation and the second load operation in a sequence of operations held in a release queue based on the fact that the first load operation and the second load operation depend on a common operand and the availability of the common operand in a set of registers; A means for generating a first address in response to the first load operation; A means for generating a second address in response to the second load operation; A means for comparing the first address and the second address in the loading unit; and A means for causing a merge lookup to be performed in the local temporary storage device of the loading unit based on the first address and the second address when the difference between the first address and the second address is less than a predetermined address range characteristic of the local temporary storage device.

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