Updating a correction read voltage offset in non-volatile random access memory

Abstract

According to a method, a computer-implemented method includes: calibrating a given page in a block using a first calibration scheme (606) by calculating a first number of independent read voltage offset values ​​for the given page. An attempt is made to read the calibrated given page (608), and in response to determining that an error correction code failure occurred during the attempt to read the calibrated given page, the given page in the block is recalibrated using a second calibration scheme (612). The second calibration scheme is configured to calculate a second number of independent read voltage offset values ​​for the given page. An attempt is also made to read the recalibrated given page (614). In response to determining that an error correction code failure did indeed occur during the attempt to read the recalibrated given page, one or more instructions (618) are sent for relocating data stored in the given page.

Description

BACKGROUND

[0001] The present invention relates to data storage systems, and more specifically, the present invention relates to updating a correct read voltage offset value for a memory block in a non-volatile random access memory (NVRAM).

[0002] NVRAM is a random access memory that retains information stored thereon even after power is turned off, and includes a variety of different forms. Using flash memory as an example, the performance characteristics of a conventional NAND flash-based solid state drive (SSD) are fundamentally different from those of a traditional hard disk drive (HDD). Data in a conventional SSD is typically organized in pages of 4, 8, or 16 KB size. In addition, page read operations in an SSD are typically an order of magnitude faster than write operations, and the latency does not depend on the current location of the operation nor on the previous location of the operation.

[0003] The raw bit error rate (RBER) of a flash memory block will typically increase over time due to additional program / erase (P / E) cycles, charge leakage over time (i.e., data retention), and additional charge placed in the cell by a read or program operation (i.e., read or program disturb errors, respectively). Typically, a flash memory block is retired when any page in the block exhibits a codeword that reaches a page retirement error count limit. This limit is typically set to be implemented in conjunction with an appropriate error correcting code (ECC) such that the uncorrectable bit error rate (UBER) after applying the ECC to the flash memory block is set to be similar to the UBER in a traditional hard disk drive, e.g., approximately 10 -15 but can be more or less.

[0004] Block calibration refers to an algorithm that adjusts the read voltage, and block calibration has been shown to significantly improve RBER, and thus endurance and retention, particularly for enterprise class flash systems that use modern three-dimensional (3-D) triple level cell (TLC) or quad level cell (QLC) NAND flash. Previous attempts to maintain effective memory performance typically include checking the read voltage of each memory block in a scan fashion or through a read voltage shift algorithm that tracks and corrects the read voltage depending on how the threshold voltage distribution changes due to cycling or retention or other disturb effects.

[0005] Ideally, the read voltage for each page in a block of memory is updated individually. However, as the storage capacity of memory increases, the amount of storage consumed by maintaining a set of read voltage offset values for each page in each block of memory also increases, depending on the number of read voltages associated with reading a given page. For example, progressing from 3 bits per cell in TLC NAND flash to 4 bits per cell in QLC NAND flash, each block implements 16 threshold voltage levels (instead of 8 in TLC) and 15 different read voltages (instead of 7 in TLC) to read any page included therein. Depending on the page type (e.g., lower, upper, extra, top), a subset of those 15 read voltages is used to read a given page. Furthermore, as vertical stacking and process technology improves, the number of layers in each new generation of 3-D NAND flash also increases. Subsequently, the number of pages in each block also increases. For example, current 3-D QLC NAND flash can have more than 90 layers and each block can have more than 4000 pages. Thus, if all of these 15 different read voltages in 3-D QLC NAND are calibrated independently (or individually), the amount of metadata involved in storing a single set of read offset values for each page or group of pages in a block and the number of calibration reads per page significantly increases.

[0006] As the storage capacity of memory continues to increase, the reliability issues associated with memory also increase. Thus, in addition to the number of read voltage offset values associated with each page in each block of memory increasing, conventional calibration engines also experience an increase in the amount of processing overhead caused by the decreased reliability of memory. SUMMARY

[0007] According to one method, a computer-implemented method includes, for each page in a block of memory: calibrating a given page in the block using a first calibration scheme. The first calibration scheme is configured to compute a first number of individual read voltage offset values and a first number of common read voltage offset values for pages in a block of memory. Attempting to read the calibrated given page, and in response to determining that an error correction code failure occurs when attempting to read the calibrated given page, recalibrating the given page in the block using a second calibration scheme. The second calibration scheme is configured to compute a second number of individual read voltage offset values and a second number of common read voltage offset values for pages in a block of memory. Further, the first number of individual read voltage offset values is less than the second number of individual read voltage offset values. Attempting to read the recalibrated given page as well. In response to determining that an error correction code failure does occur when attempting to read the recalibrated given page, sending one or more instructions to relocate data stored in the given page.

[0008] In some methods, calibrating a given page in a block using a first calibration scheme includes determining one or more read voltages associated with a page type corresponding to the given page, and determining one or more existing read voltage offset values corresponding to the one or more read voltages. A correction offset is calculated for each existing read voltage offset value, and the existing read voltage offset values are updated using the correction offsets. In other methods, calibrating a given page in a block using a second calibration scheme includes determining one or more read voltages associated with a page type corresponding to the given page, and determining one or more existing read voltage offset values corresponding to the one or more read voltages. A correction offset is calculated for each existing read voltage offset value, and the existing read voltage offset values are updated using the correction offsets.

[0009] As such, different types of calibration schemes can be more desirable for different situations, where a particular calibration scheme indicates how a page will be calibrated in practice. For example, a calibration scheme involving the computation of common read voltage offset values for each subset of read voltages associated with a corresponding page type in a word line involves less computational overhead and computational delay as compared to a calibration algorithm involving the computation of common read voltage offset values for only a portion of read voltages in a word line and independent voltage offset values for the remaining read voltages in the word line. Despite the additional computational overhead and computational delay associated with a calibration algorithm involving the computation of common read voltage offset values for only a portion of read voltages in a word line and independent voltage offset values for the remaining read voltages in the word line, increased read performance is also achieved due to the additional accuracy.

[0010] Accordingly, the various methods included herein can improve the operation of a memory and / or memory controller by significantly reducing calibration overhead while also ensuring efficient performance of the memory. These improvements can be achieved at least in part as a result of implementing a first calibration scheme during nominal operation and implementing a second calibration scheme on-demand in the event of an error recovery mode. While the second calibration scheme can achieve more accurate calibration results as compared to the first calibration scheme, the first calibration scheme produces less calibration overhead relative to implementing the second calibration scheme as a result. Thus, by selectively implementing the second calibration scheme, performance is improved while also ensuring advantageous memory management.

[0011] According to another method, a computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and / or executable by a processor to cause the processor to, for each page in a block of memory: perform the aforementioned method.

[0012] According to another method, a system includes: a plurality of NVRAM blocks configured to store data; a processor; and logic integrated with and / or executable by the processor. The logic is configured to perform the aforementioned method for each page of one of the blocks.

[0013] Other aspects and methods of the invention will become apparent from the following detailed description, which, when taken in conjunction with the accompanying drawings, illustrates the principles of the invention by way of example. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of a non-volatile memory card based on one method.

[0015] Figure 2 This is a schematic diagram of a data storage system architecture based on a particular method.

[0016] Figure 3 It is based on a system diagram of a method.

[0017] Figure 4A It is based on a conceptual diagram of a method that includes block-strip and page-strip.

[0018] Figure 4B It is a partial perspective view of a 3-D non-volatile memory structure based on a method.

[0019] Figure 5 This is a graph showing the threshold voltage shift phenomenon according to one method.

[0020] Figure 6A It is based on a method flowchart.

[0021] Figure 6B It is based on a method flowchart.

[0022] Figure 6C It is based on a method Figure 6A A flowchart of one of the sub-procedures in the method.

[0023] Figure 7A This is a table showing the different page types and their corresponding (multiple) read voltages according to a method.

[0024] Figure 7B This is a table showing the different page types and their corresponding (multiple) read voltages according to a method.

[0025] Figure 7C This is a table showing the read voltage offset values ​​according to a metadata structure based on a method.

[0026] Figure 7DThis illustrates how metadata is mapped to a table with a corresponding corrected offset, according to a particular method.

[0027] Figure 7E This illustrates how metadata is mapped to a table with a corresponding corrected offset, according to a particular method.

[0028] Figure 8A It is a representative view of a calibration scheme performed according to a method.

[0029] Figure 8B This is a representative view of the stored read voltage offset values ​​based on an example in use.

[0030] Figure 9 It is based on a network architecture of one method.

[0031] Figure 10 It is based on a method that can be used with Figure 9 A representative hardware environment associated with the server and / or client.

[0032] Figure 11 This is a schematic diagram of a hierarchical data storage system based on a method. Detailed Implementation

[0033] The following description is intended to illustrate the general principles of the invention and not to limit the inventive concepts claimed herein. Furthermore, the specific features described herein can be used in a variety of possible combinations and permutations with other described features.

[0034] Unless otherwise expressly defined herein, all terms shall be given the broadest possible interpretation, including the meaning implied in the specification and the meaning as understood by those skilled in the art and / or as defined in dictionaries, papers, etc.

[0035] It should also be noted that, as used in the specification and appended claims, unless otherwise stated, the singular forms “a,” “an,” and “the” include plural objects. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0036] The following description discloses several methods for data storage systems, their operation, and / or components. It should be understood that the various methods described herein can be implemented using various storage media, including, for example, NVRAM technologies such as NAND flash memory, NOR flash memory, phase-change memory (PCM), magnetoresistive RAM (MRAM), and resistive RAM (RRAM). For the purpose of providing context and to assist the reader only, various methods may be described with reference to one type of non-volatile memory. This is done by way of example only and should not be considered as limiting the invention as defined in the claims.

[0037] In a general approach, a computer-implemented method includes, for each page in a memory block: calibrating a given page in the block using a first calibration scheme. The first calibration scheme is configured to calculate a first number of independent read voltage offset values ​​and a first number of common read voltage offset values ​​for the pages in the memory block. An attempt is made to read the calibrated given page, and in response to determining that an error correction code failure occurs during the attempt to read the calibrated given page, the given page in the block is recalibrated using a second calibration scheme. The second calibration scheme is configured to calculate a second number of independent read voltage offset values ​​and a second number of common read voltage offset values ​​for the pages in the memory block. Furthermore, the first number of independent read voltage offset values ​​is less than the second number of independent read voltage offset values. An attempt is also made to read the recalibrated given page. In response to determining that an error correction code failure does indeed occur during the attempt to read the recalibrated given page, one or more instructions are sent to relocate data stored in the given page.

[0038] In another general approach, the computer program product includes a computer-readable storage medium having program instructions embodied therein. These program instructions are readable by a processor and / or executable by a processor to cause the processor to perform the aforementioned methods for each page in the memory block.

[0039] In yet another general approach, a system includes: a plurality of NVRAM blocks configured to store data; a processor; and logic integrated with and / or executable by the processor. The logic is configured to perform the aforementioned method for each page of one of the blocks.

[0040] Figure 1 A memory card 100 according to one method is shown. It should be noted that although the memory card 100 is depicted as an exemplary non-volatile data storage card in this method, various other types of non-volatile data storage cards may be used in the data storage system according to alternative methods. Therefore, the structure and / or components of the memory card 100 are not intended to limit the invention, but are presented as non-limiting examples.

[0041] Furthermore, as an alternative, this memory card 100 may be implemented in combination with features from any other methods listed herein, such as those described with reference to other figures. However, this memory card 100 and other memory cards presented herein can be used in various applications and / or in arrangements that may or may not be specifically described in the illustrative methods listed herein. Moreover, the memory card 100 presented herein can be used in any desired environment.

[0042] Continue to refer to Figure 1 The memory card 100 includes a gateway 102, a general-purpose processor (GPP) 112 (such as an ASIC, FPGA, CPU, etc.) connected to a GPP memory 114 (which may include RAM, ROM, battery-supported DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, etc., or combinations thereof), and multiple memory controllers 108, which in this example include flash memory controllers. Each memory controller 108 is connected via channel 106 to multiple NVRAM memory modules 104 (which may include NAND flash memory or other non-volatile memory types such as those listed above).

[0043] According to various methods, one or more of the controllers 108 may be or include one or more processors and / or any logic for controlling any subsystem of the memory card 100. For example, controller 108 typically controls the functions of the NVRAM memory module 104, such as data writing, data recycling, data reading, etc. Controller 108 may operate using logic known in the art as well as any logic disclosed herein, and therefore may be considered, in various methods, as a processor for any description of the non-volatile memory included herein.

[0044] Furthermore, controller 108 can be configured and / or programmable to execute or control some or all of the methods presented herein. Therefore, controller 108 can be considered to be configured to perform various operations through logic programmed into one or more chips, modules, and / or blocks; software, firmware, and / or other instructions available for one or more processors, and combinations thereof.

[0045] Still referencing Figure 1 Each memory controller 108 is also connected to a controller memory 110, which preferably includes a cache that replicates the non-volatile memory structure according to the various methods described herein. However, depending on the desired method, the controller memory 110 may be battery-supported DRAM, phase-change memory PC-RAM, MRAM, STT-MRAM, or a combination thereof.

[0046] As previously mentioned, depending on the desired approach, memory card 100 can be implemented in various types of data storage systems.Figure 2 A data storage system architecture 200 according to an exemplary method is shown, but it is by no means intended to limit the invention. Furthermore, it should be noted that... Figure 2 The data storage system 220 may include in Figure 1 The various components found in the method.

[0047] See Figure 2 The data storage system 220 includes multiple interface cards 202 configured to communicate with one or more processor systems 201 via I / O interconnects 204. The data storage system 220 may also include one or more independent redundant array of disks (RAID) controllers 206 configured to control data storage in multiple non-volatile data storage cards 208. The non-volatile data storage cards 208 may include NVRAM, flash memory cards, RAM, ROM, and / or some other known types of non-volatile memory.

[0048] I / O interconnect 204 may include any known communication protocol, such as Fibre Channel (FC), Ethernet FC (FCoE), Infiniband, Internet Small Computer System Interface (iSCSI), Transmission Control Protocol / Internet Protocol (TCP / IP), Fast Peripheral Component Interconnect (PCIe), and / or any combination thereof.

[0049] The RAID controller 206 in the data storage system 220 can execute a parity scheme similar to that used in RAID-5, RAID-6, and RAID-10, or some other suitable parity scheme that a person skilled in the art will understand upon reading this specification.

[0050] Each processor system 201 includes one or more processors 210 (e.g., CPU, microprocessor, etc.) and local data memory 211 (e.g., ... Figure 10 RAM 1014, Figure 10 (ROM 1016, etc.) and I / O adapter 218 configured to communicate with data storage system 220.

[0051] Refer again Figure 1 Memory controller 108 and / or other controllers described herein (e.g., memory controller 108 and / or other controllers described herein). Figure 2 The RAID controller 206 is capable of performing various functions on the stored data according to the desired method. Specifically, the storage controller may include logic configured to perform any one or more of the following functions, which are by no means intended to be an exclusive list. In other words, depending on the desired method, the logic of the storage system may be configured to perform additional or alternative functions, as will be understood by those skilled in the art upon reading this specification.

[0052] garbage collection

[0053] Garbage collection in the context of the SSD memory controller described herein may include the process of identifying data blocks to be reclaimed for future use and relocating all pages still valid within them. Furthermore, depending on the specific controller and / or the corresponding garbage collection operation unit, logical erase blocks (LEBs) may be identified for reclamation and / or relocation. Typically, one LEB corresponds to one block stripe, but alternative implementations may consider constructing a fixed number of block stripes with LEBs.

[0054] A physical "block" represents the smallest unit of non-volatile memory (e.g., NAND flash) that can be erased and is thus ready to be written to. However, a typical garbage collection operation unit is usually multiple physical blocks of non-volatile memory, and is also referred to here as a LEB. This is because parity information, similar to RAID, is added to the LEB. Therefore, in the event of a page or block failure, data can only be reconstructed if all blocks in the LEB still retain data. Thus, once all still valid data from all blocks in the LEB has been successfully relocated to a new location, individual blocks from the garbage collection unit can only be erased individually or as a single unit. Therefore, a complete garbage collection unit is garbage collected as a single unit. Furthermore, the size of the LEB directly affects the write amplification caused by garbage collection. The larger the LEB, the greater the likelihood that irrelevant data is stored together in the LEB, and therefore more LEB data may have to be relocated during garbage collection.

[0055] Typically, blocks from different chips and / or flash channels are grouped together, allowing blocks from the same group to be read or written in parallel, thus increasing the total bandwidth. The two methods mentioned above can also be combined, using blocks from different flash channels that can be accessed in parallel to form RAID stripes.

[0056] It should also be noted that an LEB can include any number of physical memory blocks as physical erase units. Furthermore, organizing memory blocks as LEBs not only allows for the addition of RAID-like parity protection schemes between memory blocks from different memory chips, memory planes, and / or channels, but also allows for significant performance enhancements through greater parallelism. For example, multiple non-volatile memory blocks can be grouped together in a RAID stripe. Those skilled in the art will understand upon reading this specification that RAID schemes generally improve reliability and reduce the probability of data loss.

[0057] The exemplary method is by no means intended to limit the invention; the memory controller (e.g., see...) Figure 1108) can perform garbage collection internally. As previously described, garbage collection may include selecting LEBs to be relocated, after which all data still valid on the selected LEBs may be relocated (e.g., moved). After the still valid data has been relocated, the LEBs can be erased and subsequently used to store new data. The amount of data relocated from the garbage-collected LEBs determines the write amplification. Furthermore, an efficient way to reduce write amplification includes implementing heat segregation.

[0058] thermal isolation

[0059] In this context, "hot writes" refers to the rate (e.g., frequency) at which data is updated (e.g., rewritten with new data). Memory blocks considered "hot" tend to have frequent update rates, while memory blocks considered "cold" have slower update rates than hot blocks.

[0060] Tracking write heat for logical pages may involve, for example, allocating a specific number of bits in the logical-to-physical table (LPT) mapping entry of the page to track how many write operations the page has undergone within a specific time period or window. Typically, host write operations increase write heat, while internal relocation writes decrease write heat. The actual increase and / or decrease in write heat can be deterministic or probabilistic.

[0061] Similarly, a specific number of additional bits in the LPT of each logical page can be used to track read heat. To reduce metadata, read heat can also be tracked at the physical block level, where a separate counter can be maintained for each block for straddling and non-straddling reads. However, it should be noted that when determining memory block heat using certain methods, the number of read requests and / or read operations performed on a memory block may not contribute to heat isolation. For example, a high read frequency does not necessarily mean a high update rate for a particular memory block if data is read frequently. Conversely, a high frequency of read operations performed on a given memory block can indicate the importance, value, etc., of the data stored in the memory block.

[0062] Write thermal isolation can be achieved by grouping memory blocks with the same and / or similar write hot values. Specifically, the write thermal isolation method can group hot write memory pages together in some memory blocks, while grouping cold write memory pages together in other memory blocks. Therefore, the write thermal isolation LEB is often occupied by either hot or cold write data.

[0063] The advantages of write hot isolation are twofold. First, performing garbage collection on write-hot memory blocks also prevents the relocation of write-cold data. Without hot isolation, frequent updates to write-hot data also lead to undesirable relocations of all write-cold data co-located with the hot data on the same LEB. Therefore, for methods implementing write hot isolation, write amplification caused by garbage collection is much lower.

[0064] Secondly, the relative write heat of data can be used for wear leveling purposes. For example, hot-write data can be placed in healthier (e.g., younger) memory blocks, while cold-write data can be placed in less healthy (e.g., older) memory blocks relative to those healthier blocks. Thus, the rate at which relatively older blocks wear out is effectively slowed down, thereby improving the overall durability of a given data storage system that achieves write heat isolation.

[0065] Write allocation

[0066] Write allocation involves placing the data to be written into a free space within an open LEB. Once all pages in an LEB have been written, the LEB is closed and placed in a pool that holds occupied LEBs. Typically, LEBs in the occupied pool become eligible for garbage collection. The number of open LEBs is usually limited, and any closed LEB can be replaced immediately or after a certain delay by a newly opened LEB.

[0067] During execution, garbage collection can occur simultaneously with user write operations. For example, when a user (e.g., a host) writes data to the device, the device controller can continuously perform garbage collection on LEBs containing invalid data to make room for new incoming data pages. As mentioned above, the LEB on which garbage collection is being performed will typically have some pages that are still valid at the time of the garbage collection operation; therefore, these pages are preferably relocated (e.g., written) to a new LEB.

[0068] Furthermore, the foregoing functionality is in no way intended to limit the capabilities of any storage system described and / or suggested herein. Rather, the foregoing functionality is presented by way of example, and depending on the desired approach, the logic of the storage system may be configured to perform additional or alternative functionality, as will be understood by those skilled in the art upon reading this specification.

[0069] Now for reference Figure 3System 300 is illustrated according to one method. Alternatively, system 300 may be implemented in combination with features from any other methods listed herein, such as those described with reference to other accompanying figures; however, such system 300 and other systems presented herein can be used in a variety of applications and / or in arrangements that may or may not be specifically described in the illustrative methods listed herein. Furthermore, system 300 presented herein can be used in any desired environment, such as in combination with a controller.

[0070] As shown in the figure, system 300 includes a write cache 302 coupled to several other components including a garbage collector 304. As previously described, garbage collector 304 can be used to free up LEB cells by relocating valid data and providing non-volatile memory blocks to be erased for later reuse. Therefore, garbage collector 304 can reclaim blocks of contiguous physical space according to a desired method. According to an exemplary method, a block erasure unit can be used to track and / or complete the erasure of non-volatile memory blocks handed over by garbage collector 304.

[0071] The write cache 302 is also coupled to the free block manager 306, which can track free non-volatile memory blocks after they have been erased. Furthermore, as those skilled in the art will recognize upon reading this description, the free block manager 306 can use erased free non-volatile memory blocks to create free stripes of non-volatile memory blocks from different channels (e.g., block stripes).

[0072] Still referencing Figure 3 The write cache 302 is coupled to the LPT manager 308 and the memory I / O unit 310. The LPT manager 308 maintains a logical-to-physical mapping of logical addresses to physical pages in memory. According to one example, which is by no means intended to limit the invention, the LPT manager 308 may maintain a logical-to-physical mapping of 4 KiB logical addresses. The memory I / O unit 310 communicates with the memory chip to perform low-level operations, such as reading one or more non-volatile memory pages, writing non-volatile memory pages, erasing non-volatile memory blocks, etc.

[0073] To better understand the difference between block-strip and page-strip as used in this article Figure 4AThis is based on a conceptual diagram 400 of one method. The LEB is constructed from block strips, and typically a single block strip is used to construct the LEB. However, alternative methods may use multiple block strips to form the LEB. Alternatively, this conceptual diagram 400 can be implemented by combining features from any other methods listed herein, such as those described with reference to other accompanying figures; however, such a conceptual diagram 400 and other conceptual diagrams presented herein can be used for various applications and / or permutations, which may or may not be specifically described in the illustrative methods listed herein. Furthermore, the controller conceptual diagram 400 presented herein can be used in any desired environment. Therefore, Figure 4A The exemplary non-volatile memory controller concept diagram 400 can be implemented in a cache architecture. However, depending on the desired approach, Figure 4A Conceptual diagram 400 can be implemented when defining the organization of data stored in non-volatile memory. Therefore, two implementation methods are described below in turn.

[0074] Non-volatile memory

[0075] Looking at it now Figure 4A Conceptual diagram 400 includes a set of M+1 aggregation planes, labeled "Plane 0" to "Plane M". An aggregation plane consists of all physical planes that have the same plane index on different channels. It should be noted that aggregation planes are also simply referred to as planes here.

[0076] When implemented using data stored in non-volatile memory, each physical plane on a channel can include a large set of blocks, typically on the order of 1024, 2048, or larger. Additionally, one or more physical planes may contain several extra blocks that can be used as replacement blocks for bad blocks (e.g., poorly performing blocks, blocks with undesirable characteristics, etc.).

[0077] In each plane of a nonvolatile memory, individual blocks from each channel form a corresponding block stripe. Therefore, the number of block stripes supported by a given method of nonvolatile memory can be determined by the number of blocks per plane and the number of planes.

[0078] In the exploded view of plane 0, concept diagram 400 further illustrates a single block stripe (block stripe 0) from the set of block stripes supported in the remaining planes. Block stripe 0 of plane 0 is shown as comprising 11 blocks, one block for each channel labeled "Channel 0" to "Channel 10". It should be noted that the association between blocks and block stripes can change over time, as block stripes are typically decomposed after they have been garbage collected. Erased blocks can be placed in a free block pool, whereby a new block stripe is assembled from blocks in the free block pool when a write allocation requests a new block stripe. For example, referring to concept diagram 400, block 10 from channel 0 and block 41 from channel 4 are currently associated with the shown block stripe 0 of plane 0. Furthermore, the shown block stripe 0 holds N+1 page stripes, and each block therefore holds N+1 pages labeled "Page 0" to "Page N".

[0079] Cache architecture

[0080] Still referencing Figure 4A When implemented in a cache architecture, each page block shown in the decomposition diagram of aggregation plane 0 can constitute a unique block from a channel. Similarly, each channel contributes a single, independent block that forms a block stripe. For example, referring to conceptual diagram 400, block 10 from channel 0 includes all pages within it (pages 0 to N), while block 41 from channel 4 corresponds to all pages within it, and so on.

[0081] In the context of a memory controller, for example, one capable of implementing RAID at the channel level, a block stripe consists of multiple blocks, which is equal to one stripe of a block. See also... Figure 4A Multiple blocks of aggregation plane 0 constitute block stripe 0. Although all blocks in a block stripe typically belong to the same aggregation plane, in some methods, one or more blocks of a block stripe may belong to different physical planes. Therefore, it can be concluded that each aggregation plane may include one or more block stripes. Thus, according to the illustrative method, blocks 0 through 10 from different physical planes can constitute a block stripe.

[0082] in spite of Figure 4A Whether conceptual diagram 400 is implemented using a non-volatile memory and / or cache architecture, the number of pages in each block and / or the number of channels in each plane can vary depending on the desired approach in different methods. According to one exemplary method, which is by no means intended to limit the invention, a block may include 1024 pages, but may include more or fewer pages in various methods. Similarly, the number of channels per plane and / or the number of planes can vary depending on the desired approach.

[0083] Still referencing Figure 4AA page stripe is a collection of all pages with the same page index within a block stripe. For example, page stripe 0 comprises the first page (page 0) of each channel in block stripe 0 of plane 0, and similarly, page stripe N comprises the last page (page N) of each channel in block stripe 0 of plane 0.

[0084] In some methods, Figure 4A The general memory architecture shown in conceptual diagram 400 is also implemented using a 3-D memory structure. For example, Figure 4B A representative view of a 3-D non-volatile memory structure 450 according to one method is depicted. Alternatively, this structure 450 can be implemented by combining features from any other methods listed herein, for example, with reference to other figures (e.g., Figure 4A The structures described herein are not included here. However, such structure 450 and other structures presented herein can be used in a variety of applications and / or substitutions, which may or may not be specifically described in the illustrative methods listed herein. Furthermore, structure 450 presented herein can be used in any desired environment. Therefore, Figure 4B (and other graphs) can be considered to include any possible permutations.

[0085] As shown in the figure, each layer 452 of the 3-D non-volatile memory structure 450 extends along the x-axis and y-axis. Each of these layers 452 contains multiple memory components (not shown), such as voltage supply lines, sensor stacks, transistors, etc., which are used for implementation Figure 4A The conceptual diagram 400 illustrates a general memory architecture for a non-volatile memory device, as those skilled in the art will understand after reading this description. Furthermore, the layers 452 are arranged in a stacked manner along the z-axis to increase storage density and efficiency. (The last sentence appears to be incomplete and possibly refers to a different concept.) Figure 4B Cells of different bit lines (in the x or y dimension) are logically combined to form pages. Therefore, each block includes multiple word lines, and each word line has multiple read voltages associated with it. For example, in TLC, each word line in a block contains three physical pages (e.g., a lower page, an upper page, and an extra page), and the word line typically belongs to a specific layer in the z dimension (perpendicular to the xy plane).

[0086] For a given block formed by a grid of cells connected by word lines and bit lines, the number of word lines on the same layer is typically small. Therefore, a block can be formed by word lines from all layers 452. Furthermore, word lines and pages within the same block can reside on different layers 452. It should also be noted that a block contains more than one type of page (e.g., top page, bottom page, extra page, top page), and at least one read voltage is associated with each of these page types, as will be understood by one of those skilled in the art upon reading this description.

[0087] Furthermore, due to cycling, holding, read interference, programming interference, or other mechanisms specific to 3D NAND flash technology (e.g., floating gate or charge trap based technologies), processing technology, cell and material design, circuit and array architecture, or other specific design factors, the programmable threshold voltage distribution in a memory block can change with the relatively slow or fast writing and erasing of data (cycling), reading of data (read interference), time (holding), etc. In other words, the RBER of a flash memory block increases with time and use. Each P / E cycle performed on a memory block while it is in use results in the damage of memory cells, which in turn increases the corresponding RBER.

[0088] Block calibration is an important aspect of enhancing the durability and retention of flash memory storage systems (e.g., especially enterprise-class flash systems) by reducing the RBER experienced. This block calibration corresponds to the read voltage and refers to an algorithm that can track changes in the threshold voltage distribution and adjust the read voltage accordingly, thereby significantly reducing bit errors and improving performance consistency in the corresponding device by reducing the read tail latency that would otherwise be caused by the error recovery mechanism call.

[0089] Furthermore, an adjustment to the read voltage is applied accordingly during the read command. The threshold voltage represents the voltage associated with the transistor turning on a given flash memory cell, and its value depends on the amount of charge stored during programming. However, the read voltage is a bias voltage, and its value is typically between the threshold voltages of two adjacent logic states, for example, as described below. Figure 5 The following is a more detailed explanation.

[0090] For reference only Figure 5 The example illustrates a graph 500 showing the threshold voltage shift phenomenon. The x-axis of graph 500 represents the programmed threshold voltage V. TH The y-axis represents the cell count of a QLC NAND flash memory block. In QLC NAND flash memory, each cell stores 4 bits of information; therefore, V... TH The distribution corresponds to 16 possible discrete levels (L0, L1, ..., L15). Furthermore, each different type of page in a given block of QLC NAND flash memory has a different set of read voltages corresponding to it. According to one example (which is by no means intended to limit the invention), the lower pages correspond to read voltage V8, the upper pages correspond to read voltages V4 and V12, the additional pages correspond to read voltages V2, V6, V10, and V14, and the top page corresponds to read voltages V1, V3, V5, V7, V9, V11, V13, and V15.

[0091] The solid line distribution 502 indicates the V after programming. TH Level. The vertical solid line indicates the voltage level for V. THDistribution 502 shows the optimal read voltage 504 (V1, ..., V15). The dashed distribution 506 indicates the V value due to charge loss over time. TH A negative shift of the level. Due to this negative shift to a lower voltage, the read voltage 504 is no longer optimal. In fact, a negative offset must be applied to the read voltage to account for V. TH The distribution changes from 502 to 506. The vertical dashed line 508 indicates the V value in 506. TH The optimal read voltage (V1, ..., V15) is determined during the holding period of the distribution. Typically, each of the 16 levels (L0, L1, ..., L15) shown in the diagram can have a different V. TH The shifting allows each of the 15 read voltages (V1, ..., V15) to have a different optimal shift.

[0092] Therefore, the read voltage shift value (or offset value) is preferably determined periodically shortly after and / or after the block is written. The threshold voltage can be considered as an exponent of the cell programming level (i.e., L0, L1, ..., L15), as determined by measuring the source-drain current when a control gate bias is applied to the memory cell. Typically, during a read operation, one or more read voltages between adjacent nominal threshold voltage levels are used to determine the cell state. When the threshold voltage value of the memory cell changes (as described above), the read voltage applied during the read operation is preferably shifted accordingly using a set of offset values ​​to obtain optimal read conditions and minimize RBER. The optimal read voltage shift value can then be updated periodically, for example, during a background health check, or as needed, for example, in the case of a high-bit error count or ECC failure.

[0093] While increases in RBER are irreparable for some blocks (e.g., those caused by prolonged P / E cycles), increases in RBER caused by events such as retention and / or read interference are transient in the sense that the affected block is not irreversibly damaged. This adverse increase in RBER is remedied when the corresponding memory block is recalibrated to correct the corresponding read voltage. In other methods, blocks experiencing transient RBER increases can be remedied by erasing, programming, and recalibrating. Therefore, it is clear that the RBER of a block depends on the block's state, which can be determined by cyclic state, retention state, read interference state, and / or any combination thereof. Block recalibration improves RBER by adjusting the read voltage, making them more resistant to permanent and / or transient effects. TH It is optimal under various distribution variations.

[0094] Ideally, the read voltage for each page in a memory block is updated individually. However, as memory capacity increases, the amount of storage consumed in each block by maintaining one or more read voltage offsets for each page also increases, where the number of read voltage offsets depends on the page type of a given page. For example, moving from 3 bits per cell in TLC NAND flash to 4 bits per cell in QLC NAND flash, each block implements 16 threshold voltage levels (instead of 8 in TLC) and 15 different read voltages (instead of 7 in TLC) to read any pages included within it. Furthermore, with improvements in vertical stacking and process technology, the number of layers in each new generation of 3-D NAND flash memory also increases. Subsequently, the number of pages per block also increases. For example, current 3-D QLC NAND flash memory can have more than 90 layers and more than 4,000 pages per block. Therefore, if all 15 different read voltages in a 3-D QLC NAND are calibrated independently (or individually), the amount of metadata involved in storing individual read offset value sets for each page or group of pages in a block and the number of calibration reads per page increase significantly.

[0095] As memory capacity continues to increase, so do the reliability issues associated with memory. Therefore, in addition to the increased number of read voltage offsets associated with each page in each block of memory, conventional calibration engines also experience an increase in processing overhead due to decreased memory reliability.

[0096] In stark contrast to the increasingly inefficient ways traditional storage systems manage memory performance, the various methods presented in this paper significantly reduce calibration overhead while also improving read performance. These improvements are achieved in several methods, including, for example, those described in further detail below, in addition to reducing the impact of metadata corresponding to the calibration process on storage capacity.

[0097] Now for reference Figure 6A The flowchart illustrates a method 600 for calibrating the read voltage of pages in a memory block, according to a method described herein. According to the invention, method 600 can be performed... Figures 1-5 The method can be executed in any environment described herein, wherein it can be executed in various ways. For example, any process included in method 600 can be executed relative to a block of storage space in NVRAM, such as 3-D TLC NAND flash memory, 3-D QLC NAND flash memory, 3-D five-level cell (PLC) NAND flash memory, or any other desired type of memory. Furthermore, as those skilled in the art will understand upon reading this specification, method 600 may include more than Figure 6A The specific operations described in the text may include more or fewer operations.

[0098] Each step of method 600 can be performed by any suitable component of the operating environment. For example, in various methods, method 600 can be performed partially or entirely by a controller (e.g., a flash controller, a hybrid controller, etc.), a processor, a computer, or some other device having one or more processors. Thus, in some methods, method 600 can be a computer-implemented method. It should also be noted that the terms computer, processor, and controller are used interchangeably with respect to any method herein, and such components are considered equivalent in many different arrangements of the invention.

[0099] Furthermore, for those methods that have a processor, the processor is, for example, a processing circuit, chip, and / or module implemented in hardware and / or software, and preferably has at least one hardware component that can be used in any device to perform one or more steps of method 600. Illustrative processors include, but are not limited to, central processing units (CPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations thereof, or any other suitable computing device known in the art.

[0100] like Figure 6A As shown, operation 602 of method 600 includes proceeding to the next memory block. Regarding this specification, "next memory block" can vary depending on the given method. For example, when initiating method 600, the next memory block can simply be the first memory block. In other methods, the next memory block can be the next memory logical block. Furthermore, operation 602 can be performed between memory blocks in any desired manner, such as sequentially, randomly, by usage pattern, etc. Additionally, operation 602 can be triggered periodically by a background process that checks all NAND blocks, for example, every week, or can be triggered when needed, such as when page reads in the block present a high-bit error count or an ECC failure. Furthermore, the memory preferably includes NVRAM. For example, in some methods, the memory includes 3-D TLC NAND flash memory, while in other methods, the memory includes 3-D QLC NAND flash memory.

[0101] Operation 604 also includes proceeding to the next page within a given block. As mentioned above, the "next page" can vary depending on the given method. For example, when proceeding to a new memory block, the next page can simply be the first page in the block. In other methods, the next page in the memory block can be a specific type of next page (e.g., the next extra page). In other methods, the next page can simply be a subsequent page in the given block. Thus, operation 604 can be performed between pages in a memory block in any desired manner, such as sequentially, randomly, according to usage patterns, etc.

[0102] Method 600 proceeds from operation 604 to operation 606, which includes calibrating one or more read voltage offset values ​​for a given page in the block using a first calibration scheme. As implied above, each block contains several different page types depending on the block's configuration. According to one example, which is by no means intended to limit the invention, a block of a 3-D QLC NAND flash memory includes four different types of pages, including bottom pages, top pages, extra pages, and top pages. Each of these page types further includes one or more read voltages corresponding to reading data stored therein. However, the threshold voltage value of the memory cell changes over time, thus rendering the read voltages ineffective. A read voltage offset value is thus applied during a read operation to obtain optimal data read conditions and minimize RBER. Subsequently, these read voltage offset values ​​may be periodically updated, for example, during a background health check.

[0103] Pages in a memory block can be calibrated using any one or more of many different types of calibration schemes. Each calibration scheme can vary in how it is applied (e.g., how it is performed), the accuracy of its recalibration of the block, the amount of time consumed, and / or the amount of computational resources required. Therefore, different types of calibration schemes may be needed for different situations, where a specific calibration scheme indicates how the pages will actually be calibrated.

[0104] For example, a calibration scheme involving calculating a common read voltage offset (also referred to herein as a “shift”) for each subset of read voltages associated with the corresponding page type in the word line involves less computational overhead and latency compared to a calibration algorithm that involves calculating a common read voltage offset for only a portion of the read voltages in the word line and an independent voltage offset for the remaining read voltages in the word line. Despite the additional computational overhead and latency associated with calibration algorithms involving calculating a common read voltage offset for only a portion of the read voltages in the word line and an independent voltage offset for the remaining read voltages in the word line, increased read performance is also achieved due to the added accuracy. This improved read performance is likely desirable in situations experiencing high read error counts. It is concluded that calibration schemes causing less computational overhead and / or latency can be implemented during “nominal” operation, while those incurring greater computational overhead and latency can be reserved for high-error conditions, such as ECC failures that will soon become apparent. It is concluded that different calibration algorithms can be implemented in different situations, for example, depending on the desired approach.

[0105] Referring again to operation 606, the first calibration scheme preferably involves one or more processes capable of calibrating read voltage offset values ​​while incurring a relatively low amount of computational overhead and / or computational delay. In some cases, this can be achieved by utilizing a calibration scheme that involves, for example, calculating a relatively low number of independent voltage offset values ​​and a relatively high number of common read voltage offset values ​​compared to at least a second calibration scheme described below.

[0106] Operation 608 further includes attempting to read a calibration page in a given block. In other words, operation 608 includes attempting to read the page using one or more read voltage offset values ​​generated in operation 606 by the first calibration scheme. Furthermore, decision 610 includes determining whether an ECC fault occurred during the attempt to read the page. An ECC fault corresponds to a situation where the number of bit errors experienced during the attempt to read the page is higher than the number of errors that can be corrected by the error correction capability of a given error correction code.

[0107] Therefore, in response to determining that an ECC fault did indeed occur during the attempt to read the calibration page, method 600 proceeds to operation 612. There, operation 612 includes recalibrating a given page in the block using a second calibration scheme. As described above, the first calibration scheme, which incurs less computational overhead and / or computational latency, can be implemented during “nominal” operation, while a more accurate calibration scheme involving a greater amount of computational overhead and / or computational latency can be reserved for high-error conditions, such as ECC faults. Therefore, regarding this specification, a “second calibration scheme” is a calibration scheme capable of determining the read voltage offset value of a page in a memory block more accurately than the first calibration scheme. This increased accuracy compared to the first calibration scheme is a result of calibrating a larger number of independent read voltage offset values ​​than the first calibration scheme.

[0108] Based on the example, which is by no means intended to limit the invention, the first calibration scheme is able to calibrate the eight read voltages used when reading the top page by calculating a common offset value applied to all eight read voltages, while the second calibration scheme is able to calibrate the eight read voltages by calculating four independent offset values ​​of four of the eight read voltages and a common offset value applied to the remaining four read voltages.

[0109] Continue to refer to Figure 6A Operation 614 includes attempting to read a recalibrated page from a given block. In other words, operation 614 includes attempting to read the page using one or more read voltage offset values ​​generated in operation 612 by the second calibration scheme. Furthermore, decision 616 includes determining whether an ECC fault occurred during the attempt to read the recalibrated page. As described above, an ECC fault corresponds to a situation where the number of bit errors experienced during the attempt to read the page is higher than the number of errors that can be corrected by the error correction capability of a given error correction code.

[0110] Therefore, in response to determining that an ECC failure did indeed occur during the attempt to read the recalibrated page, method 600 proceeds to operation 618. There, operation 618 includes sending one or more instructions to relocate the data stored in the given page to another page in memory. Relocating the data stored in the given page involves data reconstruction via a more advanced scheme such as a RAID scheme, and allows the page to be invalidated and deactivated at least temporarily.

[0111] Method 600 proceeds from operation 618 to decision 620, which involves determining whether all pages in a given block have been calibrated. In response to determining that at least one page in the given block has not been calibrated, method 600 returns to operation 604, allowing the next page in the given block to be calibrated. However, in response to determining that all pages in the given block have been calibrated, method 600 returns to operation 602 and proceeds to the next block in memory. It is thus concluded that the various processes included in method 600 can be repeated iteratively any desired number of times.

[0112] Returning to decision 610, method 600 proceeds to decision 622 instead of operation 612 in response to determining that no ECC failure occurred during the attempt to read the calibrated page. In other words, method 600 proceeds to decision 622 in response to determining that operation 608 was able to successfully read data from the calibrated page. As shown, decision 622 includes determining whether the error count corresponding to a given page is within a first predetermined range. Decision 622 thereby determines whether the current page has recently performed undesirably, for example, making it possible to take countermeasures to avoid additional poor performance. The first predetermined range can be predetermined by the user based on industry standards, the performance capabilities of the memory, can be dynamically updated based on past performance, etc. The error count can then be maintained for each page in memory and updated over time based on the performance of the memory. Furthermore, in some methods, various error counts can be stored in a designated memory location, while in other methods, each error count can be maintained by one or more bits associated with the corresponding page in the memory.

[0113] In response to determining that the error count corresponding to a given page is within a first predetermined range, method 600 proceeds to operation 612, such that a second calibration scheme can be used to recalibrate pages in a given block whose performance has deteriorated over time. However, in response to determining that the error count corresponding to a given page is not within the first predetermined range, it can be determined that the given page has been accurately calibrated and has been performed as desired. Therefore, method 600 proceeds directly from decision 622 to decision 620. It should be noted that "within a first predetermined range" or the use of "predetermined range" herein is by no means intended to limit the invention. Rather than determining whether a value is within a predetermined range, an equivalent determination can be made according to the desired method, such as whether the value is above a threshold, whether the value is outside a predetermined range, whether the absolute value is above a threshold, whether the value is below a threshold, etc.

[0114] Returning to decision 616, method 600 proceeds to decision 624 instead of operation 618 in response to determining that no ECC failure occurred during the attempt to read the recalibrated page. In other words, method 600 proceeds to decision 624 in response to determining that operation 614 was able to successfully read data from the calibrated page. As shown, decision 624 includes determining whether the error count corresponding to a given page is within a second predetermined range. Decision 624 thereby determines whether the current page has been executed undesirably, for example, as described above. The second predetermined range may be the same as, similar to, or different from the first predetermined range, for example, depending on the desired approach. In some approaches, the second predetermined range may be narrower than the first predetermined range in an attempt to ensure that the given page is executed as desired after the recalibration operation. Furthermore, the second range may be predetermined by the user based on industry standards, utilizing the performance capabilities of the memory, may be dynamically updated based on past performance, and so on.

[0115] In response to determining that the error count corresponding to a given page is within a second predetermined range, method 600 proceeds to operation 618, such that data stored in the given page can be relocated. However, in response to determining that the error count corresponding to the given page is not within the second predetermined range, it can be determined that the given page has been accurately recalibrated and has been performed as desired. Therefore, method 600 proceeds from decision 624 to operation 626, which includes incrementing an error recovery counter corresponding to the given page. The error recovery counter is used to maintain a count indicating the number of times a page or block has triggered the execution of a second calibration scheme. The error recovery counter can thus be used to efficiently manage the relocation of pages or blocks in memory.

[0116] The process proceeds to decision 628, where a determination is made regarding whether the error recovery counter is within a third predetermined range. In response to determining that the error recovery counter is within the third predetermined range, method 600 proceeds to operation 618, allowing data in a given page to be relocated. However, in response to determining that the error recovery counter is not within the third predetermined range, method 600 proceeds directly to decision 620, allowing the next page or block to be evaluated.

[0117] Part of managing error recovery counters involves periodically decrementing or even clearing their current value to indicate block reinitialization via an erase operation. It should also be noted that, in some cases, error recovery can also be triggered during host read operations. (Temporary reference) Figure 6B An exemplary method 650 with a process for managing error recovery counters is shown according to a method, any one or more of which can be implemented in the context of the above method 600. However, it should be noted that Figure 6B The process is described according to a method that is by no means intended to limit the invention.

[0118] As shown, method 650 includes proceeding to the next page in memory. See operation 652. In this specification, "the next page in memory" can vary depending on the given method. For example, when initiating method 650, the next page in memory can simply be the first page in memory. In other methods, the next page in memory may correspond to the next page evaluated using method 600. Therefore, it can be concluded that operation 652 can be performed between pages in memory in any desired manner, such as sequentially, randomly, in a usage pattern, etc. It is also preferred that the processes included in method 650 be performed in the background of any other ongoing data management process, such as those described above.

[0119] Still referencing Figure 6B Decision 654 includes determining whether predetermined conditions corresponding to the error recovery counter have been met. These conditions may be predetermined by the user, system administrator, etc., according to a desired method, but preferably correspond to the performance of a given page or block. According to one example, which is by no means intended to limit the invention, the predetermined conditions may specify the number of P / E cycles that a given page or block should perform before the error recovery counter can be decremented.

[0120] Therefore, in response to determining that the predetermined condition corresponding to the error recovery counter has been met, the flowchart proceeds to operation 656, which includes decrementing the error recovery counter. The amount by which the error recovery counter is decremented and / or incremented varies depending on the method. For example, in some methods, the error recovery counter is incremented and decremented by one each time. Method 650 returns from operation 656 to operation 652, for example, to allow the evaluation of the error recovery counter corresponding to the subsequent page. Furthermore, returning to decision 654, method 650 directly returns to operation 652 in response to determining that the predetermined condition corresponding to the error recovery counter has not yet been met.

[0121] Therefore, it can be concluded that the various processes in method 600 and those included in method 650 can improve the operation of the memory and / or memory controller by significantly reducing calibration overhead while ensuring efficient memory performance. These improvements can be achieved, at least in part, as a result of implementing the first calibration scheme during nominal operation and implementing the second calibration scheme on demand in error recovery mode. As mentioned above, while the second calibration scheme achieves more accurate calibration results compared to the first calibration scheme, the first calibration scheme incurs less calibration overhead relative to the implementation of the second calibration scheme. Therefore, by selectively implementing the second calibration scheme, performance is improved while also ensuring favorable memory management.

[0122] Now for reference Figure 6C An exemplary subprocess is shown, according to a method, using a first calibration scheme to calibrate one or more read voltage offset values ​​for a given page in a block. Figure 6C Any one or more of the sub-processes included can be used for execution. Figure 6A Operation 606. However, it should be noted that... Figure 6C The sub-processes are described according to a method that is by no means intended to limit the invention.

[0123] As shown in the figure Figure 6C This includes determining the page type corresponding to a given page. See sub-operation 660. Similarly, each page type has a different number of read voltages associated with it, for example, as those skilled in the art will understand.

[0124] In some cases, the page type can be determined by actually examining the physical address of a given page, while in others, it can be determined by accessing a lookup table. Therefore, any process that will be obvious to those skilled in the art after reading this specification can be used to determine the page type. In response to determining the page type, the flowchart proceeds to operation 662, which includes determining one or more read voltages associated with the page type corresponding to the given page. As mentioned above, each page type corresponds to a different subset of the total read voltages, such as 15 read voltages in a QLC NAND, and the number of read voltages in each subset can be different for each page type. Therefore, the number of read voltages determined in sub-operation 662 depends on the given page type. These read voltages are fixed for each page type and can depend on the memory device.

[0125] Furthermore, sub-operation 664 includes determining one or more existing read voltage offset values, each of which corresponds to a corresponding one of the one or more read voltages. In some methods, metadata mapping may be used to determine one or more existing read voltage offset values, but any process that will become apparent to those skilled in the art after reading this description may be used.

[0126] Sub-operation 666 further includes applying one or more existing read voltage offset values ​​to one or more read voltages, while sub-operation 668 includes calculating a correction offset for each of the existing read voltage offset values. In some methods, calculating the correction offset for each of the existing read voltage offset values ​​includes performing a level shifting algorithm using the one or more existing read voltage offset values ​​and the one or more read voltages. Subsequently, the process of calculating the correction offset for the existing read voltage offset values ​​may include actually applying one or more voltages to a given page and using the result of doing so to calculate a new set of correction offset values.

[0127] The process now proceeds to sub-operation 670, where a correction offset is used to update the existing read voltage offset value. In a preferred method, the correction offset is used to update the existing read voltage offset value based on a first metadata mapping. In this specification, a "first metadata mapping" specifies a first mapping relationship that extends (e.g., correlates) between the correction offset and the existing read voltage offset value. This first mapping relationship also corresponds to a first calibration scheme. In other words, while a correction offset can be determined for each existing read voltage offset value, sub-operation 670 is preferably able to determine a common correction offset that can be applied to each existing read voltage offset value.

[0128] It should also be noted that the above can be implemented relative to Figure 6COne or more of the described sub-processes are used to recalibrate one or more read voltage offset values ​​of a given page in the block using a second calibration scheme. However, specifically referring to sub-operation 670, it should be noted that the correction offset is preferably used to update existing read voltage offset values ​​based on a second metadata map. As mentioned above, the correction offset is used to update existing read voltage offset values ​​based on a first metadata map corresponding to the first calibration scheme. Therefore, the methods involving performing the second calibration scheme to recalibrate one or more read voltage offset values ​​of a given page in the block can differ in some respects.

[0129] For example, the correction offset determined in sub-operation 668 above is preferably used to update the existing read voltage offset value based on a second metadata mapping of the method for implementing the second calibration scheme. The second metadata mapping defines a second mapping relationship extending (e.g., their correlation) between the correction offset and the existing read voltage offset value. The second mapping relationship corresponds to the second calibration scheme.

[0130] The mapping relationship extending between the correction offset and the existing read voltage offset value varies depending on the specific method. For example, a first mapping relationship corresponds to a first calibration scheme, while a second mapping relationship corresponds to a second calibration scheme. See also Figures 7A-7E This section explains the relationship between page type, read voltage offset, and correction offset in more detail, based on some exemplary methods. Alternatively, Figures 7A-7E Any of these can be implemented by combining features from any other methods listed here, for example, referring to other diagrams, such as... Figures 6A-6C The methods described. However, this type of Figures 7A-7E The other diagrams presented herein can be used for various applications and / or permutations, which may or may not be specifically described in the methods described herein.

[0131] As mentioned above, different sets of read voltages correspond to reading different page types. According to one example—which is by no means intended to limit the invention—of the 15 read voltages used in QLC NAND, namely V1, ..., V15, read voltages V1, V3, V5, V7, V9, V11, V13, and V15 are used to read the top page, read voltages V2, V6, V10, and V14 are used to read additional pages, read voltages V4 and V12 are used to read the upper pages, and read voltage V8 is used to read the lower pages.

[0132] Figure 7ATable 710 associates each page type with a corresponding read voltage(s) according to a method. Therefore, Table 710 depicts a mapping relationship extending (e.g., their correlation) between correction offsets and existing read voltages for each page type. In some cases, this mapping relationship may also correspond to a second calibration scheme. According to the mapping relationship in Table 710, which is also not intended to limit the invention, a total of 10 correction offsets are mapped to 15 read voltages in the QLC NAND. A common read voltage offset a3 is defined for the read voltages V5, V7, V9, V11 corresponding to the top page TP, while unique correction offsets a1, a2, a4, a5 are defined for the remaining read voltages V1, V3, V13, V15 respectively corresponding to the top page TP. Therefore, a common read voltage offset a7 is defined for the read voltages V6, V10 corresponding to the additional page XP, while unique correction offsets a6, a8 are defined for the remaining read voltages V2, V14 respectively corresponding to the additional page XP.

[0133] Furthermore, a common read voltage offset a9 is defined for the read voltages V4 and V12 corresponding to the upper page UP, and a unique read voltage offset a10 is defined for the read voltage V8 corresponding to the lower page LP. Therefore, it can be concluded that in some methods, Figure 7A The implementation described herein corresponds to the second calibration scheme described above regarding method 600.

[0134] also, Figure 7B Table 730 associates each of the page types with a corresponding read voltage (one or more). Therefore, Table 730 depicts a mapping relationship extending (e.g., their correlation) between the correction offset and the existing read voltage for each page type. In some cases, this mapping relationship may also correspond to a first calibration scheme. It is thus concluded that in some methods, Figure 7B The implementation described herein can correspond to the first calibration scheme described above regarding method 600.

[0135] Figure 7C Table 740, as shown, illustrates read voltage offset values ​​according to the metadata structure. As illustrated, the metadata structure depicted in Table 740 supports ten different read voltage offset values ​​(numbered 1-10) for each word line in a given block. Furthermore, each of the read voltage offset values ​​1-10 corresponds to a specific page type: TP, XP, UP, LP. In some methods, each offset value (e.g., o2) may include only one byte of information. Therefore, each row in Table 740 represents the metadata stored for each word line in a given memory block.

[0136] It should also be noted that the read voltage and corresponding read voltage offset values ​​determined as a result of implementing the first and / or second calibration scheme can be used to update the values ​​stored in Table 740. For example, these values ​​can be used to update the offset value applied when attempting to read data from a specific page in a block of a word line. Therefore, the process of reading a given page may involve accessing Table 740, determining the resulting offset value corresponding to the page, and adjusting the read voltage using the resulting offset value.

[0137] Continue to Figure 7D Table 750 and Figure 7E Table 760 corresponds to the metadata of a given page in memory, which can be mapped to a corresponding correction offset. However, Tables 750 and 760 differ in that Table 750 includes a larger number of correction offset values, while Table 760 relies on multiple common correction offset values. Therefore, Tables 750 and / or 760 can be applied to every word line in a memory block.

[0138] See now Figure 8A The process 800 for performing a calibration scheme is illustrated by way of an example in use and is by no means intended to limit the invention. As shown, in calibration round n-1, it can be assumed that the read voltage offset value has not yet been determined, and therefore existing read voltages can be used to read data from each of the pages. However, calibration round n corresponds to a first calibration scheme applied to an exemplary additional page XP having a read voltage offset value “c2”. According to the first calibration scheme (e.g., see Table 730 above), this read voltage offset value of c2 is applied to each of the read voltages of the additional page. Similarly, according to the first calibration scheme, in calibration round n+1, a new read voltage offset value c2 is applied to each of the already adjusted read voltages, resulting in a read voltage offset value c2 that is the sum of the corrected offset values ​​for each of the offsets o6, o7, o8 in the metadata structure (e.g., see Table 740 above).

[0139] However, referring to calibration round n+2, a second calibration scheme is implemented, and the read voltages are updated using different read voltage offset values. For example, read voltages V6 and V10 are shifted by a common offset value a7, while read voltage V2 is shifted by an offset value a6 and read voltage V14 is shifted by an offset value a8. Finally, calibration round n+3 returns to the first calibration scheme, such that the same read voltage offset value c2 is applied to each read voltage, as shown in the figure.

[0140] It should be noted that it is executable. Figure 8AThe controller described in the figure may not be able to access the actual read voltage values ​​V2, V6, V10, V14, but may be able to access the applied offset values, such as o6, o7, and o8. As shown, the applied offsets o6, o7, o8 for each of the voltages may have the same or different values ​​depending on the method, and the correction offset values ​​depend on the calibration scheme implemented.

[0141] As described above, the various methods included in this paper implement different calibration schemes based on the read performance experienced when attempting to calibrate a given page. Furthermore, each of these calibration schemes implements a different number of independent read voltage offset values ​​as well as a common read voltage offset value. Therefore, the read voltage offset values ​​corresponding to each different calibration scheme are preferably interoperable, allowing them to be used interchangeably depending on the calibration scheme being implemented. This can be achieved in some methods by utilizing the metadata structure and offset update mechanism corresponding to the memory. This allows for a first calibration scheme with lower computational intensity during nominal operations, while reserving a second calibration scheme with higher computational intensity for cases where increased accuracy is desired.

[0142] Therefore, it is concluded that the read voltage offset values ​​corresponding to the first and second calibration schemes are preferably stored in memory so that they can be easily converted according to the calibration scheme being implemented. For example, see Figure 8B This illustrates an example of the use of storing read voltage offset values. As shown, background calibration of a given page p in block b can be initiated at any time. See operation 802. Operation 804 thereby calibrates page p by implementing a first calibration scheme. This process involves loading the current read voltage offset values ​​in an extended format (e.g., a format corresponding to the second calibration scheme) and using these offset values ​​to perform calibration on page p. However, the process of using the current read voltage offset values ​​loaded from metadata structure 801 involves converting the offset values ​​from their extended format (where the offset values ​​are stored) to a compact format corresponding to the first calibration scheme.

[0143] According to an example that is by no means intended to limit the invention, the current read voltage offset value is stored in metadata structure 801, making ten distinct read voltage offset values ​​available. These ten distinct values ​​comprise seven independent read voltage offset values ​​and three common read voltage offset values ​​(e.g., as seen in Table 710). However, these read voltage offset values ​​are transformed so that only four distinct read voltage offset values ​​are available for a first calibration scheme. These four distinct values ​​comprise four common read voltage offset values ​​(e.g., as seen in Table 730). Depending on the given method, the transformation of the read voltage offset values ​​can be performed in a variety of different ways. For example, in some methods, multiple independent read voltage offset values ​​can be averaged to produce a common read voltage offset value.

[0144] Continue to refer to Figure 8B The result of operation 804 is preferably converted back to a format corresponding to the second calibration scheme before being stored in the metadata structure 801. However, in response to page p experiencing an ECC fault in block b, selective calibration is performed. See operation 806. Operation 808 thereby calibrates page p by implementing the second calibration scheme. This process includes loading the current read voltage offset value from the metadata structure 801 in an extended format (e.g., a format corresponding to the second calibration scheme) and using these offset values ​​to perform calibration on page p.

[0145] Because the current read voltage offset value loaded from metadata structure 801 is already in a format corresponding to the second calibration scheme, operation 808 does not involve performing any conversion. Similarly, the result of performing operation 808 does not need to be converted before being stored in metadata structure 801. Therefore, in some methods, metadata structure 801 defines a mapping between read voltage offset values ​​corresponding to the first calibration scheme and a second mapping between read voltage offset values ​​corresponding to the second calibration scheme and a stored value. This mapping can be based on any desired function that associates multiple read voltage offset values ​​with a single value. For example, as those skilled in the art will understand after reading this specification, multiple read voltage offset values ​​can be mapped to a single value by calculating the average, median, weighted average, etc., of multiple read voltage offset values. This also ideally avoids performing frequent block relocations in error recovery mode.

[0146] Therefore, the various methods included in this paper can improve the operation of memory and / or memory controllers by significantly reducing calibration overhead while ensuring efficient memory performance. These improvements can be achieved, at least in part, as a result of implementing a first calibration scheme during nominal operation and implementing a second calibration scheme on demand in error recovery mode. As mentioned above, while the second calibration scheme achieves more accurate calibration results compared to the first, the first calibration scheme incurs less calibration overhead relative to the implementation of the second. Therefore, performance is improved by selectively implementing the second calibration scheme, while also ensuring favorable memory management. Furthermore, the way the read voltage offset values ​​are stored in memory further improves accessibility and applicability for different calibration schemes. This is achieved, at least in part, by storing these offset values ​​in the most complex format, minimizing the computational complexity of performing any conversions.

[0147] It should also be noted that the specific configurations included in any of the methods included herein are not limiting. For example, the number and / or type of pages in a given word line and / or memory block, the number and / or values ​​of read voltages, the number and / or values ​​of threshold voltage levels, the number of common and / or independent read voltage offset values ​​corresponding to each calibration scheme, etc., included in any of the methods herein are by no means intended to be limiting, but are presented only by way of example.

[0148] This invention can be a system, method, and / or computer program product at any possible level of technical detail integration. The computer program product may include a computer-readable storage medium (or media) having computer-readable program instructions thereon for causing a processor to perform aspects of the invention.

[0149] Computer-readable storage media can be tangible devices capable of retaining and storing instructions for use by an instruction execution device. Computer-readable storage media can be, for example, but not limited to, electronic storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes the following: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable optical disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices such as punch cards or recessed structures with instructions recorded thereon, and any suitable combination of the foregoing. As used herein, computer-readable storage media should not be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0150] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to a suitable computing / processing device, or via a network, such as the Internet, a local area network (LAN), a wide area network (WAN), and / or a wireless network, to an external computer or external storage device. The network may include copper cables, optical fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to a computer-readable storage medium within the respective computing / processing device.

[0151] Computer-readable program instructions used to perform the operations of this invention may be assembly instructions, instruction set architecture (ISA) instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, integrated circuit configuration data, or source code or object code written in any combination of one or more programming languages ​​(including object-oriented programming languages ​​such as Smalltalk, C++, etc.) and procedural programming languages ​​(such as the "C" programming language or similar programming languages). The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, to perform aspects of this invention, electronic circuits, including, for example, programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), may execute computer-readable program instructions to personalize the electronic circuits by utilizing the status information of the computer-readable program instructions.

[0152] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0153] These computer-readable program instructions may be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / actions specified in one or more blocks of a flowchart and / or block diagram. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and / or other devices to operate in a particular manner, such that the computer-readable storage medium in which the instructions are stored includes an article of writing comprising instructions for implementing aspects of the functions / actions specified in one or more blocks of a flowchart and / or block diagram.

[0154] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer-implemented process, such that the instructions, which execute on the computer, other programmable apparatus or other device, perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0155] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions comprising one or more executable instructions for implementing a specified logical function. In some alternative embodiments, the functions indicated in the blocks may occur in a different order than indicated in the figures. For example, two blocks shown consecutively may actually be implemented as a single step, executed simultaneously, substantially simultaneously, with partial or complete time overlap, or these blocks may sometimes be executed in reverse order, depending on the functions involved. It will also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified function or action or executes a combination of dedicated hardware and computer instructions.

[0156] Furthermore, systems according to various embodiments may include a processor and logic integrated with and / or integrateable with the processor, the logic being configured to perform one or more of the process steps described herein. The processor may be any configuration as described herein, such as a discrete processor or processing circuitry including many components such as processing hardware, memory, I / O interfaces, etc. "Integrated with" means that the processor has logic embedded therewith as hardware logic, such as application-specific integrated circuits (ASICs), FPGAs, etc. "Executable by the processor" means that the logic is hardware logic; software logic, such as firmware, part of an operating system, part of an application; etc., or some combination of hardware and software logic that is accessible to the processor and configured to cause the processor to perform a certain function when executed by the processor. The software logic may be stored on local and / or remote memory of any memory type, as is known in the art. Any processor known in the art may be used, such as software processor modules and / or hardware processors, such as ASICs, FPGAs, central processing units (CPUs), integrated circuits (ICs), graphics processing units (GPUs), etc.

[0157] Figure 9 A network architecture 900 according to one method is shown. For example... Figure 9 As shown, multiple remote networks 902 are provided, including a first remote network 904 and a second remote network 906. A gateway 901 may be coupled between the remote network 902 and a neighboring network 908. In the context of this network architecture 900, networks 904 and 906 may each take any form, including but not limited to LANs, WANs such as the Internet, public switched telephone networks (PSTN), internal telephone networks, etc.

[0158] In use, gateway 901 serves as the entry point from remote network 902 to neighboring network 908. Thus, gateway 901 can function as a router capable of routing a given data packet to gateway 901, and as a switch providing the actual path for a given packet to and from gateway 901.

[0159] The system further includes at least one data server 914 coupled to a neighboring network 908, which is accessible from a remote network 902 via a gateway 901. It should be noted that the data server 914 may include any type of computing device / component. Multiple user devices 916 are coupled to each data server 914. Such user devices 916 may include desktop computers, laptop computers, handheld computers, printers, and / or any other type of logically-containing device. It should be noted that in some methods, user devices 911 may also be directly coupled to any other device in the network.

[0160] Peripheral device 920, or a series of peripheral devices 920, such as fax machines, printers, scanners, hard drives, networking and / or local data storage units or systems, may be coupled to one or more of networks 904, 906, and 908. It should be noted that databases and / or additional components may be used with or integrated into any type of network element coupled to networks 904, 906, and 908. In the context of this specification, a network element may refer to any component of the network.

[0161] According to some methods, the methods and systems described herein can be implemented using virtual systems and / or emulate one or more other systems, and / or on virtual systems and / or emulate one or more other systems, such as UNIX systems that virtually host a Microsoft Windows environment. In some methods, this virtualization and / or emulation can be enhanced by using VMware software.

[0162] In other approaches, one or more networks 904, 906, 908 can represent a cluster of systems commonly referred to as a "cloud." In cloud computing, shared resources such as processing power, peripherals, software, data, servers, etc., are provided to any system in the cloud on an on-demand basis, thereby allowing access to and distribution of services across many computing systems. Cloud computing typically involves internet connectivity between systems operating in the cloud; however, other technologies for connecting systems can also be used, as is known in the art.

[0163] Figure 10 It shows a method and Figure 9 A representative hardware environment associated with user equipment 916 and / or server 914. Figure 10A typical hardware configuration of a processor system 1000 according to a method is shown, the processor system having a central processing unit 1010 such as a microprocessor and a plurality of other units interconnected via a system bus 1012. In some methods, the central processing unit 1010 may include the above-referenced Figure 2 Any method described by one or more processors 210.

[0164] Figure 10 The processor system 1000 shown includes RAM 1014, read-only memory (ROM) 1016, and I / O adapter 1018. According to some methods, and in no way intended to limit the invention, the I / O adapter 1018 may include the above-referenced components. Figure 2 Any method described in the I / O adapter 218. Still refer to Figure 10 In the processor system 1000, the aforementioned components 1014, 1016, and 1018 can be used to connect peripheral devices, such as the storage subsystem 1020, to the bus 1012. In some methods, the storage subsystem 1020 may include... Figure 2 The data storage system 220 has a similar and / or identical configuration. According to one example, which is by no means intended to limit the invention, the storage subsystem 1020 may include non-volatile data storage cards, for example, in addition to... Figure 2 In addition to the RAID controller shown, it also has NVRAM memory cards, RAM, ROM and / or some other known types of non-volatile memory.

[0165] Continue to refer to Figure 10 User interface adapter 1022 is used to connect keyboard 1024, mouse 1026, speaker 1028, microphone 1032 and / or other user interface devices such as touch screen, digital camera (not shown) to bus 1012.

[0166] The processor system 1000 also includes a communication adapter 1034 for connecting the processor system 1000 to a communication network 1035 (e.g., a data processing network) and a display adapter 1036 for connecting a bus 1012 to a display device 1038.

[0167] The processor system 1000 may have an operating system residing on it, such as Microsoft Windows operating system (OS), Mac OS, UNIX OS, etc. It should be understood that the preferred method can also be implemented on platforms and operating systems other than those mentioned. The preferred method can be written using JAVA, XML, C and / or C++, or other programming languages ​​along with object-oriented programming methods. Object-oriented programming (OOP), which has become increasingly used for developing complex applications, can be used.

[0168] also, Figure 11 A storage system 1100 is shown that implements a higher-level (e.g., SSD) storage layer in combination with a lower-level (e.g., magnetic tape) storage layer according to a method. Note that, according to various methods, Figure 11 Some of the components shown can be implemented as hardware and / or software. Storage system 1100 may include a storage system manager 1112 for communicating with multiple media on at least one higher storage layer 1102 and at least one lower storage layer 1106. However, in other approaches, storage system manager 1112 may communicate with multiple media on at least one higher storage layer 1102 but not on a lower storage layer. The higher storage layer (one or more) 1102 preferably includes one or more random access and / or direct access media 1104, such as hard disks, non-volatile memory (NVM), NVRAM, solid-state memory in SSDs, flash memory, SSD arrays, flash memory arrays, etc., and / or other media mentioned herein or known in the art. According to the illustrative example, Figure 3 -4 illustrates an exemplary architecture that can be used as an SSD system for a higher storage tier 1102, depending on the desired approach.

[0169] Still referencing Figure 11 The lower storage layer 1106 preferably includes one or more lower-performance storage media 1108, including sequential access media such as magnetic tape and / or optical media in a magnetic tape drive, slower access HDDs, slower access SSDs, etc., and / or other media described herein or known in the art. One or more additional storage layers 1116 may include any combination of storage memory media desired by the designer of the system 1100. Therefore, in some methods, one or more additional storage layers 1116 may include... Figures 1-2 The SSD system architectures shown are similar or identical.

[0170] Storage system manager 1112 can be accessed via network 1110, for example... Figure 11The storage area network (SAN) or some other suitable network type shown communicates with storage media 1104, 1108 on the higher storage tier 1102 and the lower storage tier 1106. The storage system manager 1112 can also communicate with one or more host systems (not shown) via a host interface 1114, which may or may not be part of the storage system manager 1112. The storage system manager 1112 and / or any other component of the storage system 1100 can be implemented in hardware and / or software and can utilize processors (not shown) for executing commands of types known in the art, such as central processing units (CPUs), field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc. Of course, any arrangement of the storage system can be used, as will be apparent to those skilled in the art upon reading this specification.

[0171] In other methods, storage system 1100 may include any number of data storage layers, and each storage layer may include the same or different storage media. For example, each data storage layer may include the same type of storage media, such as HDD, SSD, sequential access media (tape in a tape drive, optical disc in an optical disc drive, etc.), direct access media (CD-ROM, DVD-ROM, etc.), or any combination of media storage types. In such a configuration, higher storage layer 1102 may primarily include SSD storage media for storing data in a higher-performance storage environment, and the remaining storage layers, including lower storage layer 1106 and additional storage layer 1116, may include any combination of SSDs, HDDs, tape drives, etc., for storing data in a lower-performance storage environment. Thus, data accessed more frequently, data with higher priority, data requiring faster access, etc., can be stored in higher storage layer 1102, while data without any of these attributes can be stored in additional storage layer 1116, which includes lower storage layer 1106. Of course, those skilled in the art, upon reading this specification, can design many other combinations of storage media types to implement different storage schemes based on the methods presented herein.

[0172] According to some methods, a storage system (such as 1100) may include logic configured to receive a request to open a dataset, logic configured to determine whether the requested dataset is stored in a plurality of associated portions in a lower storage layer 1106 of the hierarchical data storage system 1100, logic configured to move each associated portion of the requested dataset to a higher storage layer 1102 of the hierarchical data storage system 1100, and logic configured to combine the requested dataset from the associated portions onto the higher storage layer 1102 of the hierarchical data storage system 1100.

[0173] Of course, according to various embodiments, this logic can be implemented as a method or computer program product on any device and / or system.

[0174] It is clear that the various features of the aforementioned systems and / or methods can be combined in any way, resulting in multiple combinations from the description presented above.

[0175] It should also be understood that embodiments of the present invention may be provided in the form of services deployed on behalf of customers in order to provide services on demand.

[0176] Various embodiments of the invention have been described for illustrative purposes, but are not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or improvements to existing technologies on the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A computer-implemented method comprising, for each page in a memory block: A first calibration scheme is used to calibrate a given page in the block, wherein the first calibration scheme is configured to calculate a first number of independent read voltage offset values ​​and a first number of common read voltage offset values ​​for pages in the memory block. Attempt to read the calibrated given page; In response to determining that an error correction code failure occurred while attempting to read the calibrated given page, a second calibration scheme is used to recalibrate the given page in the block, wherein the second calibration scheme is configured to calculate a second number of independent read voltage offset values ​​and a second number of common read voltage offset values ​​for pages in the memory block; Attempt to read the given page of the recalibration; as well as In response to determining that an error correction code failure did indeed occur when attempting to read the given page of the recalibration, one or more instructions are sent to relocate the data stored in the given page. The first number of independent read voltage offset values ​​is less than the second number of independent read voltage offset values.

2. The computer-implemented method according to claim 1, comprising: In response to determining that no error correction code failure occurred when attempting to read the calibrated given page, it is determined whether the error count corresponding to the given page is within a first predetermined range; as well as In response to determining that the error count corresponding to the given page is within the first predetermined range, the second calibration scheme is used to recalibrate the given page in the block.

3. The computer-implemented method according to claim 1, comprising: In response to determining that no error correction code failure occurred when attempting to read the given page of the recalibration, it is determined whether the error count corresponding to the given page is within a second predetermined range; as well as In response to determining that the error count corresponding to the given page is within the second predetermined range, one or more instructions are sent to relocate the data stored in the given page.

4. The computer-implemented method according to claim 3, comprising: In response to determining that the error count corresponding to the given page is not within the second predetermined range, the error recovery counter corresponding to the given page is incremented; Determine whether the error recovery counter corresponding to the given page is within a third predetermined range; as well as In response to determining that the error recovery counter corresponding to the given page is within the third predetermined range, one or more instructions are sent to relocate the data stored in the given page.

5. The computer-implemented method of claim 1, wherein calibrating the given page in the block using the first calibration scheme comprises: Determine one or more read voltages associated with the page type corresponding to the given page; Determine one or more existing read voltage offset values ​​corresponding to the one or more read voltages; Calculate the correction offset for each of the existing read voltage offset values; as well as The existing read voltage offset value is updated using the correction offset.

6. The computer-implemented method according to claim 5, wherein, The correction offset is used to update the existing read voltage offset value based on a first mapping relationship extending between the correction offset and the existing read voltage offset value, wherein the first mapping relationship corresponds to the first calibration scheme.

7. The computer-implemented method of claim 1, wherein calibrating the given page in the block using the second calibration scheme comprises: Determine one or more read voltages associated with the page type corresponding to the given page; Determine one or more existing read voltage offset values ​​corresponding to the one or more read voltages; Calculate the correction offset for each of the existing read voltage offset values; as well as The existing read voltage offset value is updated using the correction offset.

8. The computer-implemented method according to claim 7, wherein, The correction offset is used to update the existing read voltage offset value based on a second mapping relationship extending between the correction offset and the existing read voltage offset value, wherein the second mapping relationship corresponds to the second calibration scheme.

9. The computer-implemented method according to claim 1, wherein the memory is a three-dimensional four-level cell NAND flash memory.

10. A computer program product comprising a computer-readable storage medium having program instructions embodied therein, the program instructions being readable and / or executable by a processor to cause the processor to target each page in a block of memory: The processor uses a first calibration scheme to calibrate a given page in the block, wherein the first calibration scheme is configured to calibrate a first number of independent read voltage offset values ​​and a first number of common read voltage offset values ​​of the pages in the memory block; The processor attempts to read the calibrated given page; In response to determining that an error correction code failure occurred while attempting to read the calibrated given page, the processor uses a second calibration scheme to recalibrate the given page in the block, wherein the second calibration scheme is configured to calibrate a second number of independent read voltage offset values ​​and a second number of common read voltage offset values ​​of the pages in the memory block; The processor attempts to read the given page of the recalibrated system. as well as In response to determining that an error correction code failure did indeed occur when attempting to read the given page of the recalibration, the processor sends one or more instructions to relocate the data stored in the given page. The first number of independent read voltage offset values ​​is less than the second number of independent read voltage offset values.

11. The computer program product according to claim 10, wherein, The program instructions can be read and / or executed by a processor to cause the processor to: In response to determining that no error correction code failure occurred when attempting to read the calibrated given page, the processor determines whether the error count corresponding to the given page is within a first predetermined range; as well as In response to determining that the error count corresponding to the given page is within the first predetermined range, the processor uses the second calibration scheme to recalibrate the given page in the block.

12. The computer program product according to claim 10, wherein, The program instructions can be read and / or executed by a processor to cause the processor to: In response to determining that no error correction code failure occurred when attempting to read the given page of the recalibration, the processor determines whether the error count corresponding to the given page is within a second predetermined range; as well as In response to determining that the error count corresponding to the given page is within the second predetermined range, the processor sends one or more instructions to relocate the data stored in the given page.

13. The computer program product according to claim 12, wherein, The program instructions can be read and / or executed by a processor to cause the processor to: In response to determining that the error count corresponding to the given page is not within the second predetermined range, the processor increments the error recovery counter corresponding to the given page; The processor determines whether the error recovery counter corresponding to the given page is within a third predetermined range; as well as In response to determining that the error recovery counter corresponding to the given page is within the third predetermined range, the processor sends one or more instructions to relocate the data stored in the given page.

14. The computer program product of claim 10, wherein calibrating the given page in the block using the first calibration scheme comprises: Determine one or more read voltages associated with the page type corresponding to the given page; Determine one or more existing read voltage offset values ​​corresponding to the one or more read voltages; Calculate the correction offset for each of the existing read voltage offset values; as well as The existing read voltage offset value is updated using the correction offset.

15. The computer program product according to claim 14, wherein, The correction offset is used to update the existing read voltage offset value based on a first mapping relationship extending between the correction offset and the existing read voltage offset value, wherein the first mapping relationship corresponds to the first calibration scheme.

16. The computer program product of claim 10, wherein calibrating the given page in the block using the second calibration scheme comprises: Determine one or more read voltages associated with the page type corresponding to the given page; Determine one or more existing read voltage offset values ​​corresponding to the one or more read voltages; Calculate the correction offset for each of the existing read voltage offset values; as well as The existing read voltage offset value is updated using the correction offset.

17. The computer program product according to claim 16, wherein, The correction offset is used to update the existing read voltage offset value based on a second mapping relationship extending between the correction offset and the existing read voltage offset value, wherein the second mapping relationship corresponds to the second calibration scheme.

18. The computer program product of claim 10, wherein the memory is a three-dimensional four-level cell NAND flash memory.

19. A system comprising: Multiple blocks of non-volatile random access memory (NVRAM) are configured to store data; processor; as well as Logic integrated with and / or potentially integrated by the processor, the logic being configured to, for each page in one block of the block: The processor uses a first calibration scheme to calibrate a given page in the block, wherein the first calibration scheme is configured to calibrate a first number of independent read voltage offsets and a first number of common read voltages of pages in the memory block; The processor attempts to read the calibrated given page; In response to determining that an error correction code failure occurred while attempting to read the calibrated given page, the processor uses a second calibration scheme to recalibrate the given page in the block, wherein the second calibration scheme is configured to calibrate a second number of independent read voltage offset values ​​and a second number of common read voltages of the pages in the memory block; The processor attempts to read the given page of the recalibrated system. as well as In response to determining that an error correction code failure did indeed occur when attempting to read the given page of the recalibration, the processor sends one or more instructions to relocate the data stored in the given page. The first number of independent read voltage offset values ​​is less than the second number of independent read voltage offset values.

20. The system of claim 19, wherein the logic is configured as follows: In response to determining that no error correction code failure occurred when attempting to read the calibrated given page, the processor determines whether the error count corresponding to the given page is within a first predetermined range; and In response to determining that the error count corresponding to the given page is within the first predetermined range, the processor uses the second calibration scheme to recalibrate the given page in the block.

21. The system of claim 19, wherein the logic is configured as follows: In response to determining that no error correction code failure occurred when attempting to read the given page of the recalibration, the processor determines whether the error count corresponding to the given page is within a second predetermined range; and In response to determining that the error count corresponding to the given page is within the second predetermined range, the processor sends one or more instructions to relocate the data stored in the given page.

22. The system of claim 21, wherein the logic is configured as follows: In response to determining that the error count corresponding to the given page is not within the second predetermined range, the processor increments the error recovery counter corresponding to the given page; The processor determines whether the error recovery counter corresponding to the given page is within a third predetermined range; as well as In response to determining that the error recovery counter corresponding to the given page is within the third predetermined range, the processor sends one or more instructions to relocate the data stored in the given page.

23. The system of claim 19, wherein the memory is a three-dimensional four-level cell NAND flash memory.

24. The system of claim 19, wherein calibrating the given page in the block using the first calibration scheme comprises: Determine one or more read voltages associated with the page type corresponding to the given page; Determine one or more existing read voltage offset values ​​corresponding to the one or more read voltages; Calculate the correction offset for each of the existing read voltage offset values; and The existing read voltage offset value is updated using the correction offset.

25. The system according to claim 24, wherein, The correction offset is used to update the existing read voltage offset value based on a first mapping relationship extending between the correction offset and the existing read voltage offset value, wherein the first mapping relationship corresponds to the first calibration scheme.

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