Method of manufacturing a semiconductor device using laser annealing

Abstract

Aspects of the present disclosure provide a semiconductor device and a method of manufacturing the semiconductor device. A channel hole is formed in a stack including alternating first and second layers. The stack is formed over a substrate of the semiconductor device. A gate dielectric layer and a channel layer are formed in the channel hole in sequence. Laser annealing is performed on the channel layer using a laser. An angle of incidence of the laser on an upper surface of the channel layer causes total internal reflection at an interface between the channel layer and the gate dielectric layer and at an interface between the channel layer and an insulating layer adjacent to the channel layer.

Description

BACKGROUND

[0001] As critical dimensions of devices in integrated circuits are scaled to the limits of common memory cell technology, newer technologies are being developed to achieve greater storage capacity. The vertical structure of 3D NAND memory devices involves more complex fabrication processes compared to planar transistor structures. As 3D NAND memory devices migrate to configurations with more layers of memory cells to achieve higher densities at lower cost-per-bit, improving the structure and its fabrication methods (e.g., forming high quality channel structures) becomes increasingly challenging. SUMMARY

[0002] According to aspects of the present disclosure, a method of fabricating a semiconductor device includes forming a channel hole in a stack including alternating first and second layers. The stack can be formed over a substrate of the semiconductor device. The method includes forming a gate dielectric layer over an inner surface of the channel hole and forming a channel layer over an inner surface of the gate dielectric layer. The channel layer can have an upper surface that is parallel to a surface of the substrate. The method includes performing laser annealing on the channel layer using a laser. An angle of incidence of the laser on the upper surface of the channel layer causes total internal reflection at (i) an interface between the channel layer and the gate dielectric layer and (ii) an interface between the channel layer and an insulating layer adjacent to the channel layer. The angle of incidence is between the laser and an axis that is perpendicular to the upper surface of the channel layer.

[0003] In an embodiment, an inner surface of the channel layer forms a first angle with the axis that is perpendicular to the upper surface of the channel layer, and the angle of incidence of the laser is determined based on the first angle, a first refractive index of the channel layer, a second refractive index of the gate dielectric layer, and a third refractive index of the insulating layer to cause the total internal reflection. The first refractive index can be greater than the second and third refractive indices.

[0004] In an example, the first angle is zero, and the inner surface of the channel layer has a cylindrical shape, and the angle of incidence is less than a threshold angle determined based on the first, second, and third refractive indices.

[0005] In an example, the first angle is greater than zero, and the inner surface of the channel layer has a conical cylindrical shape, and the angle of incidence is zero. In an example, the first angle is in a range of 0° to 10°.

[0006] In an embodiment, a wavelength of the laser is determined based on an absorption coefficient of the channel layer. In an example, the wavelength is in a range of 520 to 560 nanometers (nm).

[0007] In an example, the gate dielectric layer includes a silicon oxide blocking insulating layer, a silicon nitride charge storage layer, and a silicon oxide tunneling insulating layer formed in sequence over an inner surface of the channel hole, the channel layer includes polysilicon having a first refractive index, the tunneling insulating layer has a second refractive index, and the insulating layer includes silicon oxide having a third refractive index. The first refractive index can be greater than the second refractive index and the third refractive index.

[0008] In an example, the laser annealing is performed with a laser having a square beam shape.

[0009] In an embodiment, forming the channel layer includes depositing polysilicon over the inner surface of the gate dielectric layer, and performing the laser annealing causes a crystal size in a top portion of the channel layer to increase by 20% to 30%.

[0010] In an embodiment, the semiconductor device is subjected to a rapid thermal anneal.

[0011] In an example, after performing the laser annealing, single-crystal Si is formed in the top portion of the channel layer.

[0012] In an example, after performing the laser annealing, a distribution of crystal sizes in the top portion of the channel layer is more uniform than a distribution of crystal sizes in a bottom portion of the channel layer.

[0013] According to aspects of the present disclosure, a semiconductor device includes a transistor string disposed along a channel hole. The transistor string can be vertically stacked above a substrate along a vertical direction perpendicular to a surface of the substrate. The transistor string can include a gate dielectric layer formed over an inner surface of the channel hole and a channel layer formed over the inner surface of the gate dielectric layer including polysilicon having a first refractive index. The channel layer can have an upper surface parallel to the surface of the substrate. The first refractive index can be greater than a second refractive index of the gate dielectric layer. The transistor string can further include an insulating layer over the inner surface of the channel layer. The first refractive index is greater than a third refractive index of the insulating layer. An average crystal size of the polysilicon in a top portion of the channel layer is greater than an average crystal size of the polysilicon in a bottom portion of the channel layer.

[0014] In an embodiment, the average crystal size of the polysilicon in the top portion of the channel layer is at least 20% greater than the average crystal size of the polysilicon in the bottom portion of the channel layer.

[0015] The electrical conductivity of the top portion of the channel layer is greater than the electrical conductivity of the bottom portion of the channel layer.

[0016] The inner surface of the channel layer has a cylindrical shape or a tapered cylindrical shape, and the inner surface of the channel layer forms a first angle with an axis perpendicular to the upper surface of the channel layer, the first angle being in a range of 0 to 10 degrees.

[0017] In an example, the gate dielectric layer includes a silicon oxide blocking insulating layer, a silicon nitride charge storage layer, and a silicon oxide tunneling insulating layer formed in sequence over the inner surface of the channel hole, the insulating layer includes silicon oxide, and the second refractive index is a refractive index of the tunneling insulating layer.

[0018] In an example, single-crystal Si is formed in a top portion of the channel layer.

[0019] A distribution of crystal sizes in the top portion of the channel layer is more uniform than a distribution of crystal sizes in a bottom portion of the channel layer.

[0020] According to aspects of the present disclosure, a memory system includes a controller connected to a semiconductor device and the semiconductor device. The semiconductor device can include a transistor string disposed along a channel hole. The transistor string can be vertically stacked along a vertical direction perpendicular to a surface of a substrate, above a substrate of the semiconductor device. The transistor string can include a gate dielectric layer formed over an inner surface of the channel hole. The transistor string can include a channel layer formed over an inner surface of the gate dielectric layer including polysilicon having a first refractive index. The channel layer can have an upper surface parallel to the surface of the substrate. The first refractive index can be greater than a second refractive index of the gate dielectric layer. The semiconductor device can include an insulating layer over the inner surface of the channel layer. The first refractive index is greater than a third refractive index of the insulating layer. An average crystal size of the polysilicon in a top portion of the channel layer can be greater than an average crystal size of the polysilicon in a bottom portion of the channel layer. BRIEF DESCRIPTION OF DRAWINGS

[0021] Aspects of the disclosure can best be understood with reference to the following specific description and drawings. It should be kept in mind that the drawings referred to are only idealized representations and are not necessarily drawn to scale. In fact, the dimensions of the various features can have been arbitrarily increased or reduced for the sake of discussion.

[0022] Figures 1A-1C An example of light reflection and light refraction at an interface between two different media is shown in accordance with embodiments of the present disclosure.

[0023] Figure 1D An example of laser annealing of a semiconductor device is shown in accordance with embodiments of the present disclosure.

[0024] Figure 1E An example of laser annealing of a semiconductor device is shown in accordance with embodiments of the present disclosure.

[0025] Figure 2 、 Figures 3A-3B 、 Figures 4A-4B 、 Figures 5A-5B 、 Figures 6A-6B 、 Figures 7A-7B 、 Figures 8A-8B andFigures 9A-9B Cross-sectional views of a portion of a semiconductor device at various steps of an exemplary process are shown in accordance with example embodiments of the present disclosure.

[0026] Figure 10 A flow diagram outlining an exemplary process for fabricating a semiconductor device in accordance with embodiments of the present disclosure is shown.

[0027] Figures 11A-11B An example of a simulated power density distribution in a region of a semiconductor device in accordance with embodiments of the present disclosure is shown.

[0028] Figures 12A-12B An example of a simulated temperature distribution in a region of a semiconductor device in accordance with embodiments of the present disclosure is shown.

[0029] Figure 13 A block diagram of a memory system device (or memory system) 1300 in accordance with some examples of the present disclosure is shown. DETAILED DESCRIPTION

[0030] The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the making of a first feature over or on a second feature in the following description does not mean that the first feature is necessarily made over or on the second feature in three-dimensional reality. Rather, such descriptions are used herein to simplify the concepts of the description. For example, the making of a first feature over or on a second feature in the following description can include embodiments where the first feature and the second feature are formed directly contacting each other, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature and the second feature can not directly contact each other. Additionally, the present disclosure can repeat certain previously described features and / or descriptions in various examples. Such repetition is for simplicity and clarity and does not itself dictate a relationship between the various embodiments and / or configurations discussed.

[0031] Furthermore, spatial relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0032] A transistor string can be formed in a semiconductor device, such as a three-dimensional (3D) NAND memory device, by etching a trench hole in a stack including alternating first and second layers, and then forming a channel structure along an inner surface (or sidewall) of the trench hole. The trench hole and the channel structure can extend along a Z-direction that is perpendicular to a surface (also referred to as a working surface or working plane) of a substrate of the semiconductor device. The channel structure can include a channel layer and a gate dielectric layer (or gate dielectric structure). In some examples, the channel layer includes polycrystalline silicon (or polysilicon). Defects in the polysilicon, such as grain boundaries, can degrade the quality (e.g., electron mobility, conductivity) of the channel layer. Annealing techniques can be applied to anneal the polysilicon of the channel layer to increase the grain size of the channel layer and reduce defects. However, in some examples, certain annealing techniques are approaching the limit of grain size optimization.

[0033] Laser annealing can be performed to raise the temperature of the channel layer to a relatively high temperature (e.g., higher than rapid thermal annealing (RTA)). Moreover, laser annealing can allow for more localized temperature increases. For example, laser annealing can raise the temperature primarily within the trench hole (e.g., channel structure) without unduly interfering with (e.g., melting) other components in the semiconductor device. However, due to light absorption of the material(s) (e.g., polysilicon) on or near the surface of the semiconductor device (e.g., within the penetration depth of the light), the laser can not penetrate deeply into the channel layer.

[0034] The channel layer is disposed between the gate dielectric layer and the insulating layer. The channel structure and the insulating layer are primarily elongated structures along the Z-direction. Thus, when the first refractive index of the channel layer is higher than the refractive indices of the gate dielectric layer and the insulating layer, the trench hole filled with the channel structure and the insulating layer can act like an optical fiber. When a laser is incident on an upper surface (e.g., Figure 1D of the channel layer 733A in the structure 700) at an angle relative to the channel layer, the laser can propagate along the channel layer without exiting the channel layer due to total internal reflection. Moreover, the wavelength of the laser can be selected such that absorption by the gate dielectric layer is reduced or minimized compared to absorption by the channel layer. Figure 1D

[0035] ​According to embodiments of the present disclosure, a deep-penetration laser anneal method can be performed to anneal the channel layer. The deep-penetration laser anneal method can include one or more of: (i) annealing the channel layer prior to forming the light-absorbing structure(s) (e.g., polysilicon plug) over the channel layer; (ii) selecting a non-zero angle of the laser relative to the channel layer to achieve total internal reflection in the channel layer, and also allow light incident on the upper surface(s) of the respective structure(s) other than the channel layer (e.g., gate dielectric layer) to reach deeper portions of the channel layer at a non-zero angle; and (iii) selecting a wavelength of the laser such that the laser is primarily absorbed by the channel layer, while being less absorbed by the structure(s) other than the channel layer (e.g., gate dielectric layer).

[0036] Accordingly, the deep-penetration laser anneal method can result in a relatively deep penetration into the channel hole, and thus into the channel layer. The laser can be absorbed in a greater portion of the channel layer (e.g., in the entire channel layer or a substantial portion of the channel layer), and thus locally increase the temperature of the region including the channel structure, and in some cases, the immediately surrounding peripheral region of the channel structure, while the temperature of other components in the semiconductor device is reduced or minimized.

[0037] As described above, the quality (e.g., electron mobility, conductivity) of the channel layer can be critical to the performance of the semiconductor device (e.g., 3D NAND memory device). Grain boundaries are interfaces between two grains or crystallites in a polycrystalline material (e.g., polysilicon). Grain boundaries are defects in the crystal structure, and can reduce the electrical and thermal conductivity of the polycrystalline material. The crystallite size (also referred to as grain size or crystal size) of the polysilicon in the channel layer can be indicative of the quality of the channel layer. For example, a smaller grain size of the polysilicon increases the number of grain boundaries, which in turn increases the number of trapping states that trap electrons. As a result, more electrons are trapped by the grain boundaries and cannot move freely in the channel layer. As a consequence, the electron mobility and on-state current can be reduced. The subthreshold swing (SS) and threshold voltage can also increase.

[0038] To increase the grain size in the channel layer, in some examples, solid phase crystallization (e.g., RTA) can be used. However, in some examples, as the number of transistors in the transistor stack increases, the solid phase crystallization is approaching the limit of the grain size optimization. Alternatively, liquid phase crystallization can be used to further increase the grain size at a temperature higher than used in solid phase crystallization (e.g., higher than the melting point of silicon).

[0039] Laser annealing can be performed to raise the temperature of the channel layer to a relatively high temperature (e.g., higher than that achieved by RTA) and to raise the temperature primarily within the channel structure while limiting effects such as heating on other components in the semiconductor device. In some examples, the material(s) (e.g., polysilicon) on the surface of the semiconductor device can absorb a significant amount of light, and thus the laser can not penetrate deeply into the channel layer to increase the temperature of certain portions (e.g., bottom portions) of the channel layer. As described above, a deep-penetration laser anneal method can be performed.

[0040] Light can propagate along a straight line in a uniform medium (e.g., a medium with a uniformly distributed refractive index). When light is incident on an interface between two different media with two different refractive indices, the light can change the direction of propagation, and light reflection (or reflection) and light refraction (or refraction) can occur. In certain cases, light is completely (or totally) reflected at the interface without refraction, and thus experiences total internal reflection (TIR) at the interface.

[0041] Figures 1A-1C Examples of light reflection and light refraction at an interface between two different media are shown in accordance with embodiments of the present disclosure. In Figure 1A In, light (e.g., an incident light ray) propagating in a first medium 190 with a first refractive index n1 is incident on an interface 183 between the first medium 190 and a second medium 191 with a second refractive index n2. A portion of the energy in the incident light ray can be reflected back into the first medium 190 as a reflected light ray, and the remaining portion of the energy in the incident light ray can propagate into the second medium 191 as a refracted light ray.

[0042] The incident angle θ1 is defined as the angle between a surface normal 184 perpendicular to the interface 183 and the direction of propagation of the incident light ray. The reflection angle θ r is defined as the angle between the surface normal 184 and the direction of propagation of the reflected light ray and is equal to the incident angle θ1. The refraction angle θ2 is defined as the angle between the surface normal 184 and the direction of propagation of the refracted light ray. Based on the first refractive index n1, the second refractive index n2, and the incident angle θ1, the refraction angle θ2 can be determined using Snell’s law as follows:

[0043] n1 Sin θ1 = n2 Sin θ2 (Equation 1)

[0044] As can be seen from Equation 1, when the second refractive index n2 is less than the first refractive index n1, the refraction angle θ2 is greater than the incident angle θ1. As the incident angle θ1 increases, the refraction angle θ2 reaches 90°, as Figure 1B shown. The incident angle θ1 at which the refraction angle θ2 is 90° is referred to as the critical angle θc. When the incident angle θ1 is greater than the critical angle θc, the light is totally reflected at the interface 183 without refraction, and thus experiences total internal reflection (TIR). CBased on Equation 1, the critical angle θ is determined as follows. C :

[0045] θ C =arcsin(n2 / n1) (Equation 2)

[0046] As the incident angle θ1 continues to increase, it exceeds the critical angle θ C The light is completely reflected back to the first medium 190 and the energy is confined within the first medium 190, such as... Figure 1C As shown.

[0047] like Figures 1A-1C As shown, when light propagates from a first medium 190 with a refractive index n1 to a second medium 191 with a refractive index n2, and the refractive index n1 is greater than the refractive index n2, when the incident angle θ1 is greater than the critical angle θ C TIR occurs. In some examples, the first medium 190 is referred to as a medium that is optically denser than the second medium 191.

[0048] TIR can be used for laser annealing of semiconductor devices. According to embodiments of this disclosure, a channel hole can be formed in a stack comprising alternating first and second layers. The stack can be formed over a substrate of the semiconductor device, and the alternating first and second layers are stacked along a Z-direction perpendicular to the surface of the substrate. A gate dielectric layer can be formed above the inner surface of the channel hole. Subsequently, a channel layer having a first refractive index n1 can be formed above the inner surface of the gate dielectric layer. The channel layer can have an upper surface planar with respect to the surface of the substrate. The first refractive index n1 can be greater than a second refractive index n2 of the gate dielectric layer and a third refractive index n3 of an insulating layer adjacent to the channel layer. A deep-penetration laser annealing method can be performed on the channel layer using a laser, wherein the incident angle of the laser on the upper surface of the channel layer causes TIR to occur at the interface between the channel layer and the gate dielectric layer and at the interface between the channel layer and the insulating layer. Additional steps can be used to form the gate structure of a transistor string.

[0049] In some embodiments, a laser can be used to perform a deep penetration laser annealing method on the channel layer, wherein the incident angle of the laser on the upper surface of the channel layer causes TIR to occur at (i) the interface between the channel layer and the gate dielectric layer or (ii) the interface between the channel layer and the insulating layer.

[0050] Figure 1D Laser annealing (e.g., deep-penetration laser annealing method) of a semiconductor device 100 according to an embodiment of this disclosure is illustrated. The semiconductor device 100 may be a non-volatile memory device, such as a 3D NAND flash memory device, wherein transistors (e.g., memory cells) may be stacked in multiple transistor strings along the Z-direction to increase storage density. ReferenceFigure 1D The region 300A of the semiconductor device 100 may include a gate dielectric layer 437A and a channel layer 733A sequentially formed in a channel via 230A. The gate dielectric layer 437A may be disposed between the channel layer 733A and a gate structure to be subsequently formed. The gate dielectric structure 437A may extend in the Z direction.

[0051] The channel via 230A, gate dielectric structure 437A, channel layer 733A, and insulating layer 820A can have any suitable shape, size, and material. Figure 1D In the example shown, the channel via 230A, the inner surface 162A of the gate dielectric structure 437A, the inner surface 161A of the channel layer 733A, and the insulating layer 820A have a cylindrical shape. The gate dielectric structure 437A may include multiple dielectric layers, such as a tunneling insulating layer 434A, a charge storage layer 435A, and a barrier insulating layer 436A, sequentially stacked above the channel layer 733A. Reference Figure 1D The inner surface of the tunneling insulating layer 434A is the inner surface 162A of the gate dielectric layer 437A and is cylindrical.

[0052] The channel layer 733A has a first refractive index n1, the tunneling insulating layer 434A has a second refractive index n2, the charge storage layer 435A has a refractive index n4, the blocking insulating layer 436A has a refractive index n5, and the insulating layer 820A has a refractive index n3. Whether light propagating in the channel layer 733A undergoes TIR can depend on the first refractive index n1 of the channel layer 733A and the refractive indices (e.g., n2 and n3) of the two layers adjacent to the channel layer 733A (e.g., the tunneling insulating layer 434A and the insulating layer 820A). When the first refractive index n1 of the channel layer 733A is greater than the refractive indices n2 and n3 of the tunneling insulating layer 434A and the insulating layer 820A, respectively, the structure 170A including the channel layer 733A, the tunneling insulating layer 434A, and the insulating layer 820A (also referred to as the fiber-like structure 170A) behaves in a manner similar to that of an optical fiber. The channel layer 733A can serve as the core of the fiber-like structure 170A, and the tunneling insulation layer 434A and the insulation layer 820A can serve as the cladding layers of the fiber-like structure 170A. Structure 170A is located inside the channel aperture 230A.

[0053] For structure 170A, the inner surface 161A of the channel layer 733A has a cylindrical shape. In a cross-sectional view perpendicular to the surface of substrate 101, for example... Figure 1D The top portion of the inner surface 161A is a straight line 151A parallel to the Z direction, and therefore the fiber axis C of the channel layer 733A (or structure 170A) is parallel to the straight line 151A. zAAlso parallel to the Z direction. The straight line 151A can be referred to as a line of intersection of the inner surface 161A of the channel layer 733A and a plane that is perpendicular to the surface of the substrate 101. The straight line 151A forms a first angle with an axis that is perpendicular to the upper surface 181A of the channel layer 733A. The inner surface of the channel layer 733A forms a first angle with an axis that is perpendicular to the upper surface 181A of the channel layer 733A. The axis is also the Z direction.

[0054] In an embodiment, a second angle (also referred to as an angle of incidence) between the laser light incident on the upper surface and an axis (also referred to as a surface normal) can be determined based on the first angle, the first refractive index n1, the second refractive index n2, and the third refractive index n3, such that the laser light incident on the upper surface of the channel layer 733A experiences total internal reflection.

[0055] Reference is made to Figure 1D , the light ray 193A is incident on the upper surface of the channel layer 733A (e.g., the first portion of the upper surface 181A) at an angle of incidence θ Figure 1D (in the Z direction in in (or the second angle) is less than an acceptance angle (also referred to as a threshold angle) θ zA parallel to the fiber axis C

[0056] A portion of the light ray 193A enters the channel layer 733A as a refracted light ray (or light ray 194A). The light ray 194A is incident on an interface between the channel layer 733A and the insulating layer 820A (also the inner surface 161 of the channel layer 733A) at an angle of incidence θ1. The angle of incidence θ1 is between the light ray 194A and a surface normal 198A of the interface. Subsequently, the light ray 194A is reflected back into the channel layer 733A as a light ray 195A. The light ray 195A is incident on an interface between the channel layer 733A and the tunneling insulating layer 434A (also the inner surface 162 of the tunneling insulating layer 434A) at an angle of incidence θ1. Subsequently, the light ray 195A is reflected back into the channel layer 733A as a light ray 196A. The above process can be repeated within the channel layer 733A until the light is absorbed in the channel layer 733A or exits the channel layer 733A.

[0057] In Figure 1D the illustrated example, the angle of incidence θ in (also referred to as the second angle) is less than an acceptance angle (also referred to as a threshold angle) θ aand light rays 194A-196A experience TIR in the channel layer 733A. Thus, light rays 194A and 196A do not enter the insulating layer 820A at the interface between the channel layer 733A and the insulating layer 820A (also the inner surface 161A of the channel layer 733A). Light ray 195A does not enter the gate dielectric layer 437A (e.g., the tunneling layer 434A) at the interface between the channel layer 733A and the tunneling insulating layer 434A (also the inner surface 162A of the tunneling insulating layer 434A). The acceptance angle Θ a is the angle between the optical fiber axis C zA of the structure 170A and the Z direction at which the angle of incidence θ C of the light rays 194A-196A becomes the critical angle θ a . Thus, the acceptance angle Θ a may depend on the refractive indices n1, n2, and n3. The acceptance angle Θ zA is a measure of the light collecting ability of the fiber-like structure 170A and can be measured as the half angle of the acceptance cone (e.g., the largest cone of light that can enter or exit the fiber-like structure 170A).

[0058] In general, the optical fiber axis (e.g., the optical fiber axis C zA ) of a fiber-like structure (e.g., the fiber-like structure 170A) can form any suitable angle with the Z direction. In Figure 1D , the optical fiber axis C zB of the fiber-like structure 170A is parallel to the Z direction. In Figure 1E , the optical fiber axis C S of the fiber-like structure 170B is angled at an angle Θ S relative to the Z direction. Figure 1D The above description of Figure 1E may apply mutatis mutandis to .

[0059] Referring to Figure 1E , the semiconductor 100 includes a region 300B. The region 300B can include a gate dielectric layer 437B and a channel layer 733B formed in the channel hole 230B in sequence. The gate dielectric layer 437B, the channel layer 733B, and the channel hole 230B can be the same as the gate dielectric layer 437A, the channel layer 733A, and the channel hole 230A, respectively, except that the inner surface 162B of the gate dielectric layer 437B, the inner surface 161B of the channel layer 733B, and the shape of the channel hole 230B are a tapered cylindrical shape. As shown in Figure 1E , in a cross-sectional view perpendicular to the surface of the substrate 101, the top portion of the inner surface 161B is a straight line 151B that forms an angle Θ S relative to the Z direction and Θ zB .is not zero. Thus, the fiber axis C of the channel layer 733B (or the fiber-like structure 170B) parallel to the straight line 151B zB forms an angle θ with respect to the Z direction S . The straight line 151B is referred to as a tangent line of the inner surface 161B of the channel layer 733B to a plane perpendicular to the surface of the substrate 101. The straight line 151B forms a first angle with respect to the Z direction, where the first angle is θ S .

[0060] As described above, the gate dielectric layer 437B can be disposed between the channel layer 733B and a gate structure to be formed later. The gate dielectric structure 437B can include a plurality of dielectric layers stacked in order over the channel layer 733B, for example, a tunnel insulating layer 434B, a charge storage layer 435B, and a blocking insulating layer 436B.

[0061] The channel layer 733B has a first refractive index n1, the tunnel insulating layer 434B has a second refractive index n2, the charge storage layer 435B has a refractive index n4, the blocking insulating layer 436B has a refractive index n5, and the insulating layer 820B has a refractive index n3. When the first refractive index n1 of the channel layer 733B is greater than the refractive indices n2 and n3 of the tunnel insulating layer 434B and the insulating layer 820B, respectively, the structure 170B including the channel layer 733B, the tunnel insulating layer 434B, and the insulating layer 820B can behave in a manner similar to an optical fiber. The channel layer 733B can act as a core of the fiber-like structure 170B. The tunnel insulating layer 434B and the insulating layer 820B can act as cladding layers of the fiber-like structure 170B.

[0062] In an embodiment, a second angle between laser light incident onto the upper surface and an axis (or a surface normal) perpendicular to the upper surface 181B of the channel layer 733B (e.g., the Z direction in S , can be determined based on the first angle (e.g., θ Figure 1E , the first refractive index n1, the second refractive index n2, and the third refractive index n3, such that the laser light incident onto the upper surface of the channel layer 733B experiences total internal reflection.

[0063] Referring to Figure 1E , the light ray 193B is perpendicularly incident onto the upper surface (e.g., the first portion of the upper surface 181B) of the channel layer 733B along the Z direction, and thus the angle of incidence θ Figure 1E (or the second angle) between the light ray 193B and the surface normal (e.g., the Z direction in in ) of the upper surface 181B is 0°. The surface normal forms an angle θ zB with respect to the fiber axis C S of the fiber-like structure 170B.

[0064] A portion of ray 193B enters channel layer 733B as a refracted ray (or ray 194B). Ray 194B is incident at an angle θ1 onto the interface between channel layer 733B and tunneling insulating layer 434B (also the inner surface 162B of tunneling insulating layer 434B). The angle θ1 is between ray 194B and the surface normal 198B of interface 162B. Subsequently, ray 194B is reflected back to channel layer 733B as ray 195B. Ray 195B is incident at an angle θ1 onto the interface between channel layer 733B and insulating layer 820B (also the inner surface 161B of channel layer 733B). Subsequently, ray 195B is reflected back to channel layer 733B as ray 196B. The above process can be repeated within channel layer 733B until the light is absorbed in or exits from channel layer 733B.

[0065] exist Figure 1E In the example shown, the angle θ S This makes the incident angle θ1 greater than the critical angle θ at interface 162B. C1 The critical angle θ at interface 161B C2 Light rays 194B-196B undergo TIR within the channel layer 733B. Therefore, light ray 195B will not enter the insulating layer 820B at the interface between the channel layer 733B and the insulating layer 820B (which is also the inner surface 161B of the channel layer 733B). Light ray 194B will also not enter the gate dielectric layer 437B (e.g., the tunneling layer 434B) at the interface between the channel layer 733B and the tunneling insulating layer 434B (which is also the inner surface 162B of the tunneling insulating layer 434B). Figure 1E In, θ S =90°-θ1, and therefore when θ S Less than (90°-θ) C1 ) and (90°-θ C2 At this point, light rays 194B-196B undergo TIR in channel layer 733B. The critical angle θ at interface 162B... C1 θ can be determined using Equation 2. C1 =arcsin(n2 / n1), and the critical angle θ at interface 161B. C2 θ can be determined using Equation 2. C2 =arcsin(n3 / n1). In the example, the refractive indices n2 and n3 are the same, then θ C equal to θ C1 and θ C2 When θ S Less than (90°-θ) C At that time, light rays 194B-196B underwent TIR in the channel layer 733B.

[0066] refer toFigures 1D-1E The deep-penetration laser annealing method involves performing laser annealing before forming a light-absorbing structure above the channel layer. Figures 1D-1E In the example shown, the laser is incident directly onto the upper surface of the channel layer (e.g., 733A or 733B). Alternatively, one or more other layers that are transparent to the laser can be formed above the channel layer.

[0067] Refer again Figures 1D-1E Laser light incident on other regions (e.g., 437A, 437B, 820B, or mask 250) different from the channel layer (e.g., 733A or 733B) can initially propagate through these other regions before entering the channel layer. After entering the channel layer, the laser light can (i) propagate within the channel layer, (ii) be absorbed by the channel layer, or (iii) exit into the insulating layer (e.g., 820A or 820B) or the gate dielectric layer (e.g., 437A or 437B). In some examples, a portion of the laser light incident on other regions (e.g., ray 176A or 176B) penetrates deeper into the channel layer. For example, ray 176B can propagate a relatively long distance within the insulating layer 820B before incident on the interface between the insulating layer 820B and the channel layer 733B. Because absorption is reduced or minimized in other regions, the laser (e.g., beam 176A or 176B) can reach deeper parts of the channel layer. In some examples, due to reduced or minimized absorption in other regions, the laser or laser energy is concentrated within the channel layer.

[0068] According to embodiments of this disclosure, the wavelength or wavelength range used for the laser can be determined based on the absorption and penetration requirements of the channel layer (e.g., polycrystalline silicon). Greater absorption of the channel layer can lead to effective heating (and therefore annealing) of the channel layer, while less absorption can lead to deeper penetration. Therefore, based on the absorption coefficient of the channel layer (e.g., polycrystalline silicon), a laser with a green wavelength (e.g., 520-560 nm) can be determined to satisfy both the absorption and penetration requirements.

[0069] In embodiments, the channel layer comprises polysilicon. According to embodiments of this disclosure, after annealing using a deep-penetration laser annealing method, the average crystal size of the polysilicon in the channel layer (e.g., 733A or 733B) can be larger than the average crystal size of the channel layer annealed using a related technique (e.g., RTA). For example, the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B) can increase by at least 20%, for example, 20% to 30%, compared to the average crystal size of the channel layer annealed using a related technique (e.g., RTA).

[0070] In an example, the electrical conductivity in the channel layer (e.g., 733A or 733B) can be greater than the electrical conductivity of a channel layer annealed by a related art (e.g., RTA) anneal.

[0071] In an embodiment, after annealing by a deep penetration laser anneal method, the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B) can be greater (e.g., at least 20% greater) than the average crystal size of the polysilicon in the bottom portion of the channel layer (e.g., 733A or 733B). Due to the increase in the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B), the electrical conductivity of the top portion of the channel layer (e.g., 733A or 733B) can be greater than the electrical conductivity of the bottom portion of the channel layer (e.g., 733A or 733B).

[0072] In an example, single crystal Si can be formed in the top portion of the channel layer (e.g., 733A or 733B).

[0073] In an example, the distribution of crystal sizes in the top portion of the channel layer (e.g., 733A or 733B) is more uniform than the distribution of crystal sizes in the bottom portion of the channel layer.

[0074] Reference is made to Figures 1D-1E Region 300A or 300B is formed in the stack 110 above the substrate 101 of the semiconductor device 100. The stack 110 includes alternating first layers 122 and second layers (also referred to as insulating layers 124). The stack 110 can also include one or more additional layers, such as insulating layers 111 and 116 and layer 123, between the substrate 101 and the lowermost first layer 122(1). A mask layer or sacrificial layer 250 can be formed and patterned above the uppermost layer of the stack 110 (e.g., the uppermost second layer 124(1)) to protect the semiconductor device 100 during subsequent processing. The mask layer 250 can include one or more hard mask sub-layers 251-253, such as silicon nitride and silicon oxide.

[0075] Figure 2 、 Figures 3A-3B 、 Figures 4A-4B 、 Figures 5A-5B 、 Figures 6A-6B 、 Figures 7A-7B 、 Figures 8A-8B and Figures 9A-9B FIGS. 1-8 show cross-sectional views of a portion of a semiconductor device 100 at various steps of an exemplary process, in accordance with example embodiments of the present disclosure. Figure 10A flowchart showing an exemplary process 1000 for semiconductor fabrication for fabricating a semiconductor device 100 according to embodiments of the present disclosure is shown. The semiconductor device 100 can be a non-volatile memory device, such as a 3D NAND flash memory device, in which transistors can be memory cells and can be stacked along a Z direction to increase storage density. As used herein, a semiconductor device 100 can include transistors (e.g., field effect transistors and floating gate transistors), integrated circuits, semiconductor chips (e.g., memory chips including 3D NAND memory devices, logic chips on a semiconductor die), stacks of semiconductor chips, semiconductor packages, semiconductor wafers, etc.

[0076] The process 1000 begins at step S1001 and proceeds to step S1010. Referring to Figure 2 and Figure 10 At step S1010, a stack 110 can be formed over a substrate 101 of the semiconductor device 100. The stack 110 can include alternating first layers 122 and second layers 124. A plurality of strings of transistors can be formed in the stack 110. The substrate 101 can be any suitable substrate and can be processed with various suitable features. The substrate 101 can be formed of any suitable semiconductor material, such as silicon (Si), germanium (Ge), SiGe, compound semiconductors, alloy semiconductors, etc. Additionally, the substrate 101 can include various layers, including conductive layers or insulating layers formed on a semiconductor substrate. The substrate 101 can be a silicon-on-insulator (SOI) substrate. Further, the substrate 101 can include an epitaxial layer formed on an insulator. Depending on design requirements, the substrate 101 can include various doping configurations.

[0077] The stack 110 can be fabricated using various semiconductor processing techniques, such as photolithography, chemical vapor deposition (CVD) (including furnace CVD, low pressure CVD, etc.), physical vapor deposition (PVD), atomic layer deposition (ALD), dry etching, wet etching, chemical mechanical planarization (CMP), ion implantation, etc.

[0078] Insulating layers 111 and 116 and layer 123 can include any suitable insulating material having any suitable thickness. In some examples, insulating layer 111 includes Si02. In examples, insulating layer 111 has a thickness of about 18 nm. Layer 123 can include silicon nitride having a thickness of 10-100 nm, and insulating layer 116 can include Si02having a thickness of 130-180 nm.

[0079] First and second layers 122 and 124 are formed alternately above insulating layer 116 and can include, for example, any suitable dielectric material having different etch rates. For example, first layers 122 can be formed of silicon nitride, and second layers 124 can be formed by using a dielectric material (e.g., Si02) having an etch rate different from that of first layers 122. In various examples, in a subsequent step, layers 123 and first layers 122 are removed and replaced with respective gate structures.

[0080] First layers 122 can have different or the same thicknesses from one another. In examples, first layers 122 have a thickness in a range of 20 to 50 nanometers, for example, first layers 122 can have a thickness of about 35 nanometers. Any suitable deposition process (e.g., CVD, PVD, ALD, or any combination thereof) can be applied to form first layers 122.

[0081] Second layers 124 can have any suitable thickness (e.g., between 20 and 40 nm) and can be formed by performing CVD, PVD, ALD, or any combination thereof. In examples, second layers 124 have a thickness of 25 nm.

[0082] In examples, stack 110 can have a thickness of about 1-20 micrometers, for example, 8-10 micrometers. Any suitable number (e.g., 32, 64, 96, 128, etc.) of transistors or memory cells in a stack of transistors can be formed in stack 110. Accordingly, the number of first and second layers 122 and 124 can vary according to the number of memory cells in stack 110.

[0083] Referring to Figure 2 , mask layer 250 can include one or more hard mask sub-layers 251-253, such as silicon nitride and silicon oxide. In various embodiments, mask layer 250 can be patterned according to any suitable technique, such as a photolithography process (e.g., photolithography or e-beam lithography), which can further include photoresist coating (e.g., spin coating), soft bake, mask alignment, exposure, post-exposure bake, photoresist development, rinsing, drying (e.g., spin-drying and / or hard bake), etc.

[0084] Referring to Figure 3A , Figure 3B andFigure 10 At step S1020 of process 1000, a plurality of channel holes extending into the substrate 101 can be formed from the patterned mask layer 250 using any suitable process (e.g., dry etching) in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250.

[0085] In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3A In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250. Figure 3B In examples, the plurality of channel holes (e.g., 230A(l)-(4) in FIG. 2A or 230B(l)-(4) in FIG. 2B) can be formed in accordance with the patterned mask layer 250.

[0086] In some examples, a subsequent plasma ashing and wet cleaning can be applied to remove the remaining mask layer 250. Alternatively, the mask layer 250 remains over the stack 110 as shown in Figures 4A-4B , Figures 5A-5B , Figures 6A-6B , Figures 7A-7B , Figures 8A-8B and Figures 9A-9B .

[0087] During subsequent fabrication steps, a plurality of transistor strings (or stacks of transistors) are formed in the channel holes (e.g., Figure 3A 230A(1)-(4) or Figure 3B 230B(1)-(4)) in region 300A (also referred to as 300A) and region 300B (also referred to as 300B) of semiconductor device 100, respectively. For clarity, subsequent descriptions of Figure 1D , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A and Figure 9A will be based on channel hole 230A(3) (also referred to as 230A) in region 300A of Figure 3A . Subsequent descriptions of Figure 1E , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B and Figure 9B will be based on channel hole 230B(3) (also referred to as 230B) in region 300B of Figure 3B . The descriptions can be adapted as appropriate for other channel holes (e.g., 230A(1), 230A(2) and 230A(4) or 230B(1), 230B(2) and 230B(4)) in semiconductor device 100.

[0088] At step S1030 of process 1000, a gate dielectric layer is formed within the channel holes (e.g., 230A(1)-(4) or 230B(1)-(4)). Referring to Figure 4A and Figure 4B , a contact layer is formed in the channel holes. In Figure 4A , contact layer 331A is formed in channel hole 230A of region 300A. In Figure 4B , contact layer 331B is formed in channel hole 230B of region 300B. The contact layer (e.g., 331A or 331B) can be formed using silicon deposited via a selective epitaxial growth technique. The contact layer (e.g., 331A or 331B) can include single-crystal Si. In an example, the contact layer (e.g., 331A or 331B) has a thickness of 190 nm. An oxide layer, e.g., silicon oxide with a thickness of 2-5 nm, can subsequently be formed over the contact layer (e.g., 331A or 331B) by an oxidation process.

[0089] Subsequently, a gate dielectric layer is formed within the channel holes (e.g., 230A(1)-(4) or 230B(1)-(4)). Referring to Figure 5AA gate dielectric layer 437A is formed within the channel hole 230A. The gate dielectric layer 437A can be formed conformally by sequentially depositing a blocking insulating layer 436A, a charge storage layer 435A, and a tunneling insulating layer 434A in the channel hole 230A and over the contact layer 331A, respectively.

[0090] Referring to Figure 5B A gate dielectric layer 437B is formed within the channel hole 230B. The gate dielectric layer 437B can be formed conformally by sequentially depositing a blocking insulating layer 436B, a charge storage layer 435B, and a tunneling insulating layer 434B in the channel hole 230B and over the contact layer 331B, respectively.

[0091] The blocking insulating layer (e.g., 436A or 436B), the charge storage layer (e.g., 435A or 435B), and the tunneling insulating layer (e.g., 434A or 434B) can be formed using any suitable process, such as an ALD process, a CVD process, a PVD process, or a combination thereof.

[0092] The tunneling insulating layer (e.g., 434A or 434B) can be formed of SiO2, Si3N4, SiON, HfO2, Al2O3, etc. and have a thickness of, for example, 1 to 5 nm based on design requirements. The charge storage layer (e.g., 435A or 435B) having a thickness of 3 to 10 nm can be formed of silicon nitride, for example, and can also include quantum dots or nanocrystals. The blocking insulating layer (e.g., 436A or 436B) having a thickness ranging between 1 to 10 nm can include SiO2, HfO2, ZrO2, Al2O3, tantalum oxide, a combination thereof, etc., for example.

[0093] In an example, the blocking insulating layer (e.g., 436A or 436B) includes SiO2 formed by oxidizing a pre-formed silicon nitride layer via an insitu steam generation (ISSG) process, the charge storage layer (e.g., 435A or 435B) includes a multi-layer configuration formed of silicon nitride and silicon oxynitride, and the tunneling insulating layer (e.g., 434A or 434B) includes a multi-layer configuration formed of silicon oxide and silicon oxynitride. In an example, the gate dielectric layer (e.g., 437A or 447B) can have a thickness in a range of 5 to 25 nm according to design requirements.

[0094] At step S1040 of the process 1000, a channel layer can be formed in the channel hole. Referring to Figure 6A and Figure 6B The channel hole (e.g., 230A or 230B) is filled with a sacrificial layer (e.g., 510A in 230A or 510B in 230B). In Figure 5AIn the illustrated example, the trench hole 230A is completely filled by the sacrificial layer 510A. In some examples, the trench hole 230A is completely covered, however, partially filled by the sacrificial layer 510A. Figure 5B In the illustrated example, the trench hole 230B is completely filled by the sacrificial layer 510B. In some examples, the trench hole 230B is completely covered, however, partially filled by the sacrificial layer 510B.

[0095] Generally, the sacrificial layer (e.g., 510A or 510B) can be formed conformally by depositing one or more sacrificial materials (e.g., polysilicon, tungsten, and / or other materials) over the gate dielectric layer (e.g., 437A or 437B). The sacrificial layer (e.g., 510A or 510B) can be formed over the top surface (e.g., surface 181A or surface 181B) of the mask layer 250. The sacrificial layer (e.g., 510A or 510B) can be formed using any suitable process (e.g., an ALD process, a CVD process, a PVD process, or a combination thereof).

[0096] Referring to Figure 7A and Figure 7B a via (e.g., 620A or 620B) is formed in the trench hole (e.g., 230A or 230B) by removing portions of the gate dielectric layer (e.g., 437A or 437B) and the sacrificial layer (e.g., 510A or 230B) exposed by the pattern of the mask layer 250. The via (e.g., 620A or 620B) can also include a portion (e.g., 621A or 621B) formed in the contact layer (e.g., 331A or 331B). The via (e.g., 620A or 620B) can be formed using an etching process, such as a dry etching process.

[0097] Referring to Figure 8A and Figure 8B the sacrificial layer (e.g., 510A or 510B) is removed from the trench hole (e.g., 230A or 230B) by an etching process (e.g., a wet etching process, a dry etching process, or a combination thereof). In an example, the etching process is a wet etching process. The etching process can selectively remove the sacrificial layer (e.g., 510A or 510B) and minimally affect the contact layer (e.g., 331A or 331B), the gate dielectric layer (e.g., 437A or 437B), the first layer 122, and the second layer 124, etc., in the stack 110.

[0098] Furthermore, one or more semiconductor materials can be deposited inside the channel via (e.g., 230A or 230B) to form a channel layer (e.g., 733A or 733B) over the gate dielectric layer (e.g., 437A or 437B). The one or more semiconductor materials in the channel layer (e.g., 733A or 733B) can include intrinsic polysilicon, doped polysilicon, etc. In the example, the one or more semiconductor materials include a polysilicon layer deposited using a low-pressure CVD process. Other suitable deposition processes can also be applied to form the channel layer (e.g., 733A or 733B), such as PVD, ALD, or any combination thereof. The channel layer (e.g., 733A or 733B) can be conformally formed on the inner surface of the tunneling insulating layer (e.g., 434A or 434B) to have a thickness between 3 and 5 nm. In the example, the channel layer (e.g., 733A or 733B) is further annealed, for example, to improve the quality of the polysilicon layer. Alternatively, the channel layer (e.g., 733A or 733B) can be annealed after the formation of the sacrificial layer (e.g., 820A or 820B), such as... Figures 1D-1E As shown. Annealing processes including deep-penetration laser annealing can be used, as described in the reference. Figures 1D-1E As mentioned above.

[0099] In various embodiments, such as those referenced above Figures 1D-1E As described, the channel layer (e.g., 733A or 733B) has a first refractive index n1, the tunneling insulating layer (e.g., 434A or 434B) has a second refractive index n2, the charge storage layer (e.g., 435A or 435B) has a refractive index n4, and the barrier insulating layer (e.g., 436A or 436B) has a refractive index n5. According to embodiments of this disclosure, the first refractive index n1 of the channel layer (e.g., 733A or 733B) may be greater than the second refractive index n2 of the tunneling insulating layer (e.g., 434A or 434B). In an example, the channel layer (e.g., 733A or 733B) is formed of polycrystalline silicon, and the first refractive index n1 (e.g., the refractive index of polycrystalline silicon) is 4.14 at or near the wavelength of green light (e.g., 520 to 560 nanometers). The tunneling insulating layer (e.g., 434A or 434B) is formed of silicon oxide (e.g., SiO2), and the second refractive index n2 (e.g., the refractive index of SiO2) is 1.47 at or near the wavelength of green light (e.g., 520 to 560 nm). In the example, the blocking insulating layer (e.g., 436A or 436B) is formed of silicon oxide (e.g., SiO2), and n5 is equal to n2 (e.g., 1.47). In the example, the charge storage layer (e.g., 435A or 435B) is formed of silicon nitride, and n4 (e.g., the refractive index of silicon nitride) is 2.057 at or near the wavelength of green light (e.g., 520 to 560 nm).

[0100] In some examples, a sacrificial layer (e.g., 230A(l)-(4) or 230A(l)-(4)) can be formed in the trench hole. Referring to Figures 9A-9B , the via (e.g., 620A or 620B) can be filled with a sacrificial layer (also referred to as an insulating layer) (e.g., 820A or 820B). In Figure 8A the illustrated example, the via 620A is completely filled with the sacrificial layer 820A. In some examples, the via 620A is completely covered, however, the via 620A is partially filled with the sacrificial layer 820A. In Figure 8B the illustrated example, the via 620B is completely filled with the sacrificial layer 820B. In some examples, the via 620B is completely covered, however, the via 620B is partially filled with the sacrificial layer 820B. The sacrificial layer (e.g., 820A or 820B) can include a dielectric material, such as Si02, one or more high-K materials, etc.

[0101] The sacrificial layer (e.g., 820A or 820B) can have a refractive index n3. In examples, the sacrificial layer (e.g., 820A or 820B) is formed of Si02, and the refractive index n3 is the refractive index of Si02, such as 1.47 for a wavelength of green light (e.g., 520-560 nm). In examples, the second refractive index n2 and the refractive index n3 are the same and 1.47 for a wavelength of green light (e.g., 520-560 nm). According to embodiments of the present disclosure, the first refractive index n1 can be greater than the second refractive index n2 and the refractive index n3.

[0102] According to embodiments of the present disclosure, when the angle between the light before the light enters the semiconductor device 100 and the fiber axis of the trench layer (e.g., 733A or 733B) is within a certain range, the light incident on the upper surface of the trench layer (e.g., 733A or 733B) can experience TIR inside the trench layer, as described above with reference to Figure 1D and 1E .

[0103] Referring back to Figure 1D , when the angle of incidence θ ZA between the light ray 193A and the fiber axis C in of the trench layer 733A is less than the acceptance angle θ a , the light rays 194A-196A experience TIR in the trench layer 733A. Referring back to Figure 1E , when the angle θ ZB between the light ray 193B and the fiber axis C S of the trench layer 733B is less than (90°- θ C1 ) and (90°- θ C2 ), the light rays 194B-196B experience TIR in the trench layer 733B, where θC1 It is arcsin(n2 / n1), and the critical angle θ C2 It is arcsin(n3 / n1). In the example, the refractive indices n2 and n3 are the same, therefore when θ S Less than (90°-θ) C At that time, light rays 194B-196B underwent TIR in the channel layer 733B.

[0104] refer to Figure 1D , Figure 1E and Figure 10 At S1050, an annealing process including a deep-penetration laser annealing method can be performed on the channel layer in each channel hole (e.g., 230A(1)-(4) or 230B(1)-(4)), so that the laser undergoes TIR in the channel layer. At S1050, for Figure 1D The structure 170A shown has a laser (e.g., indicated by ray 193A) aligned with the fiber axis C of the channel layer 733A. ZA The angle between them (also the angle of incidence θ) in It was chosen to be less than the acceptance angle θ a Therefore, the laser (e.g., indicated by light rays 194A-196A) undergoes TIR in the channel layer 733A. Thus, the laser incident on the upper surface of the channel layer 733A is concentrated within the channel layer 733A.

[0105] At S1050, for Figure 1E The structure 170B shown has a laser (e.g., indicated by ray 193B) aligned with the fiber axis C of the channel layer 733B. ZB The angle θS between them was chosen to be less than (90° - θ). C1 ) and (90°-θ C2 Therefore, the laser (e.g., indicated by rays 194B-196B) undergoes TIR within the channel layer 733B. Consequently, the laser incident on the upper surface of the channel layer 733B is concentrated within the channel layer 733B. In the example, the angle θ S It was selected as less than 10°.

[0106] As described above, structures 170A-170B can be fiber-like structures as follows: The material composition of structures 170A-170B can be similar to that of optical fibers, wherein the first refractive index n1 of the channel layer (e.g., 733A or 733B) is greater than the refractive indices n2 and n3 of the tunneling insulating layer (e.g., 434A or 434B) and the insulating layer (e.g., 820A or 820B), respectively. The shape of structures 170A-170B is fiber-like, wherein structures 170A-170B are oriented along an axis (e.g., C). zA Or C zB) elongation. For example, along the axis of the structure 170A-170B (e.g., C zA or C zB ) is 2 microns, and the top width D1 of the channel hole (e.g., 230B) is 0.1 microns, and the length-to-top-width aspect ratio is 20. Thus, under certain conditions, light propagating in the channel layer (e.g., 733A or 733B) experiences TIR, similar to light propagating in a fiber core. Thus, light propagating in the channel layer can be confined in the channel layer without exiting the interface between the channel layer (e.g., 733A or 733B) and the insulating layer (e.g., 820A or 820B) and without exiting the interface between the channel layer (e.g., 733A or 733B) and the tunneling insulating layer (e.g., 434A or 434B).

[0107] In an example, the structure 170A-170B differs from a fiber in that light is absorbed in the channel layer (e.g., 733A or 733B) to heat the channel layer and then the channel layer is annealed. In addition, the absorption profile of the structure 170A-170B is such that the absorption coefficient of the channel layer (to be annealed) is significantly greater than the absorption coefficient of other layers adjacent to the channel layer (e.g., the tunneling insulating layer 434A or 434B and the insulating layer 820A or 820B). Thus, light can be absorbed primarily in the channel layer.

[0108] The laser annealing methods described in this disclosure, such as the deep-penetration laser annealing method, can be applied to other suitable structure(s) in a semiconductor device and are not limited to the structure 170A or 170B. For example, the deep-penetration laser annealing method can be applied to one or more other structures having one or more of the following properties: (i) having a material composition similar to the structure 170A-170B or a fiber; (ii) having a shape similar to the structure 170A-170B or a fiber; (iii) an absorption profile similar to the structure 170A-170B. In an example, the deep-penetration laser annealing method can be applied to heat (or anneal) a structure having a material composition similar to the structure 170A-170B or a fiber, where the refractive index of the structure is higher than the refractive index(es) of the adjacent layer(s).

[0109] The wavelength of the laser can be selected based on the absorption coefficient of the channel layer (e.g., 733A or 733B). In an example, a relatively large absorption coefficient is selected so that the energy absorbed by the channel layer can increase the temperature in the channel layer to rearrange the grains.

[0110] For example, polysilicon has a relatively large absorption coefficient for visible wavelengths covering approximately 400 to 700 nm. The peak absorption coefficient is at ultra violet (UV) wavelengths. The wavelength of the laser can also be selected based on laser energy, cost effectiveness, and / or other. According to embodiments of the present disclosure, a green light or green laser with a large absorption coefficient and low cost is selected, for example, with a wavelength range of 520-560 nm. Alternatively, certain wavelengths shorter than green light wavelength can also be used, for example, blue light, violet light, or ultra violet light.

[0111] The deep-penetration laser annealing method can be performed with a laser having any suitable beam shape and any suitable beam size, for example, a square beam shape (e.g., 1 mm x 1 mm). In an example, the square beam shape has a more uniform energy distribution than that of a line beam (or line spot). The square beam shape can better resemble the shape of a chip (e.g., a memory chip including a 3D NAND memory device) than that of a circular beam, and thus can more uniformly increase the temperature of the chip. Moreover, the beam size of the square beam shape can be controlled such that the chip can be uniformly irradiated. In an example, the laser is uniformly incident on the semiconductor device 100, for example, the upper surface (e.g., 181A or 181B). Figures 1D-1E The light rays shown in FIG. 2 are for illustration purposes and do not represent the actual energy distribution of the laser on the upper surface (e.g., 181A or 181B).

[0112] In an embodiment, the wavelength is in the green light wavelength range (e.g., 520-560 nm), the energy density is in the range of 0.5-1 J / cm2, the beam size is 1 mm x 1 mm (or can be the size covering the chip set area), and the pulse duration is 200 ns with a period of 1 ms. In an example, the size covering the chip set area is optimal. 2

[0113] In an embodiment, after the deep-penetration laser annealing method, the average crystal size of the polysilicon in the channel layer (e.g., 733A or 733B) can be greater than that of the channel layer annealed by a related art (e.g., RTA). For example, the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B) can be increased by at least 20%, for example, 20% to 30%, compared to that of the channel layer annealed by a related art (e.g., RTA).

[0114] In an example, the electrical conductivity in the channel layer (e.g., 733A or 733B) can be greater than that of the channel layer annealed by a related art (e.g., RTA).

[0115] Figures 11A-11B ​Example simulated power density profiles in a region (e.g., region 300B) of a semiconductor device according to embodiments of the disclosure are shown. The arc length (e.g., the length of the optical fiber axis C ZB of the channel layer 733B) is 1.9 microns. Figure 11A A two-dimensional power density profile in the ZY plane is shown. Figure 11B A one-dimensional power density profile along the arc length (e.g., the optical fiber axis C ZB of the channel layer 733B) is shown.

[0116] Figure 11A It is shown that the power density within the channel layer 733B can be significantly greater than the power density in other components in the region 300B. Thus, Figure 11A It is shown that as a result of TIR, laser light (indicated by power density) can be concentrated within the channel layer 733B.

[0117] Figure 11B It is shown that the power density increases approximately within the first 150 nm and then decreases with arc length. The increase in power density within the first 150 nm can be explained as follows: for locations in the channel layer 733B near the 150 nm arc depth, laser light that experiences TIR can reach the location. In addition, laser light that initially impinges on the gate dielectric layer 437B or the insulating layer 820B can also reach the location, thereby increasing the power density. For arc lengths shallower than 150 nm, the contribution of laser light that initially impinges on the gate dielectric layer 437B or the insulating layer 820B decreases. For arc lengths deeper than 150 nm, absorption by the channel layer 733B can significantly decrease the power density with increasing arc length.

[0118] Figures 12A-12B Example simulated temperature profiles in a region (e.g., region 300B) of a semiconductor device according to embodiments of the disclosure are shown. The arc length is 1.9 microns. Figure 12A A two-dimensional temperature profile in the ZY plane is shown. Figure 12B A one-dimensional temperature profile along the arc length (e.g., the optical fiber axis C ZB of the channel layer 733B) is shown.

[0119] Figure 12A It is shown that the temperature profile can be relatively uniform in a plane parallel to the surface of the substrate.

[0120] Figure 12A and Figure 12B It is shown that the temperature is relatively flat within the top 150 nm and then decreases with arc length. The temperature is approximately greater than 1200 °C for the top 600 nm.

[0121] In an example, the power density profile and the temperature profile of the quasi-optical fiber structure 170B, respectively, are similar toFigures 11A-11B and Figures 12A-12B as shown.

[0122] Using the power density profile and the temperature profile described above, the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B) can be greater than the average crystal size of the polysilicon in the bottom portion of the channel layer (e.g., 733A or 733B).

[0123] In an example, after the deep penetration laser annealing method, the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B) can increase by at least 20%, such as 20% to 30%, compared to the average crystal size of the bottom portion of the channel layer (e.g., 733A or 733B). Due to the increase in the average crystal size of the polysilicon in the top portion of the channel layer (e.g., 733A or 733B), the conductivity of the top portion of the channel layer (e.g., 733A or 733B) can be greater than the conductivity of the bottom portion of the channel layer (e.g., 733A or 733B).

[0124] After the deep penetration laser annealing method, the defects between the grains in the channel layer (e.g., 733A or 733B) can be significantly reduced, such as by 50%, the distribution of the grain size can be more uniform, and / or a single crystal can be formed at the top portion of the channel layer (e.g., 733A or 733B).

[0125] Subsequently, gate structures can be formed. Referring to Figures 1D-1E The second layer 122 and the layer 123 can be removed, and replaced with respective gate structures, thereby forming transistors with gate structures separated by insulating layers 124, which can electrically isolate the gate structures from each other.

[0126] Each gate structure may include one or more dielectric materials and one or more conductive materials, such as a high-k (high-k) material (also called a high-k layer) and a metal layer. The high-k layer may include any suitable material that provides a relatively large dielectric constant, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), etc. The metal layer may include a metal with high conductivity, such as tungsten (W), copper (Cu), etc. The gate structure may also include a binder layer disposed between the high-k layer and the metal layer. The adhesive layer may include refractory metals such as titanium (Ti), tantalum (Ta), and their nitrides, such as TiN, TaN, W₂N, TiSiN, TaSiN, etc. Depending on the desired characteristics of the semiconductor device 100, the gate structure can have any suitable thickness. The thickness can be in the range of 20 to 50 nm, for example, 35 nm. Furthermore, the thicknesses can be equal or different from each other. Then, process 1000 proceeds to step S1099 and terminates.

[0127] Additional steps may be provided before, during, and after process 1000, and for additional embodiments of process 1000, one or more of the above steps may be replaced, eliminated, adjusted, and / or performed in a different order. In an example, a deep-penetration laser annealing method may be performed after forming the channel layer (e.g., 733A or 733B) and before forming the sacrificial layer (e.g., 820A or 820B). S1050 may be appropriately adjusted. For example, if the vias (e.g., 620A or 620B) are filled with air or nitrogen, the refractive index n3 may be 1.

[0128] Various annealing processes can be combined to optimize the characteristics of the channel layer (e.g., electrical conductivity, thermal conductivity, and / or others). Various annealing processes can be used in any suitable order. For example, performing such annealing on semiconductor device 100... Figures 9A-9B The deep-penetration laser annealing method and RTA are illustrated. In the example, the top portion (e.g., at least 1 / 3 of the channel layer) of the channel layer (e.g., 733A or 733B) is annealed due to the deep-penetration laser annealing method and RTA, while the bottom portion of the channel layer is primarily annealed by RTA. After performing the deep-penetration laser annealing method, one or more light-absorbing structures may also be formed above the channel layer (e.g., 733A or 733B).

[0129] Various additional interconnect structures (e.g., metallization layers having conductive lines and / or vias) can be formed over the semiconductor device 100. Such interconnect structures electrically connect the semiconductor device 100 with other contact structures and / or active devices to form functional circuitry. Additional device features, such as passivation layers, input / output structures, etc., can also be formed.

[0130] The process 1000 can be combined with other process flows to fabricate other suitable semiconductor components (not shown) on the semiconductor device 100, such as other types of transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, etc. In various embodiments, the process 1000 can also be combined with additional process flows to fabricate other suitable circuitry, such as peripheral circuitry for driving memory cells, sense amplifiers for reading data stored in memory cells, decoding circuitry, and / or others. The steps of the process 1000 are merely exemplary and are not limiting.

[0131] Figure 13 A block diagram of a memory system device (or memory system) 1300 is shown in accordance with some examples of the present disclosure. The memory system device 1300 includes one or more semiconductor devices, such as shown by semiconductor devices 1311-1314, which are each configured similarly to the semiconductor device 100. In some examples, the semiconductor device 100 and the semiconductor devices 1311-1314 are semiconductor memory devices. In some examples, the memory system device 1300 is a solid state drive (SSD).

[0132] The memory system device 1300 includes other suitable components. In an example, the memory system device 1300 includes a controller or host controller 1302. For example, the memory system device 1300 includes an interface 1301 and the controller 1302 coupled together as shown. The memory system device 1300 can include a bus 1320 coupling (e.g., connecting) the host controller 1302 with the semiconductor devices 1311-1314. Additionally, the host controller 1302 is connected with the semiconductor devices 1311-1314, such as shown by respective control lines 1321-1324. Figure 13

[0133] The interface 1301 is suitably mechanically and electrically configured to connect between the memory system device 1300 and a host device, and can be used to transfer data between the memory system device 1300 and the host device.

[0134] ​The host controller 1302 is configured to connect the individual semiconductor devices 1311-1314 to the interface 1301 for data transfer. For example, the host controller 1302 is configured to provide an enable / disable signal to the semiconductor devices 1311-1314 to initiate data transfer by one or more of the semiconductor devices 1111-1114, respectively.

[0135] The host controller 1302 is responsible for carrying out various instructions within the memory system device 1300. For example, the host controller 1302 can perform bad block management, error detection and correction, garbage collection, and the like.

[0136] In some embodiments, the host controller 1302 is implemented using a processor chip. In some examples, the host controller 1302 is implemented using multiple microcontroller units (MCUs).

[0137] The features of several embodiments have been summarized above in order to provide a basic understanding of aspects of the disclosure. Those skilled in the art will realize that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also realize that such equivalent constructions do not depart from the spirit and scope of the disclosure, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the disclosure.

Claims

1. A method for fabricating a semiconductor device, comprising: forming a channel hole in a stack comprising alternating first and second layers, the stack formed over a substrate of the semiconductor device; forming a gate dielectric layer over an inner surface of the channel hole; forming a channel layer over an inner surface of the gate dielectric layer, the channel layer having an upper surface parallel to a surface of the substrate; performing laser annealing on the channel layer using a laser, wherein: an angle of incidence of the laser on the upper surface of the channel layer causes total internal reflection at an interface between the channel layer and the gate dielectric layer and an interface between the channel layer and an insulating layer adjacent to the channel layer, the angle of incidence between the laser and an axis perpendicular to the upper surface of the channel layer.

2. The method of claim 1, wherein: an inner surface of the channel layer forms a first angle with the axis perpendicular to the upper surface of the channel layer, and the angle of incidence of the laser is determined to cause the total internal reflection based on the first angle, a first refractive index of the channel layer, a second refractive index of the gate dielectric layer, and a third refractive index of the insulating layer, the first refractive index being greater than the second and third refractive indices.

3. The method of claim 2, wherein: the first angle is zero and the inner surface of the channel layer has a cylindrical shape, and the angle of incidence is less than a threshold angle determined based on the first, second, and third refractive indices.

4. The method of claim 2, wherein: the first angle is greater than zero and the inner surface of the channel layer has a tapered cylindrical shape, and the angle of incidence is zero.

5. The method of claim 4, wherein, the first angle is in a range of 0° to 10°.

6. The method of claim 1, wherein: a wavelength of the laser is determined based on an absorption coefficient of the channel layer.

7. The method of claim 6, wherein, the wavelength is in a range of 520 to 560 nanometers (nm).

8. The method of claim 1, wherein: the gate dielectric layer comprises a silicon oxide blocking insulating layer, a silicon nitride charge storage layer, and a silicon oxide tunneling insulating layer formed in sequence over the inner surface of the channel hole, the channel layer comprises polysilicon having a first refractive index, the tunneling insulating layer has a second refractive index, the insulating layer comprises silicon oxide having a third refractive index, and the first refractive index is greater than the second and third refractive indices.

9. The method of claim 1, wherein, the performing comprises: performing the laser annealing with the laser having a square beam shape.

10. The method of claim 1, wherein: forming the channel layer comprises depositing polysilicon over the inner surface of the gate dielectric layer, and performing the laser annealing causes a crystal size in a top portion of the channel layer to increase by 20% to 30%.

11. The method of claim 1, further comprising: performing rapid thermal annealing on the semiconductor device.

12. The method of claim 1, wherein, forming single-crystal Si in a top portion of the channel layer after performing the laser annealing.

13. The method of claim 1, wherein, After the laser annealing is performed, a distribution of crystal sizes in a top portion of the channel layer is more uniform than a distribution of crystal sizes in a bottom portion of the channel layer.

14. A semiconductor device comprising: a transistor string disposed along a channel hole, the transistor string being vertically stacked above a substrate along a vertical direction perpendicular to a surface of the substrate, the transistor string including: a gate dielectric layer formed over an inner surface of the channel hole; a channel layer formed over an inner surface of the gate dielectric layer, including polysilicon having a first refractive index, the channel layer having an upper surface parallel to the surface of the substrate, the first refractive index being greater than a second refractive index of the gate dielectric layer; and an insulating layer over an inner surface of the channel layer, the first refractive index being greater than a third refractive index of the insulating layer, wherein an average crystal size of the polysilicon in a top portion of the channel layer is greater than an average crystal size of the polysilicon in a bottom portion of the channel layer.

15. The semiconductor device of claim 14, wherein, the average crystal size of the polysilicon in the top portion of the channel layer is at least 20% greater than the average crystal size of the polysilicon in the bottom portion of the channel layer.

16. The semiconductor device of claim 14, wherein, a conductivity of the top portion of the channel layer is greater than a conductivity of the bottom portion of the channel layer.

17. The semiconductor device according to claim 14, wherein the inner surface of the channel layer has a cylindrical shape or a tapered cylindrical shape, the inner surface of the channel layer forms a first angle with an axis perpendicular to the upper surface of the channel layer, the first angle being in a range of 0° to 10°.

18. The semiconductor device according to claim 14, wherein the gate dielectric layer includes a silicon oxide blocking insulating layer, a silicon nitride charge storage layer, and a silicon oxide tunnel insulating layer formed over the inner surface of the channel hole in this order, the insulating layer includes silicon oxide, and the second refractive index is a refractive index of the tunnel insulating layer.

19. The semiconductor device of claim 14, wherein, a single crystal Si is formed in the top portion of the channel layer.

20. The semiconductor device of claim 14, wherein, a distribution of crystal sizes in the top portion of the channel layer is more uniform than a distribution of crystal sizes in the bottom portion of the channel layer.

21. A memory system comprising: a controller connected to a semiconductor device, and the semiconductor device including: a transistor string disposed along a channel hole, the transistor string being vertically stacked above a substrate along a vertical direction perpendicular to a surface of the substrate, the transistor string including: a gate dielectric layer formed over an inner surface of the channel hole; a channel layer formed over an inner surface of the gate dielectric layer, including polysilicon having a first refractive index, the channel layer having an upper surface parallel to the surface of the substrate, the first refractive index being greater than a second refractive index of the gate dielectric layer; and an insulating layer over an inner surface of the channel layer, the first refractive index being greater than a third refractive index of the insulating layer, wherein an average crystal size of the polysilicon in a top portion of the channel layer is greater than an average crystal size of the polysilicon in a bottom portion of the channel layer.

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