Integrated assembly and method of forming an integrated assembly

Abstract

Some embodiments include a vertically stacked memory device having alternating insulative levels and conductive levels. A memory cell is along the conductive levels. The conductive levels have a control gate region including a first vertical thickness, have a wiring region including a second vertical thickness that is less than the first vertical thickness, and have a tapered transition region between the first vertical thickness and the second vertical thickness. A charge blocking material is adjacent to the control gate region. A charge storage material is adjacent to the charge blocking material. A dielectric material is adjacent to the charge storage material. A channel material extends vertically along the vertically stacked and is adjacent to the dielectric material. The memory cell includes the control gate region, and includes regions of the charge blocking material, the charge storage material, the dielectric material, and the channel material. Some embodiments also include methods of forming integrated assemblies.

Description

[0001] Relevant patent data

[0002] This application relates to U.S. Patent Application No. 16 / 681,200, filed November 12, 2019, entitled “Integrated Assemblies and Methods of Forming Integrated Assemblies,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] An integrated assembly (e.g., a memory device) and a method for forming the integrated assembly. Background Technology

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory and has many uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, computers and other devices are increasingly using flash memory in solid-state drives instead of conventional hard drives. As yet another example, flash memory is prevalent in wireless electronic devices because it allows manufacturers to support new communication protocols as it becomes standardized and provides the ability to remotely upgrade devices to enhance features.

[0005] NAND can be the basic architecture for flash memory and can be configured to include vertically stacked memory cells.

[0006] Before describing NAND in detail, it may be helpful to describe more generally the relationships within an integrated arrangement of memory arrays. Figure 1 shows a block diagram of a prior art device 1000, which includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns, and access lines 1004 (e.g., word lines for conducting signals WL0 to WLm) and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). The access lines 1004 and the first data lines 1006 are used to transfer information to and from the memory cells 1003. Row decoders 1007 and column decoders 1008 decode address signals A0 to AX on address lines 1009 to determine which of the memory cells 1003 will be accessed. Sensing amplifier circuitry 1015 operates to determine the information value read from the memory cell 1003. I / O circuitry 1017 transfers the information value between the memory array 1002 and the input / output (I / O) lines 1005. Signals DQ0 to DQN on I / O lines 1005 can represent information values ​​read from or to be written into memory cell 1003. Other devices can communicate with device 1000 via I / O line 1005, address line 1009, or control line 1020. Memory control unit 1018 controls memory operations to be performed on memory cell 1003 and utilizes signals on control line 1020. Device 1000 can receive supply voltage signals Vcc and Vss on first supply line 1030 and second supply line 1032, respectively. Device 1000 includes selection circuit 1040 and input / output (I / O) circuit 1017. Selection circuit 1040 can respond to signals CSEL1 to CSELn via I / O circuit 1017 to select signals on first data line 1006 and second data line 1013 that represent information values ​​to be read from or programmed into memory cell 1003. The column decoder 1008 can selectively activate the CSEL1 to CSELn signals based on the A0 to AX address signals on the address lines 1009. During read and program operations, the selection circuit 1040 can select the signals on the first data line 1006 and the second data line 1013 to provide communication between the memory array 1002 and the I / O circuit 1017.

[0007] The memory array 1002 of Figure 1 may be a NAND memory array, and Figure 2 shows a schematic diagram of a three-dimensional NAND memory device 200 that can be used with the memory array 1002 of Figure 1. Device 200 includes multiple strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked one on top of the other, wherein each charge storage device corresponds to, for example, one of thirty-two layers (e.g., layers 0 to 31). The charge storage devices in corresponding strings may share a common channel region, for example, a region formed in a corresponding pillar of a semiconductor material (e.g., polysilicon), around which the string of charge storage devices is formed. In a second direction (X-X'), the multiple strings of each first group (e.g., sixteen first groups) may include, for example, eight strings sharing multiple (e.g., thirty-two) access lines (i.e., “global control gate (CG) lines”, also referred to as word lines (WL)). Each of the access lines may couple to a charge storage device within a layer. When each charge storage device includes a unit capable of storing two bits of information, charge storage devices coupled by the same access line (and therefore corresponding to the same level) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. On a third direction (Y-Y'), multiple strings in each second group (e.g., eight second groups) may include sixteen strings coupled by corresponding ones of eight data lines. The size of a memory block may include 1,024 pages and approximately 16 MB in total (e.g., 16 WL x 32 levels x 2 bits = 1,024 pages / block, block size = 1,024 pages x 16 KB / page = 16 MB). The number of strings, levels, access lines, data lines, first groups, second groups, and / or pages may be greater than or less than the number shown in Figure 2.

[0008] Figure 3 shows a cross-sectional view of a memory block 300 of the 3D NAND memory device 200 of Figure 2 in the X-X' direction. The memory block 300 contains fifteen strings of charge storage devices from one of the sixteen strings in the first group described in Figure 2. The multiple strings of the memory block 300 can be grouped into multiple subsets 310, 320, 330 (e.g., tile columns), such as tile columns. I , block column J and block list KEach subset (e.g., a block column) comprises a “partial block” of memory block 300. A global drain-side select-gate (SGD) line 340 may be coupled to multiple strings of SGDs. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding ones of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a corresponding subset (e.g., a block column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or disconnect the SGD of the corresponding partial block (e.g., a block column) of strings, independently of the SGDs of the strings of other partial blocks. A global source-side select-gate (SGS) line 360 ​​may be coupled to multiple strings of SGSs. For example, a global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via corresponding ones of a plurality of sub-SGS drivers 322, 324, 326, where each sub-SGS line corresponds to a corresponding subset (e.g., a block column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or disconnect the SGS of the corresponding sub-block (e.g., a block column) string, independent of the SGS of the strings of other sub-blocks. A global access line (e.g., a global CG line) 350 may couple to a charge storage device corresponding to a corresponding layer of each of the plurality of strings. Each global CG line (e.g., global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via corresponding ones of a plurality of sub-string drivers 312, 314, 316. Each of the sub-string drivers may simultaneously couple or disconnect the charge storage device corresponding to the corresponding sub-block and / or layer, independent of the charge storage devices of other sub-blocks and / or other layers. Charge storage devices corresponding to a subset (e.g., a partial block) and a layer may include “partial layers” (e.g., a single “piece”) of charge storage devices. Strings corresponding to a subset (e.g., a partial block) may be coupled to their counterparts in sub-sources 372, 374, and 376 (e.g., “piece source”), where each sub-source is coupled to a corresponding power source.

[0009] Alternatively, the NAND memory device 200 is described with reference to the schematic diagram in FIG4.

[0010] Memory array 200 includes word lines 2021 to 202 N and position lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string contains 2081 to 208 charge storage transistors. NCharge storage transistors can use floating gate materials (e.g., polysilicon) to store charge, or they can use charge trapping materials (e.g., silicon nitride, metal nanodots, etc.) to store charge.

[0012] Charge storage transistor 208 is located at the intersection of word line 202 and string 206. Charge storage transistor 208 represents a non-volatile memory cell for data storage. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source-side selected gate (SGS)) 210 and a drain select device (e.g., drain-side selected gate (SGD)) 212. Each source select device 210 is located at the intersection of string 206 and source select line 214, and each drain select device 212 is located at the intersection of string 206 and drain select line 215. Select devices 210 and 212 can be any suitable access device and are generally illustrated in blocks in FIG. 4.

[0013] The source of each source select device 210 is connected to a common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 corresponding to the NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 corresponding to the NAND string 2061. The source select device 210 is connected to the source select line 214.

[0014] The drain of each drain selector 212 is connected to the bit line (i.e., digital line) 228 at its drain contact. For example, the drain of drain selector 2121 is connected to bit line 2281. The source of each drain selector 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain selector 2121 is connected to the drain of the charge storage transistor 208N of the corresponding NAND string 2061.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 couples its control gate 236 to a word line 202. A column of the charge storage transistor 208 consists of transistors coupled to a given word line 228 within a NAND string 206. A row of the charge storage transistor 208 consists of transistors commonly coupled to a given word line 202.

[0016] The goal is to develop an improved NAND architecture and an improved method for manufacturing the NAND architecture. Attached Figure Description

[0017] Figure 1 shows a block diagram of a prior art memory device having a memory array containing memory cells.

[0018] Figure 2 shows a schematic diagram of the prior art memory array of Figure 1 in the form of a 3D NAND memory device.

[0019] Figure 3 shows a cross-sectional view of the prior art 3D NAND memory device of Figure 2 in the X-X' direction.

[0020] Figure 4 is a schematic diagram of a conventional NAND memory array.

[0021] Figure 5 It is a schematic cross-sectional side view of the integrated assembly of the area of ​​the example memory device.

[0022] Figure 5A yes Figure 5 A schematic cross-sectional top view of a portion of the integrated assembly, and along its... Figure 5 Line 5A-5A.

[0023] Figures 6 to 19 This is a schematic cross-sectional side view of the area of ​​the integrated assembly shown in the instance sequence process stage of the instance method for manufacturing an instance memory device. Detailed Implementation

[0024] Operation of a memory cell may include moving charge between a channel material and a charge storage material. For example, programming a memory cell may include moving charge (i.e., electrons) from the channel material into the charge storage material and then storing the charge within the charge storage material. Erasing a memory cell may include moving holes into the charge storage material to recombine with electrons stored in the charge storage material, thereby releasing the charge from the charge storage material. The charge storage material may include a charge trapping material (e.g., silicon nitride, metal nanodots, etc.). A problem with conventional memories is that the charge trapping material extends across multiple memory cells in the memory array, which may result in charge migration from one memory cell to another. Charge migration can lead to data retention problems. Some embodiments include memory devices (e.g., NAND architectures) with breaks in the charge trapping material in the regions between memory cells; and such breaks can advantageously hinder charge migration between memory cells.

[0025] Another problem encountered with conventional memory cells is that the control gate may be too narrow to achieve the desired fast programming and erasing of the memory cell. Some embodiments include memory devices with relatively wide control gates, which are customized to provide a wider program / erase window than is generally available in conventional architectures. The wide control gate can be combined with a customized narrow wiring structure (word line) to reduce unwanted parasitic capacitances between vertically stacked wiring structures. (Reference) Figures 5 to 19 Describe an example implementation.

[0026] refer to Figure 5 The structure (i.e., assembly, architecture, etc.) 10 comprises a vertically stacked 12 of alternating first layers 14 and second layers 16. The first layer 14 is a conductive layer, and the second layer 16 is an insulating layer.

[0027] Conductive level 14 is a memory cell level of the NAND configuration (also referred to herein as a word line level or wiring / control gate level). The NAND configuration comprises strings of memory cells (i.e., NAND strings), where the number of memory cells in a string is determined by the number of vertically stacked levels 14. NAND strings can include any suitable number of memory cell levels. For example, NAND strings can have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc. Vertical stacking 12 is indicated to extend vertically beyond the illustrated area to demonstrate that a higher density of memory cells is possible than... Figure 5 The diagram illustrates more vertically stacked layers.

[0028] Stack 12 is shown supported above substrate 18. Substrate 18 may include semiconductor materials; and may include, for example, monocrystalline silicon, substantially composed of monocrystalline silicon, or composed of monocrystalline silicon. Substrate 18 may be referred to as a semiconductor substrate. The term "semiconductor substrate" means any construction including semiconducting materials, including (but not limited to) bulk semiconducting materials, such as a semiconducting wafer (alone or in a combination including other materials) and layers of semiconducting materials (alone or in a combination including other materials). The term "substrate" refers to any support structure including (but not limited to) the semiconductor substrate described above. In some applications, substrate 18 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include one or more of, for example, refractory metal materials, barrier materials, diffusion materials, insulating materials, etc.

[0029] A gap is provided between stack 12 and substrate 18 to indicate that other components and materials may be available between stack 12 and substrate 18. Such other components and materials may include additional stack levels, source line levels, source-side selected gate (SGS), etc.

[0030] Insulation layer 16 includes insulating material 20. Insulating material 20 may include any suitable composition; and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0031] The conductive layer 14 includes a conductive region 22. The conductive region includes an inner conductive material 24 and an outer conductive material 26. The inner conductive material 24 can be considered as configured as a conductive core 25, and the outer conductive material 26 can be considered as configured as an outer conductive layer (liner) 27 extending along the periphery of the conductive core.

[0032] Conductive materials 24 and 26 may comprise any suitable conductive composition; for example, one or more of various metals (e.g., titanium, tungsten, cobalt, nickel, platinum, ruthenium, etc.), metal-containing compositions (e.g., metal silicides, metal nitrides, metal carbides, etc.), and / or conductive doped semiconductor materials (e.g., conductive doped silicon, conductive doped germanium, etc.). The compositions of conductive materials 24 and 26 may differ from each other. In some embodiments, core material 24 may comprise one or more metals (e.g., may include tungsten), and outer conductive material 26 may comprise one or more metal nitrides (e.g., may include titanium nitride). In some embodiments, material 26 may be referred to as a conductive liner material, and conductive material 24 may be referred to as a conductive core material.

[0033] Dielectric material 28 extends along the outer conductive material 26. Dielectric material 28 may be a dielectric barrier material and may include any suitable composition. In some embodiments, dielectric material 28 comprises a high-k material, wherein the term "high-k" means a dielectric constant greater than that of silicon dioxide. In some embodiments, dielectric material 28 may comprise one or more of AlO, HfO, HfSiO, ZrO, and ZrSiO, substantially composed of one or more of them, or composed of one or more of them; wherein the chemical formula indicates the principal component rather than a specific stoichiometry.

[0034] The conductive layer (word line layer) 14 includes a first region 30 having a first vertical thickness T1, and a second region (terminal region) 32 having a second vertical thickness T2 greater than the first vertical thickness. In some embodiments, the second vertical thickness T2 is greater than the first vertical thickness T1 by an amount ranging from about 10% to about 70%. In the illustrated embodiment, the first region 30 is approximately vertically centered relative to the second region 32.

[0035] Conductive layer 14 has a flared transition region (tapered transition region) 31 connecting the first region 30 to the second region 32 (i.e., between the first region 30 and the second region 32). In the illustrated embodiment, materials 24, 26, and 28 all have surfaces extending along a taper within the flared transition region. Specifically, material 28 has a peripheral surface 33 with a taper along the flared transition region 31, material 26 has a peripheral surface 35 with a taper along the flared transition region 31, and material 24 has a peripheral surface 37 with a taper along the flared transition region 31.

[0036] Charge blocking material 34 extends along terminal region 32. Charge blocking material 34 is configured to extend vertically through the continuous layers of stack 12. Charge blocking material 34 may include any suitable composition; and in some embodiments may include silicon oxynitride (SiON), substantially composed of silicon oxynitride, or composed of silicon oxynitride; wherein the chemical formula lists the main components rather than specific stoichiometry.

[0037] The charge blocking material 34 has a continuous layer having a first sidewall surface 39 adjacent to the layers 14 and 16 of the stack 12, and a second sidewall surface 41 opposite to the first sidewall surface. The first sidewall surface 39 has an undulating topography (first undulating topography) including a first recessed region 43 along the insulating layer 16, and the second sidewall surface 41 has an undulating topography (second undulating topography) including a second recessed region 45 along the conductive layer 14.

[0038] The charge blocking material 34 is adjacent to the dielectric barrier material 28 and is separated from the conductive material 26 of the terminal region 32 by the dielectric barrier material (high k material) 28.

[0039] The charge storage material 38 is adjacent to the charge blocking material and is disposed in vertically stacked segments 40. The segments 40 are along the conductive layer 14 and close to the terminal region 32 of such conductive layer. In the illustrated embodiment, the segments 40 of the charge storage material are within a second recessed region 45 defined by the undulating topography of the charge blocking material 34.

[0040] Segments 40 (i.e., segments of charge storage material 38) are perpendicularly spaced from each other by gaps 36. Charge storage material 38 may include any suitable composition. In some embodiments, charge storage material 38 may include a charge trapping material; for example, silicon nitride, silicon oxynitride, conductive nanodots, etc. For example, in some embodiments, charge storage material 38 may include silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride.

[0041] The dielectric material (i.e., tunneling material, gate dielectric material) 42 is adjacent to the charge storage material 38. The dielectric material 42 may include any suitable composition. In some embodiments, the dielectric material 42 may include one or more of, for example, silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, etc. The dielectric material 42 may be bandgap designed to achieve the desired electrical properties; and therefore may include a combination of two or more different materials.

[0042] Channel material 44 is adjacent to dielectric material 42 and extends perpendicularly along stack 12. Channel material 44 may include semiconductor materials; and may include any suitable composition or combination of compositions. For example, channel material 44 may include one or more of silicon, germanium, group III / V semiconductor materials (e.g., gallium phosphide), semiconductor oxides, etc.; wherein the term group III / V semiconductor material refers to semiconductor materials including elements selected from groups III and V of the periodic table (where group III and V are old nomenclature and are now referred to as groups 13 and 15). In some embodiments, channel material 44 may include silicon, and is substantially composed of or composed of silicon.

[0043] Insulating material 46 is adjacent to channel material 44. Insulating material 46 may include any suitable composition; and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide.

[0044] Figure 5A The diagram shows a top view of an area of ​​assembly 10, illustrating that channel material 44 can be configured as an annular ring surrounding insulating material 46. The illustrated configuration of the channel material can be considered as including a hollow channel configuration, wherein insulating material 46 is provided within the "hollow" space of the annular channel configuration. In other embodiments (not shown), the channel material may be configured as a solid pillar configuration.

[0045] Refer again Figure 5 The conductive layer 14 can be considered to include a control gate region 48 adjacent to the channel material 44 and a word line (wiring) region 50 adjacent to the control gate region. In the illustrated embodiment, the control gate region 48 includes a terminal region 32.

[0046] The control gate region 48, dielectric barrier material 28, charge blocking material 34, charge storage material 38, gate dielectric material 42, and channel material 44 are incorporated into the memory cell 52 (e.g., a NAND memory cell similar to the NAND memory cell described above with reference to Figures 1 to 4). The illustrated memory cell 52 forms part of a vertically extending string of memory cells. This string may represent a large number of substantially identical NAND strings formed during the manufacture of the NAND memory assembly (where the term "substantially identical" means identical within reasonable manufacturing and measurement tolerances).

[0047] Figure 5 The assembly 10 can be considered as corresponding to an instance memory device, wherein this memory device includes memory cells 52. The wiring region 50 can electrically couple the control gate 48 of the memory cells to other circuitry (e.g., a line decoder circuitry of the type described above with respect to FIG1).

[0048] It is worth noting that, in Figure 5In this configuration, in contrast to undulations, the channel material 44 is "flat" (i.e., substantially vertical with a continuous thickness and substantially straight). Flat channel material can positively influence series currents compared to non-flat configurations in some conventional designs. In some embodiments, the configuration of channel material 44 may be referred to as a "flat configuration."

[0049] In operation, charge storage material 38 may be configured to store information in memory cells 52. The value of the information stored in an individual memory cell (where the term "value" means one or more bits) may be based on the amount of charge (e.g., the number of electrons) stored in the charge storage region of the memory cell. The amount of charge in an individual charge storage region may be controlled (e.g., increased or decreased) based at least in part on the voltage value applied to the associated gate 48 and / or on the voltage value applied to the channel material 44.

[0050] Tunneling material 42 forms tunneling regions of memory cell 52. Such tunneling regions can be configured to allow the desired migration (e.g., transport) of charge (e.g., electrons) between charge storage material 38 and channel material 44. The tunneling regions can be configured (i.e., engineered) to achieve selected criteria, such as (for example) (but not limited to) equivalent oxide thickness (EOT). EOT quantifies the electrical properties (e.g., capacitance) of the tunneling region in terms of representative physical thickness. For example, EOT can be defined as the theoretical thickness of the silicon dioxide layer required to have the same capacitance density as a given dielectric, neglecting leakage current and reliability considerations.

[0051] The charge blocking material 34 is adjacent to the charge storage material 38 and provides a mechanism to block charge from flowing from the charge storage material 38 to the associated gate 48.

[0052] A dielectric barrier material 28 is provided between the charge blocking material 34 and the associated gate 48, and can be used to suppress charge carriers from tunneling backward from the gate 48 toward the charge storage material 38. In some embodiments, the dielectric barrier material 28 may be considered as forming a dielectric barrier region within the memory cell 52.

[0053] Figure 5 One embodiment has insulating material 20 throughout the entire insulating layer 16. In other embodiments, gaps may exist within the insulating layer.

[0054] Figure 5 The instance memory device 10 can be formed using any suitable processing. (See reference) Figures 6 to 19 Describe instance processing.

[0055] refer to Figure 6The construction (integrated assembly, integrated structure) 10 comprises alternating vertical stacks 12 of first layers 14 and second layers 16. The first layer 14 includes a first material 60, and the second layer 16 includes a second material 20 (as mentioned above). Figure 5 The first and second materials 60 may comprise any suitable composition and may be different from each other. In some embodiments, the first material 60 may comprise silicon nitride, be substantially composed of silicon nitride, or be composed of silicon nitride; and the second material 20 may comprise silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. Layers 14 and 16 may have any suitable thickness; and may be the same thickness as each other or may be different thicknesses relative to each other. In some embodiments, layers 14 and 16 may have a vertical thickness ranging from about 10 nanometers (nm) to about 400 nm. In some embodiments, layers 14 and 16 may have a thickness ranging from about 10 nm to about 50 nm.

[0056] Stack 12 is shown as being supported above base 18.

[0057] refer to Figure 7 This forms an opening 64 extending through the stack 12. The opening 64 has sidewalls 65 extending along the first material 60 and the second material 20. When viewed from above, the opening 64 may have a closed shape (circular, elliptical, polygonal, etc.), and in Figure 6 The sidewall 65 shown in the cross-section may be a portion of a single continuous sidewall extending around the closed shape of the opening 64. The opening 64 may represent... Figure 6 The process stages form a large number of substantially identical openings in the memory cells used to manufacture memory arrays (e.g., NAND architecture); where the term “substantially identical” means identical within reasonable manufacturing and measurement tolerances.

[0058] refer to Figure 8 The second layer 16 is recessed relative to the first layer 14 to form a cavity 62. The second layer 16 may be recessed to any suitable amount, and in some embodiments may be recessed to an amount ranging from about 3 nm to about 25 nm. The first layer 14 has a protruding end 63 extending beyond the recess of the second layer 16. The cavity 62 is recessed along the second layer 16 and is perpendicularly located between the protruding ends 63.

[0059] A third material 66 is formed around the protruding end 63 and extends within the cavity 62. The third material 66 narrows the cavity 62. The third material 66 may include any suitable composition; and in some embodiments may include silicon dioxide, be substantially composed of silicon dioxide, or be composed of silicon dioxide. The third material 66 may include any suitable thickness, and in some embodiments may have a thickness ranging from about 3 nm to about 25 nm. The third material is conformally deposited along layers 14 and 16 and may be deposited using any suitable methodology (e.g., atomic layer deposition, chemical vapor deposition, etc.).

[0060] refer to Figure 9 A fourth material 68 is formed within the narrowed cavity 62. The fourth material may include any suitable composition; and in some embodiments may include silicon (e.g., one or both of polycrystalline silicon and amorphous silicon), substantially composed of silicon, or composed of silicon.

[0061] A fourth material 68 may be deposited and then etched so that the fourth material 68 and the first material 60 together form a substantially flat vertical surface 67 along the interior of the opening 64.

[0062] refer to Figure 10 The area of ​​the third material 66 is removed to expose the protruding end 63 of the first layer 14, leaving the protruding structure 70 along the second layer 16. The protruding structure 70 is perpendicularly spaced from the protruding end 63 by an intermediate gap 72.

[0063] refer to Figure 11 , making the fourth material 68 ( Figure 10 Oxidation. In the illustrated embodiments, the fourth material 68 ( Figure 10 It includes silicon, and oxidation converts it into silicon dioxide, which is then combined with the silicon dioxide of the third material 66. Therefore, in Figure 11 During the processing stage, the prominent structure 70 may be essentially composed of silicon dioxide 66 or composed of silicon dioxide 66.

[0064] refer to Figure 12 This forms an additional first material 60 surrounding the protruding end 63, surrounding the protruding structure 70, and extending within the intermediate gap 72. The additional first material 60 will be merged with the material 60 of the first level 14, but will be presented as a different material 60 from the first level to help the reader visualize the additional first material 60.

[0065] refer to Figure 13The majority of the additional first material 60 is converted into charge-blocking material 34. This conversion may include the oxidation of silicon nitride of material 60 to form silicon oxynitride of charge-blocking material 34. Oxidation may utilize any suitable oxidant; including, for example, H2O, O2, O3, H2O2, etc. Notably, regions of the additional first material 60 extending into the intermediate gap 72 are not converted into charge-blocking material 34 due to geometric constraints (and / or other reasons) that prevent oxidants from reaching such regions of the additional first material 60. The remaining regions of material 60 within the intermediate gap 72 may be considered as unconverted regions 76.

[0066] The unconverted area 76 directly abuts the surface of the protruding end 63 of the first layer 14 and comprises the same material (60) as the first layer 14. Figure 14 Display and Figure 13 The same processing stage, but it displays the unconverted region 76 merged with the prominent end 63.

[0067] The charge blocking material 34 extends vertically through the stack 12 and has an edge 41 with an undulating morphology, the edge 41 defining a recessed region (cavity) 45 along the first layer 14. In some embodiments, the edge 41 of the charge blocking material 34 may be referred to as the inner edge because it runs along the interior of the opening 64.

[0068] refer to Figure 15 Charge storage material 38 is formed within the recess 45. The charge storage material 38 may be deposited and then etched such that the charge storage material 38 and the charge blocking material 34 together form a substantially flat vertical surface 77 along the interior of the opening 64. The etching of the charge storage material 38 can utilize any suitable conditions and etchant, and in some embodiments, this etching can utilize phosphoric acid.

[0069] refer to Figure 16 A dielectric material 42 is formed along a substantially flat vertical surface 77, a channel material 44 is formed adjacent to the dielectric material 42, and an insulating material 46 is formed adjacent to the channel material 44.

[0070] refer to Figure 17 Remove the first material 60 ( Figure 16 This leaves a gap 78 along the first layer 14. The first material 60 can be removed under any suitable conditions and with an etchant, and in some embodiments, this removal can be made using phosphoric acid.

[0071] refer to Figure 18 Within the void 78, dielectric barrier material 28, conductive material 26, and conductive material 24 are formed. Figure 17 Material 28 may be provided to first line the gap 78, then material 26 may be provided to further line the gap, and finally material 24 may be provided to fill the lined gap.

[0072] Figure 18 The first level 14 is similar to the above about Figure 5 The conductive level described.

[0073] Materials 66 and 20 along the second layer 16 may comprise the same composition as each other (e.g., both may comprise silicon dioxide), and thus such materials may be combined and may be represented as a single material 20, such as Figure 19 As shown in the image. Figure 19 The structure 10 is related to the above. Figure 5 The construction described is the same, and therefore can be considered as a memory device including vertically stacked memory cells 52.

[0074] The embodiments described herein advantageously provide a methodology for customizing gate lengths (i.e., the vertical thickness (T2) of the terminal region of the control gate 48) where such gate lengths are equal to or greater than the length of the memory node (i.e., the segment 40 of the charge storage material 38) within the memory cell (i.e., memory cell 52). This enables a desiredly wide program / erase window associated with the memory cell. Furthermore, the wiring region (word line region) 50 can be kept relatively narrow (relative to the control gate), which mitigates unwanted parasitic capacitances between vertically adjacent wiring regions. In some embodiments, gaps may be provided along the second layer 16 to further mitigate unwanted parasitic capacitances between vertically adjacent wiring regions 50.

[0075] The assemblies and structures discussed above can be used within integrated circuits (where the term "integrated circuit" means electronic circuitry supported by a semiconductor substrate) and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power supply modules, communication modems, processor modules, and special-purpose modules, and can comprise multi-layered, multi-chip modules. Electronic systems can be anything within a wide range of systems, such as (for example) cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0076] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable methodology now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0077] The terms “dielectric” and “insulating” are used to describe materials having insulating electrical properties. These terms are considered synonymous in this disclosure. The use of the term “dielectric” in some instances and the term “insulating” (or “electrically insulating”) in others provides a linguistic variation within this disclosure to simplify the premises of the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0078] The terms "electrical connection" and "electrical coupling" are both used in this disclosure. The terms are considered synonymous. Using one term in some instances and another in others provides linguistic variation within this disclosure to simplify the presuppositions of the appended claims.

[0079] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and the embodiments may be rotated relative to the shown orientation in some applications. The descriptions provided herein and the appended claims relate to any structure having the described relationships between various features, regardless of whether the structure is in or rotated relative to the specific orientation of the drawings.

[0080] The accompanying cross-sectional views show only the features in the plane of the cross-section and do not show the material behind the plane of the cross-section (unless otherwise indicated) in order to simplify the diagram.

[0081] When a structure is referred to above as "on another structure," "adjacent to," or "against" another structure, it may be directly on said other structure or there may be an intermediate structure present. In contrast, when a structure is referred to as "directly on another structure," "directly adjacent to," or "directly against" another structure, there is no intermediate structure present. The terms "directly below," "directly above," etc., do not indicate direct physical contact (unless explicitly stated otherwise), but rather indicate upright alignment.

[0082] A structure (e.g., a layer, material, etc.) may be described as “vertically extending” to indicate that the structure extends generally upward from the underlying substrate (e.g., a base plate). A vertically extending structure may or may not extend substantially orthogonally relative to the upper surface of the substrate.

[0083] Some embodiments include an integrated structure with alternating insulating and conductive layers stacked vertically. The conductive layers have a first region with a first vertical thickness, a terminal region with a second vertical thickness greater than the first vertical thickness, and a flared transition region between the first region and the terminal region. A charge-blocking material is adjacent to the terminal region. A charge-storing material is adjacent to the charge-blocking material and disposed in segments of the vertical stack. The segments are perpendicularly spaced from each other along the conductive layers and by gaps. A dielectric material is adjacent to the charge-storing material. A channel material is adjacent to the dielectric material.

[0084] Some embodiments include a vertically stacked memory device having alternating insulating and conductive levels. Memory cells are arranged along conductive levels. Each conductive level has a control gate region with a first vertical thickness, a wiring region with a second vertical thickness less than the first vertical thickness, and a tapered transition region between the first and second vertical thicknesses. A charge-blocking material is adjacent to the control gate region. A charge-storage material is adjacent to the charge-blocking material. A dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the vertical stack and is adjacent to the dielectric material. The memory cell includes a control gate region and regions containing charge-blocking material, charge-storage material, dielectric material, and channel material.

[0085] Some embodiments include a method of forming an integrated structure. Alternating first and second layers are formed in a vertical stack. The first layer includes a first material and the second layer includes a second material. An opening extending through the stack is formed. The second layer is recessed relative to the first layer. The first layer has protruding ends extending beyond the recessed second layer. A cavity is formed along the recessed second layer and perpendicularly between the protruding ends. A third material is formed around the protruding ends and extending within the cavity. The third material narrows the cavity. A fourth material is formed within the narrowed cavity. A region of the third material is removed to leave a protruding structure along the second layer. The protruding structure includes the fourth material. The protruding structure is perpendicularly spaced from the protruding ends by an intermediate gap. Additional first material is formed around the protruding ends and extending around the protruding structure and into the intermediate gap. Most of the additional first material is converted into a charge-blocking material. The region of the additional first material within the intermediate gap is an unconverted region. The unconverted region is directly adjacent to the surface of the protruding ends. The charge-blocking material extends vertically through the stack and has edges with undulating morphology, the edges defining a cavity along the first layer. A charge-storing material is formed within the cavity. Charge storage material and charge blocking material are combined to form a substantially flat surface. A dielectric material is formed along the substantially flat surface. Channel material is formed adjacent to the dielectric material. The first layer and the first material in the unconverted regions are removed to leave voids. A conductive material is formed within these voids.

[0086] In accordance with regulations, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the methods disclosed herein include exemplary embodiments. Therefore, the claims should be given the full scope as literal and should be properly interpreted in accordance with the doctrine of equivalence.

Claims

1. An integrated structure comprising: a vertical stack of alternating insulative levels and conductive levels; the conductive levels having a first region of a first vertical thickness, a terminal region having a second vertical thickness greater than the first vertical thickness, and a flared transition region between the first region and the terminal region; a conductive liner material in direct contact with the first region, the terminal region, and the flared transition region of the conductive levels; a dielectric barrier material in direct contact with the conductive liner material; a charge blocking material in direct contact with the dielectric barrier material and adjacent the terminal region; a charge storage material adjacent the charge blocking material and disposed in segments of the vertical stack, wherein the charge blocking material is configured as a continuous layer extending vertically between the charge storage material and the conductive liner material adjacent each of the terminal regions and having sidewalls with a contoured topography; the segments vertically spaced apart from one another along the conductive levels and by gaps; a dielectric material adjacent the charge storage material; and a via material adjacent the dielectric material, the insulative levels comprising insulative material extending within an overall structure over the first regions of the conductive levels, over the terminal regions, over the dielectric barrier material, and over portions of the charge blocking material, the overall structure comprising a terminal region having upper, lower, and side edges in physical contact with the charge blocking material.

2. The integrated structure of claim 1, wherein the conductive liner material extends along a peripheral surface of a conductive core material.

3. The integrated structure of claim 2, wherein the conductive liner material comprises titanium nitride and the conductive core material comprises tungsten.

4. The integrated structure of claim 3, wherein the conductive liner material of individual ones of the conductive levels has a peripheral surface extending along a taper within a flared transition region associated with the individual ones of the conductive levels.

5. The integrated structure of claim 4, wherein the conductive core material of the individual ones of the conductive levels has a peripheral surface also extending along the taper within the flared transition region associated with the individual ones of the conductive levels.

6. The integrated structure of claim 1, wherein the continuous layer has a first sidewall surface adjacent the insulative and conductive levels of the stack, and has a second sidewall surface in opposing relation to the first sidewall surface; wherein the first sidewall surface has a first contoured topography including a first recess region along the insulative levels; and wherein the second sidewall surface has a second contoured topography including a second recess region along the conductive levels.

7. The integrated structure of claim 6, wherein the segments of the charge storage material are within the second recess region.

8. The integrated structure of claim 1, further comprising a high-k material between the terminal region and the charge blocking material.

9. The integrated structure of claim 8, wherein the high-k material comprises one or more of the chemical formulas of AIO, HfO, HfSiO, ZrO, and ZrSiO; wherein the one or more chemical formulas indicate a primary constituent rather than a specific stoichiometry.

10. The integrated structure of claim 1, wherein the channel material is planar along the vertical stack.

11. A memory device comprising: a vertical stack of alternating insulative levels and conductive levels; memory cells along the conductive levels; the conductive levels having control gate regions comprising a first vertical thickness, having wiring regions comprising a second vertical thickness that is less than the first vertical thickness, and having tapered transition regions between the first vertical thickness and the second vertical thickness; an outer conductive layer material in direct contact with the control gate regions, the wiring regions, and the tapered transition regions of the conductive levels; a high-k material in direct contact with the outer conductive layer material; a charge blocking material in direct contact with the high-k material and adjacent the control gate regions; a charge storage material adjacent the charge blocking material, wherein the charge blocking material is configured as a continuous layer that extends vertically between the charge storage material and the outer conductive layer material adjacent each of the control gate regions and has sidewalls that possess a relief profile; a dielectric material adjacent the charge storage material; a channel material extending vertically along the vertical stack and adjacent the dielectric material; and the memory cells include the control gate regions and include regions of the charge blocking material, the charge storage material, the dielectric material, and the channel material, the insulative levels comprising insulative material that extends over the wiring regions, over the control gate regions, over the high-k material, and over portions of the charge blocking material within an overall structure that includes a terminal region having upper, lower, and side edges that physically contact the charge blocking material.

12. The memory device of claim 11, wherein each conductive level comprises a conductive core at least partially surrounded by the outer conductive layer, wherein the conductive core comprises a composition that is different than the outer conductive layer; and wherein the high-k material is between the outer conductive layer and the charge blocking material.

13. The memory device of claim 12, wherein the conductive core comprises one or more metals, and wherein the outer conductive layer comprises a metal nitride.

14. The memory device of claim 13, wherein: the conductive core comprises tungsten; the outer conductive layer comprises titanium nitride; and the high-k material comprises one or more of the chemical formulas of AIO, HfO, HfSiO, ZrO, and ZrSiO, wherein the one or more chemical formulas indicate a primary constituent rather than a specific stoichiometry.

15. The memory device of claim 11, wherein the charge storage material is a charge trapping material.

16. The memory device of claim 11, wherein the charge storage material comprises silicon nitride.

17. The memory device of claim 11, wherein the charge storage material is arranged in vertically stacked segments, the segments vertically spaced apart from one another by gaps.

18. A method of forming an integrated structure, comprising: forming a vertical stack of alternating first tiers and second tiers; the first tiers comprising a first material and the second tiers comprising a second material; forming an opening extending through the stack; recessing the second tiers relative to the first tiers; the first tiers having protruding ends extending beyond the recessed second tiers; cavities along the recessed second tiers and vertically between the protruding ends; forming a third material around the protruding ends and extending within the cavities, the third material narrowing the cavities; forming a fourth material within the narrowed cavities; removing regions of the third material to leave protruding structures along the second tiers, the protruding structures comprising the fourth material; the protruding structures vertically spaced apart from the protruding ends by intervening gaps; forming additional first material around the protruding ends and extending around the protruding structures and into the intervening gaps; converting a majority of the additional first material to a charge blocking material, regions of the additional first material within the intervening gaps being unconverted regions; the unconverted regions directly adjacent surfaces of the protruding ends; the charge blocking material extending vertically through the stack and having edges comprising a relief profile, the edges defining pockets along the first tiers; forming a charge storage material within the pockets; the charge storage material and the charge blocking material together forming a substantially planar surface; forming a dielectric material along the substantially planar surface; forming a channel material adjacent the dielectric material; removing the first material of the first tiers and the unconverted regions to leave voids; and forming a conductive material within the voids, wherein the conductive material within the voids forms a conductive tier; and wherein the conductive tier has a first region of a first vertical thickness, a second region of a second vertical thickness greater than the first vertical thickness, and a tapered transition region between the first region and the second region.

19. The method of claim 18, wherein the second region is between the first region and the charge blocking material.

20. The method of claim 18, further comprising forming a high-k material within the voids to line the voids prior to forming the conductive material within the voids.

21. The method of claim 18, wherein the conductive material comprises a conductive core material and a conductive liner material at least partially surrounding a periphery of the conductive core material.

22. The method of claim 18, wherein the converting comprises oxidation of the additional first material.

23. The method of claim 18, wherein the charge storage material comprises a charge trapping material.

24. The method of claim 18, wherein the charge storage material comprises silicon nitride.

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