Test method for junction-to-case thermal resistance of silicon carbide metal oxide semiconductor field effect transistors

Abstract

The present disclosure relates to a method for testing the thermal resistance of the junction case of a silicon carbide metal oxide semiconductor field effect transistor, which includes powering on and testing the silicon carbide metal oxide semiconductor field effect transistor to obtain the bias voltage of the silicon carbide metal oxide semiconductor field effect transistor; under the condition of the bias voltage, testing the voltage V sd between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor and temperature data to obtain the functional relationship between the voltage V sd and temperature; combining the functional relationship, using the transient double-interface method to test and obtain the cooling time data of the silicon carbide metal oxide semiconductor field effect transistor; according to the cooling time data, calculating and obtaining the thermal resistance of the junction case of the silicon carbide metal oxide semiconductor field effect transistor. The present disclosure helps to eliminate the influence of the monotonicity of the MOSFET cooling test curve and improves the accuracy of the SiC MOSFET thermal resistance measurement.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuit thermal analysis, and in particular to a method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor. Background Art

[0002] With the development of semiconductor technology, metal oxide semiconductor field effect transistors, also known as metal-oxide-semiconductor field-effect transistors (MOSFET), are widely used in analog and digital circuits. Among them, silicon carbide metal oxide semiconductor field effect transistors (SiC MOSFET) have the characteristics of high blocking voltage, high operating frequency, strong high temperature resistance, low on-state resistance and low switching loss, and have broad application prospects in high-frequency and high-voltage power systems. The junction-to-case thermal resistance is a parameter that measures the heat diffusion capacity of semiconductor devices from the chip surface to the package surface. As a key indicator to characterize the thermal characteristics of SiC MOSFET, it plays an important role in the screening, identification and reliability evaluation of SiC MOSFET devices.

[0003] However, compared with Si-based MOSFET, SiC MOSFET has more defects in the interface between SiO2 and SiC of SiC MOSFET gate, which results in a large number of trapped charge carriers in this area. This causes the trapped charge carriers to move and form current during the current switching process of the electrical thermal resistance test, thus affecting the monotonicity of the cooling test curve of the device under test, for example Figure 1 The temperature drop test curve of the device under test shown in the figure first rises and then falls, which is inconsistent with the facts. This is mainly affected by the interface state of SiO2 and SiC. This problem makes the accuracy of thermal resistance measurement of SiC MOSFET devices need to be improved. Summary of the invention

[0004] Based on this, it is necessary to provide a method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor to address the problem that the thermal resistance of SiC MOSFET is difficult to accurately measure in the prior art, including:

[0005] Performing a power-on test on a silicon carbide metal oxide semiconductor field effect transistor to obtain a bias voltage of the silicon carbide metal oxide semiconductor field effect transistor;

[0006] Under the bias voltage condition, the voltage V between the source and the drain of the silicon carbide metal oxide semiconductor field effect transistor is tested. sd With the temperature data, the voltage V sd Functional relationship with temperature;

[0007] In combination with the functional relationship, a transient double interface method is used to test and obtain cooling time data of the silicon carbide metal oxide semiconductor field effect transistor;

[0008] The junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor is calculated according to the temperature drop time data.

[0009] In one embodiment, powering on a silicon carbide metal oxide semiconductor field effect transistor for testing to obtain a bias voltage of the silicon carbide metal oxide semiconductor field effect transistor comprises:

[0010] A fixed negative voltage V is applied to the gate of the SiC MOSFET. gs , the drain is loaded with a negative pulse voltage V ds ;

[0011] Draw different V gs The I between the source and drain of the SiC metal oxide semiconductor field effect transistor under the condition ds -V ds Characteristic curve;

[0012] Select the I ds -V ds When multiple curves in the characteristic curve overlap, V gs The absolute value of V is the minimum value. gs as the bias voltage.

[0013] The beneficial effect of this embodiment is to obtain the IV curve through electrical testing, determine the bias voltage of the gate and the source, and apply a fixed negative voltage V to the gate and the source respectively. gs , negative pulse voltage V ds , so that the negative voltage suppresses the charge carriers captured by the SiC MOSFET gate due to SiO2 and SiC interface defects, and suppresses the test artefacts formed by the disorder of electronic charge carriers in the subsequent cut-off current test.

[0014] In one embodiment, the SiC MOSFET is mounted on a test fixture, and a source and a drain of the SiC MOSFET are connected using Kelvin connection.

[0015] In one embodiment, the negative pulse voltage V ds The pulse duty cycle is less than or equal to 0.5%.

[0016] In one embodiment, the voltage V is obtained sd Functions of temperature include:

[0017] Applying the bias voltage between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor;

[0018] A constant test current I is loaded between the drain and source of the silicon carbide metal oxide semiconductor field effect transistor. M , record the voltage V between the drain and source of the SiC MOSFET sd ;

[0019] Placing the silicon carbide metal oxide semiconductor field effect transistor in a temperature device and setting the temperature parameters of the temperature device;

[0020] Record V at different temperature points sd Data, and perform linear fitting to obtain the voltage V sd Functional relationship with temperature.

[0021] Here the test current I M That is, the current I sd , current flows from source to drain.

[0022] In one embodiment, the temperature parameters include the temperature of the initial data collection point, the temperature step length, and the time required for temperature equilibrium.

[0023] In one embodiment, in combination with the functional relationship, using a transient double interface method to test and obtain the cooling time data of the silicon carbide metal oxide semiconductor field effect transistor includes:

[0024] Performing the processing steps of the first experiment, the processing steps of the first experiment comprising:

[0025] Fixing the silicon carbide metal oxide semiconductor field effect transistor to a test cold plate through a clamp, and applying the bias voltage between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor;

[0026] A constant heating current I is loaded between the drain and source of the silicon carbide metal oxide semiconductor field effect transistor. H and the constant test current I M ;

[0027] The heating current I H The heating current I is turned on and the heating current I is turned off when the temperature of the silicon carbide metal oxide semiconductor field effect transistor rises to a temperature equilibrium state. H , record the voltage V between the source and drain of the SiC MOSFET during the cooling process of the SiC MOSFET sd Experimental data, obtaining first cooling time data according to the functional relationship;

[0028] After executing the processing steps of the first experiment, executing the processing steps of the second experiment, the processing steps of the second experiment include:

[0029] Thermal conductive paste is applied between the silicon carbide metal oxide semiconductor field effect transistor and the contact surface of the cold plate, and the processing steps of the first experiment are repeated to obtain second cooling time data.

[0030] In one embodiment, the test current I M The value range is 1mA~100mA, and the test current I M The power generated does not exceed 0.1W.

[0031] In one embodiment, calculating the junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor according to the cooling time data includes:

[0032] According to the first cooling time data and the second cooling time data, respectively draw a first cooling curve when the silicon carbide metal oxide semiconductor field effect transistor is directly fixed on a test cold plate, and a second cooling curve when thermal conductive paste is applied between the contact surface of the silicon carbide metal oxide semiconductor field effect transistor and the cold plate;

[0033] A structure function algorithm is used to obtain a differential or integral structure function curve of the first cooling curve and the second cooling curve under dual interface test conditions, and the junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor is determined through the separation point of the structure function curve.

[0034] In this embodiment, a transient double-interface method is used to obtain the cooling time data of SiC MOSFET and a structure function model is used to parse out a structure function including thermal resistance and thermal capacitance, and the thermal structure characteristics on the heat transfer path of the SiC MOSFET device are analyzed. Not only the total thermal resistance from the junction to the environment of the SiC MOSFET device can be obtained, but also the thermal resistance of each structural layer of the device can be intuitively analyzed from the structure function curve diagram, and the measurement repeatability is good, thereby providing a direct and reliable basis for evaluating the packaging quality and heat dissipation performance of the SiC MOSFET device.

[0035] In one embodiment, before constructing the structure function curve, electrical correction is also included to adjust the heating current I H The electrical interference during switching is corrected. Since there is a heating current I H Switch to test current I M Therefore, there is electronic interference in the initial stage of the test, so a certain cut-off time t needs to be removed cut Signal points recorded during the period. Temperature change ΔT during this periodJ(tcut) Can not be ignored, during this period of time, ΔT J(tcut) It is approximately linearly related to the square root of time, and the junction temperature T at t=0 can be derived. J0 .

[0036] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects:

[0037] The present invention discloses a method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor, which adopts an electrical testing method based on a structure function, and tests the I between the source and drain of the SiC MOSFET. ds -V ds The cut-off voltage of MOSFET is obtained by using the characteristic curve. The device is heated while ensuring that SiC MOSFET is completely cut off. The voltage V between the source and drain of SiC MOSFET is used. sd As a temperature sensitive parameter, the fitting voltage V sd The functional relationship between the voltage V and the temperature can be used to obtain the cooling time data of the SiC MOSFET in the future. sd The temperature is obtained by the functional relationship with temperature, which avoids the influence of the SiO2 and SiC interface state on the direct temperature measurement, thus improving the accuracy of SiC MOSFET thermal resistance measurement and effectively supporting the screening, identification and reliability evaluation of SiC MOSFET devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A schematic diagram of a cooling curve of the device under test provided in the background technology;

[0040] Figure 2 It is a schematic flow chart of a method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor provided in one embodiment;

[0041] Figure 3 The I between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor provided in an embodiment ds -V ds Characteristic test circuit diagram;

[0042] Figure 4The I between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor provided in an embodiment ds -V ds Schematic diagram of characteristic curve;

[0043] Figure 5 for Figure 4 A partial enlarged view of part A;

[0044] Figure 6 A schematic diagram of a K-line test circuit for a temperature sensitivity coefficient of a silicon carbide metal oxide semiconductor field effect transistor provided in an embodiment;

[0045] Figure 7 A schematic diagram of K-line measurement fitting of the temperature sensitivity coefficient of a silicon carbide metal oxide semiconductor field effect transistor is provided in one embodiment;

[0046] Figure 8 A schematic diagram of a thermal resistance test circuit for a silicon carbide metal oxide semiconductor field effect transistor device provided in an embodiment;

[0047] Fig. 9 A schematic diagram of a cooling curve of a silicon carbide metal oxide semiconductor field effect transistor tested by a double interface method provided in an embodiment;

[0048] Fig.10 A schematic diagram of a differential structure function curve under dual interface test conditions provided in an embodiment;

[0049] Fig.11 Schematic diagram of an integrated structure function curve under dual interface test conditions provided in an embodiment. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0052] It should also be understood that the terms “include / comprises” or “having” and the like specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0053] See also Figure 2 The present invention provides a method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor, comprising the following steps:

[0054] S10: Performing a power-on test on the silicon carbide metal oxide semiconductor field effect transistor to obtain a bias voltage of the silicon carbide metal oxide semiconductor field effect transistor.

[0055] Silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) consists of three electrodes, namely gate (G), source (S) and drain (D), V sd is the source potential minus the drain potential, V ds is the drain potential minus the source potential, V gs = Gate potential minus source potential. MOSFET is a voltage-controlled device, that is, only a certain voltage (greater than the threshold voltage) is required between the gate (G) and the source (S) to turn on the MOSFET. When the MOSFET is powered on and works normally and can amplify the input signal without distortion, there is a suitable and stable static operating point, which is the bias voltage.

[0056] S20: Under bias voltage conditions, test the voltage V between the source and drain of the SiC MOSFET sd With the temperature data, the voltage V sd Functional relationship with temperature.

[0057] The bias voltage obtained in the gate application step S10 of the SiC MOSFET is applied, and the voltage V between the source and drain of the SiC MOSFET is measured under different constant temperature conditions. sd The corresponding relationship with temperature is shown in the voltage V sd As a temperature sensitive parameter, it is convenient for subsequent experiments to use the voltage V sd Get temperature data.

[0058] S30: In combination with the functional relationship, a transient double interface method is used to test and obtain cooling time data of the silicon carbide metal oxide semiconductor field effect transistor.

[0059] In this embodiment, the transient double interface method is used to obtain the cooling time data of SiC MOSFET, and other pre-set experimental methods can also be used to obtain it. When the transient double interface method is used to obtain the cooling time data of SiC MOSFET, the voltage V is recorded. sd and time, combined with the voltage V in step S20 sd The functional relationship with temperature is finally obtained to obtain the cooling time data of SiC MOSFET.

[0060] S40: Calculate the junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor according to the cooling time data.

[0061] A cooling curve can be drawn according to the cooling time data. In order to reduce various errors caused by the shell temperature, this embodiment uses a structure function algorithm to calculate the junction-to-shell thermal resistance of the SiC MOSFET.

[0062] The junction-to-case thermal resistance test method of the silicon carbide metal oxide semiconductor field effect transistor (SiC MOSFET) in this example does not require unsealing the device. It is an electrical thermal resistance test based on the structure function. By testing the I between the source and drain of the SiC MOSFET ds -V ds The characteristic curve is used to obtain the complete cut-off voltage of the MOSFET. The device is heated under the condition that the SiC MOSFET is completely cut off, and the voltage V between the source and drain of the SiC MOSFET is used. sd As a temperature-sensitive parameter. The specific description is as follows:

[0063] In the above example, in step S10, the following steps are specifically included:

[0064] S12: Load a fixed negative voltage V on the SiC MOSFET gate gs , the drain is loaded with a negative pulse voltage V ds .

[0065] In actual operation, the SiC MOSFET is installed in a test fixture, where the test fixture is preferably a high-precision test fixture dedicated to transistors. By applying a fixed negative voltage V to the gate and source respectively gs , negative pulse voltage V ds The negative voltage suppresses the charge carriers captured by the SiC MOSFET gate due to the interface defects of SiO2 and SiC, and suppresses the test artefacts formed by the disorder of electronic charge carriers in the subsequent current cut-off test.

[0066] like Figure 3 The SiC MOSFET source and drain I ds -V ds Characteristic test circuit, the source and drain of SiC MOSFET adopt Kelvin connection. Among them, the negative pulse voltage V ds The pulse duty cycle is less than or equal to 0.5%, reducing the impact of SiC MOSFET self-heating on the test.

[0067] S14: Draw different V gs I between the source and drain of SiC MOSFET under the condition ds -V ds Characteristic curves, such as Figure 4shown.

[0068] S16: Select I ds -V ds When multiple curves in the characteristic curve overlap, V gs The absolute value of V is the minimum value. gs as bias voltage.

[0069] Combined with Figure 5 As shown, Figure 4 The enlarged view of the part in the dotted rectangle A, where from right to left are V gs I between the source and drain of SiC MOSFET at 0V, -1V, -2V, ..., -8V ds -V ds The characteristic curve shows clearly that V gs When it is -5 V to -8 V, it overlaps near the inflection point, and it can be seen that the bias voltage is -5 V. Here, the bias voltage can make the body diode between the drain and source of the SiC MOSFET work normally and work in the linear region.

[0070] Step S20 in the above example obtains the voltage V sd The functional relationship with temperature includes the following steps:

[0071] S22: Apply a bias voltage between the source and drain of the SiC MOSFET.

[0072] like Figure 6 The SiC MOSFET test circuit shown in the figure loads a test voltage V between the source and drain of the SiC MOSFET. M According to the loaded voltage obtained in step S1, which is -5V, it can be known that the test voltage V M is -5 V.

[0073] S24: Load a constant test current I between the drain and source of the SiC MOSFET M (i.e. current I sd , current flows from source to drain), record the voltage V between the drain and source of SiC MOSFET sd , here we use voltage test equipment to collect and record voltage V sd .

[0074] S26: Place the SiC MOSFET in a temperature device and set the temperature parameters of the temperature device. The temperature device can control the temperature during the heating process. The temperature parameters include the temperature of the initial data collection point, the temperature step, and the time required for temperature balance. The temperature device here refers to a device with a heating function that can control the heating temperature and can regularly record the real-time temperature during the heating process.

[0075] S28: Record V at different temperature points sd Data is collected and linear fitting is performed to obtain the fitted linear function and goodness of fit.

[0076] According to V at different temperature points sd After the data is linearly fitted, the slope is calculated. The reciprocal of the slope is called the K factor of the device (in K / mV). Goodness of fit usually refers to the degree of fit of the regression line to the observed value. The statistic that measures the goodness of fit is the coefficient of determination (also known as the coefficient of determination) R². The maximum value of R² is 1. The closer the value of R² is to 1, the better the fit of the regression line to the observed value; conversely, the smaller the value of R², the worse the fit of the regression line to the observed value. Figure 7 As shown, the Y coordinate is V sd , the X coordinate is temperature, the fitted linear function is y=-0.0021x+2.6056, and the goodness of fit is R 2 =0.9992.

[0077] Step S30 in the above example specifically includes the following steps:

[0078] The processing steps of the first experiment are performed, and the processing steps of the first experiment include:

[0079] S32: Fix the SiC MOSFET to the test cold plate through a fixture, such as Figure 8 The thermal resistance test circuit of SiC MOSFET device shown in the figure loads bias voltage between the source and drain of SiC MOSFET. Here the fixture is preferably fixed by pneumatic ejector pressure, or other specific fixtures with good thermal insulation performance.

[0080] S34: Load a constant heating current I between the drain and source of the SiC MOSFET H and constant test current I M , where the test current I M The test current I in step S22 M same;

[0081] S36: Make the heating current I H The heating current I is turned on and turned off when the SiC MOSFET heats up and reaches a temperature equilibrium state. H , switch to test current I M , record the voltage V between the source and drain of SiC MOSFET during the cooling process of SiC MOSFET sd The first cooling time data is obtained according to the functional relationship obtained in step S28.

[0082] After executing the processing steps of the first experiment, the processing steps of the second experiment are executed. The processing steps of the second experiment include:

[0083] S38: Apply thermal paste between the SiC MOSFET and the contact surface of the cold plate, repeat the processing steps S31~S33 of the first experiment, and obtain the second cooling time data. Here, it is necessary to first remove the SiC MOSFET from the test cold plate, and then apply a uniform layer of thermal paste between the bottom of the SiC MOSFET device and the contact surface of the cold plate. Thermal paste is also called thermal interface material and has good thermal conductivity.

[0084] In the above steps S24 and S34, the test current I M The value range is 1mA~100mA, and the test current I M The power generated does not exceed 0.1W, avoiding significant temperature rise effects on SiC MOSFET devices.

[0085] In the above example, step S40 specifically includes the following steps:

[0086] S42: based on the first cooling time data and the second cooling time data obtained in step S3, respectively draw a first cooling curve when the SiC MOSFET is directly fixed on the test cold plate, and a second cooling curve when thermal conductive paste is applied between the contact surface of the SiC MOSFET and the cold plate.

[0087] Combination Fig. 9 As shown, the horizontal axis is time, the vertical axis is temperature, curve a1 is the first cooling curve of the first experiment, and curve b1 is the second cooling curve of the second experiment. Figure 1 The temperature drop curve of the SiC MOSFET device tested by the double interface method in the prior art is shown in FIG. Fig. 9 and Figure 1 contrast, Fig. 9 The temperature drop curve is monotonically decreasing. Figure 1 The temperature drop curve first rises and then drops, which is inconsistent with the facts. This is mainly affected by the interface state of SiO2 and SiC. Therefore, it can be seen that the monotonicity of the temperature drop test curve of this scheme is better.

[0088] S44: Obtain a differential or integral structure function curve of the first cooling curve and the second cooling curve under the dual-interface test condition using a structure function algorithm, and determine the junction-to-case thermal resistance of the SiC MOSFET through the separation point of the structure function curve.

[0089] According to the structural function theory model proposed by V. Szekely et al., any thermal model can be equivalent to a network model with thermal resistance Rth and thermal capacitance Cth in parallel. By testing to obtain the transient response curve of temperature, supplemented by structural function analysis, the internal structural information of SiC MOSFET devices can be analyzed, and the various structures on the heat conduction path can be layered for structural analysis.

[0090] Since the thermal impedance curve of SiC MOSFET is measured twice in step S30, the first time is when SiC MOSFET directly contacts the test cold plate, and the test environment of SiC MOSFET is under low thermal conductivity conditions, and the second time is when thermal paste is applied between SiC MOSFET and the test cold plate, and the test environment of SiC MOSFET is under high thermal conductivity conditions. Since the difference in the thermal conduction paths between the two is only in the contact surface from the SiC MOSFET device shell to the test cold plate, under the two test conditions, the thermal impedance curves from junction to shell overlap, and separation occurs at the thermal paste, and the separation point is the tube shell position of the SiC MOSFET device, so the thermal resistance before the separation point of the two thermal impedance curves can be identified as the junction-to-shell thermal resistance.

[0091] Steps S42 and S44 also include electrical correction, which is to adjust the heating current I H Correct electrical interference at the switching moment.

[0092] Since in step S36, there is a heating current I H Switch to test current I M Therefore, there is electronic interference in the initial stage of the test. The V collected at this stage sd The data is invalid, so a certain cut-off time t needs to be removed cut Signal points recorded during the period. Temperature change ΔT during this period J(tcut) Can not be ignored, during this period of time, ΔT J(tcut) It is approximately linearly related to the square root of time, and the junction temperature T at t=0 can be derived. J0 The principle is as follows:

[0093] For a semi-infinite plate of uniform material (that is, a plate with infinite surface area—ensuring that the one-dimensional heat flow is perpendicular to the surface—and infinite thickness), the surface heating power density is constant at P H / A, when heating power is applied or cut off, the surface temperature increases / decreases in a linear relationship with the square root of the heating / cooling time.

[0094]

[0095]

[0096] Among them, c, ρ and λ are the specific heat, density and thermal conductivity of the material respectively. Therefore, the junction temperature T at t=0 can be linearly extrapolated from the graph J0 .

[0097] In this embodiment, after the electrical correction step S44, the final result is as follows: Fig.10 The differential structure function curves of the first cooling curve and the second cooling curve under the dual interface test conditions shown in the figure, the horizontal axis is the thermal resistance Rth, the vertical axis is the derivative of the heat capacity Cth to the thermal resistance Rth, curve a2 is the differential structure function curve of the first experiment, and curve b2 is the differential structure function curve of the second experiment. The thermal impedance of the SiC MOSFET device can be obtained by the separation point of curve a2 and curve b2. The peaks on the curves correspond to the material layer with high thermal conductivity (such as chips or heat sinks), and the trough area corresponds to the structural layer with low thermal conductivity (such as solder layer or air).

[0098] like Fig.11 The integral structure function curves of the first cooling curve and the second cooling curve under the dual interface test conditions are shown, the horizontal axis is the thermal resistance Rth, the vertical axis is the integral of the heat capacity Cth over the thermal resistance Rth, curve a3 is the integral structure function curve of the first experiment, and curve b3 is the integral structure function curve of the second experiment. The integral structure function curve reflects the structural information of the SiCMOSFET device chip to the test cold plate. Similar to the differential structure function curve, the thermal impedance of the SiC MOSFET device can be obtained through the separation point.

[0099] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0100] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for testing the junction-to-shell thermal resistance of a silicon carbide metal oxide semiconductor field effect transistor, characterized in that: include: Performing a power-on test on a silicon carbide metal oxide semiconductor field effect transistor to obtain a bias voltage of the silicon carbide metal oxide semiconductor field effect transistor; Under the bias voltage condition, the voltage V between the source and the drain of the silicon carbide metal oxide semiconductor field effect transistor is tested. sd With the temperature data, the voltage V sd Functional relationship with temperature; In combination with the functional relationship, a transient double interface method is used to test and obtain cooling time data of the silicon carbide metal oxide semiconductor field effect transistor; According to the cooling time data, the junction-to-shell thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor is calculated. The step of conducting a power-on test on a silicon carbide metal oxide semiconductor field effect transistor to obtain a bias voltage of the silicon carbide metal oxide semiconductor field effect transistor comprises: A fixed negative voltage V is applied between the gate and source of the silicon carbide metal oxide semiconductor field effect transistor. gs , a negative pulse voltage V is applied between the drain and source ds ; Plot different negative pressure V gs The source and drain I of the SiC metal oxide semiconductor field effect transistor under the condition ds -V ds Characteristic curve; Select the I ds -V ds When multiple curves in the characteristic curve overlap, the negative pressure V gs The negative pressure V when the absolute value is the minimum gs As the bias voltage, The silicon carbide metal oxide semiconductor field effect transistor is installed in a test fixture, and the source and drain of the silicon carbide metal oxide semiconductor field effect transistor are connected by Kelvin; The negative pulse voltage V ds The pulse duty cycle is less than or equal to 0.5%.

2. The testing method according to claim 1, characterized in that: Get the voltage V sd Functions of temperature include: Applying the bias voltage between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor; A constant test current I is loaded between the drain and source of the silicon carbide metal oxide semiconductor field effect transistor. M , record the voltage V between the drain and source of the SiC MOSFET sd ; Placing the silicon carbide metal oxide semiconductor field effect transistor in a temperature device and setting the temperature parameters of the temperature device; Record V at different temperature points sd Data, and perform linear fitting to obtain the voltage V sd Functional relationship with temperature.

3. The testing method according to claim 2, characterized in that: The temperature parameters include the temperature of the initial data collection point, the temperature step length and the time required for temperature equilibrium.

4. The testing method according to claim 2, characterized in that: In combination with the functional relationship, the cooling time data of the silicon carbide metal oxide semiconductor field effect transistor is obtained by testing using a transient double interface method, including: Performing the processing steps of the first experiment, the processing steps of the first experiment comprising: Fixing the silicon carbide metal oxide semiconductor field effect transistor to a test cold plate through a clamp, and applying the bias voltage between the source and drain of the silicon carbide metal oxide semiconductor field effect transistor; A constant heating current I is loaded between the drain and source of the silicon carbide metal oxide semiconductor field effect transistor. H and the constant test current I M ; The heating current I H The heating current I is turned on and the heating current I is turned off when the temperature of the silicon carbide metal oxide semiconductor field effect transistor rises to a temperature equilibrium state. H , record the voltage V between the source and drain of the SiC MOSFET during the cooling process of the SiC MOSFET sd Experimental data, obtaining first cooling time data according to the functional relationship; After executing the processing steps of the first experiment, executing the processing steps of the second experiment, the processing steps of the second experiment include: Thermal conductive paste is applied between the silicon carbide metal oxide semiconductor field effect transistor and the contact surface of the cold plate, and the processing steps of the first experiment are repeated to obtain second cooling time data.

5. The testing method according to claim 4, characterized in that: The test current I M The value range is 1mA~100mA, and the test current I M The power generated does not exceed 0.1W.

6. The testing method according to claim 4, characterized in that: According to the cooling time data, the junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor is calculated and obtained by: According to the first cooling time data and the second cooling time data, respectively draw a first cooling curve when the silicon carbide metal oxide semiconductor field effect transistor is directly fixed on a test cold plate, and a second cooling curve when thermal conductive paste is applied between the contact surface of the silicon carbide metal oxide semiconductor field effect transistor and the cold plate; A structure function algorithm is used to obtain a differential or integral structure function curve of the first cooling curve and the second cooling curve under dual interface test conditions, and the junction-to-case thermal resistance of the silicon carbide metal oxide semiconductor field effect transistor is determined through the separation point of the structure function curve.

7. The testing method according to claim 6, characterized in that: Before constructing the structure function curve, electrical correction is also included to adjust the heating current I H Correction for electrical disturbances during switching.

Images