Semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to semiconductor devices and methods of manufacturing the same. One method includes doping a region through a first surface of a semiconductor substrate, forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region, forming a plurality of transistors over the first surface, wherein each of the transistors includes one or more source / drain structures that are electrically coupled to the doped region through a respective one of the doped structures, forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors, and testing electrical connections between the interconnect structures and the transistors based on detecting a signal present on the doped region through a second surface of the semiconductor substrate, the second surface being opposite the first surface.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to semiconductor devices and methods of manufacturing the same. BACKGROUND

[0002] One way to miniaturize integrated circuits is by using circuits on the backside of the substrate, i.e., by using backside circuits, as opposed to the frontside. Such backside circuits can include, for example, backside power rails. Using backside circuits can allow for smaller circuit elements on the frontside of the substrate, i.e., in the frontside circuits. However, the manufacturing of backside circuits is an expensive process. If the frontside circuits have defects, the cost of manufacturing the backside circuits can be wasted. SUMMARY

[0003] According to one aspect of the present disclosure, a method of manufacturing a semiconductor device includes doping a region through a first surface of a semiconductor substrate, wherein the region extends at least along a lateral direction; forming a plurality of doping structures within the semiconductor substrate, wherein each of the plurality of doping structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors includes one or more source / drain structures that are electrically coupled to the doped region through a respective one of the doping structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting a signal present on the doped region through a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0004] According to another aspect of the present disclosure, a method of manufacturing a semiconductor device includes forming a doped layer through a first surface of a semiconductor substrate; forming a plurality of transistors over the first surface of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the doped layer; coupling the transistors to each other by forming a plurality of first interconnect structures over the first surface; applying a test signal through the first interconnect structures; and checking electrical connections between the transistors and the first interconnect structures by monitoring a signal present on the doped layer from a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0005] According to yet another aspect of the present disclosure, a system for testing a semiconductor device is provided, comprising: a semiconductor device comprising: a semiconductor substrate having a buried doped layer within a thickness of the substrate; a plurality of gate-all-around (GAA) transistors on a first side of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the buried doped layer; and a plurality of interconnect structures between the plurality of GAA transistors on the first side of the semiconductor substrate; a test apparatus on a second side of the semiconductor substrate, the second side being opposite the first side; the test apparatus configured to test electrical connections in the plurality of interconnect structures between the GAA transistors. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the disclosure can be best understood with reference to the following specific description in conjunction with the accompanying drawings. It should be noted that the various features are not drawn to scale. In fact, the dimensions of the various features can have been arbitrarily expanded or reduced for the sake of discussion. It is also to be understood that the specific devices illustrated in the attached figures, and described in the following specification, are simply exemplary embodiments of the inventive concepts defined by the appended claims. Hence, specific dimensions and other physical characteristics relating to the embodiments disclosed herein are not to be considered as limiting, unless the claims expressly state otherwise.

[0007] Figure 1 A general method of the present disclosure is shown.

[0008] Figure 2A A structure is schematically shown that includes a substrate having a buried doped layer, the substrate having front side circuitry but no back side circuitry formed. Figure 2B A test apparatus (e.g., a microscope) is schematically shown being used to test the front side circuitry of the substrate in Figure 2A The test apparatus is placed facing the back side of the substrate. Figure 2C A final structure formed from the structure of Figure 2B is schematically shown in the case where the front side circuitry passes testing. Figure 2A The final structure in Figure 2C has back side circuitry and the same front side circuitry as the structure in Figure 2A .

[0009] Figure 3 An exemplary layout design of a structure is shown that includes a substrate having a buried doped layer, the substrate having front side circuitry but no back side circuitry formed.

[0010] Figure 4 A perspective view of an exemplary circuit formed on the front side of a substrate having a buried doped layer is provided (“front side circuitry”), the substrate having front side circuitry but no back side circuitry formed.

[0011] Figure 5 A flowchart of a process flow of an exemplary method of manufacturing a semiconductor device is shown that involves testing front side circuitry prior to forming back side circuitry.

[0012] Figure 6A- Figure 6G Cross-sectional views illustrating steps of a method of manufacturing a semiconductor device are shown, the method involving testing of front side circuitry prior to forming back side circuitry. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments, or examples, for implementing different characteristics of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature can include embodiments where the first feature is formed directly in contact with the second feature, and can also include embodiments where additional features can be formed between the first feature and the second feature such that the first feature can not be directly in contact with the second feature. Furthermore, the present disclosure can repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed herein.

[0014] Moreover, spatially relative terms (e.g., "beneath," "below," "lower," "above," "upper," and the like) can be used herein for ease of describing one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0015] One way to miniaturize integrated circuits is by using circuitry on the backside of the substrate opposite the frontside, i.e. by using backside circuitry. Such backside circuitry can comprise, for example, backside power rails. Using backside circuitry can allow for using smaller circuit elements on the frontside of the substrate, i.e. in the frontside circuitry. However, the manufacturing of backside circuitry is an expensive process. If the frontside circuitry is defective, the cost of manufacturing the backside circuitry can be wasted.

[0016] The present disclosure proposes a method of manufacturing a semiconductor device. In Figure 1The method schematically illustrated in the flowchart may include 101: forming a front circuit on the front side of a semiconductor substrate, having a buried doped semiconductor layer; 102: testing the front circuit before forming a circuit on a back side of the substrate opposite to the front side; 103: if the front circuit passes test 102, forming the back circuit; 104: if the front circuit fails test 102, the semiconductor substrate having the front circuit can be discarded. For devices that pass test 102 and have had their back circuit formed in step 103, a final test 105 may be performed. The final test may involve testing the front and / or back circuits.

[0017] Figure 2A It schematically shows that in Figure 1 The structure (or partially formed semiconductor device) 200 formed in element (101). Figure 2A The structure includes a semiconductor substrate 201. Substrate 201 may include a semiconductor material substrate, such as silicon. Alternatively, the substrate may include other elemental semiconductor materials, such as germanium. The substrate may also include compound semiconductors, such as silicon carbide, gallium arsenide, indium arsenide, and indium phosphide. The substrate may include alloy semiconductors, such as silicon germanium, silicon germanium carbide, gallium arsenide, and gallium indium phosphide. The substrate may include an epitaxial layer. For example, the substrate may have an epitaxial layer covering the bulk semiconductor.

[0018] According to various embodiments, substrate 201 may include a buried doped semiconductor layer 202, which may serve as a sacrificial layer configured to test the front-side circuitry of substrate 201 prior to the formation of any circuitry on the back side of substrate 201. The buried doped semiconductor layer 202 may be an n-doped layer or a p-doped layer. Substrate 201 may include dielectric layers 205A and 205B located on opposite sides of the buried doped semiconductor layer 202. Each of dielectric layers 205A and 205B may be an oxide layer, which may be formed from an oxide of the semiconductor material of substrate 201.

[0019] Structure 200 includes a front-side circuit 203 on the top surface of substrate 201. The front-side circuit 203 includes a plurality of transistors 204, such as transistors 204A and 204B. A first subgroup of transistors 204 may form a first unit, namely unit A (which may correspond to the first circuit), while a second subgroup of transistors 204 may form a second unit, namely unit B (which may correspond to the second circuit), such as... Figure 2AThe transistors can include transistors selected from three-dimensional transistors (e.g., three-dimensional field effect transistors (e.g., FinFETs), gate-all-around (GAA) transistors (e.g., nanosheet transistors)) and / or planar transistors (e.g., metal-oxide-semiconductor field effect transistors (MOSFETs)). Each transistor includes an active region, which can be a fin-shaped region of one or more three-dimensional field effect transistors (e.g., FinFETs), a sheet-shaped region of one or more gate-all-around (e.g., GAA) transistors (e.g., nanosheet transistors), a line-shaped region of one or more GAA transistors (e.g., nanowire transistors), or an oxide-defined (OD) region of one or more planar metal-oxide-semiconductor field effect transistors (MOSFETs). Some portions of the active region can each function as a source structure or a drain structure (or feature) of the respective transistor(s); and some portions of the active region can each function as a conductive channel of the respective transistor(s).

[0020] One or more transistors 204 can be electrically connected to the buried doped semiconductor layer 202 through an interconnect structure(s) 207, which can extend from a top surface of the substrate 201 through a thickness of the dielectric layer 205. The interconnect structure(s) 207 can be formed of a doped semiconductor, such as doped silicon, doped germanium, or doped SiGe. In certain embodiments, each transistor 204 can be electrically connected to the buried doped semiconductor layer through the interconnect structure 207. For example, each transistor 204 can include one or more source / drain, which can be electrically coupled or connected to the buried doped semiconductor layer 202 through the interconnect structure 207.

[0021] The frontside circuitry 203 also includes electrical interconnects 206, which can provide electrical interconnections between the transistors 204. The interconnects 206 can include multiple metallization layers on the frontside (e.g., the bottom-most metallization layer on the frontside, often referred to as M0). The structure 200 does not include circuitry on the backside 208 of the substrate 201.

[0022] Figure 2B schematically shown Figure 1The test 102 can involve placing a test device 209 to face the backside 208 of the substrate 201. The test device 209 can be, for example, a microscope, such as a photonic microscope (e.g., an emission microscope (EMMI)) or an electron beam microscope (e.g., an electron beam irradiation microscope (EBI)). The test 102 can include applying electrical signals to the frontside circuitry 203 through the topmost frontside metallization layer 206T and using the test device 209 to detect signals, which can include, for example, photons and / or electrons, such as secondary electrons, that pass through the buried doped layer 202. The test 102 can include testing the electrical interconnects 206 between the transistors 204. If no bad events or issues (e.g., defective electrical connections (e.g., electrical opens or electrical shorts)) between the interconnect structures in the metallization layer and the transistors, defective electrical connections (e.g., electrical opens or electrical shorts) between the interconnect structures in the metallization layer, and / or defective electrical connections (e.g., electrical opens or electrical shorts) between the transistors are observed, or the number of bad events or issues is within a predefined threshold, then the structure 200 (or its frontside circuitry 203 or electrical interconnects 206) can pass the test 102.

[0023] In some embodiments, the test device can be an emission microscope (EMMI). An EMMI microscope can perform emission microscopy analysis, which can be an effective optical analysis technique for detecting and locating certain integrated circuit (IC) faults. Emission microscopy is non-invasive and can be performed from either the frontside or backside of a device. For example, many defects in integrated circuits can cause weak light emissions in the visible and near-infrared (IR) light spectrum.

[0024] An EMMI microscope can include a sensitive camera for viewing and capturing these light emissions, allowing the device to detect and locate certain IC defects. Since emissions can be detected from the backside, an EMMI microscope can also include a laser, such as an IR laser, to create an overlay image of the circuit. This can allow faults to be directly correlated to circuit features, speeding up fault resolution. A typical EMMI photo can include or consist of an overlay of two images: the circuit and the emission points. Each image can be arbitrarily colored differently for clarity.

[0025] Figure 2CA semiconductor device 200F formed from structure 200 with frontside electrical interconnects 206 passing test 102 is schematically illustrated. Semiconductor device 200F includes the same frontside circuitry 203. However, semiconductor device 200F also includes backside circuitry 210. Backside circuitry 210 includes interconnect structure(s) 207F, which can extend through the thickness of dielectric layer 205A. Interconnect structure(s) 207F can be formed by replacing the doped semiconductor of interconnect structure(s) 207 with a metal, which can be selected, for example, from the group consisting of tungsten, ruthenium, copper, titanium, and alloys thereof. In comparison to structure 200, semiconductor device 200F can be devoid of doped semiconductor layer 202 and dielectric layer 205B. Backside circuitry 210 can also include backside electrical interconnects 211, which can provide electrical interconnects between transistors 204. Interconnects 211 can include multiple metallization layers on the backside (e.g., the bottom-most metallization layer on the backside, commonly referred to as M0). At least one of the backside metallization layers can be disposed on the bottom surface of dielectric layer 205A. At least one of the backside metallization layers can be used as a power rail 212. Power rail 212 can be configured to provide power to transistors 204 on the top surface of substrate 201, which can be, for example, VDD (a relatively high voltage) or VSS (a relatively low voltage or ground voltage).

[0026] Figure 3 An example of a layout design 300 of structure 200 is schematically illustrated. Layout design 300 includes two (standard) cells 300A and 300B that are contiguous to each other along the X-direction. Cells 300A and 300B share common buried doped layers 380 and 381 that extend along the X-direction. Each of cells 300A and 300B can be used as respective circuitry that includes one or more transistors that are operably coupled to each other. Layout design 300 is simplified for illustrative purposes. Thus, layout design 300 can include other patterns.

[0027] Layout design 300 includes patterns 310 and 360 each extending along the X direction, each configured to form an active region (hereinafter referred to as “active regions 310 and 360”) over the front side of the substrate. Each of active regions 310 and 360 can include p-type dopants or n-type dopants. The type of dopants in active region 310 and the type of dopants in active region 360 can be the same or different. Each of active regions 310 and 360 can be one of the following: a fin-shaped region of one or more three-dimensional field effect transistors (e.g., FinFETs), a sheet-shaped region of one or more gate-all-around (e.g., GAA) transistors (e.g., nanosheet transistors), a line-shaped region of one or more GAA transistors (e.g., nanowire transistors), or an oxide-defined (OD) region of one or more planar metal-oxide-semiconductor field effect transistors (MOSFETs). Some portions of the active regions can each function as a source structure or a drain structure (or feature) of the respective transistor(s); and some portions of the active regions can each function as a conduction channel of the respective transistor(s).

[0028] In examples where layout design 300 is used to fabricate one or more GAA transistors, the portions of each of active regions 310 and 360 that are covered by gate structures (e.g., 301-309, which will be discussed below) can form multiple groups of nanoscale structures (e.g., nanosheets, nanowires, etc.) that are vertically separated from each other and extend along the X direction. Each group of such nanoscale structures can be configured as a channel of a respective GAA transistor. The portions of each of active regions 310 and 360 that are not covered by gate structures (e.g., 312-318, 362-368, which will also be discussed below) can form source or drain structures of the respective GAA transistor.

[0029] Layout design 300 includes patterns 301, 302, 303, 304, 305, 306, 307, 308, and 309. Patterns 301-309 can extend along the Y direction, configured to form gate structures (hereinafter referred to as “gate structures 301-309,” respectively). In embodiments, gate structures 301-309 can initially be formed as dummy (e.g., polysilicon) gate structures that span respective portions of active regions 310 and 360, and subsequently replaced by active (e.g., metal) gate structures.

[0030] In some embodiments, gate structures 301 and 306 can be disposed along or on first and second boundaries of cell 300A, respectively, and gate structures 307 and 309 can be disposed along or on first and second boundaries of cell 300B, respectively. Boundary gate structures such as gate structures 301, 306, 307, and 309 can not provide an electrical or conductive path, and can prevent or at least reduce / minimize current leakage across components between gate structures 301 and 306 in cell 300A and gate structures 307 and 309 in cell 300B. Boundary gate structures such as gate structures 301, 306, 307, and 309 can include polysilicon or metal lines, which are sometimes referred to as poly on OD edge (PODE). Such PODE and underlying active / dummy regions can be replaced with a dielectric material in order to electrically isolate a cell from another cell laterally (e.g., along the X direction) adjacent to the cell, e.g., to isolate cell 300A from cell 300B.

[0031] Non-boundary gate structures such as gate structures 302-305 of cell 300A and gate structure 308 of cell 300B are formed of one or more conductive materials (e.g., polysilicon(s), metal(s)), can cover (e.g., encircle) respective portions of active regions 310 and / or 360 to define one or more transistors. Continuing the example above of using layout design 300 to fabricate one or more GAA transistors, each non-boundary gate structure can correspond to a metal gate encircling a respective portion of active regions 310 and / or 360, where non-overlapping portions of the active regions (e.g., 312, 313, 314, 315, 316, 317, 318, 362, 363, 364, 365, 367, and 368) serve as respective source / drain structures of the one or more GAA transistors.

[0032] Layout design 300, which is located on top of cells 300A and 300B, includes patterns 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, and 331. Patterns 320-331 are configured to form via interconnect structures (hereinafter referred to as“via structures 320-331,” respectively, and sometimes referred to as MDs). One or more of via structures 320-327 can interconnect source / drain structures of cell 300A, i.e., one or more source / drain structures 312-316 and one or more source / drain structures 362-366. For example, via structure 322 interconnects source / drain structure 313 and source / drain structure 363, while via structure 325 interconnects source / drain structure 315 and source / drain structure 365. However, one or more via structures of cell 300A or cell 300B can not interconnect source / drain structures of the respective cell. For example, via structures 320, 321, 323, 324, 326, 327 of cell 300A and via structures 328-331 of cell 300B do not provide interconnections between source / drain structures. Via structures 320-327 of cell 300A can connect source / drain structures of cell 300A, i.e., source / drain structures 312-316 and 362-366, to an interconnect structure (hereinafter referred to as“interconnect structure 332”) formed by pattern 332. Similarly, via structures 328-321 of cell 300B can connect source / drain structures of cell 300B, i.e., source / drain structures 317, 318, 367, 368, to an interconnect structure (hereinafter referred to as“interconnect structure 378”) formed by pattern 333. Interconnect structures 332 and 333 can be formed on the front side of the substrate, e.g., the side on which source regions 310 and 360 are formed.

[0033] Layout design 300 includes backside via interconnects 341, 342, 343, 344, 345, 346, 347, 348, 349, and 350, which electrically connect transistors of cell 300A and cell 300B to buried doped layers 380 and 381. A buried doped layer, such as buried doped layer 380 or 381, can extend over multiple cells, such as cell 300A or 300B. In some embodiments, a buried doped layer can extend over multiple cells of a same type, such as multiple cells 300A or multiple cells 300B. In some embodiments, a buried doped layer can extend over multiple cells of different types, such as multiple cells 300A and multiple cells 300B. Figure 3In the above, back via interconnects 341, 342, and 343 connect the transistor of cell 300A formed along the active region 310 to the buried doped layer 380; back via interconnects 344, 345, and 346 connect the transistor of cell 300A formed along the active region 360 to the buried doped layer 381; back via interconnects 347 and 348 connect the transistor of cell 300B formed along the active region 310 to the buried doped layer 380; and back via interconnects 349 and 350 connect the transistor of cell 300B formed along the active region 360 to the buried doped layer 381.

[0034] Figure 4 A perspective view of structure 400 is provided, which includes an exemplary circuit (“front circuit”) 400 formed on the front side of a substrate having a buried doped layer, the substrate having the front circuit but not having circuit formed on a back side of the substrate opposite to the front side. Structure 400 may be based on Figure 3 The layout design 300 is fabricated using at least a portion thereof, such as cells 300A or 300B. For example, structure 400 includes multiple transistors formed on the front side of the substrate, a buried doped layer in the substrate, and no circuitry on the back side of the substrate (opposite to the front side). Therefore, Figure 4 The following discussion can be combined Figure 3 .exist Figure 4 In the illustrated embodiment, the transistor on the front side of the substrate is implemented as a GAA transistor. However, it should be understood that the transistor can be implemented as any of a variety of other types of transistors, while still remaining within the scope of this disclosure.

[0035] exist Figure 4 In the structure 400, an active region 402 is included, which may include multiple parts (or sub-regions) 402-1, 402-2, 402-3, 402-4, 402-5, 402-6, and 402-7. This can be based on... Figure 3 The active region 402 is formed by a pattern 310 or 360. Structure 400 includes (e.g., active) gate structures 404-1, 404-2, and 404-3. Gate structures 404-1 to 404-3 can be based on... Figure 3 The patterns are formed by three of the three patterns in 301-309.

[0036] In certain embodiments, the gate structure 404-1 can encircle each nanosheet (e.g., nanosheet) of the portion 402-2 that collectively function as a channel of the first GAA transistor; the gate structure 404-2 can encircle each nanosheet (e.g., nanosheet) of the portion 402-4 that collectively function as a channel of the second GAA transistor; and the gate structure 404-3 can encircle each nanosheet (e.g., nanosheet) of the portion 402-6 that collectively function as a channel of the third GAA transistor. Further, the portions 402-1 and 402-3 disposed on opposite sides of the gate structure 404-1 can function as respective source / drain structures of the first GAA transistor; the portions 402-3 and 402-5 disposed on opposite sides of the gate structure 404-2 can function as respective source / drain structures of the second GAA transistor; and the portions 402-5 and 402-7 disposed on opposite sides of the gate structure 404-3 can function as respective source / drain structures of the third GAA transistor.

[0037] The structure 400 includes interconnect structures 406-1, 406-2, 406-3, and 406-4 disposed (e.g., electrically connected to) on top of the portions (source / drain structures) 402-1, 402-3, 402-5, and 402-7, respectively. Such interconnect structures 406-1 to 406-4 connected to source / drain structures can sometimes be referred to as MDs. The structure 400 can also include interconnect structures 408-1, 408-2, and 408-3. The interconnect structures 408-1 to 408-3 are disposed (e.g., electrically connected to) on top of the gate structures 404-1 to 404-3, respectively. Such interconnect structures 408-1 to 408-3 connected to gate structures can sometimes be referred to as VGs.9.

[0038] The active regions 402, the gate structures 404-1 to 404-3, and the interconnect structures 408-1 to 408-3 are formed on a front side of a substrate (not shown). Specifically, the interconnect structures 408-1 to 408-3 can include a plurality of metallization layers on the front side (e.g., a bottommost metallization layer on the front side, commonly referred to as M0). The interconnect structures 408-1 to 408-3 can correspond to the interconnect structures 206 in FIG. 2. Figure 2A to Figure 2C

[0039] The structure 400 also includes a buried doped semiconductor layer 414 within a depth of the substrate. Figure 4 The buried doped semiconductor layer 414 in FIG. 4 can correspond to the buried doped semiconductor layer 414 in FIG. 2. Figure 3 Figure 2A to Figure 2B ​​The buried doped semiconductor layer 414 can be electrically connected or coupled to one or more of the source / drain structures 402-1, 402-3, 402-5, and 402-7, respectively, through one or more interconnect structures (e.g., structures 412-1, 412-2, 412-3, and 412-4). The interconnect structures 412-1 through 412-4 can be formed based on four of the patterns 341 through 350 of FIG. 3B. The interconnect structures 412-1 through 412-4 can be formed of a doped semiconductor, and can correspond to the structures 207 of FIG. 2B. Figure 3 Figure 2A to Figure 2B

[0040] The structure 400 can also correspond to the semiconductor 200F of FIG. 2A. In this case, the element 414 can correspond to the backside power rail 212 of FIG. 2B, while the interconnect structures 412-1 through 412-4 can instead be formed of a doped semiconductor of a metal, for example, selected from tungsten, ruthenium, titanium, and alloys thereof. Figure 2C Figure 2C

[0041] Figure 5 A flowchart of a method 500 of fabricating a semiconductor device is provided, which allows for testing of frontside circuitry (i.e., circuitry of a frontside of a substrate) including frontside interconnects prior to forming backside circuitry including interconnects on a backside (as opposed to a frontside) of the substrate. At least some operations of the method 500 can be used to form a semiconductor device including one or more non-planar structures. For example, the semiconductor device can include one or more gate-all-around (GAA) transistors. However, it should be understood that the transistors of the semiconductor device can each be configured as any of a variety of other types of transistors, such as FinFET, planar complementary metal-oxide-semiconductor (CMOS) transistors, while remaining within the scope of the present disclosure.

[0042] The method 500 is just one example and is not intended to limit the present disclosure. Therefore, additional operations can be provided before, during, and / or after the method 500, and some other operations can be described only briefly here. Some operations of the method 500 can be associated with the views shown in FIGS. 2A-2B. Figure 4 Figure 6G

[0043] ​​​​​​Method 500 can begin with operation 502 of providing a semiconductor substrate. The semiconductor substrate can be a bulk semiconductor substrate, which can be doped (e.g., doped with p-type or n-type dopants) or undoped. When a doped substrate is used, the dopant concentration (the concentration of doped impurities) in the substrate can be less than the dopant concentration in the buried doped semiconductor layer. For example, the dopant concentration in the substrate can be at least one-half or at least one-fifth, or at least one-tenth or at least one-twentieth, or at least one-fiftieth or at least one-hundredth of the dopant concentration in the buried doped semiconductor layer. The substrate can be a wafer, such as a silicon wafer. In some embodiments, the bulk semiconductor material of the substrate can include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0044] After operation 502, method 500 can include operation 504 of forming a first buried dielectric layer, such as a buried oxide layer. The buried oxide layer can be an oxide layer of the semiconductor that forms the substrate. For example, in a bulk silicon substrate, the buried oxide layer can be a silicon oxide layer. The buried oxide layer can be formed, for example, by implanting oxygen ions through a top surface of the substrate, within a thickness of the bulk semiconductor substrate, and then annealing the bulk semiconductor substrate with the implanted oxygen ions. The first buried dielectric layer can be formed substantially parallel to a top surface of the substrate, at a distance from the top surface that is less than the thickness of the substrate. The first buried dielectric layer can extend in at least one (i.e., one or both) lateral direction (i.e., a direction parallel to the top surface of the substrate). In certain embodiments, after the first buried dielectric layer is formed, a first additional semiconductor can be grown on the top surface of the substrate. The first additional semiconductor can be the same as or different from the bulk semiconductor of the original substrate. The growth of the first additional semiconductor can be performed by known semiconductor growth methods, such as chemical vapor deposition, including epitaxial growth.

[0045] The first buried dielectric layer and the second buried dielectric layer (each of which can be a buried oxide layer) can prevent the penetration or diffusion of dopants from the buried doped semiconductor layer to other regions of the substrate.

[0046] Figures 6A through 6C illustrate operation 504 of forming a first buried dielectric layer (e.g., a buried oxide layer). Figure 6A illustrates the implantation of oxygen ions into a semiconductor substrate 601, which may be a bulk silicon substrate. Figure 6B illustrates annealing the bulk semiconductor substrate 601 with the implanted oxygen ions to form a buried oxide layer 602. Figure 6C shows the growth of a first additional semiconductor using known semiconductor growth methods, such as chemical vapor deposition, including epitaxial methods. After operation 504, substrate 601 may include a top semiconductor layer, such as layer 604; a first buried dielectric layer, such as buried oxide layer 602, below the top semiconductor layer 604; and a bottom semiconductor layer, such as layer 603, below the buried oxide layer 602.

[0047] Following operation 504, method 500 may include operation 506, forming a buried-doped semiconductor layer over the first buried dielectric layer. For example, a semiconductor material layer of the substrate directly above the first buried dielectric layer (which may include at least a portion of the first additional semiconductor) may be implanted onto the top surface of the substrate using n-type or p-type dopant. In the case where a group IV semiconductor (e.g., silicon or germanium) is used as the bulk material of the substrate, the p-type dopant may be a group III dopant, such as B, Al, In, or Ga; and the n-type dopant may be a group V dopant, such as P, As, Sb, or Bi. After implantation of the dopant, the substrate may be annealed. The concentration of the dopant in the doped semiconductor layer may vary. In some embodiments, for example, the concentration of the dopant may be from 1 × 10⁻⁶. 13 cm -3 Up to 1×10 18 cm -3 Or from 1×10 14 cm -3 Up to 1×10 17 cm -3 Or from 0.5×10 15 cm -3 Up to 1×10 16 cm -3 Or from 1×10 15 cm -3 Up to 1×10 16 cm -3 For example, 3×10 15 cm -3 In some embodiments, the concentration of the dopant impurity can be greater than 1 × 10⁻⁶. 18 cm -3 .

[0048] After operation 506, the method 500 can include operation 508 of forming a second buried dielectric layer in the portion of the bulk semiconductor of the substrate that is above the buried doped semiconductor layer, which can be a buried oxide layer. The formation of the second buried dielectric layer can be similar to the formation of the first buried dielectric layer. For example, the formation can include implanting oxygen atoms in the portion of the bulk semiconductor of the substrate that is above the buried doped semiconductor layer, followed by annealing. In some embodiments, the annealing of the second buried dielectric layer and the buried doped semiconductor layer can be combined. In other words, the oxygen atom implantation for the second buried dielectric layer (but not the annealing) can be performed after implanting n-type or p-type dopant impurities for the buried doped semiconductor layer. The combined annealing of both the second buried dielectric layer and the buried doped semiconductor layer can be performed after the oxygen atoms of the second buried dielectric layer are implanted.

[0049] FIGS. 6D-6F illustrate operations 506 and 508. FIG. 6D illustrates implantation of dopants into a top semiconductor layer 604 over the first dielectric layer 602 to define a doped semiconductor layer 605. FIG. 6E illustrates implantation of oxygen ions in the portion of the top semiconductor layer 604 that is above the doped semiconductor layer 605 to define a second dielectric layer 606, which can be an oxide layer, i.e., an oxide layer of the semiconductor of the top semiconductor layer 604. FIG. 6F illustrates annealing of the substrate 601 to complete the formation of the doped semiconductor layer 605 and the second dielectric layer 606.

[0050] After operation 508, the substrate 601 from top to bottom can include the following layers: the second buried dielectric layer 606, the buried doped semiconductor layer 605, the first buried dielectric layer 602, and the bottom semiconductor layer 603. Thus, the depth of the first buried dielectric layer 602 from the top surface of the substrate 601 is greater than the depth of the buried doped semiconductor layer 605, which in turn is greater than the depth of the second buried dielectric layer 606.

[0051] Operations 510-526 provide exemplary steps for forming front-side circuitry on the top surface of the front-side semiconductor layer. To form the front-side circuitry, a layout design, e.g., portions of the layout design 300, can be used.

[0052] Operation 510 can include forming a doped contact structure that extends from the buried doped semiconductor layer through the second buried dielectric layer to the top surface of the substrate. For example, FIG. 6F shows a doped contact structure 607 that extends vertically from the doped semiconductor layer 605 to the top surface of the substrate 601. The doped contact structure 607 includes n-doped or p-doped semiconductor and can correspond to the interconnect structure(s) 207 in Figure 2A and Figure 2B the structures 412-1 through 412-4 in Figure 4 or the structures 412-1 through 412-4 in Figure 3Structures 341 to 350 are shown in the figures. In some embodiments, the doped contact structure may be a doped SiGe structure.

[0053] Operations 512 to 524 are for forming GAA transistors on the top surface of the substrate, such that at least some of the GAA transistors pass through the contact structures formed in operation 510 (e.g., Figures 6F to 524). Figure 6G The doped contact structure 607 in Figure 2A to Figure 2B Structure 207 in Figure 4 Structures 412-1 to 412-4, or Figure 3 The exemplary step involves structures 341 to 350 being electrically connected to a buried doped semiconductor layer. In some embodiments, each GAA transistor may have one of its source / drain structures, for example... Figure 4 The source / drain structures 402-1, 402-3, and 402-5 in the figure can be made possible by the contact structures formed in operation 510 (e.g., Figures 6F to 610). Figure 6G The doped contact structure 607 in Figure 2A to Figure 2B Structure 207 in Figure 4 Structures 412-1 to 412-4, or Figure 3 Structures 341 to 350 in the diagram are electrically coupled or connected to buried doped semiconductor layers, such as those in Figures 6F to 650. Figure 6G Layer 605 in the middle Figure 2A to Figure 2B Layer 202 in the middle Figure 4 Component 414, or Figure 3 Components 380 or 381 in the diagram. A GAA transistor can be formed by at least some of the following process steps: forming a fin structure protruding from a substrate, wherein the fin structure comprises a plurality of first nanostructures and a plurality of second nanostructures alternately stacked on top of each other; forming a plurality of dummy gate structures across the plurality of fin structures; forming one or more pairs of source / drain structures in the fin structure, each pair of source / drain structures disposed on opposite sides of each dummy gate structure, and at least one source / drain structure electrically connected to a doped contact structure, such as those shown in Figures 6F to 6A. Figure 6G The doped contact structure 607 in Figure 2A to Figure 2B Structure 207 in Figure 4 Structures 412-1 to 412-4 or Figure 3 Structures 341 to 350 in the middle; removing the dummy gate structure; removing the first nanostructure; and forming multiple active (e.g., metal) gate structures.

[0054] Operation 512 involves forming a plurality of channel layers (which can be semiconductor layers) and a plurality of sacrificial layers (which can be, for example, sacrificial polysilicon layers) stacked in an alternating order. Both the channel layers and the sacrificial layers can be formed via epitaxial deposition techniques. Thus, operation 512 can involve forming a stack of epitaxial layers including a plurality of semiconductor epitaxial layers and a plurality of sacrificial epitaxial layers stacked in an alternating order.

[0055] Operation 514 involves defining and forming a fin structure including a stack of strips oriented along a first direction by patterning the stack including a plurality of channel layers (which can be semiconductor layers) and a plurality of sacrificial layers stacked in an alternating order. For example, operation 514 can involve forming a fin structure including a stack of strips by patterning the stack of epitaxial layers including a plurality of semiconductor epitaxial layers and a plurality of sacrificial epitaxial layers stacked in an alternating order, the stack of strips including a plurality of semiconductor strips and a plurality of sacrificial strips formed by patterning the plurality of semiconductor layers and the plurality of sacrificial layers, respectively.

[0056] Operation 516 involves forming a sacrificial gate structure (dummy gate) for the fin structure formed in operation 514. The dummy gate can include, for example, a sacrificial polysilicon layer, a sacrificial cap layer, and / or a sacrificial dielectric layer. The sacrificial cap layer and the sacrificial liner layer can be silicon oxide or other suitable dielectric material.

[0057] Operation 518 involves forming source / drain recesses from the strips by removing portions of the plurality of sacrificial strips, each recessed sacrificial strip including a recessed edge surface.

[0058] Operation 520 involves forming a buried insulator or dielectric layer(s) in the substrate, which can be a buried oxide layer. Operation 520 can be optional given that the substrate already includes first and second buried dielectric layers, such as layers 602 and 606 in FIG. 6. The buried insulator or dielectric(s) can be used to stop the thinning of the substrate in operation 528.

[0059] Operation 522 involves forming source / drain structures. The source / drain structures can be formed adjacent to the plurality of recessed sacrificial strips and the plurality of semiconductor strips.

[0060] Operation 524 involves replacing the dummy gate structure with an active (i.e., conductive) gate structure, which can be formed from a conductive material such as metal. Operation 524 can involve removing the dummy gate and the sacrificial strips, leaving open spaces and forming replacement conductive gates in the open spaces.

[0061] Operation 526 involves forming frontside interconnect structures, for example Figure 2Astructure 206 in FIG. 6. This operation can involve depositing multiple metallization layers that will provide interconnects between the transistors formed on the front side of the substrate.

[0062] After operation 526, the resulting structure can be Figure 2A structure 200 in FIG. 2. This structure can be exposed to Figure 1 test 102 in FIG. 1. If the front-side circuitry of this structure fails test 102, it can be discarded. If the front-side circuitry of the structure passes test 102, the structure can be used to form back-side circuitry.

[0063] In some embodiments, forming back-side circuitry can include operation 528, which can involve thinning the substrate from the back side. For example, such thinning can involve removing bottom semiconductor layer 603, first buried dielectric layer 602, and buried doped semiconductor layer 605. As a result of the thinning, a bottom of second dielectric layer 606 can be exposed.

[0064] In addition to operation 528, forming back-side circuitry can include operation 530, forming back-side interconnect structure(s) of the exposed back-side surface of the second buried dielectric layer (e.g., layer 606 or 205A). Forming back-side interconnect structure(s) can involve replacing the doped semiconductor in the doped contact structure (e.g., structure 607 or structure 207) with a metal, which can be selected, for example, from tungsten, ruthenium, titanium, or alloys thereof, to form a metal contact structure, such as structure 207F. Forming back-side interconnect structure(s) can also involve forming multiple back-side metallization layers. At least one of the back-side metallization layers can be used as a power rail, such as power rail 212 in FIG. 2. Figure 2C The back-side interconnect structure(s) can be formed by one or more of the following process steps: forming multiple via structures connecting each (merged) source / drain structure; and forming back-side interconnect structure(s) connecting the via structures together. Thus, the back-side interconnect structure(s) can connect the respective source / drain structures of the GAA transistors together.

[0065] After forming the back-side interconnect structure(s), the resulting semiconductor device with front-side circuitry and back-side circuitry can be subjected to final testing.

[0066] In one aspect of the disclosure, a method of fabricating a semiconductor device is disclosed. The method includes doping a region through a first surface of a semiconductor substrate, wherein the region extends at least along a lateral direction; forming a plurality of doping structures within the semiconductor substrate, wherein each of the plurality of doping structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors above the first surface, wherein each of the transistors includes one or more source / drain structures that are electrically coupled to the doped region through a respective one of the doping structures; forming a plurality of interconnect structures above the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting a signal present on the doped region through a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0067] In another aspect of the disclosure, a method of fabricating a semiconductor device is disclosed. The method includes forming a doped layer through a first surface of a semiconductor substrate; forming a plurality of transistors above the first surface of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the doped layer; coupling the transistors to each other by forming a plurality of first interconnect structures above the first surface; applying a test signal through the first interconnect structures; and checking electrical connections between the transistors and the first interconnect structures by monitoring a signal present on the doped layer from a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0068] In yet another aspect of the disclosure, a method of fabricating a semiconductor device is disclosed. The method includes doping a region buried in a semiconductor substrate with a semiconductor impurity; forming a plurality of gate-all-around (GAA) transistors on a first side of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the doped region; electrically coupling the GAA transistors to each other by forming a plurality of interconnect structures on the first side; applying a test signal through the interconnect structures; placing a microscope on a second side of the semiconductor substrate, the second side being opposite the first side; determining, based on results of the microscope detection, that there are no or a number of electrical connection problems between the GAA transistors and the interconnect structures that are within a threshold; removing the doped region; and forming one or more power rails electrically coupled to the GAA transistors on the second side of the semiconductor substrate.

[0069] Yet another embodiment is a system for testing a semiconductor device, comprising: a semiconductor device and a test apparatus. The semiconductor device comprises a semiconductor substrate having a buried doped layer within a thickness of the substrate, a plurality of gate-all-around (GAA) transistors on a first side of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the buried doped layer, and a plurality of interconnect structures between the plurality of GAA transistors on the first side of the semiconductor substrate. The test apparatus is on a second side of the semiconductor substrate, the second side being opposite the first side. The test apparatus is configured to test electrical connections in the plurality of interconnect structures between the GAA transistors.

[0070] The foregoing has outlined rather generally the features of several embodiments in order that the detailed description that follows can be better understood. Those skilled in the art will appreciate that they can readily use the disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or for achieving the same advantages that the embodiments introduced herein demonstrate.

[0071] Example 1. A method of fabricating a semiconductor device, comprising: doping a region through a first surface of a semiconductor substrate, wherein the region extends at least along a lateral direction; forming a plurality of doped structures within the semiconductor substrate, wherein each of the plurality of doped structures extends along a vertical direction and is in contact with the doped region; forming a plurality of transistors over the first surface, wherein each of the transistors includes one or more source / drain structures that are electrically coupled to the doped region through a respective one of the doped structures; forming a plurality of interconnect structures over the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting a signal present on the doped region through a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0072] Example 2. The method of example 1, further comprising: forming a first dielectric layer within the semiconductor substrate prior to doping the region; forming a second dielectric layer within the semiconductor substrate after doping the region; and patterning the second dielectric layer to form the doped structures.

[0073] Example 3. The method of example 2, wherein the step of forming a first dielectric layer comprises implanting oxygen atoms in the semiconductor substrate to a first depth from the surface; the step of doping the region comprises implanting a semiconductor impurity in the semiconductor substrate to a second depth from the surface; and the step of forming a second dielectric layer comprises implanting oxygen atoms in the semiconductor substrate to a third depth from the surface, wherein the first depth is greater than the second depth, and the second depth is greater than the third depth.

[0074] Example 4. The method of example 1, wherein the step of forming a plurality of transistors further comprises: alternately stacking a plurality of semiconductor channel layers and a plurality of semiconductor sacrificial layers over the first surface; epitaxially growing the one or more source / drain structures of each transistor based on the semiconductor channel layers; and forming a plurality of metal gate structures for the transistors based on removing the semiconductor sacrificial layers, wherein each of the metal gate structures encircles at least some portions of the semiconductor channel layers.

[0075] Example 5. The method of example 1, wherein the step of testing electrical connections between the interconnect structures and the transistors further comprises: applying an electrical signal through a topmost interconnect structure of the interconnect structures, and wherein the detected signal present on the doped region comprises at least one of a photon or a secondary electron.

[0076] Example 6. The method of example 5, further comprising: placing at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope next to a second surface of the semiconductor substrate to detect the signal present on the doped region.

[0077] Example 7. The method of example 1, further comprising: replacing the doped region and the doped structure with a metal structure and a plurality of metal contacts, respectively.

[0078] Example 8. The method of example 7, wherein the step of replacing the doped region and the doped structure further comprises: thinning the semiconductor substrate through the second surface; and forming the metal structure electrically coupled to one or more of the plurality of transistors through the metal contacts.

[0079] Example 9. The method of example 7, wherein the metal structure comprises a power rail configured to provide a power supply voltage to the transistors.

[0080] Example 10. The method of example 7, wherein each of the metal contacts comprises a via structure.

[0081] Example 11. A method of fabricating a semiconductor device, comprising: forming a doped layer through a first surface of a semiconductor substrate; forming a plurality of transistors over the first surface of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the doped layer; coupling the transistors to one another by forming a plurality of first interconnect structures over the first surface; applying a test signal through the first interconnect structures; and inspecting electrical connections between the transistors and the first interconnect structures by monitoring a signal present on the doped layer from a second surface of the semiconductor substrate, the second surface being opposite the first surface.

[0082] Example 12. The method of example 11, wherein each of the transistors includes a gate structure surrounding each channel of that transistor.

[0083] Example 13. The method of example 11, wherein the step of forming a doped layer further comprises: implanting the semiconductor substrate with oxygen atoms through the first surface to form a first dielectric layer; implanting the semiconductor substrate through the first surface to form the doped layer disposed over the first dielectric layer; implanting the semiconductor substrate through the first surface to form a second dielectric layer disposed over the doped layer; and patterning the second dielectric layer and implanting the semiconductor substrate through the first surface to form a plurality of doped structures that electrically couple the doped layer to the plurality of transistors.

[0084] Example 14. The method of example 11, wherein the step of inspecting electrical connections between the transistors and the first interconnect structures further comprises: placing a microscope next to the second surface of the semiconductor substrate to monitor the signal, wherein the microscope includes at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope.

[0085] Example 15. The method of example 14, further comprising: determining, based on the monitored signal, that there is no electrical connection problem; removing the doped layer; and forming a plurality of second interconnect structures, the plurality of second interconnect structures being opposite the first interconnect structures with respect to the transistors.

[0086] Example 16. The method of example 15, wherein at least one of the plurality of second interconnect structures includes a power rail configured to deliver a power supply voltage to the transistors.

[0087] Example 17. The method of example 14, further comprising: determining, based on the monitored signal, that there is an electrical connection problem; and stopping further processing until a location of the problem is identified.

[0088] Example 18. A system for testing a semiconductor device, comprising: a semiconductor device, comprising: a semiconductor substrate having a buried doped layer within a thickness of the substrate; a plurality of gate-all-around (GAA) transistors on a first side of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the buried doped layer; and a plurality of interconnect structures between the plurality of GAA transistors on the first side of the semiconductor substrate; a test apparatus on a second side of the semiconductor substrate, the second side opposite the first side; the test apparatus configured to test electrical connections in the plurality of interconnect structures between the GAA transistors.

[0089] Example 19. The system of example 18, wherein the test apparatus is a microscope.

[0090] Example 20. The system of example 19, wherein the microscope is at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope.

Claims

1. A method of fabricating a semiconductor device, comprising: doping a region through a first surface of a semiconductor substrate to form a buried doping layer within a thickness of the semiconductor substrate, wherein the buried doping layer is at a non-zero depth from the first surface of the semiconductor substrate and extends parallel to the first surface of the semiconductor substrate; forming a plurality of doping structures within the semiconductor substrate, wherein each of the plurality of doping structures extends along a vertical direction and is in contact with the buried doping layer; forming a plurality of transistors above the first surface, wherein each of the transistors includes one or more source / drain structures that are electrically coupled to the buried doping layer through a respective one of the doping structures; forming a plurality of interconnect structures above the first surface, wherein each of the interconnect structures is electrically coupled to at least one of the transistors; and testing electrical connections between the interconnect structures and the transistors based on detecting a signal present on the buried doping layer through a second surface of the semiconductor substrate, the second surface being opposite the first surface.

2. The method of claim 1, further comprising: forming a first dielectric layer within the semiconductor substrate prior to doping the region; forming a second dielectric layer within the semiconductor substrate after doping the region; and patterning the second dielectric layer to form the doping structures.

3. The method of claim 2, wherein: the step of forming a first dielectric layer includes implanting oxygen atoms in the semiconductor substrate at a first depth from the first surface; the step of doping the region includes implanting semiconductor impurities in the semiconductor substrate at a second depth from the first surface; and the step of forming a second dielectric layer includes implanting oxygen atoms in the semiconductor substrate at a third depth from the first surface, wherein the first depth is greater than the second depth, and the second depth is greater than the third depth. the step of forming a plurality of transistors further comprises:

4. The method of claim 1, wherein, alternately stacking a plurality of semiconductor channel layers and a plurality of semiconductor sacrificial layers above the first surface; epitaxially growing the one or more source / drain structures of each transistor based on the semiconductor channel layers; and forming a plurality of metal gate structures for the transistors based on removing the semiconductor sacrificial layers, wherein each of the metal gate structures encircles at least some portions of the semiconductor channel layers. the step of testing electrical connections between the interconnect structures and the transistors further comprises applying an electrical signal through a topmost one of the interconnect structures, and wherein the detected signal present on the buried doping layer includes at least one of a photon or a secondary electron.

5. The method of claim 1, wherein, 6. The method of claim 5, further comprising: placing at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope next to a second surface of the semiconductor substrate to detect the signal present on the buried doping layer. ​ 7. The method of claim 1, further comprising: replacing the buried doped layer and the doped structure with a metal structure and a plurality of metal contacts, respectively.

8. The method of claim 7, wherein, the step of replacing the buried doped layer and the doped structure further comprises: thinning the semiconductor substrate through the second surface; and forming the metal structure electrically coupled to one or more of the plurality of transistors through the metal contacts.

9. The method of claim 7, wherein, the metal structure comprises a power rail configured to provide a power supply voltage to the transistors.

10. The method of claim 7, wherein, each of the metal contacts comprises a via structure.

11. A method of fabricating a semiconductor device, comprising: forming a buried doped layer within a thickness of a semiconductor substrate through a first surface of the semiconductor substrate, wherein the buried doped layer is at a non-zero depth from the first surface of the semiconductor substrate and extends parallel to the first surface of the semiconductor substrate; forming a plurality of transistors over the first surface of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the buried doped layer; coupling the transistors to one another through forming a plurality of first interconnect structures over the first surface; applying a test signal through the first interconnect structures; and inspecting electrical connections between the transistors and the first interconnect structures by monitoring a signal present on the buried doped layer from a second surface of the semiconductor substrate, the second surface being opposite the first surface.

12. The method of claim 11, wherein, each of the transistors comprises a gate structure surrounding each channel of the transistor.

13. The method of claim 11, wherein, the step of forming a buried doped layer further comprises: implanting the semiconductor substrate with oxygen atoms through the first surface to form a first dielectric layer; implanting the semiconductor substrate through the first surface to form the buried doped layer disposed over the first dielectric layer; implanting the semiconductor substrate through the first surface to form a second dielectric layer disposed over the buried doped layer; and patterning the second dielectric layer and implanting the semiconductor substrate through the first surface to form a plurality of doped structures electrically coupling the buried doped layer to the plurality of transistors.

14. The method of claim 11, wherein, the step of inspecting electrical connections between the transistors and the first interconnect structures further comprises: placing a microscope next to the second surface of the semiconductor substrate to monitor the signal, wherein the microscope comprises at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope.

15. The method of claim 14, further comprising: determining, based on the monitored signal, that there is no electrical connection issue; removing the buried doped layer; and forming a plurality of second interconnect structures opposite the first interconnect structures with respect to the transistors.

16. The method of claim 15, wherein, at least one of the plurality of second interconnect structures comprises a power rail configured to deliver a power supply voltage to the transistors.

17. The method of claim 14, further comprising: determining, based on the monitored signal, that there is an electrical connection issue; and stopping further processing until a location of the issue is identified.

18. A system for testing a semiconductor device, comprising: a semiconductor device, comprising: a semiconductor substrate having a buried doped layer within a thickness of the semiconductor substrate; a plurality of gate-all-around (GAA) transistors on a first side of the semiconductor substrate, wherein the plurality of transistors are operably coupled to the buried doped layer; and a plurality of interconnect structures between the plurality of GAA transistors on the first side of the semiconductor substrate; a testing apparatus on a second side of the semiconductor substrate, the second side opposite the first side; the testing apparatus configured to test electrical connections in the plurality of interconnect structures between the GAA transistors.

19. The system of claim 18, wherein, the testing apparatus is a microscope.

20. The system of claim 19, wherein, the microscope is at least one of an emission microscope (EMMI), a laser scanning microscope, or an electron beam irradiation (EBI) microscope.

Images