Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a manufacturing method thereof. The packaging structure includes a conductive member, multiple chips, a dielectric, a circuit layer, and a patterned insulating layer. The multiple chips are disposed on the conductive member. A portion of the conductive member surrounds the multiple chips. The dielectric covers the multiple chips. The circuit layer is located on the dielectric. The circuit layer electrically connects the multiple chips. The patterned insulating layer covers the circuit layer. Part of the patterned insulating layer is located between adjacent chips.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a packaging structure with a conductive member surrounding a plurality of chips and a manufacturing method thereof. Background Art

[0002] In recent years, electronic devices have become increasingly important to human life. To accelerate the integration of various functions and reduce the size of packaging structures, multiple independently operating chips can be combined into a single package. Therefore, minimizing signal interference between these chips during operation has become a pressing issue. Summary of the Invention

[0003] The present invention is directed to a packaging structure and a manufacturing method thereof, wherein the manufacturing process is relatively simple and the yield and quality can be improved.

[0004] According to an embodiment of the present invention, a package structure includes a conductive member, multiple chips, a dielectric, a circuit layer, and a patterned insulating layer. The multiple chips are disposed on the conductive member. A portion of the conductive member surrounds the multiple chips. The dielectric covers the multiple chips. The circuit layer is located on the dielectric. The circuit layer electrically connects the multiple chips. The patterned insulating layer covers the circuit layer. Part of the patterned insulating layer is located between adjacent chips.

[0005] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps: configuring multiple chips on a substrate; forming a dielectric material on the substrate to cover the multiple chips; forming a dielectric body covering the multiple chips by at least removing a portion of the dielectric material; forming a patterned conductive layer on the dielectric body, with a portion of the patterned conductive layer electrically connecting the multiple chips; forming a patterned insulating layer to cover the patterned conductive layer, with a portion of the patterned insulating layer located between adjacent multiple chips.

[0006] Based on the above, during the manufacturing process of the package structure, the substrate used for supporting the chip can be used as part of the conductive element. The second conductive portion, which serves as another part of the conductive element, can be made from the same film layer as the circuit layer used to electrically connect the chip. Furthermore, the conductive element surrounding the chip can reduce interference from external electromagnetic signals. This simplifies the manufacturing process of the package structure and improves the yield and quality of the package structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1A to 1E is a partial cross-sectional schematic diagram of a partial manufacturing method of a packaging structure according to the first embodiment of the present invention;

[0008] Figure 1F is a schematic cross-sectional view of a packaging structure according to a first embodiment of the present invention;

[0009] Figure 1G is a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention;

[0010] Figure 1H is a partial top view schematically illustrating a partial method for manufacturing a package structure according to a first embodiment of the present invention;

[0011] Figure 1I is a partial top view schematically illustrating a packaging structure according to a first embodiment of the present invention;

[0012] Figure 2 is a partial cross-sectional schematic diagram of a packaging structure according to a second embodiment of the present invention;

[0013] Figure 3 is a partial cross-sectional schematic diagram of a packaging structure according to a third embodiment of the present invention.

[0014] Description of Reference Numerals

[0015] 100, 200, 300: packaging structure;

[0016] 110, 120: chip;

[0017] 111, 121: substrate;

[0018] 110a, 120a: active surface;

[0019] 110b, 120b: back;

[0020] 110c, 120c: side;

[0021] 112, 122: chip connection pads;

[0022] 113, 123: chip protection layer;

[0023] 139: dielectric material;

[0024] 130: dielectric;

[0025] 130a: dielectric top surface;

[0026] 130b: dielectric bottom surface;

[0027] 130c: dielectric side;

[0028] 131, 132: dielectric part;

[0029] 131d, 132d: dielectric openings;

[0030] 130d: ditch;

[0031] 130h: maximum thickness;

[0032] 140: circuit layer;

[0033] 141, 142: lines;

[0034] 141s, 142s, 146s: seed layer;

[0035] 141p, 142p, 146p: plating layer;

[0036] 149: patterned conductive layer;

[0037] 150: patterned insulating layer;

[0038] 151d, 152d: insulation opening;

[0039] 150w: sidewall;

[0040] 150h: maximum thickness;

[0041] 161: substrate;

[0042] 361: conductive layer;

[0043] 161w: sidewall;

[0044] 160, 360: conductive parts;

[0045] 162: second conductive portion;

[0046] 162b: bottom surface;

[0047] 162w: sidewall;

[0048] 171, 172: conductive terminals;

[0049] 179: conductive layer;

[0050] 281: thermal interface material layer;

[0051] 382: substrate;

[0052] 191: adhesive layer;

[0053] F1, F2: interface;

[0054] S1, S2: accommodation space;

[0055] R1: Region. DETAILED DESCRIPTION

[0056] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0057] The directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are used only with reference to the drawings and are not intended to imply absolute orientations. In addition, for clarity, some layers or components may be omitted from the drawings.

[0058] Unless otherwise limited, the terms "disposed," "connected," "contacted," and other similar terms herein are used in a broad sense and encompass both direct and indirect dispositions, connections, contacts, and other similar terms. Accordingly, the drawings and descriptions should be regarded as illustrative in nature and not restrictive.

[0059] Unless otherwise expressly stated, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0060] The present invention will be more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, dimensions, or sizes of layers or regions in the drawings may be exaggerated for clarity. Identical or similar reference numbers denote identical or similar components, and detailed descriptions will not be repeated in the following paragraphs.

[0061] Figures 1A to 1E FIG1 is a partial cross-sectional schematic diagram of a partial manufacturing method of a package structure according to the first embodiment of the present invention. Figure 1H FIG. 1 is a partial top view of a method for manufacturing a package structure according to a first embodiment of the present invention. For example, Figure 1H Can be corresponding to Figure 1B , a schematic top view of the area near a first chip 110 and a second chip 120.

[0062] Please refer to Figure 1A , providing a substrate 161. In one embodiment, in subsequent processes, the substrate 161 may be suitable for supporting a structure formed thereon or a component disposed thereon.

[0063] In this embodiment, the substrate 161 may include a block-shaped conductive substrate, but the present invention is not limited thereto. For example, the substrate 161 may include a block-shaped steel plate, copper plate, aluminum plate, or other suitable metal plate.

[0064] In one embodiment, the surface of the substrate 161 may be plated or coated with a suitable conductive material or film (which may be considered part of the substrate), but the present invention is not limited thereto. For example, the substrate 161 may include a bulk insulating substrate, and the surface of the bulk insulating substrate may be plated or coated with a suitable conductive material or film.

[0065] Please continue to refer to Figure 1A , multiple chips are configured on the substrate 161. For example, the first chip 110 and the second chip 120 can be configured on the substrate 161. Figure 1A In the figure, only two first chips 110 and two second chips 120 are shown as examples, but the present invention is not limited thereto.

[0066] In this embodiment, the first chip 110 may include a substrate 111, a plurality of first chip connection pads 112, and a first chip protection layer 113. One side of the substrate 111 includes a component region (not shown), and the surface where the component region is located may be referred to as a first active surface 110a. The surface opposite the first active surface 110a may be referred to as a first back surface 110b. The surface connected between the first active surface 110a and the first back surface 110b may be referred to as a first side surface 110c. The first chip connection pads 112 may be located on the first active surface 110a. The first chip protection layer 113 may cover the first chip connection pads 112, with the first chip protection layer 113 exposing a portion of the first chip connection pads 112. In typical chip designs, components within the component region (e.g., components within the component region of the first chip 110) may be electrically connected to corresponding connection pads (e.g., a portion of the first chip connection pads 112 of the first chip 110) via corresponding back-end of line (BEOL) interconnects.

[0067] In this embodiment, the first chip connection pad 112 is, for example, an aluminum pad or a copper pad, but the invention is not limited thereto.

[0068] In this embodiment, the second chip 120 may include a substrate 121, a plurality of second chip connection pads 122, and a second chip protection layer 123. One side of the substrate 121 has a component area (not shown), and the surface where the component area is located may be referred to as a second active surface 120a. The surface opposite the second active surface 120a may be referred to as a second back surface 120b. The surface connecting the second active surface 120a and the second back surface 120b may be referred to as a second side surface 120c.

[0069] In this embodiment, the second chip 120 may be identical to or similar to the first chip 110. For example, the substrate 121 may be identical to or similar to the substrate 111, the second chip connection pads 122 may be identical to or similar to the first chip connection pads 112, and the second chip protection layer 123 may be identical to or similar to the first chip protection layer 113, and therefore, details thereof are omitted here.

[0070] In one embodiment, the first chip 110 and the second chip 120 can be homogeneous chips or heterogeneous chips, which is not limited in the present invention.

[0071] In one embodiment, an adhesive layer 191 may be provided between the chip (eg, the first chip 110 or the second chip 120 ) and the substrate 161 , but the present invention is not limited thereto. The adhesive layer 191 may include a die attach film (DAF), but the present invention is not limited thereto.

[0072] Please continue to refer to Figure 1A , a dielectric material 139 is formed on the substrate 161. The dielectric material 139 may cover the first chip 110 and the second chip 120. For example, the dielectric material 139 may cover the first active surface 110a and the first side surface 110c of the first chip 110, and the dielectric material 139 may cover the second active surface 120a and the second side surface 120c of the second chip 120. In one embodiment, the dielectric material 139 may be formed by coating or other suitable processes, but the present invention is not limited thereto. In one embodiment, the dielectric material 139 may directly contact the first chip connection pad 112 of the first chip 110 and the second chip connection pad 122 of the second chip 120.

[0073] Please refer to Figure 1A to Figure 1B and Figure 1H , at least a portion of the dielectric material 139 is removed, and then a dielectric body 130 covering multiple chips can be formed.

[0074] In this embodiment, the dielectric material 139 may be a photoimageable dielectric material (PID material). In one embodiment, a portion of the photoimageable dielectric material may be cured by photopolymerization and / or baking. After curing the portion of the photoimageable dielectric material, the remaining uncured photoimageable dielectric material may be removed by wet cleaning or other suitable methods.

[0075] In one embodiment, the formation method of the dielectric 130 can be adjusted according to its properties, which is not limited in the present invention.

[0076] In this embodiment, the dielectric body 130 may have a first dielectric opening 131d, a second dielectric opening 132d, and a trench 130d. The first dielectric opening 131d may expose the first chip connection pad 112 of the first chip 110, and the second dielectric opening 132d may expose the second chip connection pad 122 of the second chip 120. The trench 130d may expose the substrate 161 or a film layer (if any) located on the substrate 161.

[0077] In this embodiment, the dielectric body 130 may include multiple dielectric portions separated from each other by trenches 130d. In one embodiment, each dielectric portion may enclose each chip. For example, the dielectric body 130 may include a first dielectric portion 131 and a second dielectric portion 132 separated from each other by trenches 130d. The first dielectric portion 131 may cover the first side surface 110c and a portion of the first active surface 110a of the first chip 110. The second dielectric portion 132 may cover the second side surface 120c and a portion of the second active surface 120a of the second chip 120.

[0078] Please refer to Figures 1B to 1C , a patterned conductive layer 149 is formed on the substrate 161 . The patterned conductive layer 149 may cover the dielectric body 130 .

[0079] In the present embodiment, the patterned conductive layer 149 can be formed by a sputtering process, a photolithography process, an electroplating process and / or an etching process, but the present invention is not limited thereto. For example, a seed layer can be formed on the surface of the dielectric 130 by a sputtering process. Then, a patterned photoresist layer can be formed on the seed layer by a photolithography process. Then, a plating layer can be formed on the portion of the seed layer exposed by the patterned photoresist layer by an electroplating process. Then, the patterned photoresist layer and another portion of the seed layer not covered by the plating layer can be removed by an etching process. The patterned seed layers 141s, 142s, 146s (marked at Figure 1G ) and the patterned plating layers 141p, 142p, 146p thereon (indicated at Figure 1G ) can constitute a patterned conductive layer 149.

[0080] In this embodiment, the patterned conductive layer 149 may include a circuit layer 140 and a second conductive portion 162. The circuit layer 140 may electrically connect multiple chips. The second conductive portion 162 may conformally cover the trench 130d (indicated by Figure 1B or Figure 1H That is, the second conductive portion 162 filled in the trench 130 d may be located between the first dielectric portion 131 and the second dielectric portion 132 .

[0081] In this embodiment, the circuit layer 140 may include a first circuit 141. The first circuit 141 may be located on the first dielectric portion 131, and the first circuit 141 may completely fill the first dielectric opening 131d (indicated by Figure 1B or Figure 1H That is, the first circuit 141 can directly contact the first chip connection pad 112 of the first chip 110. For example, the patterned seed layer 141s (marked at Figure 1G ) can directly contact the first chip connection pad 112 of the first chip 110. The layout design of the first circuit 141 can be adjusted according to design requirements and is not limited in the present invention.

[0082] In one embodiment, the wiring area of ​​the first circuit 141 may be larger than the first active surface 110a of the first chip 110. In one embodiment, the first circuit 141 may be referred to as a fan-out circuit.

[0083] In this embodiment, the circuit layer 140 may include a second circuit 142. The second circuit 142 may be located on the second dielectric portion 132, and the second circuit 142 may completely fill the second dielectric opening 132d (indicated by Figure 1B or Figure 1H That is, the second circuit 142 can directly contact the second chip connection pad 122 of the second chip 120. For example, the patterned seed layer 142s (marked at Figure 1G ) can directly contact the second chip connection pad 122 of the second chip 120. The wiring design of the second circuit 142 can be adjusted according to design requirements and is not limited to this in the present invention.

[0084] In one embodiment, the wiring area of ​​the second circuit 142 may be larger than the second active surface 120a of the second chip 120. In one embodiment, the second circuit 142 may be referred to as a fan-out circuit.

[0085] In this embodiment, the second conductive portion 162 may be located on the first dielectric portion 131 and the second dielectric portion 132, and the second conductive portion 162 may further extend to the bottom of the trench 130d. In one embodiment, the second conductive portion 162 extending to the trench 130d may conformally cover the bottom and sidewalls of the trench 130d. In one embodiment, the second conductive portion 162 covering the trench 130d (indicated by Figure 1B or Figure 1H ) can be coplanar with the dielectric bottom surface 130b of the dielectric body 130.

[0086] In this embodiment, the second conductive portion 162 at the bottom of the trench 130d may contact the substrate 161. For example, a portion of the patterned seed layer 146s (marked at Figure 1G ) can directly contact the substrate 161.

[0087] In this embodiment, the second conductive portion 162 and the substrate 161 are formed through different steps. Thus, an interface F1 (indicated by Figure 1G For example, the portion of the patterned seed layer 146s (marked at Figure 1G ) may have an interface F1 between it and the substrate 161.

[0088] In this embodiment, the first line 141 and the second line 142 can be electrically isolated from each other. In another embodiment, the first line 141 and the second conductive portion 162 can be electrically isolated from each other. In another embodiment, the second line 142 and the second conductive portion 162 can be electrically isolated from each other.

[0089] Please refer to Figure 1C to Figure 1D A patterned insulating layer 150 is formed on the substrate 161. The material of the patterned insulating layer 150 may include an inorganic material, an organic material, other suitable insulating materials, or a stack thereof, and the present invention is not limited thereto. In one embodiment, the formation method of the patterned insulating layer 150 may be adjusted according to its properties, and the present invention is not limited thereto.

[0090] In this embodiment, the patterned insulating layer 150 may cover the patterned conductive layer 149. The patterned insulating layer 150 may have a plurality of insulating openings to expose portions of the patterned conductive layer 149. For example, the first insulating opening 151d may expose portions of the first wiring 141, and the second insulating opening 152d may expose portions of the second wiring 142.

[0091] In this embodiment, part of the patterned insulating layer 150 may be located between adjacent chips. For example, part of the patterned insulating layer 150 may also extend to the trench 130d (marked at Figure 1B or Figure 1H ), and may be located between the first chip 110 and the second chip 120. That is, the patterned insulating layer 150 filled in the trench 130d may be located between the first dielectric portion 131 and the second dielectric portion 132.

[0092] In this embodiment, the patterned insulating layer 150 may contact the dielectric body 130 . For example, the patterned insulating layer 150 may directly contact a portion of the dielectric top surface 130 a of the dielectric body 130 .

[0093] In this embodiment, the patterned insulating layer 150 and the dielectric body 130 are formed through different steps. Thus, an interface F2 (indicated by Figure 1G ).

[0094] Please refer to Figures 1D to 1E After forming the patterned insulating layer 150, a plurality of conductive terminals 171 and 172 may be formed. The conductive terminals 171 and 172 may be electrically connected to the first circuit 141 or the second circuit 142 in the circuit layer 140. For example, the conductive terminals 171 and 172 may include a first conductive terminal 171 and a second conductive terminal 172. The first conductive terminal 171 may be electrically connected to the first circuit 141. The second conductive terminal 172 may be electrically connected to the second circuit 142.

[0095] The conductive terminals 171 and 172 may be conductive pillars, solder balls, conductive bumps, or other conductive terminals having other forms or shapes. The conductive terminals 171 and 172 may be formed by electroplating, deposition, ball placement, reflow, and / or other suitable processes.

[0096] In this embodiment, other conductive layers (e.g., conductive layer 179) or corresponding insulating layers (not shown) may be provided between the conductive terminals 171 and 172 and the circuit layer 140. It is worth noting that the present invention does not limit the number of conductive layers. In one embodiment, the conductive layer 179 in contact with the conductive terminals 171 and 172 may be referred to as under-bump metallurgy (UBM).

[0097] Please continue to refer to Figures 1D to 1E In this embodiment, a plurality of package structures 100 may be formed through a singulation process. The singulation process may include, for example, a dicing process (cutting process) to cut through the substrate 161, the second conductive portion 162 of the patterned conductive layer 149 and / or fill the trench 130d (indicated at Figure 1B or Figure 1H ) within the partially patterned insulating layer 150.

[0098] It is worth noting that after the singulation process, similar component numbers will be used for the singulated components. For example, substrate 161 (such as Figure 1D As shown) can be a substrate 161 (as shown) after singulation. Figure 1E As shown), the first chip 110 (as Figure 1D As shown) after singulation, it can be the first chip 110 (as shown Figure 1E As shown), the second chip 120 (as Figure 1D As shown) can be the second chip 120 (as shown) after singulation. Figure 1E As shown), the first dielectric portion 131 (as Figure 1D As shown) after singulation, it can be the first dielectric portion 131 (as shown Figure 1E As shown), the second dielectric portion 132 (as Figure 1D As shown) after singulation, it can be the second dielectric portion 132 (as shown Figure 1E As shown), the first line 141 (as Figure 1D As shown) after being singulated, it can be the first line 141 (as shown Figure 1E As shown), the second line 142 (as Figure 1D As shown) after being singulated, it can be the second line 142 (as shown Figure 1E As shown), the patterned insulating layer 150 (as Figure 1D As shown) after singulation, the patterned insulating layer 150 (as shown) may be formed. Figure 1E Other simplified components will follow the same component symbol rules as above and will not be described or specifically shown here.

[0099] It should be noted that the present invention does not limit the order of configuring the conductive terminals 171 (if any), the conductive terminals 172 (if any), and the singulation process (if any).

[0100] Figure 1F This is a cross-sectional diagram of a packaging structure according to the first embodiment of the present invention. Figure 1F After the above steps, the production of the packaging structure 100 of this embodiment can be substantially completed.

[0101] In this embodiment, the sidewalls 161w of the substrate 161 and the sidewalls 150w of the patterned insulating layer 150 can be made substantially flush with each other through a cutting process that is the same as or similar to the aforementioned process. In another embodiment, the sidewalls 161w of the substrate 161, the sidewalls 162w of the second conductive portion 162, and the sidewalls 150w of the patterned insulating layer 150 can be made substantially flush with each other through a cutting process that is the same as or similar to the aforementioned process.

[0102] In one embodiment, the patterned insulating layer 150 may expose a portion of the second conductive portion 162 through a cutting process that is the same as or similar to the aforementioned cutting process. For example, the patterned insulating layer 150 may expose a sidewall 162 w of the second conductive portion 162 .

[0103] In this embodiment, the electrically connected substrate 161 and second conductive portion 162 can be referred to as a conductive member 160. The conductive member 160 has corresponding accommodation spaces S1 and S2, and the multiple chips 110 and 120 are disposed in the corresponding accommodation spaces S1 and S2. For example, the conductive member 160 can have a first accommodation space S1 and a second accommodation space S2, with the first chip 110 disposed in the first accommodation space S1 and the second chip 120 disposed in the second accommodation space S2.

[0104] Figure 1G is a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention. Figure 1I FIG. 1 is a partial top view of a packaging structure according to a first embodiment of the present invention. Figure 1G Can be corresponding to Figure 1F Magnified view of the middle region R1. Figure 1F The cross-sectional schematic diagram may correspond to Figure 1I The position of the section line II' in FIG. Figure 1I Some of the membrane layers or components are omitted. Figure 1I The patterned insulating layer 150 and the conductive terminals 171 and 172 are omitted in the figure.

[0105] Please refer to Figure 1F 、 Figure 1G and Figure 1I The package structure 100 includes a conductive member 160 , a plurality of chips 110 and 120 , a dielectric 130 , a circuit layer 140 and a patterned insulating layer 150 .

[0106] The chips 110 and 120 are disposed on the conductive member 160, and portions of the conductive member 160 surround the chips 110 and 120. For example, the first chip 110 and the second chip 120 may be disposed on a substrate 161 constituting the conductive member 160 (which may be referred to as a first conductive portion of the conductive member 160), and the second conductive portion 162 constituting the conductive member 160 may surround the first chip 110 and the second chip 120.

[0107] The dielectric body 130 encapsulates the plurality of chips 110 and 120. For example, the dielectric body 130 may include a first dielectric portion 131 and a second dielectric portion 132 separated from each other. The first dielectric portion 131 may encapsulate the first chip 110, and the second dielectric portion 132 may encapsulate the second chip 120.

[0108] In this embodiment, the dielectric body 130 may have a dielectric top surface 130a, a dielectric bottom surface 130b, and a dielectric side surface 130c. The dielectric bottom surface 130b is opposite to the dielectric top surface 130a, and the dielectric side surface 130c connects the dielectric top surface 130a and the dielectric bottom surface 130b. The second conductive portion 162 constituting the conductive element 160 may cover the dielectric side surface 130c. For example, the second conductive portion 162 may surround and cover the dielectric side surface 130c located on the first dielectric portion 131 and the dielectric side surface 130c located on the second dielectric portion 132.

[0109] The circuit layer 140 is located on the dielectric top surface 130a of the dielectric body 130 and electrically connects the chips 110 and 120. For example, the circuit layer 140 may include a first circuit 141 and a second circuit 142. The first circuit 141 may be electrically connected to the first chip 110, and the second circuit 142 may be electrically connected to the second chip 120.

[0110] In this embodiment, the first circuit 141 and the second circuit 142 are electrically isolated from each other. Furthermore, the conductive member 160 can shield electromagnetic signals between the first chip 110 and the second chip 120. This allows for signal isolation between the first chip 110 and the second chip 120, and reduces unexpected electromagnetic signal interference between the first chip 110 and the second chip 120.

[0111] In this embodiment, the second conductive portion 162 and the circuit layer 140 constituting the conductive element 160 may be formed from the same film layer. For example, the second conductive portion 162 and the circuit layer 140 may be formed through the same steps (eg, Figure 1C The second conductive portion 162 and the circuit layer 140 include corresponding seed layers 141s, 142s, and 146s and plated layers 141p, 142p, and 146p. For another example, the seed layer 141s, the seed layer 142s, and the seed layer 146s are substantially the same film layer, and the plated layer 141p, the plated layer 142p, and the plated layer 146p are substantially the same film layer.

[0112] The patterned insulating layer 150 covers the circuit layer 140 , and a portion of the patterned insulating layer 150 is located between the adjacent first chip 110 and the second chip 120 .

[0113] In this embodiment, the patterned insulating layer 150 may surround the second conductive portion 162. For example, the patterned insulating layer 150 may surround and cover the second conductive portion 162 located on the dielectric side surface 130c. This can reduce the possibility of peeling of the second conductive portion 162.

[0114] In this embodiment, the maximum thickness 150h of the patterned insulating layer 150 may be greater than the maximum thickness 130h of the dielectric body 130 , but the present invention is not limited thereto.

[0115] In this embodiment, the substrate 161 can be a block metal plate or other suitable conductive block substrate. During the manufacturing process of the package structure 100, the substrate 161 can be suitable for carrying the structure formed thereon or the component configured thereon. Moreover, the substrate 161 as a part of the conductive member 160 can reduce the electromagnetic wave signal from causing unexpected interference to the first chip 110 and / or the second chip 120. Moreover, the substrate 161 can be thermally coupled to the first chip 110 and / or the second chip 120. That is, the substrate 161 used for carrying during the manufacturing process of the package structure 100 can be used as an electromagnetic interference shielding (EMI Shielding) and / or heat dissipation component in the package structure 100. In this way, the manufacturing process of the package structure 100 can be relatively simple. Moreover, the yield and quality of the package structure 100 can be better.

[0116] In this embodiment, the second conductive portion 162 and the circuit layer 140 constituting the conductive element 160 can be formed in the same film layer in the same steps. This simplifies the manufacturing process of the package structure 100 and improves the yield and quality of the package structure 100.

[0117] In one embodiment, the substrate 161 may be a block-shaped plate that is not patterned (e.g., without perforations or recesses). This simplifies the manufacturing process of the package structure 100 and improves the yield and quality of the package structure 100.

[0118] Figure 2 The package structure 200 of the second embodiment is similar to the package structure 100 of the first embodiment. Similar components are denoted by the same reference numerals and have similar functions, materials, or formation methods, and their descriptions are omitted.

[0119] Please refer to Figure 2The package structure 200 may include a conductive member 160, a plurality of chips 110, 120, a dielectric 130, a circuit layer 140, a patterned insulating layer 150, and a thermal interface material layer (TIM layer) 281. The thermal interface material layer 281 may include a thermally conductive adhesive, a thermally conductive paste, a thermally conductive adhesive film, or a thermally conductive tape having a conductive material (e.g., conductive particles), but the present invention is not limited thereto. In one embodiment, the thermal interface material layer 281 may enhance the thermal coupling between the substrate 161 and the chip (e.g., the first chip 110 and / or the second chip 120).

[0120] Figure 3 1 is a cross-sectional view of a package structure according to a third embodiment of the present invention. The package structure 300 of the third embodiment is similar to the package structure 100 of the first embodiment. Similar components are denoted by the same reference numerals and have similar functions, materials, or formation methods, and their descriptions are omitted.

[0121] Please refer to Figure 3 The package structure 300 may include a conductive member 360 , a plurality of chips 110 , 120 , a dielectric 130 , a circuit layer 140 , and a patterned insulating layer 150 .

[0122] In this embodiment, substrate 382 may be a block-shaped insulating plate, and a conductive layer 361 may be provided on a surface of substrate 382. Conductive layer 361 and second conductive portion 162, which are electrically connected to each other, may be referred to as a conductive member 360. First chip 110 and second chip 120 may be disposed on conductive layer 361 (referred to as a first conductive portion) constituting conductive member 360.

[0123] In this embodiment, the substrate 382 and the conductive layer 361 thereon can be suitable for supporting structures formed thereon or components disposed thereon during the manufacturing process of the package structure 300. The conductive layer 361 can be a single film layer or a plurality of stacked film layers.

[0124] In summary, during the manufacturing process of the package structure, the substrate used for carrying the chip can serve as part of the conductive element. The second conductive portion, another part of the conductive element, can be made of the same film layer as the circuit layer used to electrically connect the chip. Furthermore, the conductive element surrounding the chip can reduce interference from external electromagnetic signals. This simplifies the manufacturing process of the package structure and improves the yield and quality of the package structure.

[0125] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, characterized in that: include: Conductive parts; A plurality of chips are disposed on the conductive member, and a portion of the conductive member surrounds the plurality of chips; a dielectric body covering the plurality of chips; a circuit layer, located on the dielectric body and electrically connected to the plurality of chips; as well as A patterned insulating layer covers the circuit layer, and a portion of the patterned insulating layer is located between adjacent chips, wherein: The conductive member includes a first conductive portion and a second conductive portion, the dielectric body is located on the first conductive portion, and the second conductive portion surrounds each of the plurality of chips; The sidewalls of the first conductive portion of the conductive member, the sidewalls of the second conductive portion of the conductive member, and the sidewalls of the patterned insulating layer are flush; The dielectric body has a dielectric top surface, a dielectric bottom surface, and a dielectric side surface, wherein the dielectric bottom surface is opposite to the dielectric top surface, and the dielectric side surface connects the dielectric top surface and the dielectric bottom surface; The circuit layer is located on the dielectric top surface of the dielectric body; The second conductive portion covers a portion of the dielectric top surface of the dielectric body, extends from the dielectric top surface of the dielectric body and covers the dielectric side surface to contact the first conductive portion; and The second conductive portion of the conductive element and the circuit layer are film layers formed through the same step.

2. The packaging structure according to claim 1, wherein: The multiple chips include a substrate, a chip connection pad and a chip protection layer, the chip connection pad is located on the substrate, the chip protection layer covers the substrate and exposes part of the chip connection pad, and the circuit layer passes through part of the dielectric to directly contact the chip connection pad.

3. The packaging structure according to claim 1, wherein: The patterned insulating layer surrounds the second conductive portion.

4. The packaging structure according to claim 1, wherein: The circuit layer includes a first circuit and a second circuit, the multiple chips include a first chip and a second chip, the first circuit is electrically connected to the first chip, the second circuit is electrically connected to the second chip, and the first chip and the second chip are signal-isolated from each other.

5. The packaging structure according to claim 1, wherein: The dielectric body includes a first dielectric portion and a second dielectric portion that are adjacent to and separated from each other, and a portion of the conductive element and a portion of the patterned insulating layer are located between the first dielectric portion and the second dielectric portion.

6. The packaging structure according to claim 1, wherein: The patterned insulating layer is in contact with the dielectric body, and an interface is formed between the patterned insulating layer and the dielectric body.

7. The packaging structure according to claim 1, wherein: The maximum thickness of the patterned insulating layer is greater than the maximum thickness of the dielectric body.

8. A method for manufacturing a packaging structure, characterized in that: include: Arrange a plurality of chips on a substrate; forming a dielectric material on the substrate to cover the plurality of chips; forming a dielectric body covering the plurality of chips by removing at least a portion of the dielectric material; forming a patterned conductive layer on the dielectric body, wherein a portion of the patterned conductive layer is electrically connected to the plurality of chips, and another portion of the patterned conductive layer constitutes a portion of the conductive element; as well as A patterned insulating layer is formed to cover the patterned conductive layer, and a portion of the patterned insulating layer is located between adjacent chips, wherein: The conductive member includes a first conductive portion and a second conductive portion, the dielectric body is located on the first conductive portion, and the second conductive portion surrounds each of the plurality of chips; The sidewalls of the first conductive portion of the conductive member, the sidewalls of the second conductive portion of the conductive member, and the sidewalls of the patterned insulating layer are flush; The dielectric body has a dielectric top surface, a dielectric bottom surface, and a dielectric side surface, wherein the dielectric bottom surface is opposite to the dielectric top surface, and the dielectric side surface connects the dielectric top surface and the dielectric bottom surface; The circuit layer is located on the dielectric top surface of the dielectric body; The second conductive portion covers a portion of the dielectric top surface of the dielectric body, extends from the dielectric top surface of the dielectric body and covers the dielectric side surface to contact the first conductive portion; and The second conductive portion of the conductive element and the circuit layer are film layers formed through the same step.

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