Memory device and method of manufacturing the same

Abstract

The present disclosure relates to a memory device and a method of manufacturing the same. A memory device is disclosed. The memory device includes a first transistor and a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time programmable (OTP) memory cell. The first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulating layer between the first bottom metal terminal and the first top metal terminal. The first insulating layer includes a first portion, a second portion separated from the first portion, and a third portion extending vertically between the first portion and the second portion. The first bottom metal terminal is located directly below and in contact with the first portion of the first insulating layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to a memory device and a method of manufacturing the same. BACKGROUND

[0002] One-time programmable (OTP) devices are a type of non-volatile memory (NVM) commonly used in read-only memory (ROM). Once an OTP device is programmed, the device cannot be reprogrammed. Common types include electrical fuses using metal fuses (e.g., eFuse) and anti-fuses using gate dielectrics. One issue with typical OTP devices is high voltage tolerance, which causes the OTP device to deteriorate over time. As technology continues to advance and follow Moore’s Law, devices are desired that require low voltage and small cell area. SUMMARY

[0003] A first aspect of the present disclosure relates to a memory device, comprising: a first transistor; and a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time programmable (OTP) memory cell; wherein the first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulating layer between the first bottom metal terminal and the first top metal terminal; wherein the first insulating layer comprises a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion; and wherein the first bottom metal terminal is directly below and in contact with the first portion of the first insulating layer.

[0004] A second aspect of the present disclosure relates to a memory device, comprising: a substrate; a memory array disposed above the substrate, the memory array comprising a plurality of one-time programmable (OTP) memory cells; wherein the plurality of OTP memory cells are formed based on a plurality of first interconnect structures, a plurality of insulating layers, and a plurality of second interconnect structures, and wherein each of the plurality of insulating layers comprises a stepped profile.

[0005] A third aspect of the present disclosure relates to a method of manufacturing a memory device, comprising: forming a transistor above a substrate; forming a first interconnect structure above the transistor to be electrically coupled to the transistor, wherein the first interconnect structure is disposed in a first metallization level; exposing a portion of the first interconnect structure; forming a stepped insulating layer above the first interconnect structure, wherein a lateral portion of the stepped insulating layer is in contact with the exposed portion of the first interconnect structure; and forming a second interconnect structure above the lateral portion of the stepped insulating layer, thereby forming a capacitor based at least on the first interconnect structure, the lateral portion of the stepped insulating layer, and the second interconnect structure; wherein the transistor and the capacitor collectively function as a one-time programmable (OTP) memory cell. Attached Figure Description

[0006] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. Note that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic block diagram of a storage device according to some embodiments is shown.

[0008] Figure 2A , Figure 2B and Figure 2C These are schematic circuit diagrams of memory cells in various operations according to some embodiments.

[0009] Figure 3A and Figure 3B Cross-sectional views of transistors and capacitors according to some embodiments are shown.

[0010] Figure 4A A circuit diagram of a storage device according to some embodiments is shown.

[0011] Figure 4B Illustrations are shown according to some embodiments Figure 4A The layout of the capacitors in the storage device is shown.

[0012] Figure 4C , Figure 4D , Figure 4E and Figure 4F Illustrations are shown according to some embodiments Figure 4A A top-down view of each layer of the storage device.

[0013] Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4K , Figure 4L and Figure 4M Illustrations are shown according to some embodiments Figure 4A The storage cells of the storage device are divided into various layers.

[0014] Figure 5A A circuit diagram of a storage device according to some embodiments is shown.

[0015] Figure 5B Illustrations are shown according to some embodiments Figure 5A The layout of the capacitors in the storage device is shown.

[0016] Figure 5C , Figure 5D , Figure 5E and Figure 5F A top-down view of various layers of a memory device according to some embodiments. Figure 5A A top-down view of various layers of a memory device according to some embodiments.

[0017] Figure 5G , Figure 5H , Figure 5I , Figure 5J , Figure 5K , Figure 5L and Figure 5M A top-down view of various layers of a memory device according to some embodiments. Figure 5A A top-down view of various layers of a memory device according to some embodiments.

[0018] Figure 6A A circuit schematic of a memory device according to some embodiments.

[0019] Figure 6B A layout of a capacitor of a memory device according to some embodiments. Figure 6A A layout of a capacitor of a memory device according to some embodiments.

[0020] Figure 6C , Figure 6D , Figure 6E and Figure 6F A top-down view of various layers of a memory device according to some embodiments. Figure 6A A top-down view of various layers of a memory device according to some embodiments.

[0021] Figure 6G , Figure 6H , Figure 6I , Figure 6J , Figure 6K , Figure 6L and Figure 6M A top-down view of various layers of a memory device according to some embodiments. Figure 6A A top-down view of various layers of a memory device according to some embodiments.

[0022] Figure 7A A circuit schematic of a memory device according to some embodiments.

[0023] Figure 7B A layout of a capacitor of a memory device according to some embodiments. Figure 7A A layout of a capacitor of a memory device according to some embodiments.

[0024] Figure 7C , Figure 7D , Figure 7E and Figure 7F A top-down view of various layers of a memory device according to some embodiments. Figure 7A A top-down view of various layers of a memory device according to some embodiments.

[0025] Figure 7G , Figure 7H , Figure 7I , Figure 7J , Figure 7K , Figure 7L and Figure 7M Illustrations are shown according to some embodiments Figure 7A The storage cells of the storage device are divided into various layers.

[0026] Figure 8 A flowchart of an example method for manufacturing a MIM capacitor according to some embodiments is shown.

[0027] Figure 9A , Figure 9B , Figure 9C , Figure 9D , Figure 9E , Figure 9F , Figure 9G , Figure 9H , Figure 9I and Figure 9J The passage according to some embodiments is shown. Figure 8 Cross-sectional views of an example MIM capacitor manufactured using this method during various manufacturing stages.

[0028] Figure 10 Illustrations are shown according to some embodiments Figure 3B The cross-section of the storage device shown. Detailed Implementation

[0029] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature can include embodiments in which the first and second features are formed in direct contact, and can also include embodiments in which an additional feature can be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0030] Furthermore, spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein shall be interpreted accordingly.

[0031] Integrated circuits (ICs) sometimes include one-time programmable (OTP) memory to provide non-volatile memory (NVM) in which data is not lost when the IC is powered off. One type of OTP device includes anti-fuse memory. An anti-fuse memory cell typically includes a program MOS transistor (or MOS capacitor) and at least one read MOS transistor. The gate dielectric of the program MOS transistor is broken down causing the gate and source or drain regions of the program MOS transistor to be interconnected. One of the disadvantages of anti-fuse is the need for a high voltage (typically about 5V) to program the device. Another type of OTP device includes an eFuse that uses a metal fuse. The eFuse is programmed by electrically blowing a strip of metal or polycrystalline material using a high density current flow using an I / O voltage. The eFuse is programmed using a program voltage of about 1.8V, which is an advantage over anti-fuse. However, the eFuse requires more area for a memory cell. For example, a typical eFuse cell area is about 1.769 μm 2 , while a typical anti-fuse memory cell area is about 0.0674 μm 2 . Thus, eFuse is not desirable for applications requiring dense memory, but as noted above, anti-fuse requires a high voltage, which is undesirable for low power applications.

[0032] In some embodiments, the memory cell has a single transistor single capacitor (1T1C) configuration with a capacitor and a transistor coupled in series between a bit line and ground. A gate terminal of the transistor is coupled to a word line. The capacitor is an inter-metal (or insulator)-metal (MIM) capacitor above the transistor. The insulating material of the capacitor is configured to break down at a predetermined breakdown voltage or higher voltage applied across the insulating material. When the insulating material has not broken down, the memory cell stores a first data, such as a logic "1". When the insulating material breaks down, the memory cell stores a second data, such as a logic "0". The memory cell in at least one embodiment provides one or more improvements over other methods, such as gate oxide anti-fuse and metal fuse, including but not limited to smaller chip area, lower program voltage, lower disturb voltage, etc. An OTP device including the MIM capacitor of the disclosed technology can be superior to anti-fuse devices and eFuse devices because the OTP memory cell including the MIM capacitor can have a smaller cell area (about 0.0378 μm 2 to about 0.0674 μm 2 ) and a low program voltage (less than about 1.8V), which is a superior combination of advantages over eFuse and anti-fuse technology.

[0033] Figure 1A schematic block diagram of a memory device 100 is shown in accordance with some embodiments. A memory device is a class of IC devices. In at least one embodiment, a memory device is a standalone IC device. In some embodiments, a memory device is included as part of a larger IC device that includes circuitry for other functions in addition to the memory device.

[0034] The memory device 100 includes at least one memory cell MC and a controller (also referred to as “control circuitry”) 102 coupled to control operation of the memory cell MC. In Figure 1 In an example configuration, the memory device 100 includes a plurality of memory cells MC arranged in a plurality of columns and rows in a memory array 104. The memory device 100 also includes a plurality of word lines WL[0] through WL[m] extending along the rows of memory cells MC, a plurality of source lines SL[0] through SL[m] extending along the rows of memory cells MC, and a plurality of bit lines (also referred to as “data lines”) BL[0] through BL[k] extending along the columns of memory cells MC. Each memory cell MC is coupled to the controller 102 by at least one of the word lines, at least one of the source lines, and at least one of the bit lines. Examples of word lines include, but are not limited to, a read word line for transmitting an address of a memory cell MC to be read, a write word line for transmitting an address of a memory cell MC to be written, and the like. In at least one embodiment, a set of word lines is configured to function as both a read word line and a write word line. Examples of bit lines include a read bit line for transmitting data read from a memory cell MC indicated by a corresponding word line, a write bit line for transmitting data to be written to a memory cell MC indicated by a corresponding word line, and the like. In at least one embodiment, a set of bit lines is configured to function as both a read bit line and a write bit line. In one or more embodiments, each memory cell MC is coupled to a pair of bit lines, which pair of bit lines is referred to as a bit line and a bit line bar. Word lines are generally referred to herein as WL, source lines are generally referred to herein as SL, and bit lines are generally referred to herein as BL. Various numbers of word lines and / or bit lines and / or source lines in the memory device 100 are within the scope of various embodiments. In at least one embodiment, the source lines SL are arranged in columns, rather than rows as shown in Figure 1

[0035] In Figure 1 ​In the example configuration of the memory device 100, the controller 102 includes a word line driver 112, a source line driver 114, a bit line driver 116, and a sense amplifier (SA) 118, which are configured to perform at least one of a read operation or a write operation. In at least one embodiment, the controller 102 also includes one or more clock generators for providing clock signals to various components of the memory device 100, one or more input / output (I / O) circuits for exchanging data with external devices, and / or one or more controllers for controlling various operations in the memory device 100. In at least one embodiment, the source line driver 114 is omitted.

[0036] The word line driver 112 is coupled to the storage array 104 via word lines WL. The word line driver 112 is configured to decode a row address of a storage cell MC selected for access in a read operation or a write operation. The word line driver 112 is configured to provide a voltage to a selected word line WL corresponding to the decoded row address, and to provide a different voltage to other unselected word lines WL. The source line driver 114 is coupled to the storage array 104 via source lines SL. The source line driver 114 is configured to provide a voltage to a selected source line SL corresponding to a selected storage cell MC, and to provide a different voltage to other unselected source lines SL. The bit line driver 116 (also referred to as a “write driver”) is coupled to the storage array 104 via bit lines BL. The bit line driver 116 is configured to decode a column address of a storage cell MC selected for access in a read operation or a write operation. The bit line driver 116 is configured to provide a voltage to a selected bit line BL corresponding to the decoded column address, and to provide a different voltage to other unselected bit lines BL. In a write operation, the bit line driver 116 is configured to provide a write voltage (also referred to as a “program voltage”) to a selected bit line BL. In a read operation, the bit line driver 116 is configured to provide a read voltage to a selected bit line BL. The SA 118 is coupled to the storage array 104 via bit lines BL. In a read operation, the SA 118 is configured to sense data read from a storage cell MC accessed and retrieved through a corresponding bit line BL. The described memory device configuration is an example, and other memory device configurations are within the scope of various embodiments. In at least one embodiment, the memory device 100 is a one-time programmable (OTP) non-volatile memory, and the storage cells MC are OTP storage cells. Other types of memory are also within the scope of various embodiments. Example memory types for the memory device 100 include, but are not limited to, eFuse, anti-fuse, magnetoresistive random access memory (MRAM), etc.

[0037] Figures 2A-2Cis a schematic circuit diagram of a storage cell 200 in various operations according to some embodiments. In at least one embodiment, the storage cell 200 corresponds to at least one storage cell MC in the memory device 100.

[0038] In Figure 2A , the storage cell 200 includes a capacitor C and a transistor T. The transistor T has a gate terminal 222 coupled to a word line WL, a first terminal 224, and a second terminal 226. The capacitor C has a first terminal 234 coupled to the first terminal 224 of the transistor T, a second terminal 236 coupled to a bit line BL, and an insulating material (not shown in Figure 2A ) between the first terminal 234 and the second terminal 236. The insulating material is configured to break down at a predetermined breakdown voltage or higher voltage applied between the first terminal 234 and the second terminal 236.

[0039] In Figure 2A an example configuration, the second terminal 226 is coupled to a source line SL. In other words, the capacitor C is coupled in series with the transistor T between the bit line BL and the source line SL. In at least one embodiment, the word line WL corresponds to at least one word line WL in the memory device 100, the source line SL corresponds to at least one source line SL in the memory device 100, and the bit line BL corresponds to at least one bit line BL in the memory device 100. In at least one embodiment, the source line SL is omitted, and the second terminal 226 is coupled to a node at a predetermined voltage. Examples of the predetermined voltage include, but are not limited to, a ground voltage VSS or a positive supply voltage VDD, among others.

[0040] Examples of the transistor T include, but are not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS) transistor, a P-channel metal-oxide-semiconductor (PMOS), an N-channel metal-oxide-semiconductor (NMOS), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a P-channel and / or N-channel field-effect transistor (PFET / NFET), a FinFET, a planar MOS transistor with raised source / drain, a nanosheet FET, a nanowire FET, among others. The first terminal 224 is a source / drain of the transistor T, and the second terminal 226 is another source / drain of the transistor T. In the example configuration described with respect to Figure 2A , the transistor T is an NMOS transistor, the first terminal 224 is a drain of the transistor T, and the second terminal 226 is a source of the transistor T. Other configurations including a PMOS transistor instead of an NMOS transistor are within the scope of various embodiments.

[0041] Examples of capacitor C include, but are not limited to, MIM capacitors. Other capacitor configurations (e.g., MOS capacitors) are within the scope of various embodiments. A MIM capacitor includes a lower electrode (i.e., a lower terminal) corresponding to one of the first end 234 or the second end 236, an upper electrode (i.e., an upper terminal) corresponding to the other of the first end 234 or the second end 236, and an insulating material between the lower electrode and the upper electrode. Example materials of the insulating material include, but are not limited to, silicon oxide, silicon dioxide, aluminum oxide, hafnium oxide, tantalum oxide, ZrO, TiO2, HfO x , high-k dielectrics, etc. Examples of high-k dielectrics include, but are not limited to, zirconium dioxide, hafnium dioxide, zirconium silicate, hafnium silicate, etc. In at least one embodiment, the insulating material of capacitor C is the same as or similar to a gate dielectric included in a transistor (e.g., transistor T). In at least one embodiment, transistor T is formed over a semiconductor substrate in a front-end-of-line (FEOL) process, and then capacitor C is formed as a MIM capacitor over transistor T in a back-end-of-line (BEOL) process. Further details regarding the formation of a MIM capacitor are described in connection with Figure 8 , Figures 9A to 9J and Figure 10 Other example structures and example fabrication processes of a memory cell according to some embodiments are described.

[0042] In some embodiments, the operation of memory cell 200 is controlled by a controller (e.g., controller 102 of memory device 100). For example, when memory cell 200 is selected in a program operation (also referred to as a “write operation”), controller 102 is configured to apply a turn-ON voltage to gate terminal 222 of transistor T via word line WL to turn ON transistor T. Controller 102 is also configured to apply a program voltage to second end 236 of capacitor C via bit line BL, and to apply a ground voltage VSS to source line SL. In at least one embodiment, source line SL is always grounded. When transistor T is turned ON by the turn-ON voltage and electrically couples first end 234 of capacitor C to the ground voltage VSS on source line SL, the program voltage applied from bit line BL to second end 236 results in a predetermined breakdown voltage or higher voltage to be applied between first end 234 and second end 236 of capacitor C. As a result, the insulating material of capacitor C shorts at the applied breakdown voltage or higher. In other words, the insulating material is broken down and becomes a resistive structure, e.g., as described in connection with Figure 2B The broken down insulating material corresponds to a first data or a first logic value stored in memory cell 200. In at least one embodiment, the first data corresponding to the broken down insulating material is a logic “0”.

[0043] When the storage cell 200 is not selected in a program operation, the controller 102 is configured to not apply at least one of the turn-on voltage, the program voltage, or the ground voltage VSS to the respective gate terminal 222, the bit line BL, or the source line SL. As a result, the insulating material of the capacitor C is not broken down, and the capacitor C retains the capacitive structure, e.g., as described with respect to Figure 2C The insulating material that has not been broken down corresponds to a second data or second logic value stored in the storage cell 200. In at least one embodiment, the second data corresponding to the insulating material that has not been broken down is a logic “1.”

[0044] When the storage cell 200 is selected in a read operation, the controller 102 is configured to apply a turn-on voltage to the gate terminal 222 of the transistor T via the word line WL to turn on the transistor T. The controller 102 is also configured to apply a read voltage to the second terminal 236 of the capacitor C via the bit line BL, and to apply a ground voltage VSS to the source line SL. In at least one embodiment, the source line SL is always grounded. When the transistor T is turned on by the turn-on voltage and electrically couples the first terminal 234 of the capacitor C to the ground voltage VSS on the source line SL, the controller 102 is configured to sense a current flowing into the storage cell 200, e.g., by using the SA 118, to detect the data stored in the storage cell 200.

[0045] In Figure 2B which the storage cell 200 has previously been programmed to store a logic “0,” the insulating material of the capacitor C has been broken down and becomes the resistive structure 238, and the read voltage applied to the bit line BL causes a current I read to flow through the resistive structure 238 and the turned-on transistor T to the ground voltage VSS at the source line SL. The SA 118 is configured to sense the current I read . The controller 102 is configured to detect that the storage cell 200 stores a logic “0” based on the sensed current I read .

[0046] In Figure 2C which the storage cell 200 has not been previously programmed, the storage cell 200 stores a logic “1,” the insulating material of the capacitor C has not been broken down, and the capacitor C retains the capacitive structure. The read voltage applied to the bit line BL is below the breakdown voltage and causes no current, or a current I read that is close to zero, to flow through the capacitor C and the turned-on transistor T to the ground at the source line SL. The SA 118 is configured to sense no current, or a current I read that is close to zero, flowing through the storage cell 200. Accordingly, the controller 102 is configured to detect that the storage cell 200 stores a logic “1.”

[0047] In at least one embodiment, the turn-on voltage in the program operation is the same as the turn-on voltage in the read operation. Other configurations that apply different turn-on voltages in different operations are within the scope of various embodiments. The read voltage is lower than the program voltage. In at least one embodiment, the program voltage is about 1.2V or lower, the breakdown voltage is about 1.2V, and the read voltage is about 0.75V. Other voltage schemes are within the scope of various embodiments.

[0048] In some embodiments, the storage cells having the described 1T1C configuration can achieve one or more advantages over other approaches, including but not limited to smaller chip area (i.e., the area that the storage cell occupies on a wafer), lower program voltage, lower disturb voltage, improved reliability, enhanced data security, etc. In addition, the present disclosure includes embodiments that form the capacitor in an interconnect layer to reduce area and / or cost.

[0049] For example, a storage cell according to other approaches that use a gate oxide antifuse occupies about 0.0674 pm2of chip area and has a program voltage of about 5V, a program disturb voltage of about 2.0V, and a read disturb voltage of about 1.3V. In contrast, an example storage cell having a 1T1C configuration according to some embodiments of the present disclosure occupies about 0.0378 pm2to 0.0674 pm2of smaller chip area, has a lower program voltage of less than 1.8V, and lower disturb voltages. 2 2 2 The higher program voltage of a storage cell that uses a gate oxide antifuse causes reliability issues. The lower program voltage of a storage cell according to some embodiments creates lower stress in the storage cell, thus improving reliability. The storage cell according to some embodiments is also suitable for advanced process nodes. In contrast, a storage cell that uses a gate oxide antifuse encounters scalability and / or manufacturability issues at advanced process nodes.

[0050] For another example, a storage cell according to other approaches that use a metal fuse (e.g., eFuse) occupies about 1.769 pm2of chip area and has a program voltage of about 1.8V. In contrast, an example storage cell having a 1T1C configuration according to some embodiments occupies about 0.0378 pm2to 0.0674 pm2of smaller chip area, has a lower program voltage of less than 1.8V, and lower disturb voltages. 2 2 2 ​​​​smaller chip area, which corresponds to a chip area reduction of up to about 90%. The lower programming voltage of the storage cell according to some embodiments generates lower stress in the storage cell, thus improving reliability compared to storage cells using metal fuses. In addition, storage cells using metal fuses have data security issues that are eliminated in the storage cell according to some embodiments. Furthermore, the storage cell according to some embodiments is suitable for advanced process nodes. In contrast, storage cells using gate oxide antifuses or metal fuses encounter scalability and / or manufacturability issues at advanced process nodes.

[0051] Figure 3A and Figure 3B A cross-sectional view of a transistor and a capacitor according to some embodiments is shown. Figure 3A and Figure 3B The transistor and capacitor can be Figures 2A-2C the transistor T and capacitor C shown, but the disclosure is not limited thereto. For example, the transistor can be p-type or can take any other suitable modification. Figure 3A and Figure 3B The transistor 302 in both the word line driver 200 and the memory cell 100 can include a gate terminal 222, a first electrode 224, and a second electrode 226 that are electrically coupled to a word line, a source line, and an electrode of the capacitor C, respectively, as shown in Figure 2A .

[0052] Figure 3A A cross-sectional view of a transistor 302 and a capacitor 300A having one structure according to some embodiments is shown. The capacitor 300A includes a top electrode 304, an insulator 306, and a bottom electrode 308. The top electrode 304 is formed on top of the dielectric insulator 306 and under a via 310. A metal layer (sometimes referred to as a metallization layer) M6 of an interconnect structure formed over the semiconductor device is shown, but the metal layer formed over the capacitor 300A need not be the metal layer M6 and can be any other metal layer suitable for a memory device. For example, it can be the metal layer Ml, M2, etc. As described above, the insulator 306 can include a high-k dielectric insulator, but is not limited thereto. The via 310 is a conductive via that electrically connects the metal layer M6 to the top electrode 304, and the metal layer M6 can be connected to, for example, a bit line. The bottom electrode 308 can be part of the metal layer M5, or part of any layer formed under the via 310. For example, if the metal layer formed over the via 310 is the metal layer M3, the metal layer that includes the bottom electrode 308 can be the metal layer M2.

[0053] Figure 3BA cross-sectional view of a transistor 302 and a capacitor 300B having another structure is shown in accordance with some embodiments. The capacitor 300B includes a via 312 as a top electrode, an insulator 306, and a bottom electrode 308. For the capacitor 300B, unlike the capacitor 300A, Figure 3A a separate top electrode is not formed, and the via 312 can be used as a top electrode. By omitting a separately formed top electrode in the capacitor 300B, the manufacturing process can reduce costs and materials during manufacturing.

[0054] Figure 4A A circuit schematic of a memory device 400 is shown in accordance with some embodiments. The memory device 400 includes four memory cells, which can be made up of four transistors and four capacitors, source lines SL[0] and SL[l], word lines WL[0] and WL[l], and a bit line BL[0]. It can be appreciated that Figure 4A the memory device 400 in is just one example, and the memory device 400 can have a variety of different schematics, including those discussed below. Reference is made to Figure 4G-Figure 4M Details of the layout layers of the memory cell 400A are shown and described.

[0055] The memory device 400 includes four 1T1C memory cells electrically connected to each other. The cells include a cell 1 (i.e., the memory cell 400A) having a transistor T1 and a capacitor C1, a cell 2 having a transistor T2 and a capacitor C2, a cell 3 having a transistor T3 and a capacitor C3, and a cell 4 having a transistor T4 and a capacitor C4. The source electrode of each of the transistors T1-T4 is connected to the same bit line BL[0]. The gate electrode of each of the transistors T1 and T3 is connected to the word line WL[0], and the gate electrode of each of the transistors T2 and T4 is connected to the word line WL[l]. The first electrode (i.e., the top electrode) of each of the capacitors C1 and C2 is connected to the source line SL[0], and the first electrode (i.e., the top electrode) of each of the capacitors C3 and C4 is connected to the source line SL[l]. The second electrode (i.e., the bottom electrode) of each of the capacitors C1-C4 is connected to the drain electrode of the transistors T1-T4, respectively. In some embodiments, the first electrode of the capacitors C1-C4 includes the top electrode 304 of the capacitor 300A or the via 312 of the capacitor 300B (which is used as a top electrode), and the second electrode of the capacitors C1-C4 includes the bottom electrode 308 of the capacitor 300A or the capacitor 300B.

[0056] The chip area of the memory cell 400 in some embodiments is reduced by about 25% compared to the typical chip area of a one-time programmable memory chip having a similar circuit of a prior art design due to the MIM capacitor being formed in a metal layer above the source / drain electrodes of the transistors.

[0057] Figure 4B A layout of a capacitor CI of the memory device 400 is shown in accordance with some embodiments. Figure 4A The layout of the capacitor CI of the memory device 400 is shown. The capacitor CI is formed from a bottom electrode 402, an insulator 406, and a top electrode 404. While this layout shows only a few layers, this is for illustrative purposes only, and one of ordinary skill in the art will recognize that additional layers can exist above, below, or between the layers shown.

[0058] The layout of several layers of one memory cell of the memory device 400 can look like Figure 4B For example, for the capacitor CI, the metal layer that includes the bottom electrode 402 can extend in the y-direction, and the metal layer that includes the top electrode can extend in the x-direction. At the intersection of the two metal layers and between the two metal layers, the insulator 406 is formed, such that the combination of the metal layers and the insulator 406 forms the capacitor CI of the memory device 400. The bottom electrode 402 and the top electrode 404 are formed from metal. The bottom electrode 402 can be the metal layer M5 in the interconnect structure described above, but is not limited thereto. The top electrode 404 can be the metal layer M6 in the interconnect structure described above, but is not limited thereto. For example, the bottom electrode 402 can be the metal layer M6, and the top electrode can be the metal layer M7.

[0059] Figures 4C-4F A top-down view of various layers of the memory device 400 is shown in accordance with some embodiments. Figure 4A These layers are illustrated as an example of how the memory device 400 can be layered to form the transistors T1-T4, and to form the interconnect structure above the transistors to form the capacitors CI-C4. One of ordinary skill in the art will recognize that the memory device 400 can be arranged in different ways to form Figure 4A the circuit shown. Figures 4C-4F Each of the layouts in Figure 4A four adjacent instances of the memory device 400; in other words, 16 memory cells are shown. While not shown for clarity, at different regions of the layers shown, a plurality of vias are formed through the layers or between the layers. Figures 4C-4F

[0060] Figure 4C ​A gate layer PO and an active layer OD forming some portions of the transistors T1-T4 are shown in accordance with some embodiments. The gate layer PO is formed of an electrically conductive material such as polysilicon and serves as the gate of the transistors T1-T4. Other electrically conductive materials (e.g., metals) for the gate layer PO are within the scope of various embodiments. The active layer OD is formed of a semiconductor material and can include p-type or n-type dopants. The active layer OD includes the source and drain terminals of the transistors T1-T4 and the conduction channel when the transistors are turned on. The gate layer PO extends in the y-direction and the active layer OD extends in the x-direction.

[0061] Figure 4D Metal layers M0, M1, and M2 are shown in accordance with some embodiments. The metal layer M0 is the lowest metal layer of the interconnect structure formed above the transistors T1-T4. The metal layer M1 is formed above the metal layer M0 and the metal layer M2 is formed above the metal layer M1. In Figure 4D , the metal layers M0 and M2 substantially overlap each other, but these layers are not limited thereto. The metal layers M0 and M2 extend in the x-direction and M1 extends in the y-direction.

[0062] The metal layers M0 and M2 include bit lines BL[0], BL[1], BL[2], and BL[3] that carry respective bit line signals. For example, when the bit line driver 116 drives a high voltage on BL[0], the portions of the metal layers M0 and M2 that correspond to the bit line BL[0] will have the high voltage. The metal layer M1 includes word lines WL[0], WL[1], WL[2], and WL[3] that carry respective word line signals. For example, when the word line driver 112 drives a high voltage to WL[0], the corresponding portion of the metal layer M1 will have the high voltage. The metal layers M0-M2 can also have any voltage (e.g., low voltage, no voltage) driven by the respective bit line driver 116 or word line driver 112.

[0063] Figure 4E Metal layers M3 and M4 are shown in accordance with some embodiments. The metal layer M3 is formed above the metal layer M2 and the metal layer M4 is formed above the metal layer M3. At least some portions of the metal layer M3 and the metal layer M1 can be similarly patterned. Thus, the metal layer M1 and the metal layer M3 can overlap in some portions of the layout. Further, the metal layer M1 and M3 can be electrically coupled to each other in some portions of the layout. Further, the metal layer M4 can be similarly patterned to some portions of the metal layers M0 and M2, thus the metal layers M0, M2, and M4 can overlap in some portions of the layout. Further, the metal layers M0, M2, and M4 can be electrically coupled to each other in some portions of the layout.

[0064] Metal layer M3 can include word lines WL[0], WL[l], WL[2], and WL[3] that carry respective word line signals. For example, when word line driver 112 attempts to drive a high voltage on WL[0], the portion of metal layer M3 that corresponds to word line WL[0] will have a high voltage. Metal layer M4 can include bit lines BL[0], BL[l], BL[2], and BL[3] that carry respective bit line signals. For example, when bit line driver 116 attempts to drive a high voltage on BL[0], the portion of metal layer M3 that corresponds to bit line BL[0] will have a high voltage. Metal layer M4 can also include dummy bit lines DMY. However, these dummy bit lines DMY are not electrically coupled to any of bit line driver 116, word line driver 112, or source line driver 114, and thus do not function. Dummy bit lines DMY can be formed at the edge of memory device 400.

[0065] Figure 4F Metal layers M5 and M6 are shown in accordance with some embodiments. Metal layer M5 is formed above metal layer M4, and metal layer M6 is formed above metal layer M5. As described above, a capacitor can be formed at the overlap of metal layer M5 and metal layer M6. When a dielectric insulator is formed between metal layers M5 and M6, a MIM capacitor is formed. Figure 4F The MIM capacitor shown can be capacitor C1-C4. In Figure 4F In some embodiments, 16 MIM capacitors are shown, but embodiments are not limited to this and there can be more or less than 16 MIM capacitors.

[0066] Metal layer M6 can include source lines SL[0], SL[l], SL[2], and SL[3] that carry respective source line signals. For example, when source line driver 114 drives a high voltage on SL[0], the portion of metal layer M6 that corresponds to source line SL[0] will have a high voltage.

[0067] Figure 4G-Figure 4M Various layers of a memory cell 400A of memory device 400 are shown in accordance with some embodiments. Memory cell 400A includes Figure 4A transistor T1 and capacitor C1 of memory cell 400A, but the present disclosure is not limited to this and the layout can be applied to T2 and C2, or T3 and C3, or T4 and C4. Figure 4G-Figure 4MVarious layers of an example memory cell 400A including only one transistor Tl and one capacitor Cl are shown. These figures also show various metal layers, vias connecting the various metal layers, and their relationship to bit lines, word lines, and source lines. However, the positions of the vias relative to each other and the relative positions of the layers can not be vertically aligned. Thus, for clarity and simplicity, the layers shown in the figures are not meant to overlap each other to show a top-down view of the layout, and one of ordinary skill in the art will recognize that the layers can be rearranged to form a layout of a memory cell.

[0068] Referring to Figure 4G , according to some embodiments, the gate layer PO and the active layer OD of the memory cell 400A are shown. The memory cell 400A includes a transistor 408, which can include the transistor Tl. A via 410A is formed over the gate layer PO to electrically couple the gate layer PO to an upper layer (e.g., the word line WL[0]). A via 412A is formed over the active layer OD to electrically couple the active layer OD to an upper layer (e.g., the bit line BL[0]). A via 414A is formed over the active layer OD to electrically connect a source terminal of the transistor Tl to an upper layer (e.g., the metal layer M5) that serves as a bottom electrode of the capacitor Cl.

[0069] Referring to Figure 4H , according to some embodiments, the metal layers M0 and Ml of the memory cell 400A are shown. The metal layer M0 extends in the x-direction, and the metal layer Ml extends in the y-direction. The vias 410B, 412B, and 414B are formed between the metal layers M0 and Ml. The via 410B can overlap the via 410A, the via 412B can overlap the via 412A, and the via 414B can overlap the via 414A.

[0070] The metal layer M0 can serve as the bit line BL[0]. In such embodiments, the bit line driver 116 can drive a bit line signal through the bit line BL[0] to the active layer OD through the via 412A. Thus, the source electrode of the transistor Tl can be electrically connected to the bit line BL[0], as shown in Figure 4A .

[0071] The metal layer Ml can serve as the word line WL[0]. The word line driver 112 can drive a word line signal through the word line WL[0] to the gate layer PO through the vias 410B and 410A. Thus, the gate of the transistor Tl can be electrically connected to the word line WL[0], as shown in Figure 4A .

[0072] Referring to Figure 4IAccording to some embodiments, metal layers M1 and M2 of memory cell 400A are shown. Metal layer M1 extends in the y-direction, and metal layer M2 extends in the x-direction. Vias 410C, 412C, and 414C are formed between metal layers M1 and M2. Via 410C may overlap with vias 410A-412B, via 412C may overlap with vias 412A-412B, and via 414C may overlap with vias 414A-412B. As described above, metal layer M1 can be used as a word line [0].

[0073] Metal layer M2 can be used as bit line BL[0]. In such an embodiment, bit line driver 116 can drive the bit line signal through bit line BL[0] to active layer OD through vias 412A-412C. Therefore, the source electrode of transistor T1 can be electrically connected to bit line BL[0], as... Figure 4A As shown.

[0074] refer to Figure 4J According to some embodiments, metal layers M2 and M3 of memory cell 400A are shown. Metal layer M2 extends in the x-direction and metal layer M3 extends in the y-direction. Vias 410D, 412D and 414D are formed between metal layers M2 and M3. Via 410D may overlap with vias 410A-410C, via 412D may overlap with vias 412A-412C, and via 414D may overlap with vias 414A-414C. As described above, metal layer M2 can be used as a bit line [0].

[0075] Metal layer M3 can be used as word line WL[0]. In such an embodiment, word line driver 112 can drive the word line signal through word line WL[0] to gate layer PO through vias 410A-410D. Therefore, the gate of transistor T1 can be electrically connected to word line WL[0], as... Figure 4A As shown.

[0076] refer to Figure 4K According to some embodiments, metal layers M3 and M4 of memory cell 400A are shown. Metal layer M3 extends in the y-direction and metal layer M4 extends in the x-direction. Vias 410E, 412E and 414E are formed between metal layers M3 and M4. Via 410E may overlap with vias 410A-410D, via 412E may overlap with vias 412A-412D, and via 414E may overlap with vias 414A-414D. As described above, metal layer M3 can be used as word line WL[0].

[0077] Metal layer M4 can be used as bit line BL[0]. In such embodiments, bit line driver 116 can drive a bit line signal through bit line BL[0] to the active layer OD through vias 412A-412D. Thus, the source electrode of transistor Tl can be electrically connected to bit line BL[0], as shown in Figure 4A .

[0078] As discussed with respect to Figure 4E , dummy bit lines DMY can be formed. Referring to Figure 4K , metal layer M4 can include dummy bit lines DMY. However, dummy bit lines DMY are not used as actual bit lines and can be formed, for example, at the edge of a memory array.

[0079] Referring to Figure 4L , metal layers M4 and M5 of memory cell 400A are shown according to some embodiments. Metal layer M4 extends in the x-direction, and metal layer M5 extends in the y-direction. Via 414F is formed between metal layers M4 and M5. Via 414F can overlap vias 414A-414E. As described above, metal layer M4 can be used as bit line BL[0] or a dummy bit line DMY.

[0080] Metal layer M5 can be used as a bottom electrode of capacitor Cl. Thus, the drain of transistor Tl can be electrically connected to the bottom electrode of capacitor Cl, as shown in Figure 4A .

[0081] Referring to Figure 4M , metal layers M5 and M6 of memory cell 400A are shown according to some embodiments. Metal layer M5 extends in the y-direction, and metal layer M6 extends in the x-direction. As described above, metal layer M5 can be used as a bottom electrode of a capacitor.

[0082] Metal layer M6 can be used as a top electrode of capacitor Cl. As described above, memory cell 400A includes MIM capacitor 416, which can include capacitor Cl. Although not shown, a dielectric insulator layer is formed between metal layers M5 and M6 to form MIM capacitor 416, and a bottom electrode formed on metal layer M5 is electrically connected to the drain of transistor 408 through vias 414A-414E. Thus, MIM capacitor 416 is electrically connected to transistor 408 of Figure 4G . Further, although not shown in Figure 4M , a via can be formed between metal layers M5 and M6.

[0083] Metal layer M6 can be used as source line SL[0]. In such embodiments, source line driver 114 can drive a source line signal through source line SL[0] to metal layer M6 to the top electrode of the MIM capacitor. Thus, the top electrode of capacitor Cl can be electrically connected to source line SL[0], as shown in Figure 4A .

[0084] Although Figure 4G-Figure 4M While metal layer M5 is shown and described as including the bottom electrode of capacitor 408 (and capacitor Cl), and metal layer M6 is shown and described as including the top electrode of capacitor 408 (and capacitor Cl), embodiments are not limited thereto. As described with reference to Figure 3A and Figure 3B described, the top electrode can be formed separately above the dielectric insulator and below metal layer M6 (as shown in FIG. 3A), or when the top electrode is not formed separately, the via formed between the dielectric insulator and metal layer M6 can be used as the top electrode (as shown in FIG. 3B). Figure 3A Figure 3B

[0085] Figure 5A A circuit schematic of a memory device 500 is shown in accordance with some embodiments. Memory device 500 includes four storage cells, which can be made up of four transistors and four capacitors, source lines SL[0] and SL[l], word lines WL[0] and WL[l], and bit lines BL[0] and BL[l]. It will be appreciated that Figure 5A Memory device 500 in FIG. 4 is just one example, and memory device 500 can have a variety of different schematics, including those discussed below. Reference is made to Figure 5G-Figure 5M Details of the layout layers of storage cell 500A are shown and described.

[0086] Memory device 500 includes four 1T1C storage cells electrically connected to one another. The cells include cell 1 (i.e., storage cell 500A) having transistor T5 and capacitor C5, cell 2 having transistor T6 and capacitor C6, cell 3 having transistor T7 and capacitor C7, and cell 4 having transistor T8 and capacitor C8. The source electrode of each of transistors T5 and T6 is connected to the same bit line BL[0], and the source electrode of each of transistors T7 and T8 is connected to the same bit line BL[l]. The gate electrode of each of transistors T5 and T7 is connected to word line WL[0], and the gate electrode of each of transistors T6 and T8 is connected to word line WL[l]. The first electrode (i.e., the top electrode) of each of capacitors C5 and C7 is connected to source line SL[0], and the first electrode (top electrode) of each of capacitors C6 and C8 is connected to source line SL[l]. The second electrode (i.e., the bottom electrode) of each of capacitors C5-C8 is connected to the drain electrode of transistors T5-T8, respectively. In some embodiments, the first electrode of capacitors C5-C8 includes the top electrode 304 of capacitor 300A or the via 312 of capacitor 300B (which functions as a top electrode), and the second electrode of capacitors C5-C8 includes the bottom electrode 308 of capacitor 300A or capacitor 300B.​​

[0087] The chip area of the memory cell 500 in some embodiments is reduced by about 15% compared to the typical chip area of a one-time programmable memory chip with a similar circuit having a prior art design due to the formation of the MIM capacitor in the metal layer on top of the source / drain electrodes of the transistors.

[0088] Figure 5B A top-down view of the memory device 500 is shown according to some embodiments. Figure 5A The layout of the capacitor C5 of the memory device 500 is shown. The capacitor C5 is formed from the bottom electrode 502, the insulator 506, and the top electrode 504. While this layout shows only a few layers, this is for illustrative purposes only, and one of ordinary skill in the art will recognize that additional layers can exist above, below, or between the layers shown.

[0089] The layout of the several layers of one memory cell of the memory device 500 can look like Figure 5B For example, for the capacitor C5, the metal layer including the bottom electrode 502 can extend in the y-direction, and the metal layer including the top electrode can extend in the y-direction. At the intersection of the two metal layers and between the two metal layers, the insulator 506 is formed such that the combination of the metal layers and the insulator 506 forms the capacitor C5 of the memory device 500. The bottom electrode 502 and the top electrode 504 are formed from metal. The bottom electrode 502 can be the metal layer M5 in the interconnect structure described above, but is not limited thereto. The top electrode 504 can be the metal layer M6 in the interconnect structure described above, but is not limited thereto. For example, the bottom electrode 502 can be the metal layer M6, and the top electrode can be the metal layer M7.

[0090] Figures 5C-5F A top-down view of the memory device 500 is shown according to some embodiments. Figure 5A of the memory device 500. These layers are illustrated as an example of how the memory device 500 can be layered to form the transistors T5-T8, and to form the interconnect structure on top of the transistors to form the capacitors C5-C8. One of ordinary skill in the art will recognize that the memory device 500 can be arranged in different ways to form Figure 5A the circuit shown. Figures 5C-5F Each of the layouts in Figure 5A four adjacent instances of the memory device 500; in other words, 16 memory cells are shown. While not shown for clarity, at Figures 5C-5F At different regions of the layers shown, a plurality of vias are formed through the layers or between the layers.

[0091] Figure 5CA gate layer PO and an active layer OD forming some portions of the transistors T5-T8 are shown in accordance with some embodiments. The gate layer PO is formed of an electrically conductive material such as polysilicon and serves as the gate of the transistors T5-T8. Other electrically conductive materials (e.g., metals) for the gate layer PO are within the scope of various embodiments. The active layer OD is formed of a semiconductor material and can include p-type or n-type dopants. The active layer OD includes the source and drain terminals of the transistors T5-T8 and the conduction channel when the transistors are turned on. The gate layer PO extends in the y-direction and the active layer OD extends in the x-direction.

[0092] Figure 5D Metal layers M0, M1, and M2 are shown in accordance with some embodiments. The metal layer M0 is the lowest metal layer of the interconnect structure formed above the transistors T5-T8. The metal layer M1 is formed above the metal layer M0 and the metal layer M2 is formed above the metal layer M1. In Figure 5D In some embodiments, the metal layers M0 and M2 substantially overlap each other, but these layers are not limited thereto. The metal layers M0 and M2 extend in the x-direction and M1 extends in the y-direction.

[0093] The metal layers M0 and M2 include bit lines BL[0], BL[1], BL[2], and BL[3] that carry respective bit line signals. For example, when the bit line driver 116 drives a high voltage on BL[0], the portions of the metal layers M0 and M2 that correspond to the bit line BL[0] will have the high voltage. The metal layer M1 includes word lines WL[0], WL[1], WL[2], and WL[3] that carry respective word line signals. For example, when the word line driver 112 drives a high voltage to WL[0], the corresponding portion of the metal layer M1 will have the high voltage. The metal layers M0-M2 can also have any voltage (e.g., low voltage, no voltage) driven by the respective bit line driver 116 or word line driver 112.

[0094] Figure 5E Metal layers M3 and M4 are shown in accordance with some embodiments. The metal layer M3 is formed above the metal layer M2 and the metal layer M4 is formed above the metal layer M3. At least some portions of the metal layer M3 and the metal layer M1 can be similarly patterned. Thus, the metal layer M1 and the metal layer M3 can overlap in some portions of the layout. Further, the metal layer M1 and M3 can be electrically coupled to each other in some portions of the layout. Further, the metal layer M4 can be similarly patterned to some portions of the metal layers M0 and M2, and thus the metal layers M0, M2, and M4 can overlap in some portions of the layout. Further, the metal layers M0, M2, and M4 can be electrically coupled to each other in some portions of the layout.

[0095] Metal layer M3 can include word lines WL[0], WL[l], WL[2], and WL[3] that carry respective word line signals. For example, when word line driver 112 attempts to drive a high voltage on WL[0], the portion of metal layer M3 that corresponds to word line WL[0] will have a high voltage. Metal layer M4 can include bit lines BL[0], BL[l], BL[2], and BL[3] that carry respective bit line signals. For example, when bit line driver 116 attempts to drive a high voltage on BL[0], the portion of metal layer M3 that corresponds to bit line BL[0] will have a high voltage. Metal layer M4 can also include dummy bit lines DMY. However, these dummy bit lines DMY are not electrically coupled to any of bit line driver 116, word line driver 112, or source line driver 114, and thus do not function. Dummy bit lines DMY can be formed at the edge of memory device 500.

[0096] Figure 5F Metal layers M5 and M6 are shown in accordance with some embodiments. Metal layer M5 is formed above metal layer M4, and metal layer M6 is formed above metal layer M5. As described above, a capacitor can be formed at the overlap of metal layer M5 and metal layer M6. When a dielectric insulator is formed between metal layers M5 and M6, a MIM capacitor is formed. Figure 5F The MIM capacitors shown can be capacitors C5-C8. In Figure 5F In particular, 16 MIM capacitors are shown, but embodiments are not limited to this and there can be more or less than 16 MIM capacitors.

[0097] Metal layer M6 can include source lines SL[0], SL[l], SL[2], and SL[3] that carry respective source line signals. For example, when source line driver 114 drives a high voltage on SL[0], the portion of metal layer M6 that corresponds to source line SL[0] will have a high voltage.

[0098] Figure 5G-Figure 5M Various layers of a memory cell 500A of memory device 500 are shown in accordance with some embodiments. Memory cell 500A includes Figure 5A transistor T5 and capacitor C5, but the present disclosure is not limited to this and the layout can apply to T6 and C6, or T7 and C7, or T8 and C8. Figure 5G-Figure 5MVarious layers of an example memory cell 500A including only one transistor T5 and one capacitor C5 are shown. These figures also show various metal layers, vias connecting the various metal layers, and their relationship to bit lines, word lines, and source lines. However, the positions of the vias relative to each other and the relative positions of the layers can not be vertically aligned. Thus, for clarity and simplicity, the layers shown in the figures are not meant to overlap each other to show a top-down view of the layout, and one of ordinary skill in the art will recognize that the layers can be rearranged to form a layout of a memory cell.

[0099] Referring to Figure 5G , according to some embodiments, the gate layer PO and the active layer OD of the memory cell 500A are shown. The memory cell 500A includes a transistor 508, which can include the transistor T5. A via 510A is formed over the gate layer PO to electrically connect the gate layer PO to an upper layer (e.g., the word line WL[0]). A via 512A is formed over the active layer OD to electrically connect the active layer OD to an upper layer (e.g., the bit line BL[0]). A via 514A is formed over the active layer OD to electrically connect a source terminal of the transistor T5 to an upper layer (e.g., the metal layer M5) that serves as a bottom electrode of the capacitor C5.

[0100] Referring to Figure 5H , according to some embodiments, the metal layers M0 and M1 of the memory cell 500A are shown. The metal layer M0 extends in the x-direction, and the metal layer M1 extends in the y-direction. The vias 510B, 512B, and 514B are formed between the metal layers M0 and M1. The via 510B can overlap the via 510A, the via 512B can overlap the via 512A, and the via 514B can overlap the via 514A.

[0101] The metal layer M0 can serve as the bit line BL[0]. In such embodiments, the bit line driver 116 can drive a bit line signal through the bit line BL[0] to the active layer OD through the via 512A. Thus, the source electrode of the transistor T5 can be electrically connected to the bit line BL[0], as shown in Figure 5A .

[0102] The metal layer M1 can serve as the word line WL[0]. The word line driver 112 can drive a word line signal through the word line WL[0] to the gate layer PO through the vias 510B and 510A. Thus, the gate of the transistor T5 can be electrically connected to the word line WL[0], as shown in Figure 5A .

[0103] Referring to Figure 5IAccording to some embodiments, metal layers Ml and M2 of memory cell 500A are shown. Metal layer Ml extends in the y-direction, and metal layer M2 extends in the x-direction. Vias 510C, 512C, and 514C are formed between metal layers Ml and M2. Via 510C can overlap with vias 510A-512B, via 512C can overlap with vias 512A-512B, and via 514C can overlap with vias 514A-512B. As described above, metal layer Ml can be used as word line [0].

[0104] Metal layer M2 can be used as bit line BL[0]. In such embodiments, bit line driver 116 can drive a bit line signal through bit line BL[0] to active layer OD through vias 512A-512C. Thus, the source electrode of transistor T5 can be electrically connected to bit line BL[0], as shown. Figure 5A

[0105] Referring to Figure 5J According to some embodiments, metal layers M2 and M3 of memory cell 500A are shown. Metal layer M2 extends in the x-direction, and metal layer M3 extends in the y-direction. Vias 510D, 512D, and 514D are formed between metal layers M2 and M3. Via 510D can overlap with vias 510A-510C, via 512D can overlap with vias 512A-512C, and via 514D can overlap with vias 514A-514C. As described above, metal layer M2 can be used as bit line [0].

[0106] Metal layer M3 can be used as word line WL[0]. In such embodiments, word line driver 112 can drive a word line signal through word line WL[0] to gate layer PO through vias 510A-510D. Thus, the gate of transistor T5 can be electrically connected to word line WL[0], as shown. Figure 5A

[0107] Referring to Figure 5K According to some embodiments, metal layers M3 and M4 of memory cell 500A are shown. Metal layer M3 extends in the y-direction, and metal layer M4 extends in the x-direction. Vias 512E and 514E are formed between metal layers M3 and M4. Via 512E can overlap with vias 512A-512D, and via 514E can overlap with vias 514A-514D. As described above, metal layer M3 can be used as word line WL[0].

[0108] Metal layer M4 can be used as bit line BL[0]. In such embodiments, bit line driver 116 can drive a bit line signal through bit line BL[0] to active layer OD through vias 512A-512D. Thus, the source electrode of transistor T5 can be electrically connected to bit line BL[0], as shown. Figure 5A ​​shown.

[0109] As discussed with respect to Figure 5E , dummy bit lines DMY can be formed. Referring to Figure 5K , metal layer M4 can include dummy bit lines DMY. However, dummy bit lines DMY are not used as actual bit lines and can be formed at, for example, the edge of a memory array.

[0110] Referring to Figure 5L , according to some embodiments, metal layers M4 and M5 of memory cell 500A are shown. Metal layer M4 extends in the x-direction, and metal layer M5 extends in the y-direction. Via 514F is formed between metal layers M4 and M5. Via 514F can overlap with vias 514A-514E. As described above, metal layer M4 can be used as bit line BL[0] or a dummy bit line DMY.

[0111] Metal layer M5 can be used as a bottom electrode of capacitor C5. Thus, the drain of transistor T5 can be electrically connected to the bottom electrode of capacitor C5, as Figure 5A shown.

[0112] Referring to Figure 5M , according to some embodiments, metal layers M5 and M6 of memory cell 500A are shown. Metal layer M5 extends in the y-direction, and metal layer M6 extends in the y-direction. As described above, metal layer M5 can be used as a bottom electrode of a capacitor.

[0113] Metal layer M6 can be used as a top electrode of capacitor C5. As described above, memory cell 500A includes MIM capacitor 516, which can include capacitor C5. Although not shown, a dielectric insulator layer is formed between metal layers M5 and M6 to form MIM capacitor 516, and a bottom electrode formed on metal layer M5 is electrically connected to the drain of transistor 508 through vias 514A-514E. Thus, MIM capacitor 516 is electrically connected to Figure 5G transistor 508. Further, although not shown in Figure 5M , a via can be formed between metal layers M5 and M6.

[0114] Metal layer M6 can be used as source line SL[0]. In such embodiments, source line driver 114 can drive a source line signal through source line SL[0] to metal layer M6 to the top electrode of the MIM capacitor. Thus, the top electrode of capacitor C5 can be electrically connected to source line SL[0], as Figure 5A shown.

[0115] Although Figure 5G-Figure 5MMetal layer M5 including the bottom electrode of capacitor 508 (and capacitor C5) and metal layer M6 including the top electrode of capacitor 508 (and capacitor C5) are shown and described, but embodiments are not limited thereto. As described with reference to Figure 3A and Figure 3B the top electrode can be formed separately above the dielectric insulator and below metal layer M6 (as shown in FIG. 3A), or when the top electrode is not formed separately, a via formed between the dielectric insulator and metal layer M6 can be used as the top electrode (as shown in FIG. 3B). Figure 3A Figure 3B

[0116] Figure 6A A circuit schematic of a memory device 600 according to some embodiments is shown. Memory device 600 includes four memory cells, which can be made up of four transistors and four capacitors, source line SL[0], word lines WL[0], WL[1], WL[2], and WL[3], and bit line BL[0]. It can be appreciated that Figure 6A Memory device 600 in FIG. 3A is just one example, and memory device 600 can have a variety of different schematics, including those discussed below. Reference is made to Figure 6G-Figure 6M Details of the layout layers of memory cell 600A are shown and described.

[0117] Memory device 600 includes four 1T1C memory cells electrically connected to one another. The cells include cell 1 (i.e., memory cell 600A) having transistor T9 and capacitor C9, cell 2 having transistor T10 and capacitor C10, cell 3 having transistor T11 and capacitor C11, and cell 4 having transistor T12 and capacitor C12. The source electrode of each of transistors T9-T12 is connected to the same bit line BL[0]. The gate electrode of each of transistors T9-T12 is connected to word lines WL[0]-WL[3], respectively. The first electrode (i.e., the top electrode) of each of capacitors C9-C12 is connected to source line SL[0]. The second electrode (i.e., the bottom electrode) of each of capacitors C9-C12 is connected to the drain electrode of transistors T9-T12, respectively. In some embodiments, the first electrode of capacitors C9-C12 includes top electrode 304 of capacitor 300A or via 312 of capacitor 300B (which functions as a top electrode), and the second electrode of capacitors C9-C12 includes bottom electrode 308 of capacitor 300A or capacitor 300B.

[0118] Compared to typical costs of manufacturing one-time programmable memory chips having similar circuitry designed by prior art, memory cell 600 in some embodiments has substantially lower cost due to the MIM capacitors formed in metal layers above the source / drain electrodes of the transistors. ​​

[0119] Figure 6B A layout of a capacitor C9-C12 of the memory device 600 is shown in accordance with some embodiments. Figure 6A The capacitor C9-C12 is formed by a bottom electrode 602, an insulator 606, and a top electrode 604. While this layout shows only a few layers, this is for illustrative purposes only, and one of ordinary skill in the art will recognize that additional layers can exist above, below, or between the layers shown.

[0120] The layout of several layers of one memory cell of the memory device 600 can look like the layout in Figure 6B For example, for each of the capacitors C9-C12, the metal layer that includes the bottom electrode 602 can extend in the y-direction, and the metal layer that includes the top electrode can extend in the x-direction. Furthermore, even though there are four separate capacitors C9-C12, only one metal layer is formed that forms the top electrode 604 of each of the capacitors C9-C12. Between the two metal layers and at the intersection of the two metal layers, the insulator 606 is formed such that the combination of the metal layers and the insulator 606 forms the capacitor C9-C12. The bottom electrode 602 and the top electrode 604 are formed of metal. The bottom electrode 602 can be the metal layer M5 in the interconnect structure described above, but is not limited thereto. The top electrode 604 can be the metal layer M6 in the interconnect structure described above, but is not limited thereto. For example, the bottom electrode 602 can be the metal layer M6, and the top electrode can be the metal layer M7.

[0121] Figures 6C-6F A top-down view of various layers of the memory device 600 is shown in accordance with some embodiments. Figure 6A These layers are illustrated as an example of how the memory device 600 can be layered to form the transistors T9-T12, and to form the interconnect structure above the transistors to form the capacitors C9-C12. One of ordinary skill in the art will recognize that the memory device 600 can be layered differently to form Figure 6A the circuit shown. Figures 6C-6F Each of the layouts in Figure 6A two adjacent instances of the memory device 600; in other words, 8 memory cells are shown. Although not shown for clarity, at different regions of the layers shown, a plurality of vias are formed through the layers or between the layers. Figures 6C-6F

[0122] Figure 6C ​A gate layer PO and an active layer OD forming some portions of the transistors T9-T12 are shown in accordance with some embodiments. The gate layer PO is formed of an electrically conductive material such as polysilicon and serves as the gate of the transistors T9-T12. Other electrically conductive materials (e.g., metals) for the gate layer PO are within the scope of various embodiments. The active layer OD is formed of a semiconductor material and can include p-type or n-type dopants. The active layer OD includes the source and drain terminals and the conduction channel of the transistors T9-T12 when the transistors are on. The gate layer PO extends in the y-direction and the active layer OD extends in the x-direction.

[0123] Figure 6D Metal layers M0, M1, and M2 are shown in accordance with some embodiments. The metal layer M0 is the lowest metal layer of the interconnect structure formed above the transistors T9-T12. The metal layer M1 is formed above the metal layer M0 and the metal layer M2 is formed above the metal layer M1. In Figure 6D , the metal layers M0 and M2 substantially overlap each other, but these layers are not limited thereto. The metal layers M0 and M2 extend in the x-direction and M1 extends in the y-direction.

[0124] The metal layers M0 and M2 include bit lines BL[0] and BL[1] that carry respective bit line signals. For example, when the bit line driver 116 drives a high voltage on BL[0], the portions of the metal layers M0 and M2 that correspond to the bit line BL[0] will have the high voltage. The metal layer M1 includes word lines WL[0], WL[1], WL[2], and WL[3] that carry respective word line signals. For example, when the word line driver 112 drives a high voltage to WL[0], the corresponding portion of the metal layer M1 will have the high voltage. The metal layers M0-M2 can also have any voltage (e.g., low voltage, no voltage) driven by the respective bit line driver 116 or word line driver 112.

[0125] Figure 6E Metal layers M3 and M4 are shown in accordance with some embodiments. The metal layer M3 is formed above the metal layer M2 and the metal layer M4 is formed above the metal layer M3. At least some portions of the metal layer M3 and the metal layer M1 can be similarly patterned. Thus, the metal layer M1 and the metal layer M3 can overlap in some portions of the layout. Further, the metal layer M1 and M3 can be electrically coupled to each other in some portions of the layout. Further, the metal layer M4 can be similarly patterned to some portions of the metal layers M0 and M2, thus the metal layers M0, M2, and M4 can overlap in some portions of the layout. Further, the metal layers M0, M2, and M4 can be electrically coupled to each other in some portions of the layout.

[0126] Metal layer M3 can include word lines WL[0], WL[1], WL[2], and WL[3] that carry respective word line signals. For example, when word line driver 112 attempts to drive a high voltage on WL[0], the portion of metal layer M3 that corresponds to word line WL[0] will have a high voltage. Metal layer M4 can include bit lines BL[0] and BL[1] that carry respective bit line signals. For example, when bit line driver 116 attempts to drive a high voltage on BL[0], the portion of metal layer M3 that corresponds to bit line BL[0] will have a high voltage. Metal layer M4 can also include dummy bit lines DMY. However, these dummy bit lines DMY are not electrically coupled to any of bit line driver 116, word line driver 112, or source line driver 114, and thus do not function. The dummy bit lines DMY can be formed at the edge of memory device 600.

[0127] Figure 6F Metal layers M5 and M6 are shown in accordance with some embodiments. Metal layer M5 is formed above metal layer M4, and metal layer M6 is formed above metal layer M5. As described above, a capacitor can be formed at the overlap of metal layer M5 and metal layer M6. When a dielectric insulator is formed between metal layers M5 and M6, a MIM capacitor is formed. Figure 6F The MIM capacitors shown can be capacitors C9-C12. In Figure 6F Sixteen MIM capacitors are shown in the middle, but embodiments are not limited to this and there can be more or less than sixteen MIM capacitors.

[0128] Metal layer M6 can include source lines SL[0] and SL[1] that carry respective source line signals. For example, when source line driver 114 drives a high voltage on SL[0], the portion of metal layer M6 that corresponds to source line SL[0] will have a high voltage.

[0129] Figure 6G-Figure 6M Various layers of a memory cell 600A of memory device 600 are shown in accordance with some embodiments. Memory cell 600A includes Figure 6A transistor T9 and capacitor C9, but the present disclosure is not limited to this and the layout can be applied to T10 and C10, or T11 and C11, or T12 and C12. Figure 6G-Figure 6M Various layers of an example memory cell 600A that includes only one transistor T9 and one capacitor C9 are shown. These figures also show various metal layers, vias that connect the various metal layers, and their relationship to bit lines, word lines, and source lines. However, the positions of the vias relative to each other and the relative positions of the layers can not be vertically aligned. Thus, for the sake of clarity and simplicity, the layers shown in the figures are not meant to be on top of each other to show a top-down view of the layout, and one of ordinary skill in the art will recognize that these layers can be rearranged to form a layout of a memory cell.

[0130] Referring to Figure 6G , according to some embodiments, the gate layer PO and the active layer OD of the storage unit 600A are shown. The storage unit 600A includes a transistor 608, which can include the transistor T9. A via 610A is formed over the gate layer PO to electrically connect the gate layer PO to an upper layer (e.g., the word line WL[0]). A via 612A is formed over the active layer OD to electrically connect the active layer OD to an upper layer (e.g., the bit line BL[0]). A via 614A is formed over the active layer OD to electrically connect a source terminal of the transistor T9 to an upper layer (e.g., the metal layer M5) that is a bottom electrode of the capacitor C9.

[0131] Referring to Figure 6H , according to some embodiments, the metal layers M0 and M1 of the storage unit 600A are shown. The metal layer M0 extends in the x-direction, and the metal layer M1 extends in the y-direction. The vias 610B, 612B, and 614B are formed between the metal layers M0 and M1. The via 610B can overlap the via 610A, the via 612B can overlap the via 612A, and the via 614B can overlap the via 614A.

[0132] The metal layer M0 can be used as the bit line BL[0]. In such embodiments, the bit line driver 116 can drive a bit line signal through the bit line BL[0] to the active layer OD through the via 612A. Thus, the source electrode of the transistor T9 can be electrically connected to the bit line BL[0], as shown in Figure 6A .

[0133] The metal layer M1 can be used as the word line WL[0]. The word line driver 112 can drive a word line signal through the word line WL[0] to the gate layer PO through the vias 610B and 610A. Thus, the gate of the transistor T9 can be electrically connected to the word line WL[0], as shown in Figure 6A .

[0134] Referring to Figure 6I , according to some embodiments, the metal layers M1 and M2 of the storage unit 600A are shown. The metal layer M1 extends in the y-direction, and the metal layer M2 extends in the x-direction. The vias 610C, 612C, and 614C are formed between the metal layers M1 and M2. The via 610C can overlap the vias 610A-612B, the via 612C can overlap the vias 612A-612B, and the via 614C can overlap the vias 614A-612B. As noted above, the metal layer M1 can be used as the word line WL[0].

[0135] Metal layer M2 can be used as bit line BL[0]. In such an embodiment, bit line driver 116 can drive the bit line signal through bit line BL[0] to active layer OD via vias 612A-612C. Therefore, the source electrode of transistor T9 can be electrically connected to bit line BL[0], as... Figure 6A As shown.

[0136] refer to Figure 6J According to some embodiments, metal layers M2 and M3 of memory cell 600A are shown. Metal layer M2 extends in the x-direction and metal layer M3 extends in the y-direction. Vias 610D, 612D and 614D are formed between metal layers M2 and M3. Via 610D may overlap with vias 610A-610C, via 612D may overlap with vias 612A-612C, and via 614D may overlap with vias 614A-614C. As described above, metal layer M2 can be used as a bit line [0].

[0137] Metal layer M3 can be used as word line WL[0]. In such an embodiment, word line driver 112 can drive the word line signal through word line WL[0] to gate layer PO through vias 610A-610D. Therefore, the gate of transistor T9 can be electrically connected to word line WL[0], as... Figure 6A As shown.

[0138] refer to Figure 6K According to some embodiments, metal layers M3 and M4 of memory cell 600A are shown. Metal layer M3 extends in the y-direction and metal layer M4 extends in the x-direction. Vias 612E and 614E are formed between metal layers M3 and M4. Via 612E may overlap with vias 612A-612D, and via 614E may overlap with vias 614A-614D. As described above, metal layer M3 can be used as word line WL[0].

[0139] Metal layer M4 can be used as bit line BL[0]. In such an embodiment, bit line driver 116 can drive the bit line signal through bit line BL[0] to active layer OD via vias 612A-612D. Therefore, the source electrode of transistor T9 can be electrically connected to bit line BL[0], as... Figure 6A As shown.

[0140] Such as about Figure 6E The discussed scenario can form a dummy bitline DMY. (See reference) Figure 6K The metal layer M4 may include a dummy bit line DMY. However, the dummy bit line DMY is not used as an actual bit line and may be formed, for example, at the edge of a memory array.

[0141] refer to Figure 6LAccording to some embodiments, metal layers M4 and M5 of memory cell 600A are shown. Metal layer M4 extends in the x-direction, and metal layer M5 extends in the y-direction. Via 614F is formed between metal layers M4 and M5. Via 614F can overlap with vias 614A-614E. As described above, metal layer M4 can function as bit line BL[0] or dummy bit line DMY.

[0142] Metal layer M5 can function as a bottom electrode of capacitor C9. Thus, the drain of transistor T9 can be electrically connected to the bottom electrode of capacitor C9, as shown in Figure 6A .

[0143] Referring Figure 6M to FIG. 6B, according to some embodiments, metal layers M5 and M6 of memory cell 600A are shown. Metal layer M5 extends in the y-direction, and metal layer M6 extends in the x-direction. As described above, metal layer M5 can function as a bottom electrode of a capacitor.

[0144] Metal layer M6 can function as a top electrode of capacitor C9. As described above, memory cell 600A includes MIM capacitor 616, which can include capacitor C9. Although not shown, a dielectric insulator layer is formed between metal layers M5 and M6 to form MIM capacitor 616, and a bottom electrode formed on metal layer M5 is electrically connected to the drain of transistor 608 through vias 614A-614E. Thus, MIM capacitor 616 is electrically connected to transistor 608 of Figure 6G . Furthermore, although not shown in Figure 6M , a via can be formed between metal layers M5 and M6.

[0145] Metal layer M6 can function as source line SL[0]. In such embodiments, source line driver 114 can drive a source line signal through source line SL[0] to metal layer M6 to the top electrode of the MIM capacitor. Thus, the top electrode of capacitor C9 can be electrically connected to source line SL[0], as shown in Figure 6A .

[0146] Although Figure 6G-Figure 6M metal layer M5 including a bottom electrode of capacitor 608 (and capacitor C9) and metal layer M6 including a top electrode of capacitor 608 (and capacitor C9) are shown and described, embodiments are not limited thereto. As described with reference to Figure 3A and Figure 3B , the top electrode can be formed separately above the dielectric insulator and below metal layer M6 (as shown in Figure 3A ), or when the top electrode is not formed separately, a via formed between the dielectric insulator and metal layer M6 can function as the top electrode (as shown in Figure 3B .

[0147] Figure 7A A circuit schematic of a memory device 700 is shown in accordance with some embodiments. The memory device 700 includes eight memory cells, which can be comprised of eight transistors and eight capacitors, source lines SL[0] and SL[1], word lines WL[0], WL[1], WL[2], and WL[3], and a bit line BL[0]. It can be appreciated that, Figure 7A The memory device 700 in FIG. 1 is just one example, and the memory device 700 can have a variety of different schematics, including those discussed below. Reference is made to Figures 7G-7M Details of the layout layers of the memory cell 700A are shown and described.

[0148] The memory device 700 includes four 1T1C memory cells electrically connected to one another. These cells include cell 1 (i.e., memory cell 700A) having transistor T13 and capacitor C13, cell 2 having transistor T14 and capacitor C14, cell 3 having transistor T15 and capacitor C15, cell 4 having transistor T16 and capacitor C16, cell 5 having transistor T17 and capacitor C17, cell 6 having transistor T18 and capacitor C18, cell 7 having transistor T19 and capacitor C19, and cell 8 having transistor T20 and capacitor C20. The source electrode of each of transistors T13-T20 is connected to the same bit line BL[0]. The gate electrode of each of transistors T13 and T17 is connected to word line WL[0], the gate electrode of each of transistors T14 and T18 is connected to word line WL[3], the gate electrode of each of transistors T15 and T19 is connected to word line WL[1], and the gate electrode of each of transistors T16 and T20 is connected to word line WL[2]. The first electrode (i.e., top electrode) of each of capacitors C13-C16 is connected to source line SL[0], and the first electrode (i.e., top electrode) of each of capacitors C17-C20 is connected to source line SL[1]. The second electrode (i.e., bottom electrode) of each of capacitors C13-C20 is connected to the drain electrode of transistors T13-T20, respectively. In some embodiments, the first electrode of capacitors C13-C20 includes the top electrode 304 of capacitor 300A or the via 312 of capacitor 300B (which functions as a top electrode), and the second electrode of capacitors C13-C20 includes the bottom electrode 308 of capacitor 300A or capacitor 300B.

[0149] The chip area of the memory cell 700 in some embodiments is reduced by approximately 43.8% compared to the typical chip area of a one-time programmable memory chip having a similar circuit of prior art designs due to the formation of the MIM capacitor in the metal layer above the source / drain electrodes of the transistors.

[0150] Figure 7B A layout of the capacitors C13-C20 of the memory device 700 is shown in accordance with some embodiments. Figure 7A The layout of the capacitors C13-C20 of the memory device 700 is shown. Each of the capacitors C13-C20 is formed by a bottom electrode 702, an insulator 706, and a top electrode 704. While this layout shows only a few layers, this is for illustrative purposes only, and one of ordinary skill in the art will recognize that additional layers can exist above, below, or between the layers shown.

[0151] The layout of a few layers of one memory cell of the memory device 700 can look like Figure 7B For example, for the capacitor C13, the metal layer that includes the bottom electrode 702 can extend in the y-direction, and the metal layer that includes the top electrode can extend in the x-direction. At the intersection of the two metal layers and between the two metal layers, the insulator 706 is formed, such that the combination of the metal layers and the insulator 706 forms the capacitors C13-C20 of the memory device 700. The bottom electrode 702 and the top electrode 704 are formed of metal. The bottom electrode 702 can be the metal layer M5 in the interconnect structure described above, but is not limited thereto. The top electrode 704 can be the metal layer M6 in the interconnect structure described above, but is not limited thereto. For example, the bottom electrode 702 can be the metal layer M6, and the top electrode can be the metal layer M7.

[0152] Figures 7C-7F A top-down view of the various layers of the memory device 700 is shown in accordance with some embodiments. Figure 7A These layers are illustrated as an example of how the memory device 700 can be layered to form the transistors T13-T20, and to form the interconnect structure above the transistors to form the capacitors C13-C20. One of ordinary skill in the art will recognize that the memory device 700 can be layered differently to form Figure 7A The circuit shown in Figures 7C-7F Each of the layouts in Figure 7A two adjacent instances of the memory device 700; in other words, 16 memory cells are shown. Although not shown for clarity, in Figures 7C-7F At different regions of the layers shown, vias are formed through the layers or between the layers

[0153] Figure 7CA gate layer PO and an active layer OD that form some portions of 16 transistors are shown in accordance with some embodiments. The gate layer PO is formed of an electrically conductive material such as polysilicon and serves as a gate of the transistors. Other electrically conductive materials (e.g., metals) for the gate layer PO are within the scope of various embodiments. The active layer OD is formed of a semiconductor material and can include p-type or n-type dopants. The active layer OD includes source and drain terminals and a conductive channel of the transistors when the transistors are turned on. The gate layer PO extends in the y-direction and the active layer OD extends in the x-direction.

[0154] Figure 7D Metal layers M0, M1, and M2 are shown in accordance with some embodiments. The metal layer M0 is the lowest metal layer of an interconnect structure formed above the transistors. The metal layer M1 is formed above the metal layer M0 and the metal layer M2 is formed above the metal layer M1. In Figure 7D the metal layers M0 and M2 substantially overlap each other, but these layers are not limited thereto. The metal layers M0 and M2 extend in the x-direction and M1 extends in the y-direction.

[0155] The metal layers M0 and M2 include bit lines BL[0] and BL[1] that carry respective bit line signals. For example, when the bit line driver 116 drives a high voltage on BL[0], the portions of the metal layers M0 and M2 that correspond to the bit line BL[0] will have the high voltage. The metal layer M1 includes word lines WL[0], WL[1], WL[2], WL[3], WL[4], WL[5], WL[6], and WL[7] that carry respective word line signals. For example, when the word line driver 112 drives a high voltage to WL[0], the corresponding portion of the metal layer M1 will have the high voltage. The metal layers M0-M2 can also have any voltage (e.g., a low voltage, no voltage) driven by the respective bit line driver 116 or word line driver 112.

[0156] Figure 7E Metal layers M3 and M4 are shown in accordance with some embodiments. The metal layer M3 is formed above the metal layer M2 and the metal layer M4 is formed above the metal layer M3. At least some portions of the metal layer M3 and the metal layer M1 can be similarly patterned. Thus, the metal layer M1 and the metal layer M3 can overlap in some portions of the layout. Further, the metal layer M1 and M3 can be electrically coupled to each other in some portions of the layout. Further, the metal layer M4 can be similarly patterned to some portions of the metal layers M0 and M2, and thus the metal layers M0, M2, and M4 can overlap in some portions of the layout. Further, the metal layers M0, M2, and M4 can be electrically coupled to each other in some portions of the layout.

[0157] Metal layer M3 can include word lines WL[0]-WL[7] that carry respective word line signals. For example, when word line driver 112 attempts to drive a high voltage on WL[0], the portion of metal layer M3 that corresponds to word line WL[0] will have a high voltage. Metal layer M4 can include bit lines BL[0]-BL[1] that carry respective bit line signals. For example, when bit line driver 116 attempts to drive a high voltage on BL[0], the portion of metal layer M3 that corresponds to bit line BL[0] will have a high voltage. Metal layer M4 can also include dummy bit lines DMY. However, these dummy bit lines DMY are not electrically coupled to any of bit line driver 116, word line driver 112, or source line driver 114, and thus do not function. The dummy bit lines DMY can be formed at the edge of memory device 700.

[0158] Figure 7F Metal layers M5 and M6 are shown in accordance with some embodiments. Metal layer M5 is formed above metal layer M4, and metal layer M6 is formed above metal layer M5. As described above, a capacitor can be formed at the overlap of metal layer M5 and metal layer M6. When a dielectric insulator is formed between metal layers M5 and M6, a MIM capacitor is formed. Figure 7F The MIM capacitors shown can be capacitors C13-C20. In Figure 7F In the example shown, 16 MIM capacitors are shown, but embodiments are not limited to this and there can be more or less than 16 MIM capacitors.

[0159] Metal layer M6 can include source lines SL[0], SL[1], SL[2], and SL[3] that carry respective source line signals. For example, when source line driver 114 drives a high voltage on SL[0], the portion of metal layer M6 that corresponds to source line SL[0] will have a high voltage.

[0160] Figures 7G-7M Various layers of a memory cell 700A of memory device 700 are shown in accordance with some embodiments. Memory cell 700A includes Figure 7A transistor T13 and capacitor C13, but the present disclosure is not limited to this and the layout can be applied to Figure 7A any 1T1C combination. Figures 7G-7M Various layers of an example memory cell 700A that includes only one transistor T13 and one capacitor C13 are shown. These figures also show various metal layers, vias that connect the various metal layers, and their relationship to bit lines, word lines, and source lines. However, the positions of the vias relative to each other and the relative positions of the layers can not be vertically aligned. Thus, for the sake of clarity and simplicity, the layers shown in the figures are not meant to overlap each other to show a top-down view of the layout, and one of ordinary skill in the art will recognize that these layers can be rearranged to form a layout of a memory cell.

[0161] Referring to Figure 7G , according to some embodiments, the gate layer PO and the active layer OD of the storage unit 700A are shown. The storage unit 700A includes a transistor 708, which can include the transistor T13. A via 710A is formed over the gate layer PO to electrically connect the gate layer PO to an upper layer (e.g., word line WL[0]). A via 712A is formed over the active layer OD to electrically connect the active layer OD to an upper layer (e.g., bit line, BL[0]). A via 714A is formed over the active layer OD to electrically connect a source terminal of the transistor T13 to an upper layer (e.g., metal layer M5) that serves as a bottom electrode of a capacitor C13.

[0162] Referring to Figure 7H , according to some embodiments, the metal layers M0 and M1 of the storage unit 700A are shown. The metal layer M0 extends in the x-direction, and the metal layer M1 extends in the y-direction. Vias 710B, 712B, and 714B are formed between the metal layers M0 and M1. The via 710B can overlap the via 710A, the via 712B can overlap the via 712A, and the via 714B can overlap the via 714A.

[0163] The metal layer M0 can serve as the bit line BL[0]. In such embodiments, the bit line driver 116 can drive a bit line signal through the bit line BL[0] to the active layer OD through the via 712A. Thus, the source electrode of the transistor T13 can be electrically connected to the bit line BL[0], as shown in Figure 7A .

[0164] The metal layer M1 can serve as the word line WL[0]. The word line driver 112 can drive a word line signal through the word line WL[0] to the gate layer PO through the vias 710B and 710A. Thus, the gate of the transistor T13 can be electrically connected to the word line WL[0], as shown in Figure 7A .

[0165] Referring to Figure 7I , according to some embodiments, the metal layers M1 and M2 of the storage unit 700A are shown. The metal layer M1 extends in the y-direction, and the metal layer M2 extends in the x-direction. Vias 710C, 712C, and 714C are formed between the metal layers M1 and M2. The via 710C can overlap the vias 710A-712B, the via 712C can overlap the vias 712A-712B, and the via 714C can overlap the vias 714A-712B. As noted above, the metal layer M1 can serve as the word line WL[0].

[0166] Metal layer M2 can be used as bit line BL[0]. In such an embodiment, bit line driver 116 can drive the bit line signal through bit line BL[0] to active layer OD through vias 712A-712C. Therefore, the source electrode of transistor T13 can be electrically connected to bit line BL[0], as... Figure 7A As shown.

[0167] refer to Figure 7J According to some embodiments, metal layers M2 and M3 of memory cell 700A are shown. Metal layer M2 extends in the x-direction and metal layer M3 extends in the y-direction. Vias 710D, 712D and 714D are formed between metal layers M2 and M3. Via 710D may overlap with vias 710A-710C, via 712D may overlap with vias 712A-712C, and via 714D may overlap with vias 714A-714C. As described above, metal layer M2 can be used as a bit line [0].

[0168] Metal layer M3 can be used as word line WL[0]. In such an embodiment, word line driver 112 can drive the word line signal through word line WL[0] to gate layer PO through vias 710A-710D. Therefore, the gate of transistor T13 can be electrically connected to word line WL[0], as... Figure 7A As shown.

[0169] refer to Figure 7K According to some embodiments, metal layers M3 and M4 of memory cell 700A are shown. Metal layer M3 extends in the y-direction and metal layer M4 extends in the x-direction. Vias 712E and 714E are formed between metal layers M3 and M4. Via 712E may overlap with vias 712A-712D, and via 714E may overlap with vias 714A-714D. As described above, metal layer M3 can be used as word line WL[0].

[0170] Metal layer M4 can be used as bit line BL[0]. In such an embodiment, bit line driver 116 can drive the bit line signal through bit line BL[0] to active layer OD via vias 712A-712D. Therefore, the source electrode of transistor T13 can be electrically connected to bit line BL[0], as... Figure 7A As shown.

[0171] Such as about Figure 7E The discussed scenario can form a dummy bitline DMY. (See reference) Figure 7K The metal layer M4 may include a dummy bit line DMY. However, the dummy bit line DMY is not used as an actual bit line and may be formed, for example, at the edge of a memory array.

[0172] refer to Figure 7LAccording to some embodiments, metal layers M4 and M5 of memory cell 700A are shown. Metal layer M4 extends in the x-direction, and metal layer M5 extends in the y-direction. Via 714F is formed between metal layers M4 and M5. Via 714F can overlap with vias 714A-714E. As described above, metal layer M4 can function as bit line BL[0] or dummy bit line DMY.

[0173] Metal layer M5 can function as a bottom electrode of capacitor C13. Thus, the drain of transistor T13 can be electrically connected to the bottom electrode of capacitor C13, as shown in Figure 7A .

[0174] Referring to Figure 7M , according to some embodiments, metal layers M5 and M6 of memory cell 700A are shown. Metal layer M5 extends in the y-direction, and metal layer M6 extends in the y-direction. As described above, metal layer M5 can function as a bottom electrode of a capacitor.

[0175] Metal layer M6 can function as a top electrode of capacitor C13. As described above, memory cell 700A includes MIM capacitor 716, which can include capacitor C13. Although not shown, a dielectric insulator layer is formed between metal layers M5 and M6 to form MIM capacitor 716, and a bottom electrode formed on metal layer M5 is electrically connected to the drain of transistor 708 through vias 714A-714E. Thus, MIM capacitor 716 is electrically connected to transistor 708 of Figure 7G . Furthermore, although not shown in Figure 7M , a via can be formed between metal layers M5 and M6.

[0176] Metal layer M6 can function as source line SL[0]. In such embodiments, source line driver 114 can drive a source line signal through source line SL[0] to metal layer M6 to the top electrode of the MIM capacitor. Thus, the top electrode of capacitor C13 can be electrically connected to source line SL[0], as shown in Figure 7A .

[0177] Although Figures 7G-7M metal layer M5 including a bottom electrode of capacitor 708 (and capacitor C13) and metal layer M6 including a top electrode of capacitor 708 (and capacitor C13) are shown and described, embodiments are not limited thereto. As described with reference to Figure 3A and Figure 3B , the top electrode can be formed separately above the dielectric insulator and below metal layer M6 (as shown in Figure 3A ), or when the top electrode is not formed separately, a via formed between the dielectric insulator and metal layer M6 can function as the top electrode (as shown in Figure 3B ).

[0178] Figure 8 A flowchart of an example method for fabricating a MIM capacitor is shown in accordance with some embodiments. It is noted that process 800 is just an example and is not intended to limit the present disclosure. Thus, it is to be understood that additional steps / operations can be provided before, during, and after process 800, and some of the operations described can be modified or eliminated, depending on the Figure 8 embodiments. The operations of process 800 can be associated with example MIM capacitor 300A shown in cross-sectional views of various fabrication stages, respectively, as shown in FIGS. 3A-3E, which will be discussed in more detail below. Figures 9A-9J

[0179] Briefly stated, process 800 begins with an operation 802 of forming a transistor on a substrate. Process 800 can then proceed to an operation 804 of forming a first metal layer. Process 800 can then proceed to an operation 806 of forming an oxide over the first metal layer. Process 800 can then proceed to an operation 808 of forming a porous low-k material over the oxide. Process 800 can then proceed to an operation 810 of etching a portion of the porous low-k material. Process 800 can then proceed to an operation 812 of etching a portion of the oxide. Process 800 can then proceed to an operation 814 of forming a first dielectric film. Process 800 can then proceed to an operation 816 of forming a second dielectric film. Process 800 can then proceed to an operation 818 of forming a top electrode. Process 800 can then proceed to an operation 820 of polishing the top electrode. Process 800 can then proceed to an operation 822 of forming an interlayer dielectric. Process 800 can then proceed to an operation 824 of defining a via in the interlayer dielectric. Process 800 can then proceed to an operation 826 of forming a metal layer over an exposed portion of the top electrode.

[0180] Operation 802 includes forming a transistor over a substrate (not shown). Although the transistor is not shown in the figures for simplicity, it is contemplated that the transistor can be any suitable type of transistor including, but not limited to: a metal-oxide-semiconductor field-effect transistor (MOSFET), a complementary metal-oxide-semiconductor (CMOS) transistor, a P-channel metal-oxide-semiconductor (PMOS), an N-channel metal-oxide-semiconductor (NMOS), a bipolar junction transistor (BJT), a high-voltage transistor, a high-frequency transistor, a P-channel and / or N-channel field-effect transistor (PFET / NFET), a FinFET, a planar MOS transistor with raised source / drain, a nanosheet FET, a nanowire FET, etc. After the transistor is formed, a back-end-of-line (BEOL) process is performed to connect interconnect structures over the transistor.

[0181] Corresponding to operations 804, 806, and 808, Figure 9A ​is a resulting cross-sectional view of the MIM capacitor 300A at one of the various manufacturing stages including a first metal layer 902, an oxide 904, and a first interlayer dielectric (ILD) 906. The first metal layer 902 can be formed of at least one of W, TiN, TaN, Ru, Co, Al, Cu, or any conductive material. The oxide 904 can be formed of an insulating material including, but not limited to, silicon dioxide, silicate glass, carbon-doped silicon oxide, ZrO, TiO2, HfOx, high-k dielectrics, etc. The first ILD 906 can be formed of a porous low-k dielectric material, for example, silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method, for example, CVD, PECVD, or FCVD.

[0182] The first metal layer 902 can serve as a bottom electrode 308 of the MIM capacitor 300A. Thus, the first metal layer 902 can include the metal layer M5 described above, but is not limited thereto, and can include any metal layer M5 formed over a semiconductor device formed over a substrate.

[0183] Corresponding to operation 810, Figure 9B is a cross-sectional view of the MIM capacitor 300A at one of the various manufacturing stages including a portion of the ILD 906 that has been etched. This portion of the etched first ILD 906 must be defined using a mask. The etching can be performed by any suitable method, for example, reactive ion etching (RIE), neutral beam etching (NBE), plasma etching, etc., or a combination thereof.

[0184] Corresponding to operation 812, Figure 9C is a cross-sectional view of the MIM capacitor 300A at one of the various manufacturing stages including a portion of the oxide 904 that has been etched. The etching can be performed by any suitable method, for example, reactive ion etching (RIE), neutral beam etching (NBE), plasma etching, etc., or a combination thereof. After operation 812, the resulting structure will include an etched portion 908.

[0185] Corresponding to operation 814, Figure 9Dis a cross-sectional view of the MIM capacitor 300A including the first dielectric film 910 at one of the various stages of fabrication. The first dielectric film 910 can have a thickness of about 0.1 nanometers (nm) to about 50 nm, but is not limited thereto. Varying the thickness of the first dielectric film 910 can result in different breakdown voltages of the MIM capacitor 300A, such that a circuit designer can design a circuit including the MIM capacitor 300A to break down and program a memory cell including the MIM capacitor 300A at a desired voltage. When the MIM capacitor 300A is thicker, the breakdown voltage will be greater, and when the MIM capacitor 300A is thinner, the breakdown voltage will be less. The first dielectric film 910 can be formed of any suitable insulator material, such as SiO2, SiN, AI2O3, HfO, TaO, etc. The first dielectric film 910 can be formed by any suitable method, such as a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process (e.g., a metal organic CVD (MOCVD) process, a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD)), and / or other suitable epitaxial growth processes.

[0186] corresponding to operation 816, Figure 9E is a cross-sectional view of the MIM capacitor 300A including the second dielectric film 912 at one of the various stages of fabrication. Although Figure 9E forming the second dielectric film 912 having a similar thickness as the first dielectric film 910 is shown, the thickness of the second dielectric film 912 is not limited thereto. The second dielectric film 912 can have a thickness of 0 nm to about 50 nm. In other words, the second dielectric film 912 can not be formed to reduce the thickness of the dielectric layer and / or fabrication costs.

[0187] The second dielectric film 912 can be formed of any suitable insulator material, such as SiO2, SiN, AI2O3, HfO, TaO, etc. The second dielectric film 912 can be formed by any suitable method, such as a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process (e.g., a metal organic CVD (MOCVD) process, a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD)), and / or other suitable epitaxial growth processes.

[0188] The first dielectric film 910, the second dielectric film 912, or a combination of both, can be used as the insulator 306 of the MIM capacitor 300A. As Figure 9E shown, a via 903 is formed.

[0189] corresponding to operation 818, Figure 9Fis a cross-sectional view of the MIM capacitor 300A including the second metal layer 914 at one of the various stages of fabrication. The second metal layer 914 can be formed of at least one of W, TiN, TaN, Ru, Co, Al, Cu, or any conductive material.

[0190] corresponding to operation 820, Figure 9G is a cross-sectional view of the MIM capacitor 300A including the second metal layer 914 that has been polished at one of the various stages of fabrication. The thickness of the second metal layer 914 can be from 0 nm to about 60 nm. The thickness can be 0 nm because the second metal layer 914 can be omitted (see Figure 3B and Figure 10 ).

[0191] As noted above, the second metal layer 914 can serve as the top electrode 304 of the MIM capacitor 300A.

[0192] corresponding to operation 822, Figure 9H is a cross-sectional view of the MIM capacitor 300A including a second interlayer dielectric (ILD) 916 at one of the various stages of fabrication. The second ILD 916 can be formed of a porous low-k dielectric material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc., and can be deposited by any suitable method, such as CVD, PECVD, or FCVD.

[0193] corresponding to operation 824, Figure 9I is a cross-sectional view of the MIM capacitor 300A including a portion of the second ILD 916 that has been etched at one of the various stages of fabrication. The portion of the second ILD 916 that is etched must be defined using a mask. The etching can be performed by any suitable method, such as reactive ion etching (RIE), neutral beam etching (NBE), plasma etching, etc., or a combination thereof. According to some embodiments, both the first dielectric film 910 and the second dielectric film 912 can have a stepped profile.

[0194] For example, each of the first dielectric film 910 and the second dielectric film 912 includes a vertical portion that is connected to two lateral portions that extend away from each other at both ends, respectively. As Figure 9IAs shown, the first dielectric film 910 includes a vertical portion 910A and two lateral portions 910B and 910C; and the second dielectric film 912 includes a vertical portion 912A and two lateral portions 912B and 912C. At least one of the lateral portions 910B or 910C, together with the vertical portion 910A, can form a stepped profile. Similarly, at least one of the lateral portions 912B or 912C, together with the vertical portion 912A, can form a stepped profile. In an example where the first dielectric film 910 is used as the sole insulator 306 of the MIM capacitor 300A, the lateral portion 910B can be in contact with the first metal layer 902 used as the bottom electrode 308 of the MIM capacitor 300A. In another example where both the first dielectric film 910 and the second dielectric film 912 are used as the insulator 306 of the MIM capacitor 300A, the lateral portion 912B can be coupled to the first metal layer 902 used as the bottom electrode 308 of the MIM capacitor 300A through the lateral portion 910B.

[0195] corresponding to operation 826, Figure 9J is a cross-sectional view of the MIM capacitor 300A including a third metal layer 918 at one of the respective manufacturing stages. The third metal layer 918 can be formed of at least one of W, TiN, TaN, Ru, Co, Al, Cu, or any conductive material. The third metal layer 918 can include the metal layer M6 described above, but is not limited thereto. Thus, the third metal layer 918 can be electrically coupled to the second metal layer 914.

[0196] Figure 10 is a cross-sectional view of the MIM capacitor 300B without a separately formed top electrode at one of the respective manufacturing stages. With reference to the process 800, operations 818-820 can be optionally skipped to form the MIM capacitor 300B. In other words, after operation 816 of forming the via 903, the process can proceed to step 822 to form the second ILD 916. The second ILD 916 is then etched to the bottom of the via 903 to expose the first dielectric film 910 and / or the second dielectric film 912, depending on whether one or both of the films 910 and 912 are used. The third metal layer 918 can then be formed thereon. Thus, the portion of the third metal layer formed in and on the via 903 Figure 3B of the via 312) can be used as the top electrode of the MIM capacitor 300B. Thus, the manufacturing of the MIM capacitor 300B can reduce cost and time.

[0197] In one aspect of the disclosure, a memory device is disclosed. The memory device includes a first transistor and a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time programmable (OTP) memory cell. The first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulating layer between the first bottom metal terminal and the first top metal terminal. The first insulating layer includes a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion. The first bottom metal terminal is directly below and in contact with the first portion of the first insulating layer.

[0198] In another aspect of the disclosure, a memory device is disclosed. The memory device includes a substrate and a memory array disposed over the substrate and including a plurality of one-time programmable (OTP) memory cells. The plurality of OTP memory cells are formed based on a plurality of first interconnect structures, a plurality of insulating layers, and a plurality of second interconnect structures, wherein each of the plurality of insulating layers includes a stepped profile.

[0199] In yet another aspect of the disclosure, a method of fabricating a memory device is disclosed. The method includes forming a transistor over a substrate, and forming a first interconnect structure over the transistor to be electrically coupled to the transistor, wherein the first interconnect structure is disposed in a first metallization level. The method further includes exposing a portion of the first interconnect structure, and forming a stepped insulating layer over the first interconnect structure, wherein a lateral portion of the stepped insulating layer contacts the exposed portion of the first interconnect structure. The method further includes forming a second interconnect structure over the lateral portion of the stepped insulating layer, thereby forming a capacitor based at least on the first interconnect structure, the lateral portion of the stepped insulating layer, and the second interconnect structure, wherein the transistor and the capacitor collectively function as a one-time programmable (OTP) memory cell.

[0200] The foregoing summarizes features of several embodiments to enable a person of ordinary skill in the art to better understand aspects of the present disclosure. Those of ordinary skill in the art should realize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to implement the methods introduced herein and / or to implement the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.

[0201] Example 1. A memory device, comprising:

[0202] a first transistor; and

[0203] a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time programmable (OTP) memory cell;

[0204] wherein the first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulating layer between the first bottom metal terminal and the first top metal terminal;

[0205] wherein the first insulating layer includes a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion; and

[0206] wherein the first bottom metal terminal is directly below and in contact with the first portion of the first insulating layer.

[0207] Example 2. The memory device of example 1, wherein the first insulating layer has a dielectric material selected from the group consisting of: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

[0208] Example 3. The memory device of example 1, further comprising:

[0209] a first interconnect structure disposed in a first metallization layer and coupled to a source / drain terminal of the first transistor, wherein the first interconnect structure extends along a first lateral direction;

[0210] a second interconnect structure disposed in a second metallization layer and coupled to a gate terminal of the first transistor, wherein the second interconnect structure extends along a second lateral direction; and

[0211] a third interconnect structure disposed in a third metallization layer and coupled to the first top metal terminal of the first capacitor, wherein the third interconnect structure extends along one of the first lateral direction or the second lateral direction.

[0212] Example 4. The memory device of example 3, further comprising:

[0213] a second transistor; and

[0214] a second capacitor electrically coupled to the second transistor, the second transistor and the second capacitor forming a second OTP memory cell;

[0215] wherein the second capacitor has a second bottom metal terminal, a second top metal terminal, and a second insulating layer between the second bottom metal terminal and the second top metal terminal;

[0216] The second insulating layer includes a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion; and

[0217] The second bottom metal terminal is located directly below and in contact with the first portion of the second insulating layer.

[0218] Example 5. The storage device according to Example 4, wherein each of the first bottom metal terminal and the second bottom metal terminal extends along the first lateral direction or the second lateral direction and is disposed in a fourth metallization layer, the fourth metallization layer being above the second metallization layer and below the third metallization layer.

[0219] Example 6. The storage device according to Example 5, wherein each of the first top metal terminal and the second top metal terminal includes a via structure that couples the fourth metallization layer to the third metallization layer.

[0220] Example 7. The storage device according to Example 5, wherein each of the first top metal terminal and the second top metal terminal includes a metal structure disposed below a via structure that couples the fourth metallization layer to the third metallization layer.

[0221] Example 8. The storage device according to Example 4, wherein the third interconnect structure is further coupled to the second top metal terminal of the second capacitor.

[0222] Example 9. The storage device according to Example 8, wherein the first insulating layer and the second insulating layer are substantially separated from each other.

[0223] Example 10. The storage device according to Example 8, wherein the first insulating layer and the second insulating layer are formed as an integral structure.

[0224] Example 11. A storage device comprising:

[0225] Substrate;

[0226] A memory array disposed on the substrate, the memory array comprising a plurality of one-time programmable (OTP) memory cells;

[0227] The plurality of OTP memory cells are formed based on a plurality of first interconnect structures, a plurality of insulating layers and a plurality of second interconnect structures, wherein each of the plurality of insulating layers includes a stepped profile.

[0228] Example 12. The memory device of Example 11, wherein the stepped profile includes at least one vertical portion and two lateral portions, and wherein the two ends of the at least one vertical portion are connected to the lateral portions, respectively, the at least one vertical portion configured to be broken down by a voltage applied through a respective one of the second interconnect structures.

[0229] Example 13. The memory device of Example 11, wherein

[0230] the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer;

[0231] the plurality of second interconnect structures extending along a second lateral direction perpendicular to the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and

[0232] the plurality of insulating layers are disposed between the first metallization layer and the second metallization layer.

[0233] Example 14. The memory device of Example 13, wherein each of the second interconnect structures is operatively shared by a subset of the memory cells arranged along the second lateral direction, each of the subset of memory cells including a respective one of the insulating layers and a respective one of the first interconnect structures.

[0234] Example 15. The memory device of Example 11, wherein

[0235] the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer;

[0236] the plurality of second interconnect structures also extending along the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and

[0237] the plurality of insulating layers are disposed between the first metallization layer and the second metallization layer.

[0238] Example 16. The memory device of Example 15, wherein each of the second interconnect structures is operatively shared by a subset of the memory cells arranged along the first lateral direction, each of the subset of memory cells including a respective one of the insulating layers and a respective one of the first interconnect structures.

[0239] Example 17. The memory device of Example 11, wherein

[0240] the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer;

[0241] The plurality of second interconnect structures extending along a second lateral direction perpendicular to the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and

[0242] The plurality of insulating layers are disposed between the first metallization layer and the second metallization layer.

[0243] Example 18. The memory device of example 17, wherein each of the second interconnect structures is operatively shared by a subset of the memory cells arranged along the second lateral direction, each of the subset of memory cells includes a respective one of the first interconnect structures, and the subset of memory cells shares one of the insulating layers.

[0244] Example 19. A method of fabricating a memory device, comprising:

[0245] forming a transistor over a substrate;

[0246] forming a first interconnect structure over the transistor to electrically couple to the transistor, wherein the first interconnect structure is disposed in a first metallization level;

[0247] exposing a portion of the first interconnect structure;

[0248] forming a stepped insulating layer over the first interconnect structure, wherein a lateral portion of the stepped insulating layer is in contact with the exposed portion of the first interconnect structure; and

[0249] forming a second interconnect structure over the lateral portion of the stepped insulating layer, thereby forming a capacitor based at least on the first interconnect structure, the lateral portion of the stepped insulating layer, and the second interconnect structure;

[0250] wherein the transistor and the capacitor collectively function as a one-time programmable (OTP) memory cell.

[0251] Example 20. The method of example 19, wherein the second interconnect structure includes a via structure coupling a second metallization layer to the first metallization layer, or includes a metal structure disposed below a via structure coupling a second metallization layer to the first metallization layer, and wherein the second metallization layer is disposed immediately above the first metallization layer.

Claims

1. A memory device, comprising: a first transistor; and a first capacitor electrically coupled to the first transistor, the first transistor and the first capacitor forming a first one-time programmable (OTP) memory cell; wherein the first capacitor has a first bottom metal terminal, a first top metal terminal, and a first insulating layer between the first bottom metal terminal and the first top metal terminal; wherein the first insulating layer includes a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion; and wherein the first bottom metal terminal is directly below and in contact with the first portion of the first insulating layer.

2. The memory device of claim 1, wherein, The first insulating layer has a dielectric material selected from the group consisting of: silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, and tantalum oxide.

3. The memory device of claim 1, further comprising: a first interconnect structure disposed in a first metallization layer and coupled to a source / drain terminal of the first transistor, wherein the first interconnect structure extends along a first lateral direction; a second interconnect structure disposed in a second metallization layer and coupled to a gate terminal of the first transistor, wherein the second interconnect structure extends along a second lateral direction; and a third interconnect structure disposed in a third metallization layer and coupled to the first top metal terminal of the first capacitor, wherein the third interconnect structure extends along one of the first lateral direction or the second lateral direction.

4. The memory device of claim 3, further comprising: a second transistor; and a second capacitor electrically coupled to the second transistor, the second transistor and the second capacitor forming a second OTP memory cell; wherein the second capacitor has a second bottom metal terminal, a second top metal terminal, and a second insulating layer between the second bottom metal terminal and the second top metal terminal; wherein the second insulating layer includes a first portion, a second portion separate from the first portion, and a third portion extending vertically between the first portion and the second portion; and wherein the second bottom metal terminal is directly below and in contact with the first portion of the second insulating layer.

5. The memory device of claim 4, wherein, Each of the first bottom metal terminal and the second bottom metal terminal extends along the first lateral direction or the second lateral direction and is disposed in a fourth metallization layer that is above the second metallization layer and below the third metallization layer.

6. The memory device of claim 5, wherein, Each of the first top metal terminal and the second top metal terminal includes a via structure that couples the fourth metallization layer to the third metallization layer.

7. The memory device of claim 5, wherein, Each of the first top metal terminal and the second top metal terminal includes a metal structure disposed below a via structure that couples the fourth metallization layer to the third metallization layer.

8. The memory device of claim 4, wherein, The third interconnect structure is also coupled to a second top metal terminal of the second capacitor.

9. The memory device of claim 8, wherein, The first and second insulating layers are physically separated from each other.

10. The memory device of claim 8, wherein, The first and second insulating layers are formed as an integral structure.

11. A memory device, comprising: a substrate; a memory array disposed over the substrate, the memory array comprising a plurality of one-time programmable (OTP) memory cells; wherein the plurality of OTP memory cells are formed based on a plurality of first interconnect structures, a plurality of insulating layers, and a plurality of second interconnect structures, and wherein each of the plurality of insulating layers comprises a stepped profile; wherein the stepped profile comprises at least one vertical portion and two lateral portions, both ends of the at least one vertical portion are connected to the lateral portions, respectively, and wherein one of the two lateral portions is located directly above and in contact with a respective one of the plurality of first interconnect structures.

12. The memory device of claim 11, wherein, The at least one vertical portion is configured to be broken down by a voltage applied through a respective one of the second interconnect structures.

13. The memory device of claim 11, wherein the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer; the plurality of second interconnect structures extending along a second lateral direction perpendicular to the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and the plurality of insulating layers are disposed between the first and second metallization layers.

14. The memory device of claim 13, wherein, Each of the second interconnect structures is operably shared by a subset of the memory cells arranged along the second lateral direction, each of the subset of memory cells comprising a respective one of the insulating layers and a respective one of the first interconnect structures.

15. The memory device of claim 11, wherein the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer; the plurality of second interconnect structures also extending along the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and the plurality of insulating layers are disposed between the first and second metallization layers.

16. The memory device of claim 15, wherein, Each of the second interconnect structures is operably shared by a subset of the memory cells arranged along the first lateral direction, each of the subset of memory cells comprising a respective one of the insulating layers and a respective one of the first interconnect structures.

17. The memory device of claim 11, wherein the plurality of first interconnect structures extending along a first lateral direction are disposed in a first metallization layer; the plurality of second interconnect structures extending along a second lateral direction perpendicular to the first lateral direction are disposed in a second metallization layer higher than the first metallization layer; and the plurality of insulating layers are disposed between the first and second metallization layers.

18. The memory device of claim 17, wherein, Each of the second interconnect structures is operably shared by a subset of the memory cells arranged along the second lateral direction, each of the subset of memory cells comprising a respective one of the first interconnect structures, and the subset of memory cells sharing one of the insulating layers.

19. A method of fabricating a memory device, comprising: forming a transistor over a substrate; forming a first interconnect structure over the transistor to electrically couple to the transistor, wherein the first interconnect structure is disposed in a first metallization level; exposing a portion of the first interconnect structure; forming a stepped insulating layer over the first interconnect structure, wherein a lateral portion of the stepped insulating layer is in contact with the exposed portion of the first interconnect structure; and forming a second interconnect structure over the lateral portion of the stepped insulating layer, thereby forming a capacitor based at least on the first interconnect structure, the lateral portion of the stepped insulating layer, and the second interconnect structure; wherein the transistor and the capacitor collectively function as a one-time programmable (OTP) memory cell.

20. The method of claim 19, wherein, the second interconnect structure comprises a via structure coupling a second metallization layer to the first metallization layer, or comprises a metal structure disposed below a via structure coupling a second metallization layer to the first metallization layer, and wherein the second metallization layer is disposed immediately above the first metallization layer.

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