A display panel and a display device

Abstract

An embodiment of the present application provides a display panel and a display device, including a display area and a non-display area; the non-display area includes a first power line, a second power line, a first conductive block electrically connected to the first power line, and a second conductive block electrically connected to the second power line; the non-display area includes a first area, and the first area and the display area are arranged along a first direction; in the first area, the first conductive block includes a first part and a second part, and the second conductive block includes a third part and a fourth part; the first part and the third part are located in a first conductive film layer and are separated from each other, and the second part and the fourth part are located in a second conductive film layer and are separated from each other; the fourth part and the first part overlap in the thickness direction of the display panel. By overlapping the fourth part belonging to the second conductive block and the first part belonging to the first conductive block located in different conductive film layers, the area of the second conductive block is prevented from being excessively compressed, and the resistance of the second conductive block is reduced, improving the display effect of the display panel and the display device.

Description

Technical Field

[0001] This application relates to the field of display technologies, and particularly to a display panel and a display device.

Background Art

[0002] With the increasing demand for displays from consumers, narrow bezel displays have become a popular demand at present because they can provide a better user experience. However, in related technologies, functional circuits, peripheral traces, and bonding printed circuit boards need to be provided in the peripheral circuit area of the display panel. Especially in the lower side and the left and right frames of the display panel, there are multiple components such as functional circuits, signal leads, and bonding pins in this area. In the process of achieving narrow bezel displays, how to better arrange the peripheral circuit area to improve the reliability of the display panel has become an urgent problem to be solved.

[0003]

Content of the Application

[0004] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, an embodiment of this application provides a display panel, including:

[0006] A display area;

[0007] A non-display area, which includes:

[0008] A first power line and a second power line;

[0009] A first conductive block, the first conductive block being electrically connected to the first power line;

[0010] A second conductive block, the second conductive block being electrically connected to the second power line;

[0011] Wherein, the non-display area includes a first area, and the first area and the display area are arranged along a first direction; in the first area, the first conductive block includes a first part and a second part, and the second conductive block includes a third part and a fourth part; the first part and the third part are located in a first conductive film layer, and the second part and the fourth part are located in a second conductive film layer;

[0012] The first part and the third part are separated from each other, the second part and the fourth part are separated from each other, and the fourth part and the first part overlap in the thickness direction of the display panel.

[0013] In a second aspect, an embodiment of this application provides a display device, including the display panel provided in the first aspect.

[0014] In the embodiment of the present application, by overlapping the fourth part of the second conductive block located in the second conductive film layer with the first part of the first conductive block located in the first conductive film layer, the conductivity of the first conductive block and the second conductive block can be reasonably adjusted within a limited space. When designing the display panel and the display device with a reduced border, the area compression degree of the second conductive block in the first area is greater than that of the first conductive block. By extending the fourth part of the second conductive block located in the second conductive film layer to the area where the first part of the first conductive block located in the first conductive film layer is located, it is possible to avoid a large impact on the transmitted signal due to excessive area compression of the second conductive block, and effectively reduce the resistance of the second conductive block, thereby improving the display effect of the display panel and the display device.

Description of the Drawings

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present application;

[0017] Figure 2 Schematic diagram of another display panel provided by an embodiment of the present application;

[0018] Figure 3 is Figure 1 and Figure 2 Partial enlarged schematic diagram of the first area in

[0019] Figure 4 is Figure 3 A cross-sectional schematic diagram along the MM' direction in

[0020] Figure 5 is Figure 3 A cross-sectional schematic diagram along the NN' direction in

[0021] Figure 6 is Figure 3 Another cross-sectional schematic diagram along the MM' direction in

[0022] Figure 7 is Figure 3 Another cross-sectional schematic diagram along the NN' direction in

[0023] Figure 8 Equivalent circuit diagram of a light-emitting pixel related to the present application;

[0024] Figure 9A layout schematic diagram of a pixel circuit related to this application;

[0025] Figure 10 A schematic cross-sectional view of a display area related to this application;

[0026] Figure 11 Another schematic cross-sectional view of a display area related to this application;

[0027] Figure 12 Yet another schematic cross-sectional view of a display area related to this application;

[0028] Figure 13 Still another schematic cross-sectional view of a display area related to this application;

[0029] Figure 14 is Figure 1 and Figure 2 a partial enlarged schematic diagram of the first region in;

[0030] Figure 15 is Figure 14 a schematic cross-sectional view along the MM' direction in;

[0031] Figure 16 is Figure 14 a schematic cross-sectional view along the NN' direction in;

[0032] Figure 17 is Figure 1 and Figure 2 a partial enlarged schematic diagram of the first region in;

[0033] Figure 18 is Figure 17 a schematic cross-sectional view along the MM' direction in;

[0034] Figure 19 is Figure 17 a schematic cross-sectional view along the NN' direction in;

[0035] Figure 20 is Figure 1 a partial enlarged schematic diagram in;

[0036] Figure 21 is Figure 20 a partial cross-sectional schematic view along the LL' direction in;

[0037] Figure 22 is Figure 20 another partial cross-sectional schematic view along the LL' direction in;

[0038] Figure 23 is Figure 1 another partial enlarged schematic diagram in;

[0039] Figure 24is Figure 23 a partial sectional view along the LL’ direction in

[0040] Figure 25 is Figure 1 another enlarged partial view in

[0041] Figure 26 is Figure 25 a partial sectional view along the LL’ direction in

[0042] Figure 27 is Figure 1 yet another enlarged partial view in

[0043] Figure 28 is Figure 27 a partial sectional view along the LL’ direction in

[0044] Figure 29 is Figure 27 another partial sectional view along the LL’ direction in

[0045] Figure 30 is Figure 1 still another enlarged partial view in

[0046] Figure 31 is Figure 30 a partial sectional view along the LL’ direction in

[0047] Figure 32 is Figure 30 another partial sectional view along the LL’ direction in

[0048] Figure 33 is Figure 1 still another enlarged partial view in

[0049] Figure 34 is Figure 33 a partial sectional view along the LL’ direction in

[0050] Figure 35 is Figure 33 another partial sectional view along the LL’ direction in

[0051] Figure 36 is Figure 1 yet still another enlarged partial view in

[0052] Figure 37 is Figure 1 yet still another enlarged partial view in

[0053] Figure 38 is a sectional view of the second region;

[0054] Figure 39 Schematic diagram of a display device provided by an embodiment of the present application.

Specific Embodiments

[0055] For a better understanding of the technical solution of the present application, the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0056] It should be clear that the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without making creative efforts belong to the scope of protection of the present application.

[0057] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "the" and "said" used in the embodiments of the present application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0058] It should be understood that the term "and / or" used herein is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " herein generally represents an "or" relationship between the associated objects before and after.

[0059] In the description of this specification, it should be understood that the words such as "substantially", "approximately", "about", "around", "roughly", "generally" used in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0060] It should be understood that although the terms first, second, third, etc. may be used in the embodiments of the present application to describe the conductive film layers, etc., these conductive film layers, etc. should not be limited to these terms. These terms are only used to distinguish the conductive film layers, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first conductive film layer can also be called the second conductive film layer, and similarly, the second conductive film layer can also be called the first conductive film layer.

[0061] The applicant of this case provides a solution to the problems existing in the prior art through careful and in-depth research.

[0062] Figure 1 Schematic diagram of a display panel provided by an embodiment of the present application, Figure 2 Schematic diagram of another display panel provided by an embodiment of the present application.

[0063] Such asFigure 1 and Figure 2 As shown in Figure 2 , the display panel 01 provided in the embodiment of the present application includes a display area AA and a non-display area NA. The display area AA is an area for light-emitting display, and the non-display area NA at least partially surrounds the display area AA and is mainly an area for encapsulation and setting of peripheral traces and circuits. As Figure 1 and Figure 2 shown, the area within the dashed line box can be regarded as the display area AA, and the area outside the dashed line box can be regarded as the non-display area NA.

[0064] Among them, the non-display area NA includes a first area NA1, and the first area NA1 and the display area AA are arranged along the first direction Y. In addition, a first conductive block 21 and a second conductive block 22 are provided in the non-display area NA.

[0065] Figure 3 is Figure 1 a partial enlarged schematic diagram of the first area in Figure 2 , Figure 4 is Figure 3 a cross-sectional schematic diagram along the MM' direction in Figure 5 is Figure 3 a cross-sectional schematic diagram along the NN' direction in Figure 3 . It should be noted that, for the sake of clearly illustrating the inventive concept of the present application,

[0066] Please refer to Figure 3 and Figure 4 , Figure 5 . In the first area NA1, the first conductive block 21 includes a first part 211 and a second part 212, and the second conductive block 22 includes a third part 221 and a fourth part 222. The first part 211 and the third part 221 are located in the first conductive film layer 011 and the first part 211 and the third part 221 are separated from each other. The second part 212 and the fourth part 222 are located in the second conductive film layer 012 and the second part 212 and the fourth part 222 are separated from each other. That is to say, the first conductive block 21 includes the first part 211 and the second part 212 respectively located in the first conductive film layer 011 and the second conductive film layer 012, and the second conductive block 22 includes the third part 221 and the fourth part 222 respectively located in the first conductive film layer 011 and the second conductive film layer 012. And the first part 211 located in the first conductive film layer 011 is electrically insulated from the third part 221, and the second part 212 located in the second conductive film layer 012 is electrically insulated from the fourth part 222. It can be understood that there is a gap between the orthographic projection of the first part 211 on the substrate 010 and the orthographic projection of the third part 221 on the substrate 010. And there is a gap between the orthographic projection of the second part 212 on the substrate 010 and the orthographic projection of the fourth part 222 on the substrate 010.

[0067] The first conductive block 21 in the first region NA1 is configured to have a structure composed of multiple parts located in different conductive film layers; and the second conductive block 22 in the first region NA1 is configured to have a structure composed of multiple parts located in different conductive film layers. On the one hand, it can ensure that the first conductive block 21 and the second conductive block 22 have relatively excellent conductivity, enabling the first conductive block and the second conductive block to have good signal transmission capabilities; on the other hand, it can prevent the first conductive block 21 and the second conductive block 22 from occupying too much area in the first region NA1, achieving a narrow border. It can be understood that the multiple parts of the first conductive block 21 located in different conductive film layers can be electrically connected through contact holes, and the multiple parts of the second conductive block 22 located in different conductive film layers can be electrically connected through contact holes.

[0068] In one implementation, as Figure 4 and Figure 5 shown, the first conductive film layer 011 and the second conductive film layer 012 are located on the same side of the substrate 010, and the first conductive film layer 011 is located on the side closer to the substrate 010 than the second conductive film layer 012. That is, the first part 211 of the first conductive block 21 and the third part 221 of the second conductive block 22 are prepared prior to the second part 212 of the first conductive block 21 and the fourth part 222 of the second conductive block 22. The material of the substrate 010 may include glass materials, ceramic materials, metal materials, plastic materials, or materials with flexible or bendable characteristics, etc.

[0069] Figure 6 is Figure 3 another cross-sectional schematic diagram along the MM' direction in Figure 7 is Figure 3 another cross-sectional schematic diagram along the NN' direction in

[0070] In another implementation, as Figure 6 and Figure 7 shown, the first conductive film layer 011 and the second conductive film layer 012 are located on the same side of the substrate 010, and the second conductive film layer 012 is located on the side closer to the substrate 010 than the first conductive film layer 011. That is, the second part 212 of the first conductive block 21 and the fourth part 222 of the second conductive block 22 are prepared prior to the first part 211 of the first conductive block 21 and the third part 221 of the second conductive block 22.

[0071] Figure 8 This is an equivalent circuit diagram of a light-emitting pixel related to the present application, Figure 9 This is a layout schematic diagram of a pixel circuit related to the present application, Figure 10 This is a cross-sectional schematic diagram of a display area related to the present application, Figure 11Another schematic cross-sectional view of the display area related to the present application.

[0072] As Figure 1 and Figure 2 shown, the display area AA includes light-emitting pixels 11 for light-emitting display. Please refer to Figures 8 - 11 , the light-emitting pixel 11 includes a pixel circuit PD and a light-emitting device PL. The light-emitting device PL includes a light-emitting material layer PL1, an anode PL2, and a cathode PL3. The output terminal of the pixel circuit PD is connected to one of the anode PL2 and the cathode PL3 of the light-emitting device PL, and the other of the anode PL2 and the cathode PL3 of the light-emitting device PL receives a power supply voltage. In addition, during the light emission of the light-emitting device PL, the pixel circuit PD also needs to receive a power supply voltage to generate a light-emitting drive current.

[0073] For example, as Figure 1 and Figure 8 shown, the output terminal of the pixel circuit PD is connected to the anode PL2 of the light-emitting device PL and the cathode PL3 of the light-emitting device PL directly receives a power supply voltage. In addition, the output terminal of the pixel circuit PD can also be connected to the cathode PL3 of the light-emitting device PL and the anode PL2 of the light-emitting device PL directly receives a power supply voltage. Among them, the power supply voltage received by the pixel circuit PD is different from the potential of the power supply voltage received by the anode PL2 or the cathode PL3 of the light-emitting device PL.

[0074] Please continue to refer to Figure 8 and Figure 9 , the pixel circuit PD may include a light-emitting drive transistor T0, a first reset transistor T1, a second reset transistor T2, a data voltage writing transistor T3, a threshold grabbing transistor T4, a power supply voltage writing transistor T5, a light-emitting control transistor T6, and a storage capacitor C1.

[0075] The display area AA further includes a data line 12, a scan line 13, and a first signal line 14.

[0076] One plate of the storage capacitor C1 is electrically connected to the gate of the light-emitting drive transistor T0, and the other plate is electrically connected to the input terminal of the power supply voltage writing transistor T5.

[0077] The input terminal of the first reset transistor T1 is connected to the first reset signal line Vref1, the output terminal is electrically connected to the gate of the light-emitting drive transistor T0, and the control terminal is electrically connected to the first scan line S1, and is used to reset the gate of the light-emitting drive transistor T0.

[0078] The input terminal of the second reset transistor T2 is connected to the second reset signal line Vref2, the output terminal is electrically connected to the light-emitting device PL, and the control terminal is electrically connected to the second scan line S2, and is used to reset the anode or cathode of the light-emitting device PL. The signals of the first reset signal line vref1 and the second reset signal line vref2 can be the same or different.

[0079] The input terminal of the data voltage writing transistor T3 is connected to the data line 12, the output terminal is electrically connected to the input terminal of the light-emitting driving transistor T0, and the control terminal is electrically connected to the second scan line S2; the input terminal of the threshold grabbing transistor T4 is electrically connected to the output terminal of the light-emitting driving transistor T0, the output terminal is electrically connected to the gate of the light-emitting driving transistor T0, and the control terminal is electrically connected to the second scan line S2. The data voltage writing transistor T3 and the threshold grabbing transistor T4 cooperate to write the data voltage Vdata into the gate of the light-emitting driving transistor T0.

[0080] The input terminal of the power supply voltage writing transistor T5 is connected to the first signal line 14, the output terminal is electrically connected to the input terminal of the light-emitting driving transistor T0, and the control terminal is electrically connected to the third scan line S3, and is used to write the first power supply voltage into the input terminal of the light-emitting driving transistor T0.

[0081] The input terminal of the light-emitting control transistor T6 is electrically connected to the output terminal of the light-emitting driving transistor T0, the output terminal is electrically connected to the light-emitting device PL, and the control terminal is electrically connected to the third scan line, and is used to transmit the light-emitting driving current generated by the light-emitting driving transistor T0 to the light-emitting device PL.

[0082] It should be noted that Figure 8 and Figure 9 only a structure of a pixel circuit is schematically given, and the pixel circuits in the display area can also be other structures except for Figure 8 、 Figure 9 the structure shown.

[0083] The potential of the power supply voltage received by the anode PL2 or the cathode PL3 of the light-emitting device PL is different from the potential of the power supply voltage received by the pixel circuit PD. The power supply voltage received by the pixel circuit PD is defined as the first power supply voltage, the power supply voltage received by the anode PL2 or the cathode PL3 of the light-emitting device PL is defined as the second power supply voltage, and the anode PL2 or the cathode PL3 of the light-emitting device PL that receives the second power supply voltage is defined as the first electrode. The signal line that transmits the first power supply voltage to the pixel circuit PD in the display area AA is defined as the first signal line 14, that is, the first signal line 14 transmits the first power supply voltage.

[0084] Among them, the first conductive block 21 transmits the first power supply voltage to the first signal line 14, and the second conductive block transmits the second power supply voltage to the first electrode.

[0085] In addition, the non-display area NA further includes a first power line 23 and a second power line 24. The first power line 23 can be understood as the part of the first signal line 14 extending from the display area AA to the non-display area NA, and the second power line 24 can be understood as the part of the first electrode extending from the display area AA to the non-display area NA. Among them, the first electrodes in each light-emitting device PL are connected into a whole-surface conductive structure, and the part of the whole-surface conductive structure extending into the non-display area NA and electrically connected to the second conductive block 22 is the second power line 24.

[0086] The first conductive block 21 is electrically connected to the first power line 23 and is used to transmit a first power voltage to the first power line 23. The second conductive block 22 is electrically connected to the second power line 24 and is used to transmit a second power voltage to the second power line 24. That is to say, the first conductive block 21 is electrically connected to the first signal line 14 through the first power line 23, and the second conductive block 22 is electrically connected to the first electrode through the second power line 24.

[0087] In an embodiment of the present application, please refer to Figure 1 、 Figure 2 , a bonding pin 25, a fan-shaped trace 26, etc. are also provided in the first area NA1, and the first area NA1 is the lower border area of the display area AA.

[0088] In addition, please combine Figure 1 、 Figure 2 With Figure 9 , the first direction Y can be the same as the extending directions of the data line 12 and the first signal line 14, that is, the arrangement of the first area NA1 and the display area AA is consistent with the extending directions of the data line 12 and the first signal line 14. For example, as Figure 1 shown, the first direction Y can be the Figure 1 column direction shown in

[0089] . At this time, the data line 12 and the first signal line 14 both extend along the column direction, and the first area NA1 and the display area AA are arranged along the column direction. Figure 3 With Figure 4 、 Figure 5 shown in

[0090] As described above, in order to ensure the conductivity of the first conductive block 21 and the second conductive block 22, the first conductive block 21 and the second conductive block 22 can both be designed as structures including multiple parts located in different conductive film layers. However, the traces in the first region NA1 are diverse and complex, and the areas of the structures of the first conductive block 21 and the second conductive block 22 located in different film layers are limited. At the same time, in order to achieve a narrow bezel, it is necessary to compress the widths of the first conductive block 21 and the second conductive block 22 in the first region NA1 along the first direction Y.

[0091] In the embodiment of the present application, by overlapping the fourth part 222 of the second conductive block 22 located in the second conductive film layer 012 with the first part 211 of the first conductive block 21 located in the first conductive film layer 011, the conductivity of the first conductive block 21 and the second conductive block 22 can be reasonably adjusted within a limited space.

[0092] Among them, along the second direction X, the second conductive block 22 is located outside the first conductive block 21. When designing the display panel with a reduced bezel, the area compression degree of the second conductive block 22 in the first region NA1 is greater than that of the first conductive block 21. By extending the fourth part 222 of the second conductive block 22 located in the second conductive film layer 012 to the region where the first part 211 of the first conductive block 21 located in the first conductive film layer 011 is located, the resistance of the second conductive block 22 can be effectively reduced, and the display effect of the display panel can be improved.

[0093] In addition, the first conductive block 21 is mainly disposed in the first region NA1 and is electrically connected to the first power line 23 in the first region NA1. After the area of the first conductive block 21 is compressed, the influence on the signal transmitted by it is not significant. However, the second conductive block 22 needs to extend to a region outside the first region NA1 to be electrically connected to the second power line 24. If its area is excessively compressed, the influence on the transmitted signal is relatively large. For example, when transmitting a large current instantaneously during an aging test or a large current for a high-brightness test required by a customer, there is a risk of burning of the second conductive block. Since the second conductive block is electrically connected to the pixel circuit PD in the display area AA, the display effect of the display panel will be affected. By extending the fourth part 222 of the second conductive block 22 to the region where the first part 211 of the first conductive block 21 located in the first conductive film layer 011 is located, the area of the second conductive block 22 can be prevented from being too small, the conductivity of the second conductive block 22 can be improved, the impedance of the second conductive block 22 can be reduced, and the yield of the display panel can be improved.

[0094] Among them, please combine Figure 4 、 Figure 5 with Figure 10 、 Figure 11, a first part 211 in the first conductive block 21 and a third part 221 in the second conductive block 22 can be arranged on the same layer as the first signal line 14, that is, the first signal line 14, the first part 211 in the first conductive block 21, and the third part 221 in the second conductive block 22 are all located in the first conductive film layer 011.

[0095] Please continue to refer to Figure 4 , Figure 5 and Figure 10 , Figure 11 , a second part 212 in the first conductive block 21 and a fourth part 222 in the second conductive block 22 can be arranged on a different layer from the first signal line 14. For example, they can be arranged on the side of the first conductive film layer 011 away from the substrate 010. Optionally, the second part 212 or the fourth part 222 can also be arranged on the side of the first conductive film 011 close to the substrate 010.

[0096] In one implementation, as Figure 10 shown, the data line 12 can be arranged on the same layer as the first signal line 14, then the first part 211 in the first conductive block 21 and the third part 221 in the second conductive block 22 can be arranged on the same layer as the data line 12.

[0097] In another implementation, as Figure 11 shown, the data line 12 can be arranged on a different layer from the first signal line 14, then the first part 211 in the first conductive block 21 and the third part 221 in the second conductive block 22 can be arranged on the same layer as the first signal line 14 and be located in the first conductive film layer 011, and the second part 212 in the first conductive block 21 and the fourth part 222 in the second conductive block 22 can be arranged on the same layer as the data line 12 and be located in the second conductive film layer 012.

[0098] Optionally, in the direction perpendicular to the plane of the substrate, the second conductive film layer 012 can also be the conductive film layer in the display panel located between the data line 12 and the first conductive film layer 011. Optionally, in the display panel including oxide semiconductor transistors, the second conductive film layer 012 can also be on the same layer as the gate of the oxide semiconductor transistors.

[0099] Figure 12 This is another schematic cross-sectional view of the display area related to the present application, Figure 13 This is yet another schematic cross-sectional view of the display area related to the present application.

[0100] In addition, please refer to Figure 6 , Figure 7 and Figure 12 , Figure 13, the second part 212 of the first conductive block 21 and the fourth part 222 of the second conductive block 22 can be arranged on the same layer as the first signal line 14, that is, the first signal line 14, the second part 212 of the first conductive block 21, and the fourth part 222 of the second conductive block 22 are all located in the second conductive film layer 012.

[0101] Please continue to combine Figure 6 , Figure 7 with Figure 12 , Figure 13 , the first part 211 of the first conductive block 21 and the third part 221 of the second conductive block 22 can be arranged on a different layer from the first signal line 14. For example, they are arranged on the side of the second conductive film layer 012 away from the substrate 010.

[0102] In one implementation, as Figure 12 shown, the data line 12 can be arranged on the same layer as the first signal line 14, then the second part 212 of the first conductive block 21 and the fourth part 222 of the second conductive block 22 can be arranged on the same layer as the data line 12.

[0103] In another implementation, as Figure 13 shown, the data line 12 can be arranged on a different layer from the first signal line 14, then the second part 212 of the first conductive block 21 and the fourth part 222 of the second conductive block 22 can be arranged on the same layer as the first signal line 14 and located in the second conductive film layer 012, and the first part 211 of the first conductive block 21 and the third part 221 of the second conductive block 22 can be arranged on the same layer as the data line 12 and located in the first conductive film layer 011.

[0104] As Figure 3 shown, the first conductive block 21 is electrically connected to the first power line 23 in the first region NA1. Multiple first power lines 23 are distributed along the second direction X at a position in the first region NA1 close to the display area AA, where the second direction X is the same as the extension direction of the boundary line between the display area AA and the first region NA1. As Figure 1 and Figure 2 shown, the second direction X can intersect with the first direction Y. Specifically, the second direction X can be perpendicular to the first direction Y.

[0105] In an embodiment of the present application, please combine Figure 1 , Figure 2 with Figure 3, a first part 211 in the first conductive block 21 includes a first connection portion 2110 close to the display area AA. The first connection portion 2110 extends along the second direction X and is electrically connected to the first power line 23. That is to say, the first connection portion 2110 is the part in the first conductive block 21 connected to the first power line 23. Among them, the first power line 23 can be arranged on the same layer as the first connection portion 2110.

[0106] A third part 221 located on the same conductive film layer as the first part 211 is on the side of the first connection portion 2110 away from the display area AA, as Figures 1 - 3 shown. Along the first direction Y, the third part 221 is on the side of the first connection portion 2110 away from the display area AA. And along the thickness direction of the display panel 01, the first connection portion 2110 overlaps with the second part 212, and the first connection portion 2110 overlaps with the fourth part 222. That is to say, in the first region NA1, the overlapping region of the fourth part 222 of the second conductive block 22 and the first part 211 of the first conductive block 21 includes the part of the first connection portion 2110 located between the region where the third part 221 is located and the region where the display area AA is located. For example, as Figure 1 and Figure 2 shown, the fourth part 222 in the second conductive block 22 extends from the region where the third part 221 is located towards the direction where the display area AA is located and at least partially overlaps with the first connection portion 2110.

[0107] By extending the fourth part 222 in the second conductive block 22 located in the second conductive film layer towards the direction where the first connection portion 2110 in the first conductive block 21 located in the first conductive film layer and close to the display area AA is located, the area of the fourth part 222 is increased, thereby improving the conductivity of the second conductive block 22. At the same time, it will not additionally increase the width of the first region NA1 of the display panel 01 along the first direction Y, which is beneficial to realizing a narrow border. In addition, although the fourth part 222 overlaps with the first connection portion 2110, it will not affect the width and area of the first connection portion 2110; the second conductive block 22 and the first power line 23 are electrically connected in the first region NA1, and the part in the second conductive block 22 directly connected to the first power line 23 is the first connection portion 2110. Therefore, the design of this embodiment will not have a great impact on the second conductive block 22 providing signals for the first power line 23 and the first signal line 14.

[0108] Figure 14 is Figure 1 a Figure 2 partial enlarged schematic diagram of the first region in Figure 15 is Figure 14 a Figure 16 sectional schematic diagram along the MM' direction in Figure 14 is a sectional schematic diagram along the NN' direction in

[0109] In one embodiment of the present application, please refer to Figure 14 and Figure 15 , Figure 16 , the display panel 01 further includes a substrate 010 and a first organic layer OL. The first conductive film layer 011 is disposed between the substrate 010 and the second conductive film layer 012, and the second conductive film layer 012 is disposed between the first organic layer OL and the first conductive film layer 011. That is, the substrate 010, the first conductive film layer 011, the second conductive film layer 012, and the first organic layer OL in the display panel are sequentially disposed. It can be understood that there is an insulating layer between the first conductive film layer 011 and the second conductive film layer 012.

[0110] Then, in the first region NA1, the conductive film layers where the first part 211 and the third part 221 are located are disposed between the conductive film layers where the second part 212 and the fourth part 222 are located and the substrate 010, and the first organic layer OL is disposed on the side of the conductive film layers where the second part 212 and the fourth part 222 are located away from the substrate 010.

[0111] In the first region NA1, the first organic layer OL includes an opening region H1. Making an opening design for the organic layer in the non-display region NA1 can form a dam structure to block the penetration of water and oxygen from the outside of the display panel 01 into the display panel 01 through the organic layer, thereby avoiding the erosion of the signal lines, devices, etc. inside the display panel 01 by water, oxygen, etc. from the outside.

[0112] Among them, the second part 212 and the fourth part 222 in the second conductive film layer 012 do not overlap with the opening region H1. In the first region NA1, after the first organic layer OL on the side of the second conductive film layer 012 away from the substrate 010 is provided with the opening region H1, and at the same time, the second part 212 and the fourth part 222 in the second conductive film layer 012 are designed to avoid the opening region H1 of the first organic layer PL, it can be avoided that the second part 212 and the fourth part 222 in the second conductive film 012 are etched away in the subsequent etching process, thereby affecting the reliability of the second part 212 and the fourth part 22.

[0113] In one implementation manner of this embodiment, the first organic layer OL includes a plurality of opening regions H1 in the first region NA1. Then, the second part 212 and the fourth part 222 in the second conductive film layer extend in the direction away from the display region AA and stop before the opening region H1 closest to the display region AA in the first organic layer OL, thereby avoiding the second part 212 and the fourth part 222 from being etched away in the subsequent etching process.

[0114] Figure 17 For Figure 1 and Figure 2A partial enlarged schematic view of the first region in Figure 18 is Figure 17 a cross-sectional schematic view along the MM' direction in Figure 19 is Figure 17 a cross-sectional schematic view along the NN' direction in

[0115] In an embodiment of the present application, the display panel 01 further includes a substrate 010, and the first conductive film layer 011 is disposed between the second conductive film layer 012 and the substrate 010. That is, the substrate 010, the first conductive film layer 011, and the second conductive film layer 012 in the display panel are sequentially disposed. It can be understood that there is an insulating layer between the first conductive film layer 011 and the second conductive film layer 012. Then, in the first region NA1, the conductive film layers where the first part 211 and the third part 221 are located are disposed between the conductive film layers where the second part 212 and the fourth part 222 are located and the substrate 010.

[0116] Wherein, along the thickness direction of the display panel 01, the fourth part 222 completely covers the third part 221, so that the conductivity of the second conductive block 22 can be further increased.

[0117] In addition, in this embodiment, the display panel 01 may also include a first organic layer OL, and an opening area H1 may also be provided in the part of the first organic layer OL located in the first region NA1. Among them, the fourth part 222 may overlap with the opening area H1.

[0118] And, along the thickness direction of the display panel 01, the second part 212 completely covers the first part 211, so that the conductivity of the first conductive block 21 can be further increased. In addition, the display panel 01 may also include a first organic layer OL, and an opening area H1 may also be provided in the part of the first organic layer OL located in the first region NA1. Among them, the second part 212 may overlap with the opening area H1.

[0119] Figure 20 is Figure 1 a partial enlarged schematic view in

[0120] As Figure 20 shown, the non-display area NA of the display panel includes, in addition to the first region NA1, a second region NA2, and the second region NA2 and the display area AA are arranged along the second direction X, and the first direction Y intersects with the second direction X.

[0121] In a technical solution of the present application, the non-display area NA of the display panel includes a chamfer design, wherein the chamfer region may be included in the second region NA2. And the second region NA2 may be connected to the first region NA1.

[0122] In addition, the scan line 13 may extend along the second direction X. Then, along the extending direction of the scan line 13, the non-display area NA outside all the scan lines 13 is the second area NA2. In addition, along the first direction Y, the first area NA1 is the area below the scan line 13 closest to the first area NA1, that is, the first area NA1 may have substantially the same width as the scan line 13 closest to the first area NA1 along the second direction X.

[0123] Wherein, in the second area NA2, the second conductive block 22 includes a fifth part 223, and the fifth part 223 is located in one of the first conductive film layer 011 and the second conductive film layer 12. That is, the fifth part 223 of the second conductive block 22 located in the second area NA2 and the third part 221 of the second conductive block 22 located in the first area NA1 are located in the same conductive film layer, or the fifth part 223 of the second conductive block 22 located in the second area NA2 and the fourth part 222 of the second conductive block 22 located in the first area NA1 are located in the same conductive film layer. The following is a schematic illustration with the fifth part 223 and the fourth part 222 located in the same conductive film layer.

[0124] In addition, as Figure 20 shown, the fifth part 223 includes a first sub-part 2231 and a second sub-part 2232; along the second direction X, the distance between the first sub-part 2231 and the second sub-part 2232 is greater than 0. It can be understood that since the first sub-part 2231 and the second sub-part 2232 both belong to the fifth part 223 of the second conductive block 22, the first sub-part 2231 and the second sub-part 2232 are electrically connected.

[0125] In the embodiment of the present application, by setting the fifth part 223 of the second conductive block 22 located in the second area NA2 to a structure including the first sub-part 2231 and the second sub-part 2232, the area of the fifth part 223 is increased in the non-display area NA with limited space.

[0126] Figure 21 For Figure 20 a partial cross-sectional schematic diagram along the LL' direction in Figure 22 For Figure 20 another partial cross-sectional schematic diagram along the LL' direction in

[0127] In an embodiment of the present application, please refer to Figure 20 and Figure 21 and Figure 22, the driving circuit 27 is included in the second region NA2. Among them, the first sub-part 2231 in the fifth part 223 is located on the side of the driving circuit 27 close to the display area AA, and the second sub-part 2232 is located on the side of the driving circuit 27 far from the display area AA. By adding the first sub-part 2231 on the side of the pixel driving circuit 27 close to the display area AA, the area of the second conductive block 22 in the second region NA2 can be increased, and its resistivity can be reduced.

[0128] In addition, the second region NA2 can be a non-display area NA including the driving circuit 27 relative to the first region NA1, that is, the driving circuit 27 is arranged in the second region NA2 and not in the first region NA1.

[0129] It should be noted that since there are many and complex wirings and circuit settings in the second region NA2, the statement that the first sub-part 2231 is located on the side of the driving circuit 27 close to the display area AA means that most of the area of the first sub-part 2231 is located on the side of the driving circuit 27 close to the display area AA and a small part of the area of the first sub-part 2231 can overlap with the driving circuit 27; the statement that the second sub-part 2232 is located on the side of the driving circuit 27 far from the display area AA means that most of the area of the second sub-part 2232 is located on the side of the driving circuit 27 far from the display area AA and a small part of the area of the second sub-part 2232 can overlap with the driving circuit 27.

[0130] It should also be noted that Figure 21 and Figure 22 only one transistor is schematically shown in the driving circuit 27 in, and the driving circuit 27 can also include other transistors and other types of devices, such as capacitors.

[0131] In one implementation manner of this embodiment, please continue to refer to the figure. The display area includes the scanning line 13, and the output end of the driving circuit 27 is electrically connected to the scanning line 13 through the first connection line 28. That is, the driving circuit 27 can be a shift register that outputs a scanning signal to the scanning line 13.

[0132] Among them, the first connection line 28 is located in one of the first conductive film layer 011 and the second conductive film layer 012, and the first connection line 28 is arranged in a different layer from the fifth part 223 of the second conductive block 22. That is, when the fifth part 223 is located in the first conductive film layer 011, the first connection line 28 is located in the second conductive film layer 012; when the fifth part 223 is located in the second conductive film layer 012, the first connection line 28 is located in the first conductive film layer 011.

[0133] Since the first sub - part 2231 of the fifth part 223 is located on the side of the driving circuit 27 close to the display area AA in the second region NA2, and the first connection line 28 connects the driving circuit 27 in the second region NA2 and the scanning line 13 in the display area AA, by arranging the fifth part 223 and the first connection line 28 in different layers, short - circuit between them can be avoided, and the area of the second conductive block 22 in the second region NA2 is increased.

[0134] The following takes the case where the fifth part 223 is located in the second conductive film layer 012 and the first connection line 28 is located in the first conductive film layer 011 as an illustration.

[0135] In one implementation of this embodiment, as Figure 21 shown, the conductive film layer where the scanning line 13 is located can be arranged in the same layer as the gate in the transistor, and the conductive film layer where the scanning line 13 is located is on the side of the first conductive film layer 011 and the second conductive film layer 012 close to the substrate 010. The conductive film layer where the first connection line 28 is located is on the side of the conductive film layer where the fifth part 223 is located close to the substrate 010, that is, the conductive film layer where the first connection line 28 is located is on the side of the conductive film layer where the fifth part 223 is located close to the conductive film layer where the scanning line 13 is located.

[0136] In one implementation of this embodiment, as Figure 21 shown, the conductive film layer where the scanning line 13 is located can be arranged in the same layer as the gate in the transistor, and the conductive film layer where the scanning line 13 is located is on the side of the first conductive film layer 011 and the second conductive film layer 012 close to the substrate 010. The conductive film layer where the first connection line 28 is located is on the side of the conductive film layer where the fifth part 223 is located away from the substrate 010, that is, the conductive film layer where the first connection line 28 is located is on the side of the conductive film layer where the fifth part 223 is located away from the conductive film layer where the scanning line 13 is located.

[0137] In one implementation of this embodiment, please refer to Figure 20 and Figure 21 and Figure 22 , in the second region NA2, the second conductive block 22 further includes a sixth part 224. The sixth part 224 is located in the same conductive film layer as the first connection line 28 and is on the side of the driving circuit 27 away from the display area AA. That is, the part of the second conductive block 22 in the second region NA2, in addition to including the fifth part 223, also includes a sixth part 224 arranged in a different layer from the fifth part 223. When the fifth part 223 is in the first conductive film layer 011, the sixth part 224 is in the second conductive film layer 012; when the fifth part 223 is in the second conductive film layer 012, the sixth part 224 is in the first conductive film layer 011.

[0138] Although the sixth part 224 and the first connection line 28 are located in the same conductive film layer, since the sixth part 224 is located on the side of the driving circuit 27 away from the display area AA, the sixth part 224 will not affect the setting of the first connection line 28.

[0139] In an embodiment of the present application, as Figures 20 - 22 shown, in the conductive film layer where the fifth part 223 is located, a first gap is included between the first sub - part 2231 and the second sub - part 2232. That is, in the conductive film layer where the fifth part 223 is located, the part located between the first sub - part 2231 and the second sub - part 2232 is a hollowed - out part.

[0140] In one implementation manner of this embodiment, the first gap between the first sub - part 2231 and the second sub - part 2232 overlaps at least partially with the driving circuit 27, that is, the hollowed - out part located between the first sub - part 2231 and the second sub - part 2232 in the conductive film layer where the fifth part 223 is located exposes at least part of the driving circuit.

[0141] Under the requirement of the narrow border of the display panel, the width of the second region NA2 will also be compressed. Then, the projection of at least part of the signal lines connected to the driving circuit 27 in the second region NA2 needs to overlap with the projection of the driving circuit 27, that is, these signal lines need to be arranged above the film layer of the driving circuit 27. Since the fifth part 223 is also located above the film layer of the driving circuit 27, part of the signal lines connected to the driving circuit 27 can be arranged on the same layer as the fifth part 223 and located within the first gap. For example, the clock signal line electrically connected to the driving circuit 27 can be a double - layer routing design and one of the routings can be arranged on the same layer as the second part 223 and located within the first gap.

[0142] Figure 23 For Figure 1 another partial enlarged schematic diagram in Figure 24 For Figure 23 a partial cross - sectional schematic diagram along the LL' direction in Figure 25 For Figure 1 another partial enlarged schematic diagram in Figure 26 For Figure 25 a partial cross - sectional schematic diagram along the LL' direction in

[0143] In an embodiment of the present application, please combine Figure 23 with Figure 24 and Figure 25 with Figure 26, the fifth part 223 of the second conductive block 22 further includes a third sub - part 2233, and the third sub - part 2233 is located between the first sub - part 2231 and the second sub - part 2232 and is connected to the first sub - part 2231 and the second sub - part 2232 respectively. That is, the fifth part 23 located in the second region NA2 is a continuous structure along the second direction X, which not only includes the parts on both sides of the driving circuit 27 but also includes the part above the film layer where the driving circuit 27 is located. Thus, the area of the second conductive block 22 can be effectively increased.

[0144] In one implementation of this embodiment, as Figure 23 and Figure 24 shown, when the second conductive film layer 012 is on the side of the first conductive film layer 011 away from the substrate 010, the signal lines of the driving circuit 27 can be all arranged on the first conductive film layer 011 and other conductive film layers close to the substrate 010 of the first conductive film layer 011. At this time, along the thickness direction of the display panel, the fifth part 223 can completely cover the driving circuit 27.

[0145] In one implementation of this embodiment, as Figure 25 and Figure 26 shown, when the second conductive film layer 012 is on the side of the first conductive film layer 011 close to the substrate 010, at least some of the signal lines of the driving circuit 27 need to be arranged on the side of the second conductive film layer 012 away from the substrate 010. At this time, an opening can be provided in the third sub - part 2233 of the fifth part 223 so that the driving circuit 27 is electrically connected to the signal lines above the second conductive film layer 012, that is, the third sub - part 2233 can be a grid - like structure.

[0146] Figure 27 For Figure 1 another partial enlarged schematic diagram in Figure 28 For Figure 27 a partial cross - sectional schematic diagram along the LL’ direction in Figure 29 For Figure 27 another partial cross - sectional schematic diagram along the LL’ direction in

[0147] In an embodiment of the present application, please combine Figure 27 with Figure 28 and Figure 29, the display area AA further includes a light-emitting device PL. The light-emitting device PL includes a first electrode, and the first electrode is located on the third conductive film layer 013. The second region NA2 includes a second power line 24 located on the third conductive film layer 013, and the second power line 24 is electrically connected to the first electrode. As described above, the second power line 24 can be regarded as the part of the third conductive film layer 013 located in the second region NA2. The first electrode is the anode or cathode of the light-emitting device PL, which will not be elaborated here. Hereinafter, it is schematically illustrated with the first electrode being the cathode of the light-emitting device PL.

[0148] In the second region NA2, the second power line 24 is electrically connected to the fifth part 223 in the second conductive block 22. That is, the part of the second conductive block 22 located in the second region NA2 is electrically connected to the first electrode through the second power line 24.

[0149] Since the fifth part 223 includes a first sub-part 2231 and a second sub-part 2232 arranged along the second direction X, the electrical connection manner between the second power line 24 and the fifth part 223 can be Figure 28 as shown, the second power line 24 is connected to the second sub-part 2232 in the fifth part 223 through a via; or it can be Figure 29 as shown, the second power line 22 is not only connected to the second sub-part 2232 in the fifth part 223 through a via, but also connected to the first sub-part 2231 in the fifth part 223 through a via.

[0150] It should be noted that in the second region NA2, the arrangement manners of the fifth part 223 and the driving circuit 27 have been described in detail and will not be elaborated here. However, the connection manner between the second power line 24 and the second conductive block 22 in this embodiment is applicable to any of the above-mentioned situations.

[0151] Figure 30 For Figure 1 is another partial enlarged schematic diagram in Figure 31 For Figure 30 is a partial cross-sectional schematic diagram along the LL' direction in Figure 32 For Figure 30 is another partial cross-sectional schematic diagram along the LL' direction in Figure 33 For Figure 1 is another partial enlarged schematic diagram in Figure 34 For Figure 33 is a partial cross-sectional schematic diagram along the LL' direction in Figure 35 For Figure 33 is another partial cross-sectional schematic diagram along the LL' direction in

[0152] As Figures 30 - 35As shown, in the second region NA2, the second conductive block 22 further includes a seventh portion 225, and the seventh portion 225 is located in the fourth conductive film layer 014; the fourth conductive film layer 014 is located between the third conductive film layer 013 and the conductive film layer where the fifth portion 223 is located. Among them, along the thickness direction of the display panel, the second power line 24 is electrically connected to the fifth portion 223 through the seventh portion 225. That is, the seventh portion 225 can be regarded as a connection electrode between the fifth portion 223 and the second power line 24, avoiding the risk of broken wires in the vias when the distance between the film layer where the second power line 24 is located and the film layer where the fifth portion 225 is located is too far.

[0153] Among them, please refer to Figures 10 - 13 , the seventh portion 225 can be arranged on the same layer as the anode PL2 and the second power line 24 can be arranged on the same layer as the cathode PL3. In addition, the seventh portion 225 can be arranged on the same layer as the cathode PL3 and the second power line 24 can be arranged on the same layer as the anode PL2. The following takes the seventh portion 225 being arranged on the same layer as the anode PL2 and the second power line 24 being arranged on the same layer as the cathode PL3 as an example for illustration.

[0154] One technical solution of the present application is that, as Figure 31 shown in Figure 34 , the conductive film layer where the fifth portion 223 in the second conductive block 22 is located is on the side away from the substrate 010 of the conductive film layer where the sixth portion 224 is located, and the seventh portion 225 is on the side away from the substrate 010 of the conductive film layer where the fifth portion 223 is located, then the fifth portion 223 can be connected to the seventh portion 225 through a via.

[0155] One technical solution of the present application is that, as Figure 31 shown in Figure 34 , the conductive film layer where the fifth portion 223 in the second conductive block 22 is located is on the side away from the substrate 010 of the conductive film layer where the sixth portion 224 is located, and the seventh portion 225 is on the side away from the substrate 010 of the conductive film layer where the fifth portion 223 is located, then the fifth portion 223 can be connected to the seventh portion 225 through a via.

[0156] One technical solution of the present application is that, as Figure 32 shown in Figure 35 , the conductive film layer where the fifth portion 223 in the second conductive block 22 is located is on the side close to the substrate 010 of the conductive film layer where the sixth portion 224 is located, and the seventh portion 225 is on the side away from the substrate 010 of the conductive film layer where the sixth portion 224 is located, then the fifth portion 223 is electrically connected to the seventh portion 225 through the sixth portion 224.

[0157] In one embodiment of the present application, please refer to Figure 30 shown in Figure 31, Figure 32 , the second sub - part 2232 in the fifth part 223 is located on the side of the first sub - part 2231 away from the display area AA; along the thickness direction of the display panel, the seventh part 225 overlaps with the second sub - part 2232 and does not overlap with the first sub - part 2231.

[0158] In this embodiment, since the second sub - part 2232 is located on the side of the first sub - part 2231 close to the edge of the display panel, the seventh part 225 is arranged at a position close to the edge of the display panel. Further, the part where the seventh part 225 is electrically connected to the fifth part 223 in the second area NA2 is located at a position close to the edge of the display panel in the second display NA2, thus avoiding the influence of the seventh part 225 on the signal lines in the second area NA2 when extending to the display area AA.

[0159] In an embodiment of the present application, please refer to Figure 33 and Figure 34 , Figure 35 , the seventh part 225 includes a fourth sub - part 2251 and a fifth sub - part 2252, and along the second direction X, the distance between the fourth sub - part 2251 and the fifth sub - part 2252 is greater than 0. In addition, along the thickness direction of the display panel, the fourth sub - part 2251 overlaps with the first sub - part 2231 and the fifth sub - part 2252 overlaps with the second sub - part 2232.

[0160] It can be understood that since the fourth sub - part 2251 and the fifth sub - part 2252 both belong to the seventh part 225 of the second conductive block 22, the fourth sub - part 2251 and the fifth sub - part 2252 are electrically connected.

[0161] In the embodiment of the present application, by setting the seventh part 225 of the second conductive block 22 in the second area NA2 to a structure including the fourth sub - part 2251 and the fifth sub - part 2252, the area of the seventh part 225 is increased in the non - display area NA with limited space, thereby reducing the resistance of the second conductive block 22.

[0162] In one implementation manner of this embodiment, both the fourth sub - part 2251 and the fifth sub - part 2252 are electrically connected to the second power line 24 and the fifth part 2252. That is, the fourth sub - part 2251 overlapping with the first sub - part 2231 serves as, and the fifth sub - part 2252 overlapping with the second sub - part 2232 serves as the connection electrode between the second sub - part 2232 and the second power line 24. Then the resistance between the second power line and the second conductive block 22 can be reduced.

[0163] In one implementation manner of this embodiment, as Figures 33 - 35As shown, in the conductive film layer where the seventh part 225 is located, there is a second gap between the fourth sub - part 2251 and the fifth sub - part 2252. That is, in the fourth conductive film layer 014, the part between the fourth sub - part 2251 and the fifth sub - part 2252 is a hollowed - out part. And the area where the second gap is located overlaps at least partially with the area where the first gap is located.

[0164] Figure 36 is Figure 1 another partial enlarged schematic diagram in Figure 37 is Figure 1 another partial enlarged schematic diagram in Figure 36 and Figure 37 does not show the film layer structure above the conductive film layer where the seventh part is located.

[0165] As Figure 36 and Figure 37 shown, the seventh part 225 further includes a sixth sub - part 2253. The sixth sub - part 2253 is located between the fourth sub - part 2251 and the fifth sub - part 2252 and is connected to the fourth sub - part 2251 and the fifth sub - part 2252 respectively. That is, the fifth part 23 in the second region NA2 is a continuous structure along the second direction X. It not only includes the parts on both sides of the driving circuit 27 but also includes the part above the film layer where the driving circuit 27 is located. Thus, the area of the second conductive block 22 can be effectively increased.

[0166] In one implementation, as Figure 36 shown, along the thickness direction of the display panel, the seventh part 225 can completely cover the driving circuit 27.

[0167] In one implementation, as Figure 37 shown, in the seventh part 225 in the second region NA2, there are a plurality of through - holes 2250. Among them, the through - holes 2250 can be used as exhaust holes for the organic layer below the fourth conductive film layer 014.

[0168] In addition, the through - holes can be filled with the film layer on the side of the fourth conductive film layer 014 away from the substrate 010. For example, the pixel definition layer can be used to fill the through - holes, which can effectively protect the conductive film layer included in the through - holes 2250.

[0169] Combined with Figure 20 、 Figure 23 、 Figure 25 、 Figure 27 、 30 、 Figure 33 、 Figure 36 、 Figure 37 and Figure 1 、 Figure 2, the second region NA2 includes a chamfered region, and the chamfered region is located in the second region NA2 near the first region NA1. Among them, the display area above the chamfered region is recessed in the direction away from the first region NA1 along the first direction Y relative to the display area in the upward direction of the first region.

[0170] In an embodiment of the present application, in the chamfered region, the second power supply line 24 is electrically connected to the fifth part 223 through the seventh part 225. In one implementation manner of this embodiment, the position where the second power supply line 24 is electrically connected to the fifth part 223 and the seventh part 225 is only located in the chamfered region.

[0171] In an embodiment of the present application, as Figure 20 , Figure 23 , Figure 25 , Figure 27 , 30 , Figure 33 , Figure 36 , Figure 37 shown, in the chamfered region in the second region NA2, the first conductive block 21 includes an eighth part 213, and the eighth part 213 is located on the side of the fifth part 223 close to the display area AA.

[0172] In one implementation manner of this embodiment, the eighth part 213 and the fifth part 223 are located in the same conductive film layer, and the eighth part 213 is located between the first sub-part 2231 and the display area AA. Then it is convenient for the eighth part 213 in the second region NA2 to be electrically connected to the first part 211 or the second part 212 in the first region NA1.

[0173] Figure 38 It is a schematic cross-sectional view of the second region.

[0174] As Figure 38 shown, the second region NA2 includes at least one barrier structure, the barrier structure includes a first organic structure, and the two sides of the barrier structure do not include the first organic structure, that is, along the direction parallel to the plane of the substrate 010, the opposite sides of the barrier structure include organic clearance areas (regions without organic structures), or the barrier structure is an island structure. For example, Figure 38 shows two barrier structures B1, B2 in the second region NA2, and the first organic structures in the two barrier structures B1, B2 are both located in the first organic layer OL, that is, the first organic layer OL is a discontinuous structure near the position of the barrier structure. The barrier structure can prevent external water and oxygen from invading the display area AA, extend the water and oxygen invasion path, and avoid the devices in the display area AA from being eroded by water and oxygen.

[0175] In the second region NA2, the edge of the second conductive block 22 that is far from the display area AA is the first edge L1. That is, among all the parts included in the second conductive block 22, when the edge of any part is the farthest from the display area AA, this edge of this part is the first edge L1. For example, as Figure 38 shown, when the second conductive block 22 in the second region NA2 includes the fifth part 223, the sixth part 224, and the seventh part 225 at the same time, the edge of the seventh part 225 is farther from the display area AA than the fifth part 223 and the sixth part 224. Then, the edge of the seventh part 225 that is far from the display area AA is the first edge L1.

[0176] Among them, the edge of at least one barrier structure provided in the second region NA2 that is the farthest from the display area AA is the second edge L2. For example, as Figure 38 shown, the edge of the barrier structure B2 in the second region NA2 is farther from the display area AA than the edge of the barrier structure B1. Then, the edge of the barrier structure B2 that is far from the display area AA is the second edge L2.

[0177] In the embodiment of the present application, the first edge L1 is located on the side of the second edge L2 close to the display area AA. That is, the fifth part 223 in the second region NA2 does not extend beyond the barrier structure. On the one hand, it can ensure that the edges of some conductive structures in the fifth part 223 are not damaged by processes such as etching and cutting. On the other hand, it can prevent static electricity outside the display panel from being introduced into the display panel through the fifth part 223.

[0178] Figure 39 It is a schematic diagram of a display device provided by an embodiment of the present application.

[0179] The embodiment of the present application provides a display device. As Figure 39 shown, it includes a display panel 001 provided in any of the above embodiments. The display device provided by the embodiment of the present application can be a mobile phone. In addition, the display device provided by the embodiment of the present application can also be a display device such as a computer or a television.

[0180] In the embodiment of the present application, by overlapping the fourth part of the second conductive block located in the second conductive film layer with the first part of the first conductive block located in the first conductive film layer, the conductivity of the first conductive block and the second conductive block can be reasonably adjusted in a limited space. When designing the display device with a reduced border, the area compression degree of the second conductive block in the first region is greater than that of the first conductive block. By extending the fourth part of the second conductive block located in the second conductive film layer to the region where the first part of the first conductive block located in the first conductive film layer is located, it can be avoided that the excessive compression of the area of the second conductive block has a greater impact on the transmitted signal, and the resistance of the second conductive block can be effectively reduced, improving the display effect of the display device.

[0181] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included within the scope of protection of the present application.

Claims

1. A display panel, characterized in that, comprising: a display area; a non-display area, which includes: a first power line and a second power line; a first conductive block, the first conductive block being electrically connected to the first power line; a second conductive block, the second conductive block being electrically connected to the second power line; wherein, the non-display area includes a first area, the first area and the display area are arranged along a first direction; in the first area, the first conductive block includes a first part and a second part, and the second conductive block includes a third part and a fourth part; the first part and the third part are located in a first conductive film layer, and the second part and the fourth part are located in a second conductive film layer; the first part and the third part are separated from each other, the second part and the fourth part are separated from each other, and the fourth part and the first part overlap in the thickness direction of the display panel.

2. The display panel according to claim 1, characterized in that, the first part includes a first connection portion close to the display area; the first connection portion extends along a second direction, and the third part is located on a side of the first connection portion away from the display area, and the second direction intersects with the first direction; in the thickness direction of the display panel, the first connection portion overlaps with the second part and the first connection portion overlaps with the fourth part.

3. The display panel according to claim 1, characterized in that, the display panel includes a substrate and a first organic layer, the first conductive film layer is disposed between the substrate and the second conductive film layer, and the second conductive film layer is disposed between the first organic layer and the first conductive film layer; in the first area, the first organic layer includes an opening area, and neither the second part nor the fourth part overlaps with the opening area.

4. The display panel according to claim 1, characterized in that, the display panel includes a substrate, and the first conductive film layer is disposed between the substrate and the second conductive film layer; in the thickness direction of the display panel, the fourth part completely covers the third part.

5. The display panel according to claim 1, characterized in that, the non-display area further includes a second area, the second area and the display area are arranged along a second direction, and the first direction intersects with the second direction; in the second area, the second conductive block includes a fifth part, and the fifth part is located in one of the first conductive film layer and the second conductive film layer; the fifth part includes a first sub-part and a second sub-part; along the second direction, the distance between the first sub-part and the second sub-part is greater than 0.

6. The display panel according to claim 5, characterized in that, the second area includes a driving circuit, the first sub-part is located on a side of the driving circuit close to the display area, and the second sub-part is located on a side of the driving circuit away from the display area.

7. The display panel according to claim 6, characterized in that, the display area includes a scan line, and an output end of the driving circuit is electrically connected to the scan line through a first connection line; Wherein, the first connection line is located in one of the first conductive film layer and the second conductive film layer, and is in a different layer from the fifth part.

8. The display panel according to claim 7, wherein, in the second region, the second conductive block further includes a sixth part, the sixth part is located in the same conductive film layer as the first connection line, and the sixth part is located on a side of the driving circuit away from the display area.

9. The display panel according to claim 5, wherein, in the conductive film layer where the fifth part is located, a first gap is included between the first sub-part and the second sub-part.

10. The display panel according to claim 5, wherein, the fifth part further includes a third sub-part, the third sub-part is located between the first sub-part and the second sub-part and is respectively connected to the first sub-part and the second sub-part.

11. The display panel according to claim 5, wherein, the display area further includes a light-emitting device, the light-emitting device includes a first electrode, and the first electrode is located in the third conductive film layer; the second power supply line is located in the third conductive film layer, and the second power supply line is electrically connected to the first electrode; in the second region, the second power supply line is electrically connected to the fifth part.

12. The display panel according to claim 11, wherein, in the second region, the second conductive block includes a seventh part, the seventh part is located in the fourth conductive film layer; the fourth conductive film layer is located between the third conductive film layer and the conductive film layer where the fifth part is located; wherein, along the thickness direction of the display panel, the second power supply line and the fifth part are electrically connected through the seventh part.

13. The display panel according to claim 12, wherein, the second sub-part is located on a side of the first sub-part away from the display area; along the thickness direction of the display panel, the seventh part overlaps with the second sub-part and does not overlap with the first sub-part.

14. The display panel according to claim 13, wherein, the seventh part includes a fourth sub-part and a fifth sub-part, and along the second direction, the distance between the fourth sub-part and the fifth sub-part is greater than 0; along the thickness direction of the display panel, the fourth sub-part overlaps with the first sub-part and the fifth sub-part overlaps with the second sub-part.

15. The display panel according to claim 14, wherein, both the fourth sub-part and the fifth sub-part are electrically connected to the second power supply line and the fifth part.

16. The display panel according to claim 14, wherein, in the fourth conductive film layer, a second gap is included between the fourth sub-part and the fifth sub-part.

17. The display panel according to claim 14, wherein, the seventh part further includes a sixth sub-part, the sixth sub-part is located between the fourth sub-part and the fifth sub-part and is respectively connected to the fourth sub-part and the fifth sub-part.

18. The display panel according to claim 12, It is characterized in that, the second region includes a chamfered region, and the chamfered region is located at a position in the second region close to the first region; in the chamfered region, the second power line is electrically connected to the fifth part through the seventh part.

19. The display panel according to claim 5, It is characterized in that, the second region includes at least one barrier structure, and the barrier structure includes a first organic structure; in the second region, the edge of the second conductive block far from the display area is the first edge, and the edge of the at least one barrier structure farthest from the display area is the second edge; the first edge is located on the side of the second edge close to the display area.

20. The display panel according to claim 5, It is characterized in that, the second region includes a chamfered region; in the chamfered region, the first conductive block includes an eighth part, and the eighth part is located on the side of the fifth part close to the display area.

21. The display panel according to claim 20, It is characterized in that, the eighth part and the fifth part are located in the same conductive film layer.

22. A display device, It is characterized in that, it includes the display panel according to any one of claims 1-21.

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