Dual-trench shield gate field effect transistor and method of manufacturing the same

Abstract

The application relates to a double-groove shield gate field effect transistor and a preparation method thereof. The transistor comprises a first groove region, a second groove region and a main body region; the first groove region and the second groove region are arranged on the two sides of the main body region respectively; the first groove region comprises a metal gate, a first insulating layer and longitudinally arranged control gates and shield gates; the control gates and the shield gates are attached to the main body region through the first insulating layer; the main body region comprises a drain, a substrate region, a drift region, a base region, an N-type source region, a P-type source region and a source; the second groove region comprises a floating metal electrode and a symmetrical P-type region arranged in sequence from bottom to top, and a second insulating layer; the floating metal electrode and the symmetrical P-type region are attached to the main body region through the second insulating layer; and the doping type of the shield gate is P-type doping. The scheme provided by the application can effectively improve the breakdown voltage of the transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a dual-groove shielded gate field-effect transistor and its fabrication method. Background Technology

[0002] Shielded gate trench field-effect transistors (SGTs) offer advantages such as lower specific on-resistance, lower static and dynamic losses, and faster switching speeds. This is due to their ability to effectively isolate the coupling between the control gate and drain, resulting in significant advantages in channel density, charge compensation effect, and shielded gate structure.

[0003] In traditional SGTs, avalanche tolerance limits the maximum current of the transistor in inductive load applications. Because the substrate region is shorted to the N-type source region of the connecting channel via a heavily doped P-type source region, holes can be generated due to the avalanche effect when the transistor is under forward high voltage blocking or forward high voltage conduction. This hole current flows through the substrate region channel, forming a hole current that causes the parasitic transistor to turn on. Since transistor turn-on is a key cause of transistor avalanche failure, suppressing the turn-on of the parasitic transistor in SGTs to improve transistor avalanche tolerance is a pressing problem to be solved in SGT devices.

[0004] The related technology discloses a shielded gate trench field-effect transistor, which replaces the original side oxide structure with a dielectric layer with K values ​​distributed in a certain pattern. Combined with the modulation principle that the larger the K value, the stronger the modulation capability, but the smaller the corresponding longitudinal voltage drop, the electric field intensity inside the drift region is approximately uniformly distributed, thereby improving the breakdown voltage.

[0005] However, due to the complex structure of the dielectric layer with changing trends and the difficulty of processing, the time and production cost in transistor fabrication increase. Summary of the Invention

[0006] To overcome the problems existing in related technologies, this application provides a dual-groove shielded gate field-effect transistor and its fabrication method, which can effectively improve the breakdown voltage of the transistor.

[0007] The first aspect of this application provides a dual-trench shielded gate field-effect transistor, comprising: a first trench region, a second trench region, and a main body region; the first trench region and the second trench region are respectively disposed on both sides of the main body region;

[0008] The first trench region includes: a metal gate, a first insulating layer 7, and a vertically arranged control gate 6 and a shielding gate 5; the control gate 6 and the shielding gate 5 are separated from each other by the first insulating layer 7 and are attached to the main body region by the first insulating layer 7; with the direction from the shielding gate 5 to the control gate 6 as the upper direction, the metal gate is disposed above the control gate;

[0009] The main body region includes, from bottom to top, a drain 12, a substrate region 1, a drift region 2, a base region 3, an N-type source region 4, and a source 11; the main body region also includes a P-type source region 14; the P-type source region 14 is disposed between the second trench region and the main body region, attached to the lower part of the N-type source region 4, and connected to the source 11 and the base region 3 respectively;

[0010] The second trench region includes: a floating metal electrode 9 and a symmetrical P-type region 8 arranged sequentially from bottom to top, and a second insulating layer 10; the floating metal electrode 9 and the symmetrical P-type region 8 are attached to the main body region through the second insulating layer 10;

[0011] The shielding gate 5 is doped with P-type doping, which makes the first trench region and the second trench region form a double P-type trench.

[0012] In one embodiment, the main body area further includes: a trench corner compensation area 13;

[0013] The trench corner compensation area 13 is disposed between the second trench area and the main body area;

[0014] The trench corner compensation area is L-shaped and fits into the corner of the bottom of the second trench area.

[0015] In one embodiment, the source electrode 11 is divided into a horizontal portion and a vertical portion; the horizontal portion covers the N-type source region 4 and the second trench region, and the vertical portion extends into the second trench region and connects with the second insulating layer 10.

[0016] In one embodiment, the first trench region and the second trench region have the same depth, and the depth of the second trench region is greater than the sum of the thicknesses of the N-type source region 4, the substrate region 3, and the drift region 2.

[0017] In one embodiment, the trench corner compensation region 13 is doped with P-type doping and has a heavy doping concentration.

[0018] In one embodiment, the doping concentration of the shielding gate 5 and the symmetrical P-type region 8 is medium doping concentration.

[0019] A second aspect of this application provides a method for fabricating a dual-trench shielded gate field-effect transistor, used to fabricate the dual-trench shielded gate field-effect transistor as described in any of the preceding claims, comprising:

[0020] The substrate region is fabricated using semiconductor materials;

[0021] A drift region is epitaxially formed on the substrate region;

[0022] A matrix region is formed on the drift region by ion implantation or diffusion.

[0023] An N-type source region is formed by doping the substrate region.

[0024] A first groove and a second groove are respectively etched on both sides of the drift region;

[0025] Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to obtain a shielding gate, a control gate and a first insulating layer;

[0026] A metal gate is fabricated above the control gate to form a first trench region;

[0027] Semiconductor materials and oxides are deposited in the second trench to obtain a floating metal electrode, a symmetrical P-type region, a second insulating layer and a P-type source region, thus forming the second trench region.

[0028] A source electrode is fabricated above the N-type source region, and a drain electrode is fabricated at the bottom of the substrate region to form the host region.

[0029] In one embodiment, the deposition of semiconductor material and oxide within the second trench to obtain a floating metal electrode, a symmetrical P-type region, a second insulating layer, and a P-type source region, forming the second trench region, includes:

[0030] Semiconductor material is deposited at the bottom of the second trench to form a trench corner compensation region;

[0031] A floating metal electrode is fabricated above the trench corner compensation area;

[0032] A P-type semiconductor material, an oxide, and a heavily doped P-type semiconductor material are sequentially deposited above the floating metal electrode to form the second trench region and the P-type source region.

[0033] The technical solution provided in this application may include the following beneficial effects:

[0034] The dual-trench shielded gate field-effect transistor provided in this application has a first trench region and a second trench region on both sides of the transistor. The floating metal electrode and the symmetrical P-type region in the second trench region are combined with the P-type source region and the source to form a P-type channel transistor from the drain to the source. When the transistor is reverse conducting, it is used to conduct hole current, thereby suppressing the bipolar conduction of the body diode.

[0035] In addition, since the dual-groove shielded gate field-effect transistor provided in this application has a superjunction structure composed of double P-type trenches and N-type drift regions, it can obtain a relatively flat electric field distribution when the transistor is in forward blocking, thereby improving the breakdown voltage of the device.

[0036] Compared to the structure of a dielectric layer with a changing trend, the dual-groove shielded gate field-effect transistor of this application can be obtained by etching an additional trench and depositing the corresponding material, which simplifies the fabrication process.

[0037] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0038] The above and other objects, features and advantages of this application will become more apparent from the more detailed description of exemplary embodiments thereof in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments thereof.

[0039] Figure 1 This is a schematic diagram of the structure of a dual-groove shielded gate field-effect transistor shown in an embodiment of this application;

[0040] Figure 2 This is a schematic flowchart illustrating the fabrication method of a dual-groove shielded gate field-effect transistor according to an embodiment of this application;

[0041] Figure 3 This is another schematic flowchart illustrating the fabrication method of the dual-groove shielded gate field-effect transistor shown in the embodiments of this application. Detailed Implementation

[0042] Preferred embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0043] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0044] It should be understood that although the terms "first," "second," "third," etc., may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0045] Example 1

[0046] The complex structure of the dielectric layer with changing trends and the difficulty of processing it lead to increased time and production costs in transistor fabrication.

[0047] To address the aforementioned issues, this application provides a dual-groove shielded gate field-effect transistor, which can effectively improve the transistor's breakdown voltage and has a simple fabrication process.

[0048] The technical solutions of the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0049] Figure 1 This is a schematic diagram of the structure of a dual-groove shielded gate field-effect transistor as shown in an embodiment of this application.

[0050] See Figure 1 The dual-trench shielded gate field-effect transistor includes: a first trench region, a second trench region, and a main body region; the first trench region and the second trench region are respectively disposed on both sides of the main body region;

[0051] The first trench region includes: a metal gate, a first insulating layer 7, and a vertically arranged control gate 6 and a shielding gate 5; the control gate 6 and the shielding gate 5 are separated from each other by the first insulating layer 7 and are attached to the main body region by the first insulating layer 7; with the direction from the shielding gate 5 to the control gate 6 as the upper direction, the metal gate is disposed above the control gate;

[0052] The second trench region includes: a floating metal electrode 9 and a symmetrical P-type region 8 arranged sequentially from bottom to top, and a second insulating layer 10; the floating metal electrode 9 and the symmetrical P-type region 8 are attached to the main body region through the second insulating layer 10;

[0053] The main body region includes, from bottom to top, a drain 12, a substrate region 1, a drift region 2, a matrix region 3, an N-type source region 4, and a source 11;

[0054] The main body region further includes a P-type source region 14; the P-type source region 14 is disposed between the second trench region and the main body region, attached to the lower part of the N-type source region 4, and connected to the source electrode 11 and the substrate region 3 respectively.

[0055] The shielding gate 5 in the first trench region is doped with P-type doping, so that the first trench region and the second trench region are symmetrically distributed on both sides of the main body region and form a double P-type trench. The floating metal electrode 9 and the symmetrical P-type region 8 in the second trench region are combined with the P-type source region 14 and the source 11 to form a P-type channel transistor from the drain to the source. When the transistor is reverse conducting, it is used to conduct hole current, thereby suppressing the bipolar conduction of the body diode.

[0056] Furthermore, the source electrode 11 is divided into a horizontal portion and a vertical portion; the horizontal portion covers the N-type source region 4 and the second trench region, and the vertical portion extends into the second trench region and connects with the second insulating layer 10.

[0057] In this embodiment, the substrate region 1 is doped with N-type doping and has a heavy doping concentration; the drift region 2 is doped with N-type doping and has a light doping concentration; the substrate region 3 is doped with P-type doping and has a medium doping concentration; both the N-type source region 4 and the P-type source region 14 are heavily doped; the control gate 6 is doped with either P-type or N-type doping and has a heavy doping concentration; wherein the concentrations of light doping, medium doping, and heavy doping increase sequentially.

[0058] In this embodiment of the application, preferably, the light doping concentration ranges from 1×10⁻⁶. 15 cm -3 Up to 5×10 16 cm -3 The doping concentration ranges from 1×10⁻⁶. 17 cm -3 Up to 5×10 18 cm -3 The range of heavily doped concentration is 1×10. 19 cm -3 Up to 5×10 20 cm -3 .

[0059] The dual-trench shielded gate field-effect transistor provided in this application has a first trench region and a second trench region on both sides of the transistor to form a double P-type trench. The floating metal electrode and the symmetrical P-type region introduced in the second trench region are combined with the P-type source region and the source to form a P-type channel transistor from the drain to the source. When the transistor is reverse conducting, it is used to conduct hole current, thereby suppressing the bipolar conduction of the body diode.

[0060] In addition, since the dual-groove shielded gate field-effect transistor provided in this application has a superjunction structure composed of double P-type trenches and N-type drift regions, it can obtain a relatively flat electric field distribution when the transistor is in forward blocking, thereby improving the breakdown voltage of the device.

[0061] Compared to the structure of a dielectric layer with a changing trend, the dual-groove shielded gate field-effect transistor of this application can be obtained by etching an additional trench and depositing the corresponding material, which simplifies the fabrication process.

[0062] Example 2

[0063] Based on the dual-groove shielded gate field-effect transistor shown in Embodiment 1 above, this application embodiment introduces a trench corner compensation region at the corner of the second trench region. When the power device is in forward blocking mode, the electric field lines emitted by the ionized positive charges in the bottom region of the drift region are effectively transferred through the charge compensation effect of the trench corner compensation region, thereby effectively modulating the electric field and reducing the corresponding electric field peak distribution at the corner of the second trench region and the corner of the first trench region, thereby improving the breakdown voltage of the power device.

[0064] See Figure 1 The dual-trench shielded gate field-effect transistor shown in this application embodiment includes: a first trench region, a second trench region, and a main body region;

[0065] The first trench area and the second trench area are respectively located on both sides of the main body area;

[0066] The structure of the first trench region is consistent with that described in Embodiment 1, and will not be repeated here.

[0067] The second trench region includes: a floating metal electrode 9 and a symmetrical P-type region 8 arranged sequentially from bottom to top, and a second insulating layer 10; the floating metal electrode 9 and the symmetrical P-type region 8 are attached to the main body region through the second insulating layer 10;

[0068] The main body region includes, from bottom to top, a drain 12, a substrate region 1, a drift region 2, a matrix region 3, an N-type source region 4, and a source 11;

[0069] The main body area also includes: a trench corner compensation area 13; the trench corner compensation area 13 is disposed between the second trench area and the main body area; the trench corner compensation area 13 is "L" shaped and fits into the corner of the bottom of the second trench area, that is, the two right-angled sides of the trench corner compensation area 13 are respectively connected to the second insulating layer 10 and the floating metal electrode 9.

[0070] The trench corner compensation region 13 is P-type doped and has a heavy doping concentration.

[0071] In practical applications, the trench corner compensation area 13 can also be set at the corner of the bottom of the first trench area, or a trench corner compensation area can be set at the corner of the bottom of the first trench area and the second trench area. The above description of the trench area setting area is only an example in the embodiments of this application and should not be regarded as the only limitation of this application.

[0072] The main body region further includes a P-type source region 14; the P-type source region 14 is disposed between the second trench region and the main body region, attached to the lower part of the N-type source region 4, and connected to the source electrode 11 and the substrate region 3 respectively.

[0073] Furthermore, the source electrode 11 is divided into a horizontal portion and a vertical portion; the horizontal portion covers the N-type source region 4 and the second trench region, and the vertical portion extends into the second trench region and connects with the second insulating layer 10.

[0074] That is, the longitudinal section of the source electrode 11 is "L" shaped, the horizontal part is the horizontal part, which is located above the N-type source region and connected to the N-type source region; the vertical part is the vertical part, the bottom surface of the vertical part is connected to the second insulating layer, and the side surface of the vertical part is connected to the P-type source region and the N-type source region respectively.

[0075] Furthermore, the first trench region and the second trench region have the same depth, and the depth of the second trench region is greater than the sum of the thicknesses of the N-type source region, the substrate region, and the drift region.

[0076] In this embodiment of the dual-trench shielded gate field-effect transistor, after introducing a trench corner compensation region with a doping type opposite to that of the drift region, when the power device is in forward blocking mode, because the trench corner compensation region has a doping type opposite to that of the drift region, it can effectively transfer the electric field lines emitted by the ionized positive charges in the bottom region of the drift region, thereby effectively modulating the electric field. This results in a smaller electric field peak at the corner of the first trench region and the second trench region, which reduces the corresponding electric field peak at the corner of the shielded gate and the corner of the first insulating layer, thereby further improving the breakdown voltage of the power device based on Embodiment 1. When the power device is in avalanche mode, it can effectively guide the hole current to flow through the substrate region first, so that it can be collected by the source more quickly, thereby effectively suppressing the turn-on of the parasitic transistor.

[0077] Example 3

[0078] Corresponding to the dual-groove shielded gate field-effect transistor of the aforementioned embodiment 1, this application also provides a method for fabricating a dual-groove shielded gate field-effect transistor and corresponding embodiments.

[0079] Figure 2 This is a schematic flowchart illustrating the fabrication method of a dual-groove shielded gate field-effect transistor according to an embodiment of this application.

[0080] See Figure 2 The fabrication method of the dual-groove shielded gate field-effect transistor includes:

[0081] 201. Fabricating the substrate region using semiconductor materials;

[0082] In the embodiments of this application, a substrate region is prepared using an N-type heavily doped semiconductor material, wherein the semiconductor material is silicon or silicon carbide.

[0083] 202. A drift region is epitaxially formed on the substrate region;

[0084] Epitaxial growth refers to the process of forming a single-crystal film on a single-crystal substrate, whereby the single-crystal film grows by extending along the crystal structure of the substrate. In the embodiments of this application, different epitaxial processes can be used according to actual needs, including but not limited to: vapor phase epitaxy (VPE) or chemical vapor deposition (CVD).

[0085] It should be noted that the above epitaxial process can be selected according to the actual situation, and is not the only one here.

[0086] 203. Form the matrix region on the drift region by ion implantation or diffusion;

[0087] Ion implantation is a process of doping silicon materials. In practical applications, the power device is placed at one end of the ion implanter, and the dopant ion source is placed at the other end. At the dopant ion source, the dopant atoms are ionized, thus acquiring a certain charge. They are then accelerated to ultra-high speed by an electric field, penetrating the product surface and using their momentum to implant the dopant atoms into the power device, forming a doped region.

[0088] Diffusion is a process of incorporating pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine are usually used as ion sources, and pure impurity atoms are incorporated into the surface of silicon materials through intermittent diffusion or substitutional diffusion.

[0089] It should be noted that the embodiments of this application do not have strict limitations on the preparation method of the substrate region. In actual process, different processes described above can be selected to complete the preparation of the substrate region according to actual needs.

[0090] 204. Doping is performed on the substrate region to form an N-type source region;

[0091] In the embodiments of this application, an N-type source region is obtained by doping the substrate region with an N-type heavily doped semiconductor material.

[0092] 205. The first and second grooves are etched on both sides of the drift area, respectively;

[0093] In this embodiment, a first trench and a second trench are etched on both sides of the drift region by photolithography, and then the residual photoresist is removed by wet etching or dry etching to obtain the first trench and the second trench.

[0094] 206. Oxide, polysilicon, oxide and polysilicon are deposited sequentially in the first trench to obtain a shielding gate, a control gate and a first insulating layer;

[0095] In this embodiment, oxide, P-type doped polysilicon, oxide and P-type or N-type heavily doped polysilicon are sequentially deposited in the first trench to obtain a shielding gate, a control gate and a first insulating layer.

[0096] 207. Fabricate a metal gate above the control gate to form the first trench region;

[0097] In the embodiments of this application, step 207 can be executed after step 206, that is, after depositing oxide and polysilicon in the first trench to form a control gate, a metal gate is fabricated; in the actual fabrication process, step 207 can also be executed after step 208 or step 209.

[0098] 208. Deposit semiconductor material and oxide in the second trench to obtain a floating metal electrode, a symmetrical P-type region, a second insulating layer and a P-type source region, forming the second trench region;

[0099] In this embodiment of the application, there is no strict limitation on the execution sequence of steps 206 and 208. That is, after etching to obtain the first trench and the second trench, deposition can be performed in the order of the first trench to the second trench, or in the order of the second trench to the first trench, or both can be performed in parallel.

[0100] 209. Fabricate the source electrode above the N-type source region and the drain electrode at the bottom of the substrate region to form the host region.

[0101] The dual-trench shielded gate field-effect transistor prepared by the preparation method shown in the embodiments of this application has a first trench region and a second trench region on both sides to form a double P-type trench. By utilizing the floating metal electrode and symmetrical P-type region introduced in the second trench region, a P-type channel transistor from drain to source is formed by combining the P-type source region and the source. When the transistor is reverse conducting, it is used to conduct hole current, thereby suppressing the bipolar conduction of the body diode.

[0102] In addition, since the dual-groove shielded gate field-effect transistor provided in this application has a superjunction structure composed of double P-type trenches and N-type drift regions, it can obtain a relatively flat electric field distribution when the transistor is in forward blocking, thereby improving the breakdown voltage of the device.

[0103] Compared to the structure of dielectric layers with changing trends, the fabrication process of the dual-groove shielded gate field-effect transistor of this application can be obtained simply by etching an additional trench and depositing the corresponding material, which simplifies the fabrication process.

[0104] Example 4

[0105] Corresponding to the dual-groove shielded gate field-effect transistor of Embodiment 2 above, this application also provides a method for fabricating a dual-groove shielded gate field-effect transistor and corresponding embodiments.

[0106] See Figure 3 The fabrication method of the dual-groove shielded gate field-effect transistor includes:

[0107] 301. Fabricating the substrate region using semiconductor materials;

[0108] In this embodiment, step 301 is the same as step 201 in embodiment 3, and will not be repeated here.

[0109] 302. A drift region is epitaxially formed on the substrate region;

[0110] In this embodiment, step 302 is the same as step 202 in embodiment 3, and will not be repeated here.

[0111] 303. Forming a matrix region on the drift region by ion implantation or diffusion;

[0112] In this embodiment, step 303 is the same as step 203 in embodiment 3, and will not be repeated here.

[0113] 304. Doping is performed on the substrate region to form an N-type source region;

[0114] In this embodiment, step 304 is the same as step 204 in embodiment 3, and will not be repeated here.

[0115] 305. The first groove and the second groove are etched on both sides of the drift area, respectively;

[0116] In this embodiment, step 305 is the same as step 205 in embodiment 3, and will not be repeated here.

[0117] 306. Oxide, polysilicon, oxide and polysilicon are deposited sequentially in the first trench to obtain a shielding gate, a control gate and a first insulating layer;

[0118] In this embodiment, step 306 is the same as step 206 in embodiment 3, and will not be repeated here.

[0119] 307. Fabricate a metal gate above the control gate to form the first trench region;

[0120] In this embodiment, step 307 is the same as step 207 in embodiment 3, and will not be repeated here.

[0121] 308. Deposit semiconductor material at the bottom of the second trench to form a trench corner compensation region;

[0122] In this embodiment of the application, when etching the second trench region in step 305, an "L"-shaped trench can be further etched at the bottom of the trench near the main body region to deposit a P-type heavily doped trench corner compensation region, thereby obtaining the trench corner compensation region.

[0123] 309. A floating metal electrode is prepared above the trench corner compensation zone;

[0124] 310. P-type semiconductor material, oxide and heavily doped P-type semiconductor material are sequentially deposited above the floating metal electrode to form a second trench region and a P-type source region;

[0125] After depositing a P-type doped semiconductor material above the floating metal electrode to obtain a symmetrical P-type region, an oxide layer is deposited to form a second insulating layer. Then, a heavily doped P-type semiconductor material is deposited on the side of the second insulating layer near the drift region to obtain a P-type source region. Thus, a second trench region and a P-type source region are deposited in the second trench.

[0126] 311. Fabricate the source electrode above the N-type source region and the drain electrode at the bottom of the substrate region to form the host region.

[0127] The dual-groove shielded gate field-effect transistor obtained by the fabrication method shown in the embodiments of this application, after introducing a trench corner compensation region with a doping type opposite to that of the drift region, can effectively transfer the electric field lines emitted by the ionized positive charges in the bottom region of the drift region when the power device is in forward blocking mode, because the trench corner compensation region has a doping type opposite to that of the drift region. This effectively modulates the electric field, resulting in a smaller electric field peak at the corner of the first trench region and the second trench region, thereby reducing the corresponding electric field peak at the corner of the shielded gate and the corner of the first insulating layer. This further improves the breakdown voltage of the power device based on Embodiment 1. When the power device is in avalanche mode, it can effectively guide the hole current to flow through the substrate region first, so that it can be collected by the source more quickly, thereby effectively suppressing the turn-on of the parasitic transistor.

[0128] Regarding the apparatus in the above embodiments, the specific manner in which each module performs its operation has been described in detail in the embodiments related to the method, and will not be elaborated further here.

[0129] The solution of this application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have different emphases; parts not described in detail in a certain embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art should also understand that the actions and modules involved in the specification are not necessarily essential to this application. Furthermore, it is understood that the steps in the method of this application embodiment can be adjusted, combined, and deleted according to actual needs, and the modules in the device of this application embodiment can be combined, divided, and deleted according to actual needs.

[0130] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems and methods according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0131] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A dual-groove shielded gate field-effect transistor, characterized in that, include: The first trench area, the second trench area, and the main body area; The first trench area and the second trench area are respectively disposed on both sides of the main body area; The first trench region includes: a metal gate, a first insulating layer (7), and a vertically arranged control gate (6) and a shielding gate (5); the control gate (6) and the shielding gate (5) are separated from each other by the first insulating layer (7), and both the control gate (6) and the shielding gate (5) are attached to the main body region by the first insulating layer (7); with the direction from the shielding gate (5) to the control gate (6) as the upper direction, the metal gate is disposed above the control gate; The main body region includes, from bottom to top, a drain (12), a substrate region (1), a drift region (2), a matrix region (3), an N-type source region (4), and a source (11); the main body region also includes a P-type source region (14); the P-type source region (14) is disposed between the second trench region and the main body region, attached to the bottom of the N-type source region (4), and connected to the source (11) and the matrix region (3) respectively; the second trench region includes, from bottom to top, a floating metal electrode (9) and a symmetrical P-type region (8), and a second insulating layer (10); the sides of the floating metal electrode (9) and the symmetrical P-type region (8) are attached to the main body region through the second insulating layer (10), and the bottom surface of the floating metal electrode (9) is in direct contact with the main body region; The shielding gate (5) is doped with P-type doping, which makes the first trench region and the second trench region form a double P-type trench.

2. The dual-trench shielded gate field-effect transistor according to claim 1, characterized in that, The main area also includes: a trench corner compensation area (13); The trench corner compensation area (13) is located between the second trench area and the main body area; The trench corner compensation area is L-shaped and fits into the corner of the bottom of the second trench area.

3. The dual-trench shielded gate field-effect transistor according to claim 1 or 2, characterized in that, The source electrode (11) is divided into a horizontal part and a vertical part; the horizontal part covers the N-type source region (4) and the second trench region, and the vertical part extends into the second trench region and connects with the second insulating layer (10).

4. The dual-trench shielded gate field-effect transistor according to claim 1, characterized in that, The first trench region and the second trench region have the same depth, and the depth of the second trench region is greater than the sum of the thicknesses of the N-type source region (4), the substrate region (3), and the drift region (2).

5. The dual-trench shielded gate field-effect transistor according to claim 2, characterized in that, The trench corner compensation region (13) is P-type doped and has a heavy doping concentration.

6. The dual-trench shielded gate field-effect transistor according to claim 1, characterized in that, The doping concentration of the shielding gate (5) and the symmetrical P-type region (8) is medium doping concentration.

7. A method for fabricating a dual-groove shielded gate field-effect transistor, characterized in that, The method for fabricating a dual-trench shielded gate field-effect transistor as described in any one of claims 1-6 includes: The substrate region is fabricated using semiconductor materials; A drift region is epitaxially formed on the substrate region; A matrix region is formed on the drift region by ion implantation or diffusion. An N-type source region is formed by doping the substrate region. A first groove and a second groove are respectively etched on both sides of the drift region; Oxide, polysilicon, oxide and polysilicon are sequentially deposited in the first trench to obtain a shielding gate, a control gate and a first insulating layer; A metal gate is fabricated above the control gate to form a first trench region; A floating metal electrode, a symmetrical P-type region, and a second insulating layer are generated in the second trench to form the second trench region. A P-type source region is formed between the second trench region and the main body region. The P-type source region is attached to the lower part of the N-type source region and is in contact with the substrate region and the drift region. A source electrode is fabricated above the N-type source region, and a drain electrode is fabricated at the bottom of the substrate region to form the host region.

8. The method for fabricating a dual-trench shielded gate field-effect transistor according to claim 7, characterized in that, The process of generating a floating metal electrode, a symmetrical P-type region, and a second insulating layer within the second trench to form the second trench region includes: Semiconductor material is deposited at the bottom of the second trench to form a trench corner compensation region; A floating metal electrode is fabricated above the trench corner compensation area; A P-type semiconductor material and oxide are deposited above the floating metal electrode to generate a symmetrical P-type region and a second insulating layer, forming the second trench region.

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