Inverter parallel control method, system and device for suppressing no-load parallel circulating current

Abstract

The present invention discloses a parallel control method, system, and device for inverters that suppress no-load parallel circulating current. One inverter serves as the master, and the remaining inverters serve as slaves. A control board corresponding to each inverter is provided with a transmitter and a receiver, and the transmitter and receiver are connected to a common signal bus. The method includes: detecting the active power output by the master; comparing the active power output by the master with a set lower and upper thresholds, and outputting a level reversal signal from the transmitter; when the receiver on the control board corresponding to the slave detects that the input signal flips from a low level to a high level, the slave switches from a parallel operation mode to a PWM inhibit mode; if the input signal flips from a high level to a low level, the slave switches from a PWM inhibit mode to a parallel operation mode. While suppressing the increase in bus capacitor voltage, the system does not affect the service life of the AC output switch and improves the transient response capability to sudden changes in output load power.

Description

Technical Field

[0001] The present invention relates to the technical field of inverters, and in particular to an inverter parallel control method, system and device for suppressing no-load parallel circulating current. Background Art

[0002] With the increasing number of electrical devices, the demand for power supply system capacity and reliability is increasing. Single-inverter AC power supply systems are no longer sufficient, necessitating the use of inverter paralleling technology. In a parallel inverter system, circulating currents may exist between the inverters, affecting system stability. This is especially true when the inverters differ in parameters such as input voltage, filter and line impedance, and controller carrier signal. Parallel current imbalance and common-mode voltage issues become more prominent.

[0003] Currently, inverter parallel current sharing control methods include centralized control, master-slave control, and decentralized logic control. These control methods require communication between the parallel inverters, significantly increasing system complexity. When a fault occurs in one inverter, it is difficult to replace the faulty module. Therefore, these inverter parallel control systems lack high reliability and flexibility. To improve system redundancy and enable independent operation of parallel inverters, a key development trend in parallel control is interconnection-free paralleling technology, the most commonly used of which is voltage-frequency droop control. This control method draws on the self-synchronization principle and voltage droop characteristics of synchronous generators. Each inverter achieves synchronous operation and current sharing by adjusting the amplitude, frequency, and phase of the reference voltage.

[0004] In a parallel inverter system, there is a certain line impedance, which is generally resistive and cannot be ignored compared to the equivalent output impedance. The sum of the equivalent output impedance and the line impedance is called the equivalent system impedance. When the output impedance and output voltage amplitude of the parallel inverters are inconsistent, circulating power will flow between the parallel inverters. When the equivalent system impedance is purely inductive, the output active power of the parallel inverter unit n is proportional to the phase angle. The output reactive power is proportional to the output voltage amplitude E n There is a positive correlation between the two. Therefore, when the inverter output phases are inconsistent, the circulating power is all active power, and the power size is proportional to the phase difference; when the inverter output amplitudes are inconsistent, the circulating power is all reactive power, and the power size is proportional to the amplitude difference.

[0005] Therefore, in a parallel inverter system, inconsistent output amplitude or phase between inverter units can lead to unequal output power. No-load parallel operation is the most severe operating condition, as all circulating active and reactive currents flow between the inverters, severely harming the system. Especially when the inverter's upstream stage is an isolated DC / DC converter with a transformer, circulating active current energy will accumulate on the bus capacitor of one inverter, increasing the capacitor voltage, causing an inverter bus overvoltage shutdown, and even damaging the capacitors or power components. While regulating circulating active and reactive currents can be achieved by independently adjusting the inverter output voltage amplitude or phase, a major technical difficulty in droop control is accurately detecting the inverter's output active and reactive power. When the inverter is operating at no load, its output active and reactive power is low, resulting in poor power detection accuracy and poor voltage amplitude and frequency droop control accuracy. Consequently, circulating active current between inverters cannot be completely eliminated.

[0006] To address the above problem, the traditional solution is to cut off the active circulating current loop through the output switch of the inverter unit to prevent the bus capacitor voltage from rising. The specific implementation method is as follows: the parallel inverter units are numbered 1, 2, ..., n; each inverter unit detects the active power output by itself; when the active power detection value is less than the set lower limit threshold, inverter units 2 to n disconnect the output switch and exit the parallel system, leaving only inverter unit 1 to supply power to the load; when the active power detection value is greater than the set upper limit threshold, inverter units 2 to n close the output switch, enter the parallel system and resume power supply to the load.

[0007] The invention patent with publication number CN102570884B proposes a circulating current control method, device and inverter parallel system of an inverter parallel system, which mainly includes the following steps: obtaining the voltage increase of the positive bus or negative bus of the inverter in the inverter parallel system due to the circulating current of the parallel system; obtaining a first circulating current that causes the voltage increase of the positive bus or negative bus based on the voltage increase; obtaining a second circulating current by sampling the circulating current in the system; and controlling the circulating current in the system by using these two circulating currents.

[0008] The invention patent application with publication number CN108712100A proposes a power injection method to prevent the DC voltage of inverters from being pumped up in parallel when no-loaded. The method mainly includes the following steps: sampling the capacitor voltage and current of the first and second inverters in the inverter parallel system, as well as the circulating current and bus capacitor voltage in the system; the controller analyzes the bus capacitor voltages of the two inverters to determine the inverter where the bus capacitor voltage pumping occurs, and assumes that the inverter is the second inverter and the other inverter is the first inverter; the controller controls the output voltage phase of the second inverter based on the sampled capacitor voltage Vo, circulating current Io and bus capacitor voltage increase of the second inverter, so that the excess energy stored in the bus capacitor of the second inverter is released, thereby suppressing the DC bus capacitor voltage within a normal range.

[0009] Regarding the busbar overvoltage problem caused by the active circulating current of the inverters in parallel operation at no load as described above, there are two disadvantages in cutting off the circulating current loop by the output switch of the inverter unit: (1) the inverter output switch will frequently operate as the load power changes, thereby reducing the service life of the output switch; (2) when the output load power of the inverter parallel system undergoes a step jump, especially when the rated load power is suddenly connected at no load, the inverter output voltage will drop significantly due to the slow response time of the inverter output switch action, which will seriously affect the stability of the load equipment operation.

[0010] The inverter parallel system circulating current control method described in invention patent CN102570884B uses the circulating current in the system as the feedback quantity of the inverter current inner loop, which affects the system's dynamic response performance to output load changes and has poor stability.

[0011] The power injection method described in invention patent CN108712100A controls the bus capacitor voltage by introducing the bus voltage increase into the generation of the inverter reference voltage. Since the active circulating current power is small when no-load, when the bus capacitor capacity is large, the bus voltage time constant is large and rises slowly. The parameters of the bus voltage pump control proportional regulator will be difficult to adjust. If the parameter setting is large, it is easy to cause oscillation of the inverter output voltage amplitude or frequency; if the parameter setting is small, the rise of the bus capacitor voltage cannot be effectively suppressed. Summary of the Invention

[0012] The technical problem to be solved by the present invention is to effectively suppress the increase in the no-load parallel circulating current and bus capacitor voltage of the inverter, improve the transient response capability of the inverter parallel system to sudden changes in output load power, and do not affect the service life of the AC output switch.

[0013] The present invention solves the above technical problems through the following technical means:

[0014] In one aspect, the present invention provides an inverter parallel control method for suppressing no-load parallel circulating current of multiple inverters, wherein one inverter serves as a master and the remaining inverters serve as slaves. A control board corresponding to each inverter is provided with a first transmitter and a first receiver, and the first transmitter and the first receiver are connected to a common signal bus. The method comprises:

[0015] Real-time detection of the active power output by the host;

[0016] When the active power output by the host is less than the set lower limit threshold, the output level signal of the sending end on the control board corresponding to the host is flipped from a low level to a high level; when the active power output by the host is greater than the set upper limit threshold, the output level signal of the sending end on the control board corresponding to the host is flipped from a high level to a low level;

[0017] When the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a low level to a high level, the slave switches from the parallel operation mode to the PWM prohibition mode. When the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a high level to a low level, the slave switches from the PWM prohibition mode to the parallel operation mode.

[0018] The inverter parallel control method proposed in the present invention, on the one hand, detects the active power output by the host in real time. When the active power is less than a set lower threshold, the control board's transmitter outputs a level signal reversal signal, notifying the slave to shut down the PWM output of the power tube to cut off the active circulating current loop while keeping the AC output switch closed. Compared with traditional solutions and other background technologies, this control strategy does not require additional circulating current and DC bus voltage control strategies to achieve the control goal of suppressing the increase in bus capacitor voltage, while not affecting the service life of the AC output switch. On the other hand, when the active power of the host is greater than a set upper threshold, the control board's transmitter outputs a level signal reversal signal, notifying the slave to immediately switch from PWM prohibition mode to parallel operation mode, so that the slave can immediately resume parallel operation when the output load power increases, thereby improving the transient response capability of the inverter parallel system to sudden changes in output load power.

[0019] Furthermore, each inverter communicates with each other via a CAN communication bus, and the method further includes:

[0020] Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters;

[0021] Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves;

[0022] Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal;

[0023] The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

[0024] Furthermore, a control board corresponding to each inverter is provided with a second transmitting end and a second receiving end, the second transmitting end outputs a fixed level signal, and the second receiving end receives a level signal output by a control board of an adjacent inverter, and the method further includes:

[0025] The receiving end 2 on the corresponding control board of the slave device detects in real time whether the adjacent inverter control board outputs a level reversal signal, wherein the level reversal signal includes a low level reversal to a high level and a high level reversal to a low level;

[0026] If a level flip signal is detected, the slave device is switched to the master device;

[0027] If the level inversion signal is not detected, switching between the PWM disable mode and the parallel operation mode is performed according to the level inversion signal from the common signal bus.

[0028] Furthermore, the method further comprises:

[0029] Determining whether the host fails;

[0030] If so, the host is controlled to stop, the AC output switch connected to the host is disconnected and the parallel operation is exited, and the sending terminal 2 on the control board corresponding to the host outputs the level reversal signal;

[0031] If not, the host corresponds to the control board and the sending terminal 1 outputs the level reversal signal.

[0032] Furthermore, the slave device switches from the parallel operation mode to the PWM disable mode, comprising:

[0033] Each of the slave machines turns off the PWM drive of the power tube and exits the parallel operation, and the AC output switch corresponding to each of the slave machines remains in a closed state.

[0034] Each slave latches the output frequency f according to the voltage frequency droop controller i Calculate the current reference voltage phase angle θ i ;

[0035] Each of the slave devices uses the current reference voltage phase angle θ i As the initial phase, the frequency and phase angle information of the AC side common bus voltage are detected by a software phase-locked loop (SPLL).

[0036] Furthermore, the slave device switches from the PWM disable mode to the parallel operation mode, comprising:

[0037] Each slave latches the current output phase angle of the software phase-locked loop SPLL as the initial phase angle of the reference voltage signal Real-time phase angle of the reference voltage signal f i is the frequency output by the voltage-frequency droop controller, Δt is the amplitude and control period of the frequency droop controller;

[0038] Each of the slave machines clears the integral output of the voltage outer loop PI regulator;

[0039] Each slave enables the PWM drive of the power tube and starts in voltage mode, and adjusts the amplitude E of the reference voltage signal through the voltage amplitude droop controller and the voltage frequency droop controller respectively. i and phase angle θ i , resume parallel operation;

[0040] The characteristic equation of the voltage droop controller is:

[0041] E i =E * -n i P

[0042] The characteristic equation of the voltage-frequency droop controller is:

[0043] 2πf i =2πf * +m i Q

[0044] Where, E * and f * is the rated output AC voltage amplitude and frequency, m i 、n i is the droop coefficient, P represents active power, and Q represents reactive power.

[0045] Furthermore, the calculation formula of the active power output by the host is:

[0046]

[0047] Among them, U d 、U q is the active and reactive components of the AC output voltage, I d , I q are the active and reactive components of the load current;

[0048] The calculation formula for the active and reactive components of the AC output voltage is:

[0049]

[0050] The calculation formula for the active and reactive components of the load current is:

[0051]

[0052] Among them, u α 、u β is the two-phase quadrature signal of the AC output voltage, i α 、i β is the two-phase quadrature signal of the load current, θ i The frequency f output by the voltage-frequency droop controller i Calculate the reference voltage phase angle.

[0053] In addition, the present invention also proposes an inverter parallel control system for suppressing no-load parallel circulating current, which is used to suppress the no-load parallel circulating current of multiple inverters, wherein one of the inverters serves as a master and the remaining inverters serve as slaves. The control board corresponding to each inverter is provided with a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus. The system includes:

[0054] An active power detection module, used for detecting the active power output by the host in real time;

[0055] a level reversal signal generating module, configured to reverse an output level signal of a transmitting end on a control board corresponding to the host from a low level to a high level when the active power output by the host is less than a set lower threshold; and reverse an output level signal of a transmitting end on a control board corresponding to the host from a high level to a low level when the active power output by the host is greater than a set upper threshold;

[0056] The slave mode switching module is used to control the slave to switch from the parallel operation mode to the PWM prohibition mode when the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a low level to a high level; and to control the slave to switch from the PWM prohibition mode to the parallel operation mode when the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a high level to a low level.

[0057] Furthermore, the system further includes a master-slave determination module configured to perform the following steps:

[0058] Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters;

[0059] Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves;

[0060] Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal;

[0061] The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

[0062] In addition, the present invention also proposes an inverter parallel control device, which includes a voltage amplitude droop controller, a voltage frequency droop controller, a controller, and a digital signal processor connected to each inverter. The output end of each inverter is connected to the same AC side common bus through an AC output switch. The control board corresponding to each inverter is provided with a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus.

[0063] The voltage amplitude droop controller, the voltage frequency droop controller and the output of the digital signal processor are all connected to the power operation module, and the power operation module and the master-slave determination module are both connected to the controller;

[0064] The controller is used to implement the inverter parallel control method for suppressing no-load parallel circulating current as described above.

[0065] The advantages of the present invention are:

[0066] (1) The inverter parallel control method proposed in the present invention, on the one hand, detects the active power output by the host in real time. When the active power is less than the set lower limit threshold, the level signal output by the control board sending end is reversed, notifying the slave to turn off the PWM output of the power tube to cut off the active circulating current loop while keeping the AC output switch closed. Compared with traditional solutions and other background technologies, this control strategy does not require additional circulating current and DC bus voltage control strategies to achieve the control goal of suppressing the increase in bus capacitor voltage, while not affecting the service life of the AC output switch. On the other hand, when the active power of the host is greater than the set upper limit threshold, the level signal output by the control board sending end is reversed, notifying the slave to immediately switch from PWM prohibition mode to parallel operation mode, so that the slave can immediately resume parallel operation when the output load power increases, thereby improving the transient response capability of the inverter parallel system to sudden changes in output load power.

[0067] (2) In the present invention, each inverter running in parallel sends operating status information containing its own number n through the CAN communication bus, and receives and identifies the numbers of other inverters in the parallel system, and then compares them with their own numbers. The inverter with the smallest number serves as the master, and the first group of signal ports on the control board corresponding to the master works in the signal sending mode. The other inverters serve as slaves, and the first group of signal ports on the control board corresponding to the slaves work in the signal receiving mode, thereby realizing the master-slave setting without manual intervention.

[0068] (3) In the present invention, when a host fails, the adjacent inverter slave is immediately notified by flipping the output level signal of the second sending terminal on the control board, so that it automatically switches to the host. At the same time, the sending terminal 1 on the control board corresponding to the new host switches from the signal receiving mode to the signal sending mode, so that the no-load parallel circulation suppression strategy is not affected by the host failure, effectively improving the operation reliability of the system.

[0069] (4) The method for smoothly switching the slave between the PWM disable mode and the parallel operation mode proposed in the present invention effectively suppresses the inverter output current overshoot and output voltage fluctuation, and improves the transient response capability of the inverter parallel system to sudden changes in output load power.

[0070] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] Figure 1 This is a flow chart of a method for controlling inverter parallel connection to suppress no-load parallel circulation current according to the present invention;

[0072] Figure 2 This is a control flow chart of the inverter operation mode switching from the parallel operation mode to the PWM disable mode in the present invention;

[0073] Figure 3 This is a control flow chart of the inverter operation mode switching from PWM disable mode to parallel operation mode in the present invention;

[0074] Figure 4 This is an overall flow chart of an inverter parallel control method for suppressing no-load parallel circulating current according to the present invention;

[0075] Figure 5 It is a detailed flow chart of part B in the figure of the present invention;

[0076] Figure 6 This is a schematic diagram of the hardware circuit structure of multiple inverters connected in parallel in the present invention;

[0077] Figure 7This is a control block diagram of a single-phase full-bridge inverter parallel system based on voltage amplitude and frequency droop control in the present invention;

[0078] Figure 8 The present invention is a structural diagram of an inverter parallel control system for suppressing no-load parallel circulating current. DETAILED DESCRIPTION

[0079] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0080] The embodiment of the present invention proposes a method for controlling inverter parallel connection to suppress no-load parallel connection circulating current, which is used to suppress no-load parallel connection circulating current of multiple inverters connected in parallel. Figure 6 As shown, the output ends of multiple inverters are respectively connected to the same AC side common bus through AC output switches, one of the inverters serves as a master, and the remaining inverters serve as slaves. The control board corresponding to each inverter is provided with a first group of signal ports, and the first group of signal ports includes a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus.

[0081] like Figure 1 As shown, the above-mentioned inverter parallel control method for suppressing no-load parallel circulating current includes the following steps:

[0082] S10, detecting the active power output by the host in real time;

[0083] S20, when the active power output by the host is less than the set lower limit threshold, the output level signal of the transmitting end on the control board corresponding to the host is flipped from a low level to a high level; when the active power output by the host is greater than the set upper limit threshold, the output level signal of the transmitting end on the control board corresponding to the host is flipped from a high level to a low level;

[0084] S30. When the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a low level to a high level, the slave switches from the parallel operation mode to the PWM disable mode. When the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a high level to a low level, the slave switches from the PWM disable mode to the parallel operation mode.

[0085] It should be noted that the lower threshold is set based on the rated power P of each inverter. edThe total number of inverters running in parallel in the system is set to: P ed / (2·N). The upper threshold is set based on the rated power P of each inverter. ed , set to: P ed / 2.

[0086] This embodiment proposes a no-load parallel circulating current suppression control strategy for suppressing bus capacitor voltage increases in an inverter parallel control system. When the active power is less than a set lower threshold, the level signal outputted by the control board's transmitter is flipped, notifying the slave to switch to PWM disable mode. While maintaining the AC output switch closed, the PWM output of the power transistor is turned off to disconnect the active circulating current loop. No additional circulating current and DC bus voltage control strategies are required, and the AC output switch is not activated. Disconnecting the active circulating current loop by turning off the PWM output of the inverter unit power transistor eliminates the need for additional control strategies, and the AC output switch is not activated. This achieves the control goal of suppressing bus capacitor voltage increases while maintaining the service life of the AC output switch.

[0087] On the other hand, when the active power of the master is greater than the set upper limit threshold, the level signal output by the control board's sending end is flipped, notifying the slave to immediately switch from PWM prohibition mode to parallel operation mode, so that the slave can immediately resume parallel operation when the output load power increases, effectively suppressing inverter output current overshoot and output voltage fluctuations, and improving the transient response capability of the inverter parallel system to sudden changes in output load power.

[0088] In one embodiment, the inverters communicate with each other via a CAN communication bus, and the method further comprises the following steps:

[0089] Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters;

[0090] Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves;

[0091] Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal;

[0092] The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

[0093] It should be noted that in this embodiment, each inverter running in parallel sends operating status information containing its own number n through the CAN communication bus, receives and identifies the numbers of other inverters in the parallel system, and then compares it with its own number, where n = 0, 1, ..., N, where N is the total number of inverters running in parallel in the system. The inverter with the smallest number is used as the master, and the first group of signal ports on its control board operates in signal sending mode: the sending end outputs a fixed level signal (high level or low level) to the common signal bus, and the receiving end does not receive the signal. The other inverters are used as slaves, and the first group of signal ports on their control boards operates in signal receiving mode: the sending end does not send a signal, and the receiving end receives a level signal from the common signal bus. This achieves the master-slave setting without manual intervention.

[0094] In one embodiment, the control board corresponding to each inverter is further provided with a second group of signal ports, the second group of signal ports including a second transmitting end and a second receiving end, the second transmitting end outputting a fixed level signal (high level or low level), and the second receiving end receiving a level signal output by a control board of an adjacent inverter, and the method further comprises the following steps:

[0095] Determining whether the host fails;

[0096] If so, the host is controlled to stop, the AC output switch connected to the host is disconnected and the parallel operation is exited, and the sending terminal 2 on the control board corresponding to the host outputs the level reversal signal;

[0097] If not, the host corresponds to the control board and the sending terminal 1 outputs the level reversal signal.

[0098] In one embodiment, the method further comprises the following steps:

[0099] The receiving end 2 on the corresponding control board of the slave device detects in real time whether the adjacent inverter control board outputs a level reversal signal, wherein the level reversal signal includes a low level reversal to a high level and a high level reversal to a low level;

[0100] If a level flip signal is detected, the slave device is switched to the master device;

[0101] If the level inversion signal is not detected, switching between the PWM disable mode and the parallel operation mode is performed according to the level inversion signal from the common signal bus.

[0102] In this embodiment, a method for automatic switching between a master and a slave in an inverter parallel control system is proposed. In the event of a master failure, the adjacent slave inverter is immediately notified by flipping the level signal of the second transmitting terminal of the control board, causing it to automatically switch to the master. At the same time, the first group of signal ports on the control board corresponding to the new master is switched from a signal receiving mode to a signal sending mode, so that the above-mentioned no-load parallel circulating current suppression strategy is not affected by the master failure, thereby effectively improving the operating reliability of the system.

[0103] In one embodiment, if Figure 2 As shown, in step S30, the slave switches from the parallel operation mode to the PWM disable mode, including the following steps:

[0104] Each of the slave machines turns off the PWM drive of the power tube and exits parallel operation, and the AC output switch corresponding to each of the slave machines remains in a closed state;

[0105] Each slave latches the output frequency f according to the voltage frequency droop controller i Calculate the current reference voltage phase angle θ i ;

[0106] Each of the slave devices uses the current reference voltage phase angle θ i As the initial phase, the frequency and phase angle information of the AC side common bus voltage are detected by a software phase-locked loop (SPLL).

[0107] In one embodiment, if Figure 3 As shown, in step S30, the slave device switches from the PWM prohibition mode to the parallel operation mode, including the following steps:

[0108] Each slave latches the current output phase angle of the software phase-locked loop SPLL as the initial phase angle of the reference voltage signal Real-time phase angle of the reference voltage signal f i is the frequency output by the voltage-frequency droop controller, Δt is the amplitude and control period of the frequency droop controller;

[0109] Each of the slave machines clears the integral output of the voltage outer loop PI regulator to zero, thereby avoiding current shock caused by integral output saturation during PWM disable mode;

[0110] Each slave enables the PWM drive of the power tube and starts in voltage mode, and adjusts the amplitude E of the reference voltage signal through the voltage amplitude droop controller and the voltage frequency droop controller respectively. i and phase angle θ i , resume parallel operation;

[0111] The characteristic equation of the voltage droop controller is:

[0112] E i =E * -n i P

[0113] The characteristic equation of the voltage-frequency droop controller is:

[0114] 2πf i =2πf * +m i Q

[0115] Where, E * and f * is the rated output AC voltage amplitude and frequency, P represents active power, Q represents reactive power, m i 、n i is the droop coefficient, usually m i =Δf / P max , n i =ΔE / Q max , where P max is the maximum active power output by the inverter, Q max is the maximum reactive power, Δf and ΔE are the maximum allowable deviations of the inverter output frequency and amplitude compared with the rated values.

[0116] In this embodiment, a method for smoothly switching the inverter serving as a slave between the parallel operation mode and the PWM disable mode effectively suppresses inverter output current overshoot and output voltage fluctuation, thereby improving the transient response capability of the inverter parallel system to sudden changes in output load power and the operational reliability of the system.

[0117] Specifically, the control block diagram of the single-phase full-bridge inverter parallel system based on voltage amplitude and frequency droop control is as follows: Figure 7 As shown, each inverter in the parallel system works in voltage control mode ( Figure 7 Only two inverters are shown in the figure). After specifying a reasonable droop coefficient, the reference voltage amplitude E output by the amplitude and frequency droop controller is i and frequency f i , calculate and synthesize the final reference sinusoidal voltage signal U refi :

[0118]

[0119] Where θ i The output frequency f of the voltage frequency droop controller is i Calculate the reference voltage phase angle, is the initial phase angle of the reference voltage, and Δt is the control period of the amplitude and frequency droop controller.

[0120] Each inverter converts the reference voltage signal U refiWith output voltage U oi The instantaneous feedback value is compared and the generated error signal is passed through the voltage loop controller G v The obtained control quantity is used as the current loop given I refi , I refi and the inductor current I Li The instantaneous feedback value is subtracted and passed through the current loop controller G i Modulation, the output modulation signal and the output voltage feedforward signal U oi The duty cycle signal of the PWM pulse is obtained by superimposing and then intersecting with the triangular carrier signal.

[0121] Among them, the voltage loop controller G v Using proportional integral PI regulator, current loop controller G i Use proportional P regulator.

[0122] In one embodiment, in step S10, the output voltage and current of the inverter are detected in each control cycle, and then the output active power and reactive power are calculated by sampling. The calculation formula of the active power is:

[0123]

[0124] Among them, U d 、U q is the active and reactive components of the AC output voltage, I d , I q are the active and reactive components of the load current;

[0125] The calculation formula for the active and reactive components of the AC output voltage is:

[0126]

[0127] The calculation formula for the active and reactive components of the load current is:

[0128]

[0129] Among them, u α 、u β In the current control cycle, the second-order generalized integrator (SOGI) is used to generate the two-phase quadrature signals of the AC output voltage in the stationary αβ coordinate system, i α 、i β To generate the two-phase quadrature signals of the load current in the stationary αβ coordinate system through the second-order generalized integrator (SOGI) in the current control cycle, θ i The frequency f output by the voltage-frequency droop controller i Calculate the reference voltage phase angle.

[0130] like Figures 4 and 5As shown in FIG, the overall process of the no-load parallel circulating current suppression control strategy for suppressing the increase of bus capacitor voltage in the inverter parallel control system is as follows:

[0131] Step 1): In the inverter parallel control system, each inverter samples the AC output voltage and load current in each control cycle through a digital signal processor DSP, and reads the AD values.

[0132] Step 2): In the inverter parallel control system, each inverter starts in voltage mode and closes its own AC output switch, and adjusts the amplitude E of the reference sinusoidal voltage signal through the voltage amplitude droop controller. i The phase angle θ of the reference sinusoidal voltage signal is adjusted by the voltage frequency droop controller i , to achieve parallel operation.

[0133] Step 3): In the inverter parallel control system, each inverter generates a two-phase orthogonal signal u of the AC output voltage in the stationary αβ coordinate system through a second-order generalized integrator (SOGI) in the current control cycle according to the AC output voltage and load current detected in step 1). α 、u β , and the two-phase quadrature signal of the load current i α 、i β .

[0134] Step 4): In the inverter parallel control system, each inverter generates the AC output voltage two-phase orthogonal signal u according to the AC output voltage two-phase orthogonal signal u obtained in step 3). α 、u β , load current two-phase quadrature signal i α 、i β , and in step 2) the frequency droop controller outputs the frequency f i Calculated reference voltage phase angle θ i , the Park transformation module is used to calculate the AC output voltage active and reactive components U in the rotating dq coordinate system d 、U q , and the active and reactive components of the load current Ii d , I q .

[0135] The calculation formula for the active and reactive components of the AC output voltage is:

[0136]

[0137] The calculation formula for the active and reactive components of the load current is:

[0138]

[0139] Step 5): In the inverter parallel control system, each inverter generates the AC output voltage active and reactive components U according to the AC output voltage active and reactive components U obtained in step 4). d 、U q , and the active and reactive components of the load current I d , I q , calculate the output active and reactive power P, Q:

[0140]

[0141] Step 6): Each inverter running in parallel in the inverter parallel control system sends operating status information including its own number n through the CAN communication bus, receives and identifies the numbers of other inverters in the parallel system, and then compares it with its own number, where n = 0, 1, ..., N, and N is the total number of inverters running in parallel in the system.

[0142] The inverter with the smallest number is the master, and the first group of signal ports on its control board works in signal sending mode: the sending end outputs a fixed level signal (high level or low level) to the public signal bus, the receiving end does not receive the signal, and then jumps to step 8).

[0143] The other inverters act as slaves, and the first group of signal ports on their control boards operate in signal receiving mode: the sending end does not send any signal, and the receiving end receives a level signal from the public signal bus, and then proceeds to step 7).

[0144] Step 7): Each inverter acting as a slave in the inverter parallel control system detects in real time whether the level signal of the adjacent inverter control board has flipped through the receiving end 2 of the second group of signal ports of the control board. If a level flip signal is detected, the role of the inverter in the system switches from slave to master, and the first group of signal ports of its control board switches from signal receiving mode to signal sending mode: the sending end 1 outputs a fixed level signal (high level or low level) to the common signal bus, and the receiving end 1 does not receive the signal, and then continues with step 8); if the level flip signal is not detected, jump to step 10).

[0145] Step 8): The inverter serving as the host in the inverter parallel control system determines in real time whether it has a fault. If a fault occurs, the inverter shuts down, disconnects the AC output switch and exits parallel operation, and the level signal outputted by the second transmitting end of the second group of signal ports on its control board is flipped; if no fault occurs, proceed to step 9).

[0146] Step 9): The inverter as the host in the inverter parallel control system, according to the output active power P calculated in step 5), and the set active power judgment lower limit threshold P low_limit For comparison, when P <Plow_limit When the output level signal of the sending end of the first group of signal ports of the inverter host control board is flipped from low level to high level, then the process jumps to step 11).

[0147] Step 10): Each slave inverter in the inverter parallel control system detects the high and low level status of its input signal in real time via a receiving end of the first signal port group of the control board. If the input signal is detected to flip from a low level to a high level, each slave inverter switches from parallel operation mode to PWM disable mode, and then jumps to step 12).

[0148] Step 11): The inverter serving as the host in the inverter parallel control system determines the active power P calculated in step 5) and the set upper limit threshold value P of active power. high_limit Compare, when P>P high_limit When , the output signal of the sending end of the first group of signal ports of the inverter host control board is flipped from high level to low level.

[0149] Step 12): Each slave inverter in the inverter parallel control system detects the high and low level status of its input signal in real time via a receiving end of the first group of signal ports on the control board. If the input signal is detected to flip from a high level to a low level, each slave inverter switches from a PWM disable mode to a parallel operation mode.

[0150] In addition, if Figure 8 As shown, an embodiment of the present invention further proposes an inverter parallel control system for suppressing no-load parallel circulating current, which is used to suppress no-load parallel circulating current of multiple inverters, wherein one inverter serves as a master and the remaining inverters serve as slaves. A control board corresponding to each inverter is provided with a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus. The system includes:

[0151] Active power detection module 10, used for real-time detection of the active power output by the host;

[0152] The level reversal signal generating module 20 is configured to reverse the output level signal of the transmitting end on the control board corresponding to the host from a low level to a high level when the active power output by the host is less than a set lower limit threshold; and reverse the output level signal of the transmitting end on the control board corresponding to the host from a high level to a low level when the active power output by the host is greater than a set upper limit threshold;

[0153] The slave mode switching module 30 is used to control the slave to switch from the parallel operation mode to the PWM prohibition mode when the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a low level to a high level; and to control the slave to switch from the PWM prohibition mode to the parallel operation mode when the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a high level to a low level.

[0154] Compared with the traditional solution, the parallel control system in this embodiment does not require additional circulating current and DC bus voltage control strategies, and does not perform AC output switch operation. The active circulating current loop is cut off by turning off the PWM output of the inverter unit power tube. While achieving the control goal of suppressing the increase in bus capacitor voltage, the service life of the AC output switch is not affected. By controlling the inverter slave machine to smoothly switch between the PWM disable mode and the parallel operation mode, the inverter output current overshoot and output voltage fluctuation are effectively suppressed, thereby improving the transient response capability of the inverter parallel system to sudden changes in output load power.

[0155] In one embodiment, the system further includes a master-slave determination module, which implements master-slave setting without manual intervention and is configured to perform the following steps:

[0156] Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters;

[0157] Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves;

[0158] Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal;

[0159] The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

[0160] In one embodiment, the control board corresponding to each inverter is further provided with a second group of signal ports, the second group of signal ports including a second transmitting end and a second receiving end, the second transmitting end outputting a fixed level signal (high level or low level), and the second receiving end receiving a level signal output by a control board of an adjacent inverter, and the system further includes:

[0161] A fault judgment module, used to judge whether the host has a fault;

[0162] a fault determination module, configured to, when the fault judgment module outputs a yes result, control the host to shut down, disconnect the AC output switch connected to the host, and exit parallel operation, and output the level reversal signal from the second transmitting terminal on the control board corresponding to the host;

[0163] And when the fault judgment module outputs a result of no, the host corresponds to the sending end on the control board and outputs the level reversal signal.

[0164] In one embodiment, the system further includes a master-slave switching module configured to perform the following steps:

[0165] The receiving end 2 on the corresponding control board of the slave device detects in real time whether the adjacent inverter control board outputs a level reversal signal, wherein the level reversal signal includes a low level reversal to a high level and a high level reversal to a low level;

[0166] If a level flip signal is detected, the slave device is switched to the master device;

[0167] If the level inversion signal is not detected, switching between the PWM disable mode and the parallel operation mode is performed according to the level inversion signal from the common signal bus.

[0168] In this embodiment, in the event of a failure of the host, the adjacent inverter slave is immediately notified by flipping the level signal of the second sending terminal of the control board, so that it automatically switches to the master. At the same time, the first group of signal ports on the control board corresponding to the new host is switched from signal receiving mode to signal sending mode, so that the above-mentioned no-load parallel circulation suppression strategy is not affected by the host failure, effectively improving the operation reliability of the system.

[0169] In one embodiment, the slave mode switching module 30 includes a first switching unit and a second switching unit, wherein:

[0170] The first switching unit is used to control the slave machine to switch from the parallel operation mode to the PWM disable mode, including the following steps:

[0171] Each of the slave machines turns off the PWM drive of the power tube and exits the parallel operation, and the AC output switch corresponding to each of the slave machines remains in a closed state.

[0172] Each slave latches the output frequency f according to the voltage frequency droop controller i Calculate the current reference voltage phase angle θ i ;

[0173] Each of the slave devices uses the current reference voltage phase angle θ i As the initial phase, the frequency and phase angle information of the AC side common bus voltage are detected through a software phase-locked loop (SPLL).

[0174] The second switching unit is used to control the slave to switch from the PWM prohibition mode to the parallel operation mode, including the following steps:

[0175] Each slave latches the current output phase angle of the software phase-locked loop SPLL as the initial phase angle of the reference voltage signal Real-time phase angle of the reference voltage signal f i is the frequency output by the voltage-frequency droop controller, Δt is the amplitude and control period of the frequency droop controller;

[0176] Each of the slave machines clears the integral output of the voltage outer loop PI regulator;

[0177] Each slave enables the PWM drive of the power tube and starts in voltage mode, and adjusts the amplitude E of the reference voltage signal through the voltage amplitude droop controller and the voltage frequency droop controller respectively. i and phase angle θ i , resume parallel operation.

[0178] In this embodiment, a method for smoothly switching the inverter serving as a slave between the parallel operation mode and the PWM disable mode effectively suppresses inverter output current overshoot and output voltage fluctuation, thereby improving the transient response capability of the inverter parallel system to sudden changes in output load power and the operational reliability of the system.

[0179] In one embodiment, the active power detection module 10 is configured to calculate the active power using the following formula:

[0180]

[0181] Among them, U d 、U q is the active and reactive components of the AC output voltage, I d , I q are the active and reactive components of the load current;

[0182] The calculation formula for the active and reactive components of the AC output voltage is:

[0183]

[0184] The calculation formula for the active and reactive components of the load current is:

[0185]

[0186] Among them, u α 、u β In the current control cycle, the second-order generalized integrator (SOGI) is used to generate the two-phase quadrature signals of the AC output voltage in the stationary αβ coordinate system, i α 、iβ To generate the two-phase quadrature signals of the load current in the stationary αβ coordinate system through the second-order generalized integrator (SOGI) in the current control cycle, θ i The frequency f output by the voltage-frequency droop controller i Calculate the reference voltage phase angle.

[0187] It should be noted that other embodiments or implementation methods of the inverter parallel control system for suppressing no-load parallel circulating current described in the present invention can refer to the above-mentioned method embodiments, which are not repeated here.

[0188] In addition, an embodiment of the present invention further provides an inverter parallel control device, comprising a voltage amplitude droop controller, a voltage frequency droop controller, a controller, and a digital signal processor connected to each inverter. The output end of each inverter is connected to the same AC-side common bus through an AC output switch. The control board corresponding to each inverter is provided with a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus.

[0189] The voltage amplitude droop controller, the voltage frequency droop controller and the output of the digital signal processor are all connected to the power operation module, and the power operation module and the master-slave determination module are both connected to the controller;

[0190] The controller is used to implement the inverter parallel control method for suppressing no-load parallel circulating current as described above.

[0191] It should be noted that the logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing the logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other system that can fetch and execute instructions from an instruction execution system, apparatus, or device), or in conjunction with such instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transmit a program for use by an instruction execution system, apparatus, or device, or in conjunction with such instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: an electrical connection portion having one or more wires (electronic device), a portable computer disk cartridge (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Furthermore, the computer-readable medium may even be paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium and then editing, interpreting or processing it in another suitable manner if necessary, and then storing it in a computer memory.

[0192] It should be understood that various parts of the present invention can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one of the following technologies known in the art or a combination thereof can be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application-specific integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0193] Throughout this specification, reference to terms such as "one embodiment," "some embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0194] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0195] Although the embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and are not to be construed as limitations on the present invention. A person skilled in the art may change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A method for controlling inverters in parallel to suppress no-load parallel circulating current, characterized in that: The method is used to suppress no-load parallel circulating current of multiple inverters, wherein one of the inverters serves as a master and the remaining inverters serve as slaves, and a control board corresponding to each inverter is provided with a first transmitting end and a first receiving end, wherein the first transmitting end and the first receiving end are connected to a common signal bus, and the method comprises: Real-time detection of the active power output by the host; When the active power output by the host is less than the set lower limit threshold, the output level signal of the sending end on the control board corresponding to the host is flipped from a low level to a high level; when the active power output by the host is greater than the set upper limit threshold, the output level signal of the sending end on the control board corresponding to the host is flipped from a high level to a low level; When the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a low level to a high level, the slave switches from the parallel operation mode to the PWM disabled mode; when the receiving end on the control board corresponding to the slave detects that the input signal is flipped from a high level to a low level, the slave switches from the PWM disabled mode to the parallel operation mode; The slave device switches from the parallel operation mode to the PWM disable mode, comprising: Each of the slave machines turns off the PWM drive of the power tube and exits parallel operation, and the AC output switch corresponding to each of the slave machines remains in a closed state; Each slave latches the output frequency f according to the voltage frequency droop controller i Calculate the current reference voltage phase angle θ i ; Each of the slave devices uses the current reference voltage phase angle θ i As the initial phase, the frequency and phase angle information of the AC side common bus voltage are detected by the software phase-locked loop SPLL; The slave device switches from the PWM disable mode to the parallel operation mode, comprising: Each slave latches the current output phase angle of the software phase-locked loop SPLL as the initial phase angle of the reference voltage signal Real-time phase angle of the reference voltage signal f i is the frequency output by the voltage-frequency droop controller, Δt is the amplitude and control period of the frequency droop controller; Each of the slave machines clears the integral output of the voltage outer loop PI regulator; Each slave enables the PWM drive of the power tube and starts in voltage mode, and adjusts the amplitude E of the reference voltage signal through the voltage amplitude droop controller and the voltage frequency droop controller respectively. i and phase angle θ i , resume parallel operation; The characteristic equation of the voltage droop controller is: AND i =And * -n i P The characteristic equation of the voltage-frequency droop controller is: 2πf i =2πf * +m i Q Where, E * and f * is the rated output AC voltage amplitude and frequency, m i 、n i is the droop coefficient, P represents active power, and Q represents reactive power.

2. The inverter parallel control method for suppressing no-load parallel circulating current according to claim 1, characterized in that: The inverters communicate with each other via a CAN communication bus, and the method further includes: Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters; Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves; Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal; The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

3. The inverter parallel control method for suppressing no-load parallel circulating current according to claim 1, characterized in that: The control board corresponding to each inverter is provided with a second transmitting terminal and a second receiving terminal, wherein the second transmitting terminal outputs a fixed level signal, and the second receiving terminal receives a level signal output by a control board of an adjacent inverter. The method further includes: The receiving end 2 on the corresponding control board of the slave device detects in real time whether the adjacent inverter control board outputs a level reversal signal, wherein the level reversal signal includes a low level reversal to a high level and a high level reversal to a low level; If a level flip signal is detected, the slave device is switched to the master device; If the level inversion signal is not detected, switching between the PWM disable mode and the parallel operation mode is performed according to the level inversion signal from the common signal bus.

4. The inverter parallel control method for suppressing no-load parallel circulating current according to claim 3, characterized in that: The method further comprises: Determining whether a failure occurs in the host; If so, the host is controlled to stop, the AC output switch connected to the host is disconnected and the parallel operation is exited, and the sending terminal 2 on the control board corresponding to the host outputs the level reversal signal; If not, the host corresponds to the control board and the sending terminal 1 outputs the level reversal signal.

5. The inverter parallel control method for suppressing no-load parallel circulating current according to any one of claims 1 to 4, characterized in that: The calculation formula of the active power output by the host is: Among them, U d 、U q is the active and reactive components of the AC output voltage, I d , I q are the active and reactive components of the load current; The calculation formula for the active and reactive components of the AC output voltage is: The calculation formula for the active and reactive components of the load current is: Among them, u α 、u β is the two-phase quadrature signal of the AC output voltage, i α 、i β is the two-phase quadrature signal of the load current, θ i The output frequency f of the voltage-frequency droop controller is i Calculate the reference voltage phase angle.

6. An inverter parallel control system for suppressing no-load parallel circulating current, characterized in that: The system is used to suppress no-load parallel circulating current of multiple inverters, wherein one of the inverters serves as a master and the remaining inverters serve as slaves. A control board corresponding to each inverter is provided with a first transmitting end and a first receiving end, and the first transmitting end and the first receiving end are connected to a common signal bus. The system includes: An active power detection module, used for detecting the active power output by the host in real time; a level reversal signal generating module, configured to reverse an output level signal of a transmitting end on a control board corresponding to the host from a low level to a high level when the active power output by the host is less than a set lower threshold; and reverse an output level signal of a transmitting end on a control board corresponding to the host from a high level to a low level when the active power output by the host is greater than a set upper threshold; A slave mode switching module is configured to control the slave to switch from a parallel operation mode to a PWM disable mode when the receiving end on the control board corresponding to the slave detects that the input signal flips from a low level to a high level; and to control the slave to switch from a PWM disable mode to a parallel operation mode when the receiving end on the control board corresponding to the slave detects that the input signal flips from a high level to a low level; The slave mode switching module includes a first switching unit and a second switching unit, wherein: The first switching unit is used to control the slave machine to switch from the parallel operation mode to the PWM disable mode, including the following steps: Each of the slave machines turns off the PWM drive of the power tube and exits parallel operation, and the AC output switch corresponding to each of the slave machines remains in a closed state; Each slave latches the output frequency f according to the voltage frequency droop controller i Calculate the current reference voltage phase angle θ i ; Each of the slave devices uses the current reference voltage phase angle θ i As the initial phase, the frequency and phase angle information of the AC side common bus voltage are detected through a software phase-locked loop (SPLL); The second switching unit is used to control the slave to switch from the PWM prohibition mode to the parallel operation mode, including the following steps: Each slave latches the current output phase angle of the software phase-locked loop SPLL as the initial phase angle of the reference voltage signal Real-time phase angle of the reference voltage signal f i is the frequency output by the voltage-frequency droop controller, Δt is the amplitude and control period of the frequency droop controller; Each of the slave machines clears the integral output of the voltage outer loop PI regulator; Each slave enables the PWM drive of the power tube and starts in voltage mode, and adjusts the amplitude E of the reference voltage signal through the voltage amplitude droop controller and the voltage frequency droop controller respectively. i and phase angle θ i , resume parallel operation; The characteristic equation of the voltage droop controller is: AND i =And * -n i P The characteristic equation of the voltage-frequency droop controller is: 2πf i =2πf * +m i Q Where, E * and f * is the rated output AC voltage amplitude and frequency, m i 、n i is the droop coefficient, P represents active power, and Q represents reactive power.

7. The inverter parallel control system for suppressing no-load parallel circulating current according to claim 6, characterized in that: The system further includes a master-slave determination module configured to perform the following steps: Each inverter sends operating status information including its own serial number via the CAN communication bus, and receives and identifies the serial numbers of the remaining inverters; Determine the inverter with the smallest number as the master, and determine the remaining inverters as slaves; Controlling the host to output a fixed-level signal to the common signal bus at a transmitting end on the corresponding control board, and controlling the receiving end not to receive the signal; The sending end on the corresponding control board of the slave is controlled to not send a signal and the receiving end is controlled to receive a level signal from the common signal bus.

8. An inverter parallel control device, characterized in that: The device includes a voltage amplitude droop controller, a voltage frequency droop controller, a controller, and a digital signal processor connected to each inverter. The output end of each inverter is connected to the same AC side common bus through an AC output switch. The control board corresponding to each inverter is provided with a transmitting end 1 and a receiving end 1, and the transmitting end 1 and the receiving end 1 are connected to a common signal bus. The voltage amplitude droop controller, the voltage frequency droop controller and the output of the digital signal processor are all connected to the power operation module, and the power operation module and the master-slave determination module are both connected to the controller; The controller is used to implement the inverter parallel control method for suppressing no-load parallel circulating current as described in any one of claims 1 to 5.

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