A multi-phase clock generation circuit and clock phasing method

Abstract

The application provides a multi-phase clock generation circuit and a clock phase modulation method, the multi-phase clock generation circuit comprises: a quadrature signal generation module, which delays an input signal by T / 4, T / 2 and 3T / 4 to obtain quadrature signals with phase shifts of 0°, 90°, 180° and 270° and outputs the quadrature signals to a digital phase shift module; a control code generation module, which sets a control code signal and outputs the control code signal to the digital phase shift module; and the digital phase shift module, which receives the quadrature signals and the control code signal to adjust the quadrature signals by using the control code signal. The application designs a high-speed clock signal phase modulation device, realizes comparison of signals above 3.5Gsps and solves the problem of phase modulation of high-speed clock signals.

Description

Technical Field

[0001] This invention relates to the field of information processing, and specifically to a multi-phase clock generation circuit and a clock phase modulation method. Background Technology

[0002] Existing clock phase modulation circuits mainly consist of a phase adjustment module and a control signal module. The phase adjustment module is used to adjust the phase of the input signal according to the control signal and output a multi-phase clock signal. To obtain N clock signals with different phases, N sets of control signals are generally used to adjust the phase shift. The control signal typically achieves clock signal phase adjustment by controlling the ratio of the tail current source implemented by the DAC circuit.

[0003] Clock phase modulation technology has significant advantages in terms of chip area, power consumption, and ease of process portability, and is therefore widely used. However, clock phase modulation technology also faces some challenges. While this structure offers smooth phase adjustment and fast locking speed, its accuracy decreases with design precision. When the clock phase modulation module includes N DAC circuits, the two key performance indicators of the phase adjustment circuit—differential nonlinearity (DNL) and integral nonlinearity (INL)—will change with the difference in N, potentially leading to variations in the accuracy of the clock phase modulation module. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art, improve the differential nonlinearity and integral nonlinearity of the clock phase, obtain multi-phase adjustment, and propose a clock phase adjustment method and a multi-phase clock generation circuit.

[0005] To address the above problems, this invention provides a clock phase modulation method and a multi-phase clock generation circuit, comprising:

[0006] The four-phase signal generation module delays the input signal by T / 4, T / 2, and 3T / 4 to obtain four-phase signals with phase shifts of 0°, 90°, 180°, and 270°, and outputs them to the digital phase shift module.

[0007] The control code generation module sets the control code signal and outputs it to the digital phase shift module;

[0008] The digital phase-shifting module receives the four-phase signals and the control code signal, and uses the control code signal to adjust the four-phase signals.

[0009] Furthermore, the four-phase signal generation module is implemented through code generation.

[0010] Furthermore, the control code generation module uses the encoding method of thermometer codes to set the control code signal.

[0011] Furthermore, in the control code generation module, when adjacent control signals change, only one bit of value can be changed sequentially. Each individual least squares step size is achieved by changing the state of only one current control element or by flipping one of the polarity switches.

[0012] Furthermore, the digital phase-shifting module comprises a resistor synthesis module, a dual-channel differential amplifier module, and a multi-output constant current source module. The dual-channel differential amplifier module includes seven first differential amplifier modules and nine second differential amplifier modules. The multi-output constant current source module includes two seven-output constant current source modules and one nine-output constant current source module. Each first differential amplifier module is connected to and powered by a seven-output constant current source module, and each second differential amplifier module is connected to and powered by a nine-output constant current source module.

[0013] Furthermore, the first differential amplifier module includes 14 MOSFET transistors, divided into three stages. The first stage includes eight transistors, which are paired to form a current mirror bias circuit. The drains of the two transistors in each group are connected to one of the two output terminals of the resistor synthesis module. The sources of the two transistors in each group are connected to the drain of a second-stage transistor. The second stage has four transistors, divided into two groups of two transistors each. The sources of the two transistors in each group are connected to the drain of a third-stage transistor. The gate of one of the transistors in each group of second-stage transistors is connected to an inverter. The third stage has two transistors, and the drain of each third-stage transistor is connected to a seven-output constant current source module.

[0014] Furthermore, the second differential amplifier module includes 14 MOSFET transistors, divided into three stages. The first stage includes eight transistors, which are paired to form a current mirror bias circuit. The drains of the two transistors in each group are connected to one of the two output terminals of the resistor synthesis module. The sources of the two transistors in each group are connected to the drain of a second-stage transistor. The second stage has four transistors, divided into two groups of two transistors each. The sources of the two transistors in each group are connected to the drain of a third-stage transistor. The gate of one of the transistors in each second-stage group is connected to an inverter. The third stage has two transistors. The gate of one of the third-stage transistors is also connected to an inverter. The drains of both third-stage transistors are connected to the same nine-output constant current source module.

[0015] Furthermore, the seven-output constant current source module includes a current mirror bias circuit consisting of four MOSFET transistors and a resistor, as well as seven parallel MOSFETs. The drain output of each of the seven parallel MOSFETs provides a constant current output to a first dual-channel differential amplifier module.

[0016] Furthermore, the nine-output constant current source module includes a current mirror bias circuit consisting of four MOSFET transistors and a resistor, as well as nine parallel MOSFETs. The drain output of each of the nine parallel MOSFETs outputs a constant current to a second dual-channel differential amplifier module.

[0017] Furthermore, the resistor synthesis module includes two resistors of the same size connected in parallel.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] This invention designs a high-speed clock signal phase modulation device to achieve the comparison of signals above 3.5 Gsps, thus solving the phase modulation problem of high-speed clock signals.

[0020] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0021] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0022] Appendix Figure 1 A schematic diagram of a multi-phase clock generation circuit structure according to an embodiment of the present invention is shown.

[0023] Appendix Figure 2 A schematic diagram of the control code generation module according to an embodiment of the present invention is shown.

[0024] Appendix Figure 3 A schematic diagram of a digital phase-shifting module according to an embodiment of the present invention is shown.

[0025] Appendix Figure 4 A circuit diagram of a dual-channel differential amplifier module 1 according to an embodiment of the present invention is shown.

[0026] Appendix Figure 5 A circuit diagram of a dual-channel differential amplifier module 2 according to an embodiment of the present invention is shown.

[0027] Appendix Figure 6 A schematic diagram of a seven-port constant current source module circuit according to an embodiment of the present invention is shown.

[0028] Appendix Figure 7 A schematic diagram of a nine-port constant current source module circuit according to an embodiment of the present invention is shown.

[0029] Appendix Figure 8A schematic diagram of a resistor synthesis module circuit according to an embodiment of the present invention is shown.

[0030] Appendix Figure 9 A schematic diagram of an inverter circuit according to an embodiment of the present invention is shown. Detailed Implementation

[0031] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0032] Example 1

[0033] like Figure 1 As shown, according to Embodiment 1 of the present invention, a multi-phase clock generation circuit is proposed, comprising:

[0034] The four-phase signal generation module delays the input signal to generate signals with phase shifts of 0°, 90°, 180°, and 270°, respectively, minimizing autocorrelation, sidelobes, and cross-correlation to reduce phase shift errors. This module is implemented through code generation; for a specific frequency input signal, it delays it by T / 4, T / 2, and 3T / 4 to obtain the four-phase signal.

[0035] The control code generation module uses a thermometer code encoding method to set the control signals. Thermometer code refers to an encoding method that uses the number of 1s to represent a number. When adjacent control signals change, only one bit of the value can be changed sequentially, for example, from 001 to 011 to 111. Each individual least-squares step (i.e., the transition between any two adjacent states) is achieved by changing the state of only one current control element or flipping one of the polarity switches. This minimizes phase glitches during phase position switching. Figure 2 As shown, the control code generation module is implemented using digital circuitry. Multiple MUXs control its enable pin; when the enable pin is 0, the output is 0; when the enable pin is 1, the output is 1. A logic high level is 1, and a logic low level is 0. Each MUX corresponds to a control code. For example, if EN is 111, the output will also be 111.

[0036] The digital phase-shifting module is the core module of the clock phase-adjustment method, such as... Figure 3As shown, the system consists of a resistor synthesis module, a dual-channel differential amplifier module, and a multi-output constant current source module. The signal phase is adjusted via control codes in digital form. The resistor synthesis module has two output terminals, each connected to seven first differential amplifier modules and nine second differential amplifier modules. The multi-output constant current source module includes two seven-output constant current source modules and one nine-output constant current source module. Each first differential amplifier module is connected to and powered by a seven-output constant current source module, and each second differential amplifier module is connected to and powered by a nine-output constant current source module.

[0037] The first differential amplifier module, such as Figure 4 As shown, the system includes 14 MOSFET transistors, arranged in three stages. The first stage consists of eight transistors, grouped in pairs to form a current mirror bias circuit. The drains of the two transistors in each group are connected to one of the two output terminals of the resistor synthesis module. The sources of the two transistors in each group are connected to the drain of a second-stage transistor. Therefore, the second stage has four transistors, divided into two groups of two transistors each. The sources of the transistors in these two groups are connected to the drain of a third-stage transistor, and the gate of one of the transistors in each second-stage group is connected to an inverter. Therefore, the third stage has two transistors, and the drain of each third-stage transistor is connected to a seven-output constant current source module.

[0038] The second differential amplifier module, such as Figure 5 As shown, its structure is similar to Figure 4 The first differential amplifier module is similar. The difference is that the gate of one of the transistors in the third stage is also connected to an inverter, and the drains of both third-stage transistors are connected to the same nine-output constant current source module.

[0039] Figure 4 and Figure 5In this code, Si, sq, and siq all originate from the control code module. Si and sq control the first differential amplifier module, while siq controls the second differential amplifier module. Si includes si[0], si[1], si[2], si[3], si[4], si[5], and si[6]. Sq includes sq[0], sq[1], sq[2], sq[3], sq[4], sq[5], and sq[6], which are all 7, corresponding to the seven first differential amplifier modules. Siq includes siq[0], siq[1], siq[2], siq[3], siq[4], siq[5], siq[6], siq[7], and siq[8]. These are exactly 9, corresponding to the second differential amplifier module. Among them, poli and polq are fixed as poli = si[3] and polq = sq[3], controlling the phase quadrant. Poli = 0, polq = 0, both in the first quadrant; poli = 0, polq = 1, both in the second quadrant; poli = 1, polq = 1, both in the third quadrant; poli = 1, polq = 0, both in the fourth quadrant. Poli, polq and siq are independent and determined by the values ​​of si[3] and sq[3], which determine the quadrants of these phases. poli = si[3], polq = sq[3]. vbias is a 600mV voltage source.

[0040] The input of the dual-channel differential amplifier module receives signals C2I and C2Q after quadrature modulation. si<0:6>, sq<0:6>, and siq<0:8> are control codes transmitted by the control code generation module. For specific poli and polq, poli = si <3> polq = sq <3> The digital phase-shifting module thus forms a 64-phase octagonal phase rotator. Poli and Poliq control the phase position in different quadrants, Si and Sq control the phase shift in the horizontal and vertical directions, and Siq controls the phase shift along the hypotenuse in each of the four quadrants.

[0041] exist Figure 4 and Figure 5 The C2Ip, C2In, C2Qp, and C2Qn signals shown in the figure represent input signals with phases of 0°, 90°, 180°, and 270°, respectively, and originate from the four-phase signal generation module.

[0042] Multi-output constant current source module, such as Figure 6 and Figure 7 As shown, the tail current source of the dual-path differential phase-shifting structure can suppress common-mode interference. Two sets of constant current sources are used in both differential amplifier structures, employing a bias independent of the current source. Utilizing the current mirror principle, multiple output ports are provided for a single circuit to ensure the consistency of the constant current source. Among these, Figure 6It is a seven-output constant current source module, including a current mirror bias circuit consisting of four MOSFET transistors and a resistor, and seven MOSFETs connected in parallel. The drain output of each of the seven parallel MOSFETs is a constant current output. Figure 7 It is a nine-output constant current source module, including a current mirror bias circuit consisting of four MOSFET transistors and a resistor, and nine MOSFETs connected in parallel. Each of the nine parallel MOSFETs outputs a constant current from its drain.

[0043] Resistance synthesis module, such as Figure 8 As shown, multiple differential amplifier modules are integrated together using two identical resistors connected in parallel. Appropriate output signals Vout1 and Vout2 are obtained by using appropriate resistors.

[0044] like Figure 9 The diagram shows an inverter circuit, consisting of two MOSFET transistors connected in series. The inverter ensures that when the circuit receives control code signals si, sq, and siq, regardless of whether the signal is high or low, one circuit is always conducting.

[0045] It should be noted that:

[0046] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0047] Similarly, it should be understood that, in order to simplify the invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0048] Those skilled in the art will understand that modules in the device of the embodiments can be adaptively changed and placed in one or more devices different from that embodiment. Modules, units, or components in the embodiments can be combined into a single module, unit, or component, and further, they can be divided into multiple sub-modules, sub-units, or sub-components. Except where at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or units of any method or device so disclosed. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature that serves the same, equivalent, or similar purpose.

[0049] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of the invention and form different embodiments. For example, in the following claims, any of the claimed embodiments can be used in any combination.

[0050] It should be noted that the above embodiments are illustrative of the invention and not restrictive, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention can be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In the unit claims enumerating several systems, several of these systems may be embodied by the same item of hardware. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

[0051] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A multi-phase clock generation circuit, characterized in that, include: The four-phase signal generation module delays the input signal by T / 4, T / 2, and 3T / 4 to obtain four-phase signals with phase shifts of 0°, 90°, 180°, and 270°, and outputs them to the digital phase shift module. The control code generation module sets the control code signal and outputs it to the digital phase shift module; A digital phase-shifting module receives the four-phase signals and control code signals, and uses the control code signals to adjust the four-phase signals; The digital phase-shifting module consists of a resistor synthesis module, a dual-channel differential amplifier module, and a multi-output constant current source module. The dual-channel differential amplifier module includes seven first differential amplifier modules and nine second differential amplifier modules. The multi-output constant current source module includes two seven-output constant current source modules and one nine-output constant current source module. Each first differential amplifier module is connected to and powered by a seven-output constant current source module, and each second differential amplifier module is connected to and powered by a nine-output constant current source module. The first differential amplifier module includes 14 MOSFET transistors, divided into three stages. The first stage includes eight transistors, which are paired to form a current mirror bias circuit. The drains of the two transistors in each group are connected to one of the two output terminals of the resistor synthesis module. The sources of the two transistors in each group are connected to the drain of a second-stage transistor. The second stage has four transistors, divided into two groups of two transistors each. The sources of the two transistors in each group are connected to the drain of a third-stage transistor. The gate of one of the transistors in each group of second-stage transistors is connected to an inverter. There are two third-stage transistors, and the drain of each third-stage transistor is connected to a seven-output constant current source module. The second differential amplifier module includes 14 MOSFET transistors, divided into three stages. The first stage includes eight transistors, which are paired to form a current mirror bias circuit. The drains of the two transistors in each group are connected to one of the two output terminals of the resistor synthesis module. The sources of the two transistors in each group are connected to the drain of a second-stage transistor. The second stage has four transistors, divided into two groups of two transistors each. The sources of the two transistors in each group are connected to the drain of a third-stage transistor, and the gate of one of the transistors in each second-stage group is connected to an inverter. The third stage has two transistors, one of which has its gate connected to an inverter, and the drains of both third-stage transistors are connected to the same nine-output constant current source module. The seven-output constant current source module includes a current mirror bias circuit consisting of four MOSFET transistors and a resistor, as well as seven parallel MOSFETs. The drain output of each of the seven parallel MOSFETs outputs a constant current to a first dual-channel differential amplifier module. The nine-output constant current source module includes a current mirror bias circuit consisting of four MOSFET transistors and a resistor, and nine MOSFETs connected in parallel. The drain output of each of the nine parallel MOSFETs outputs a constant current to a second dual-channel differential amplifier module. The resistor synthesis module includes two resistors of the same size connected in parallel.

2. The multi-phase clock generation circuit according to claim 1, characterized in that, The four-phase signal generation module is implemented through code generation.

3. A multi-phase clock generation circuit according to claim 1 or 2, characterized in that, The control code generation module uses the thermometer code encoding method to set the control code signal.

4. The multi-phase clock generation circuit according to claim 3, characterized in that, In the control code generation module, when adjacent control signals change, only one bit of value can be changed sequentially. Each individual least squares step size is achieved by changing the state of only one current control element or by flipping one of the polarity switches.

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