Memory device and operating method thereof

Abstract

The present application relates to a memory device and an operating method thereof. The memory device includes a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells. The memory device also includes peripheral circuitry configured to perform a sensing operation that senses selected memory cells coupled to a selected word line selected from the plurality of word lines. The memory device also includes control logic configured to control the peripheral circuitry to apply a turn-on voltage to a block word line coupled to the selected word line when the sensing operation is terminated and when a potential of the plurality of word lines increases due to a recovery operation on channels of the plurality of memory cells after the plurality of word lines have been discharged.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate generally to electronic devices, and more particularly, to memory devices and methods of operating the memory devices. Background Art

[0002] A storage device is a device that stores data under the control of a host device such as a computer, smartphone, or smart tablet. Depending on the device that stores data, examples of the storage device include devices such as hard disk drives (HDDs) that store data on magnetic disks, and devices such as solid-state drives (SSDs) or memory cards that store data on semiconductor memories (particularly nonvolatile memories).

[0003] The storage device may include a memory device that stores data and a memory controller that controls the storage of data in the memory device. Such memory devices can be classified as volatile memory or non-volatile memory. Representative examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Summary of the Invention

[0004] Various embodiments of the present disclosure relate to a memory device that controls a voltage level applied to a block word line so as to reduce a potential difference between a word line and a channel that occurs after a word line discharge operation has been performed during a sensing operation, and a method of operating the memory device.

[0005] According to an embodiment of the present disclosure, a memory device includes: a memory cell array connected to a plurality of word lines, wherein each word line is connected to a plurality of memory cells; a peripheral circuit configured to perform a sensing operation that senses selected memory cells connected to a selected word line selected from among the plurality of word lines; and control logic configured to control the peripheral circuit to apply a turn-on voltage to a block word line connected to the selected word line when the sensing operation is terminated and when potentials of the plurality of word lines increase due to a recovery operation on channels of the plurality of memory cells after the plurality of word lines have been discharged.

[0006] According to an embodiment of the present disclosure, a memory device includes: a memory cell array connected to a plurality of word lines, wherein each word line is connected to a plurality of memory cells; a peripheral circuit configured to perform a sensing operation that senses selected memory cells connected to a selected word line selected from among the plurality of word lines; an idle state sensor configured to determine whether the memory device is in an idle state in which no operation is performed on the memory cell array, and to generate state information; a voltage controller configured to generate voltage information for setting a voltage level to be applied to a block word line connected to the selected word line; and an operation signal generator configured to generate an operation signal indicating that a turn-on voltage is to be applied to the block word line based on the state information and the voltage information when the sensing operation is terminated and when the potential of the plurality of word lines increases due to a recovery operation on the channels of the plurality of memory cells after the plurality of word lines have been discharged.

[0007] An embodiment according to the present disclosure relates to a method of operating a memory device, the memory device including a memory cell array connected to a plurality of word lines, wherein each word line is connected to a plurality of memory cells, the method comprising: performing a sensing operation that senses selected memory cells connected to a selected word line selected from among the plurality of word lines; discharging the plurality of word lines after the sensing operation has been performed; performing a recovery operation on channels of the plurality of memory cells; after the recovery operation has been performed, determining whether the memory device is in an idle state in which no operation is performed on the plurality of memory cells; and applying a turn-on voltage to block word lines connected to the selected word lines in the idle state. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a storage device.

[0009] Figure 2 It is an example Figure 1 Diagram of the structure of a memory device.

[0010] Figure 3 It is an example Figure 2 FIG. 1 is a diagram of an embodiment of a memory cell array.

[0011] Figure 4 is a diagram for describing local word lines, global word lines, and block word lines.

[0012] Figure 5 is a graph illustrating changes in voltage applied to each line and changes in channel potential during a sensing operation.

[0013] Figure 6 is a diagram illustrating a shift in the threshold voltage distribution in the erased state attributable to an increase in the potential of a word line.

[0014] Figure 7 is a diagram illustrating the potential of a word line changed by discharging the word line after a restore operation.

[0015] Figure 8 is a diagram illustrating the configuration of a block word line controller.

[0016] Figure 9 is a diagram illustrating voltages applied to block word lines to discharge the word lines.

[0017] Figure 10 is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0018] Figure 11 It is an example Figure 1 FIG. 1 is a diagram of an embodiment of a memory controller.

[0019] Figure 12 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0020] Figure 13 is a block diagram illustrating a solid-state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0021] Figure 14 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0022] The specific structural or functional descriptions used to present the embodiments of the present invention are only used to describe the embodiments. The descriptions should not be interpreted as being limited to or globally applicable to other embodiments consistent with the teachings of this specification or this application.

[0023] Various embodiments of the present disclosure are described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the present disclosure are illustrated so that those having ordinary skill in the art can easily implement the technical concept of the present disclosure.

[0024] Figure 1 is a block diagram illustrating a storage device.

[0025] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 .

[0026] The storage device 50 may be a device that stores data under the control of a host 300 such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, television (TV), tablet PC, or in-vehicle infotainment system.

[0027] The storage device 50 may be manufactured as any of various types of storage devices depending on a host interface as a scheme for communicating with the host 300. For example, the storage device 50 may be implemented as any of the following types of storage devices, for example: a solid state disk (SSD), a multimedia card such as MMC, embedded MMC (eMMC), reduced size MMC (RS-MMC), or micro MMC, a secure digital card such as SD, mini SD, or micro SD, a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick.

[0028] The storage device 50 may be manufactured in any of various types of packaging. For example, the storage device 50 may be manufactured in any of various types of packaging such as package-on-package (POP), system-in-package (SIP), system-on-chip (SOC), multi-chip package (MCP), chip-on-board (COB), wafer-level fabrication package (WFP), and wafer-level stacked package (WSP).

[0029] The memory device 100 can store data. The memory device 100 operates in response to the control of the memory controller 200. The memory device 100 may include a memory cell array including a plurality of memory cells storing data. The memory cell array may include a plurality of memory blocks. Each memory block may include a plurality of memory cells that may constitute a plurality of pages. In an embodiment, each page may be a unit for storing data in the memory device 100 or a unit for reading data stored in the memory device 100. A memory block may be a unit for erasing data.

[0030] In embodiments, the memory device 100 may take many alternative forms, such as double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate 4 (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus dynamic random access memory (RDRAM), NAND flash memory, perpendicular NAND flash memory, NOR flash memory device, resistive RAM (RRAM), phase change random access memory (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), or spin transfer torque RAM (STT-RAM). In this specification, for ease of description, the memory device 100 is described under the assumption that it is a NAND flash memory.

[0031] The memory device 100 can be implemented in a two-dimensional (2D) array structure or a three-dimensional (3D) array structure. Hereinafter, although a 3D array structure is described as an embodiment, the present disclosure is not limited to the 3D array structure. The teachings of the present disclosure can also be applied not only to flash memory devices in which the charge storage layer is formed by a conductive floating gate (FG), but also to charge trap flash (CTF) memory devices in which the charge storage layer is formed by an insulating layer.

[0032] In an embodiment, the memory device 100 may operate in a single-level cell (SLC) mode in which one data bit is stored in one memory cell. Alternatively, the memory device 100 may operate in a mode in which at least two data bits are stored in one memory cell. For example, the memory device 100 may operate in a multi-level cell (MLC) mode in which two data bits are stored in one memory cell, a triple-level cell (TLC) mode in which three data bits are stored in one memory cell, or a quad-level cell (QLC) mode in which four data bits are stored in one memory cell.

[0033] The memory device 100 receives a command and an address from the memory controller 200 and can access an area selected by the address in the memory cell array. That is, the memory device 100 can perform an operation corresponding to the command on the area selected by the address. For example, the memory device 100 can perform a write operation (i.e., a programming operation), a read operation, or an erase operation in response to the received command. When a program command is received, the memory device 100 can program data to the area selected by the address. When a read command is received, the memory device 100 can read data from the area selected by the address. When an erase command is received, the memory device 100 can erase the data stored in the area selected by the address.

[0034] In an embodiment, the memory device 100 may include a block wordline controller 150. The block wordline controller 150 may control the on and off operations of transistors coupled to the block wordlines during a sensing operation. The sensing operation may be a read operation or a verification operation included in a program loop.

[0035] In detail, when the memory device 100 performs a sensing operation, a sensing voltage may be applied to a selected word line and a pass voltage may be applied to unselected word lines. The sensing operation may be performed by applying a sensing voltage to a selected word line and a pass voltage to unselected word lines.

[0036] After that, the potential of the selected word line can be increased to the pass voltage level. When the potential of the selected word line is increased to the pass voltage level, all word lines can be discharged simultaneously. This operation is called equalization operation.

[0037] However, after the equalization operation has been performed, all word lines are discharged simultaneously, so the channel potentials of the memory cells can be reduced simultaneously. That is, channel negative boosting may occur. When channel negative boosting occurs, the memory device 100 can perform a recovery operation corresponding to the channel negative boosting.

[0038] When a recovery operation corresponding to negative channel boosting is performed, the corresponding channel potential may increase. However, as the channel potential increases, the potentials of all word lines may also increase. Therefore, as the potentials of all word lines increase, the threshold voltage distribution of memory cells in the erased state connected to the word lines may shift. For example, the threshold voltage level of memory cells in the erased state may increase.

[0039] To prevent the threshold voltage distribution of memory cells from shifting, the block wordline controller 150 included in the memory device 100 may control the voltage level to be applied to the block wordline. Here, the block wordline may be a line for connecting local wordlines connected to a memory block included in the memory device 100.

[0040] For example, when the memory device 100 is in an idle state or a ready state after the recovery operation corresponding to the negative channel boosting has been completed, the block word line controller 150 may turn on the transistors connected to the block word lines. The idle state or the ready state of the memory device 100 may be a state in which the memory device 100 is waiting for a subsequent operation to be performed after the corresponding operation has been completed, that is, a state in which no operation is performed.

[0041] Thereafter, when a preset time has elapsed, the block wordline controller 150 may turn off the transistors connected to the block wordline. The preset time may be a period of time included in the time when the memory device 100 is in an idle state. The preset time may be a reference time. As used herein, the term "preset" (such as a preset period of time) with respect to a parameter means that the value of the parameter is determined before the parameter is used in a process or algorithm. For some embodiments, the value of the parameter is determined before the process or algorithm begins. In other embodiments, the value of the parameter is determined during the process or algorithm but before the parameter is used in the process or algorithm.

[0042] In one embodiment, after a recovery operation corresponding to negative channel boosting has been performed, transistors connected to the block word lines are turned on only for a preset time, thereby enabling the potential of all word lines to decrease. Therefore, after performing an equalization operation during a sensing operation, the channel potential and the potential of the word lines can be prevented from changing.

[0043] The memory controller 200 may control overall operations of the storage device 50 .

[0044] The memory controller 200 may execute firmware when power voltage is applied to the storage device 50. When the memory device 100 is a flash memory device 100, the memory controller 200 may execute firmware such as a flash translation layer (FTL) for controlling communication between the host 300 and the memory device 100.

[0045] In an embodiment, the memory controller 200 may include firmware (not shown) that receives data and a logical block address (LBA) from the host 300 and converts the logical block address (LBA) into a physical block address (PBA) indicating an address of a memory cell included in the memory device 100 and in which data is to be stored. In addition, the memory controller 200 may store a logical-physical address mapping table in a buffer memory that configures a mapping relationship between the logical block address (LBA) and the physical block address (PBA).

[0046] The memory controller 200 may control the memory device 100 so that a program operation, a read operation, or an erase operation is performed in response to a request received from the host 300. For example, upon receiving a program request from the host 300, the memory controller 200 may convert the program request into a program command and may provide the program command, a physical block address (PBA), and data to the memory device 100. Upon receiving a read request and a logical block address from the host 300, the memory controller 200 may convert the read request into a read command, select a physical block address corresponding to the logical block address, and then provide the read command and the physical block address (PBA) to the memory device 100. Upon receiving an erase request and a logical block address from the host 300, the memory controller 200 may convert the erase request into an erase command, select a physical block address corresponding to the logical block address, and then provide the erase command and the physical block address (PBA) to the memory device 100.

[0047] In an embodiment, the memory controller 200 may autonomously generate a program command, address, and data without receiving a request from the host 300, and may transmit the same to the memory device 100. For example, the memory controller 200 may provide the memory device 100 with a command, address, and data to perform background operations such as a program operation for wear leveling and a program operation for garbage collection.

[0048] In an embodiment, the storage device 50 may include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 300 and the buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data used to control the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 300 in the buffer memory, and then may transmit the data temporarily stored in the buffer memory to the memory device 100.

[0049] In various embodiments, the buffer memory may be used as a working memory or cache memory of the memory controller 200. The buffer memory may store codes or commands executed by the memory controller 200. Alternatively, the buffer memory may store data processed by the memory controller 200.

[0050] In an embodiment, the buffer memory may be implemented as a DRAM such as double data rate SDRAM (DDR SDRAM), double data rate fourth generation (DDR4) SDRAM, low power double data rate fourth generation (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, or Rambus DRAM (RDRAM), or as static RAM (SRAM).

[0051] In various embodiments, a buffer memory may be coupled to the storage device 50 from outside the storage device 50. In this case, a volatile memory device coupled to the storage device 50 may be used as the buffer memory.

[0052] In an embodiment, the memory controller 200 may control at least two memory devices. In this case, the memory controller 200 may control the memory devices according to an interleaving scheme to improve operation performance.

[0053] The host 300 may communicate with the storage device 50 using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.

[0054] Figure 2 It is an example Figure 1 Diagram of the structure of a memory device.

[0055] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0056] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are coupled to a row decoder 121 via row lines RL. Each of the memory blocks BLK1 to BLKz may be coupled to a page buffer group 123 via bit lines BL1 to BLn. Each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Memory cells coupled to the same word line may be defined as a single page. Therefore, a single memory block may include a plurality of pages.

[0057] The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line.

[0058] Each memory cell included in the memory cell array 110 may be implemented as a single-level cell (SLC) capable of storing one data bit, a multi-level cell (MLC) capable of storing two data bits, a triple-level cell (TLC) capable of storing three data bits, or a quad-level cell (QLC) capable of storing four data bits.

[0059] The peripheral circuit 120 may perform a program operation, a read operation, or an erase operation on a selected region of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operating voltages to the row lines RL and the bit lines BL1 to BLn or discharge the applied voltages under the control of the control logic 130.

[0060] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0061] The row decoder 121 is coupled to the memory cell array 110 via row lines RL. The row lines RL may include at least one source select line, a plurality of word lines, and at least one drain select line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include a pipe select line.

[0062] The row decoder 121 may decode the row address RADD received from the control logic 130. The row decoder 121 may select at least one memory block from among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line WL of the selected memory block according to the decoded address, so that the voltage generated by the voltage generator 122 is applied to the at least one word line WL.

[0063] For example, during a program operation, the row decoder 121 may apply a program voltage to a selected word line and a program pass voltage having a lower level than the program voltage to unselected word lines. During a program verification operation, the row decoder 121 may apply a verification voltage to a selected word line and a verification pass voltage having a higher level than the verification voltage to unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to a selected word line and a read pass voltage having a higher level than the read voltage to unselected word lines.

[0064] In an embodiment, an erase operation of the memory device 100 is performed on a memory block basis. During the erase operation, the row decoder 121 may select a memory block according to the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to a word line connected to the selected memory block.

[0065] The voltage generator 122 may operate under the control of the control logic 130. The voltage generator 122 may generate a plurality of voltages using an external power supply voltage provided to the memory device 100. Specifically, the voltage generator 122 may generate various operating voltages Vop for program operations, read operations, and erase operations in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. under the control of the control logic 130.

[0066] In an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operating voltage of the memory device 100.

[0067] In an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0068] For example, the voltage generator 122 may include a plurality of pumping capacitors for receiving an internal power supply voltage, and generate a plurality of voltages by selectively enabling the plurality of pumping capacitors under the control of the control logic 130 .

[0069] The generated voltage may be provided to the memory cell array 110 through the row decoder 121 .

[0070] The page buffer group 123 includes first to nth page buffers PB1 to PBn. The first to nth page buffers PB1 to PBn are connected to the memory cell array 110 through first to nth bit lines BL1 to BLn, respectively. The first to nth page buffers PB1 to PBn operate under the control of the control logic 130. In detail, the first to nth page buffers PB1 to PBn can operate in response to a page buffer control signal PBSIGNALS. For example, during a read operation or a verify operation, the first to nth page buffers PB1 to PBn can temporarily store data received through the first to nth bit lines BL1 to BLn, or can sense the voltage or current of the bit lines BL1 to BLn.

[0071] Specifically, during a program operation, when a program voltage is applied to a selected word line, the first to nth page buffers PB1 to PBn can transmit data DATA received via the input / output circuit 125 to selected memory cells via the first to nth bit lines BL1 to BLn. The memory cells in the selected page are programmed based on the received data DATA. During a program verification operation, the first to nth page buffers PB1 to PBn can read page data by sensing a voltage or current received from the selected memory cells via the first to nth bit lines BL1 to BLn.

[0072] During a read operation, the first to nth page buffers PB1 to PBn may read data DATA from memory cells in a selected page through the first to nth bit lines BL1 to BLn and may output the read data DATA to the input / output circuit 125 under control of the column decoder 124 .

[0073] During an erase operation, the first to nth page buffers PB1 to PBn may float the first to nth bit lines BL1 to BLn or may apply an erase voltage to the first to nth bit lines BL1 to BLn.

[0074] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD. For example, the column decoder 124 may exchange data with the first to nth page buffers PB1 to PBn through the data lines DL, or may exchange data with the input / output circuit 125 through the column lines CL.

[0075] The input / output circuit 125 can transmit the data from the above reference to the control logic 130. Figure 1 The memory controller described (e.g., Figure 1 200 ) receives a command CMD and an address ADDR, or may exchange data DATA with the column decoder 124 .

[0076] During a read operation or a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit VRYBIT and may compare the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current and then output a pass signal PASS or a fail signal FAIL.

[0077] The control logic 130 can control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, a page buffer control signal PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR. For example, the control logic 130 can control a read operation on a selected memory block in response to a sub-block read command and an address. In addition, the control logic 130 can control an erase operation on a selected sub-block included in a selected memory block in response to a sub-block erase command and an address. In addition, the control logic 130 can determine whether a verification operation has passed or failed in response to a pass signal PASS or a fail signal FAIL. The control logic 130 can be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 can be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0078] In an embodiment, the control logic 130 may include a block wordline controller 150. In an embodiment, the block wordline controller 150 may be provided outside the control logic 130.

[0079] In an embodiment, the block word line controller 150 may control a sensing operation of the memory device 100. The sensing operation may be a read operation or a verification operation included in a program loop.

[0080] For example, the block word line controller 150 may control operations after a recovery operation corresponding to channel negative boosting occurring after equalization has been performed during a sensing operation.

[0081] Specifically, the block wordline controller 150 may control the block wordline so that the transistors connected to the block wordline are turned on only for a preset time after the resume operation. Here, when the memory device 100 is in an idle state or a ready state, the block wordline controller 150 may control the transistors connected to the block wordline. The preset time may be a period included in the duration of the memory device 100 being in the idle state.

[0082] Figure 3 It is an example Figure 2 FIG. 1 is a diagram of an embodiment of a memory block of a memory cell array 110 .

[0083] Reference Figure 2 and Figure 3 , Figure 3 This is an example of Figure 2 A circuit diagram of any one memory block BLKa among a plurality of memory blocks BLK1 to BLKz in the memory cell array 110.

[0084] The memory block BLKa may be connected to a first selection line, a word line, and a second selection line connected in parallel with each other. For example, the word lines may be connected in parallel with each other between the first selection line and the second selection line. Here, the first selection line may be a source selection line SSL, and the second selection line may be a drain selection line DSL.

[0085] In detail, the memory block BLKa may include a plurality of strings coupled between bit lines BL1 to BLn and a source line SL. The bit lines BL1 to BLn may be coupled to the plurality of strings, respectively, and the source line SL may be coupled to the plurality of strings in common. Since the strings may be configured identically, the string ST coupled to the first bit line BL1 will be described in detail by way of example.

[0086] The string ST may include a source select transistor SST, a plurality of memory cells F1 to F16, and a drain select transistor DST connected in series between a source line SL and a first bit line BL1. A single string ST may include at least one source select transistor SST and at least one drain select transistor DST, and may include more memory cells than the memory cells F1 to F16 illustrated in the drawings.

[0087] The source of the source select transistor SST can be connected to the source line SL, and the drain of the drain select transistor DST can be connected to the first bit line BL1. The memory cells F1 to F16 can be connected in series between the source select transistor SST and the drain select transistor DST. The gates of the source select transistors included in different strings ST can be connected to the source select line SSL, the gates of the drain select transistors included in different strings ST can be connected to the drain select line DSL, and the gates of the memory cells F1 to F16 can be respectively connected to multiple word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different strings ST can be referred to as a "physical page: PPG". Therefore, the memory block BLKa can include the same number of physical pages PPG as the number of word lines WL1 to WL16.

[0088] One memory cell can store one bit of data. This cell is often designated as a "single-level cell: SLC." Here, one physical page PPG can store data corresponding to one logical page LPG. The data corresponding to one logical page LPG may include the same number of data bits as the number of memory cells included in one physical page PPG. Alternatively, one memory cell can store two or more bits of data. This cell is often designated as a "multi-level cell: MLC." Here, one physical page PPG can store data corresponding to two or more logical pages LPG.

[0089] A memory cell storing two or more bits of data in one memory cell is called a multi-level cell (MLC). However, recently, as the number of bits of data stored in one memory cell has increased, a multi-level cell (MLC) refers to a memory cell in which two bits of data are stored, and thus a memory cell in which three bits of data are stored is called a triple-level cell (TLC), and a memory cell in which four bits of data are stored is called a quad-level cell (QLC). In addition, a memory cell scheme for storing multi-bit data has been developed, and the present teachings can be applied to a memory device 100 in which a memory cell storing two or more bits of data is used.

[0090] In an embodiment, each of the memory blocks may have a three-dimensional (3D) structure. Each of the memory blocks may include a plurality of memory cells stacked on a substrate. The plurality of memory cells may be arranged in +X, +Y, and +Z directions.

[0091] Figure 4 is a diagram for describing local word lines, global word lines, and block word lines.

[0092] Reference Figure 2 and Figure 4 , Figure 4 exemplified in Figure 2 The first to fourth memory blocks BLK1 to BLK4 among the plurality of memory blocks BLK1 to BLKz. Figure 4 , it is assumed that the remaining memory blocks except the first to fourth memory blocks BLK1 to BLK4 are omitted.

[0093] exist Figure 4 In the example, it is assumed that the memory device (e.g. Figure 2 100) has a single-plane structure. Therefore, Figure 4 Memory device (e.g., Figure 2 100 ) has a single-plane structure (ie, one plane structure), and the single plane may include first to fourth memory blocks BLK1 to BLK4 .

[0094] In an embodiment, the first memory block BLK1 may be coupled to 1_1th through 1-nth local word lines LWL1_1, LWL1_n, or a plurality of memory cells included in the first memory block BLK1.

[0095] Similarly, the second memory block BLK2 can be connected to the 2_1th local word line LWL2_1 to the 2_nth local word line LWL2_n, the third memory block BLK3 can be connected to the 3_1th local word line LWL3_1 to the 3_nth local word line LWL3_n, and the fourth memory block BLK4 can be connected to the 4_1th local word line LWL4_1 to the 4_nth local word line LWL4_n.

[0096] In an embodiment, the 1_1th to 1_nth global word lines GWL1_1 to GWL1_n may be selectively coupled to the first and third memory blocks BLK1 and BLK3 through the first and second transfer switch groups PSG1 and PSG2. The 2_1st to 2_nth global word lines GWL2_1 to GWL2_n may be selectively coupled to the second and fourth memory blocks BLK2 and BLK4 through the first and second transfer switch groups PSG1 and PSG2.

[0097] In an embodiment, the first transfer switch group PSG1 may include a plurality of transfer switches that are turned on or off in response to a voltage applied to the first block word line BLKWL1, wherein the plurality of transfer switches may be implemented as NMOS transistors. The second transfer switch group PSG2 may include a plurality of transfer switches that are turned on or off in response to a voltage applied to the second block word line BLKWL2, wherein the plurality of transfer switches may be implemented as NMOS transistors.

[0098] When a turn-on voltage is applied to the first block word line BLKWL1 and the second block word line BLKWL2 and the transfer switches included in the first transfer switch group PSG1 and the second transfer switch group PSG2 are turned on, the 1_1th global word line GWL1_1 to the 1_nth global word line GWL1_n can be commonly connected to the first storage block BLK1 and the third storage block BLK3, and the 2_1th global word line GWL2_1 to the 2_nth global word line GWL2_n can be commonly connected to the second storage block BLK2 and the fourth storage block BLK4.

[0099] When a turn-on voltage is applied to the first block word line BLKWL1 and a turn-off voltage is applied to the second block word line BLKWL2, the transfer switches included in the first transfer switch group PSG1 can be turned on, and the transfer switches included in the second transfer switch group PSG2 can be turned off. Therefore, the 1_1th through 1_nth global word lines GWL1_1 through GWL1_n are coupled to the first memory block BLK1, but not to the third memory block BLK3. Furthermore, the 2_1th through 2_nth global word lines GWL2_1 through GWL2_n are coupled to the second memory block BLK2, but not to the fourth memory block BLK4.

[0100] Conversely, when a cutoff voltage is applied to the first block word line BLKWL1 and a turn-on voltage is applied to the second block word line BLKWL2, the transfer switches included in the first transfer switch group PSG1 can be turned off, while the transfer switches included in the second transfer switch group PSG2 can be turned on. Therefore, the 1_1th through 1_nth global word lines GWL1_1 through GWL1_n are coupled to the third memory block BLK3, but not to the first memory block BLK1. Furthermore, the 2_1th through 2_nth global word lines GWL2_1 through GWL2_n are coupled to the fourth memory block BLK4, but not to the second memory block BLK2.

[0101] Therefore, a memory block can be selected based on a voltage applied to a corresponding block word line, and a slave voltage generator (eg, Figure 2 The operating voltage of the 122) output.

[0102] Figure 5 is a graph illustrating changes in voltage applied to each line and changes in channel potential during a sensing operation.

[0103] Reference Figure 4 and Figure 5 , Figure 5 Illustrated in the Figure 4 Changes in voltages applied to a selected word line (Selected WL), unselected word lines (Unselected WL), and block word lines (BLKWL), and changes in channel potentials during a sensing operation performed on a selected word line (Selected WL) among a plurality of local word lines LWL1_1 through LWL1_n, LWL2_1 through LWL2_n, LWL3_1 through LWL3_n, and LWL4_1 through LWL4_n. The sensing operation may be a read operation or a verify operation.

[0104] exist Figure 5, assuming that the selected word line Selected WL among the plurality of word lines is the 1_1th local word line LWL1_1, and the remaining local word lines are unselected word lines Unselected WL. Because the 1_1th local word line LWL1_1 is the selected word line, the memory cells coupled to the 1_1th local word line LWL1_1 among the memory cells in the first memory block BLK1 may be selected memory cells.

[0105] In an embodiment, a sensing operation may be performed at time t1. The sensing operation may be an operation of sensing the 1_1th local word line LWL1_1 as the selected word line Selected WL. That is, at time t1, the sensing operation may be a read operation or a verify operation on the selected memory cell connected to the 1_1th local word line LWL1_1.

[0106] During a sensing operation on a selected memory cell coupled to word line Selected WL, control logic (eg, Figure 2 130) can control peripheral circuits (e.g., Figure 2 120 ), so that a sensing operation is performed by applying a turn-on voltage to the first block word line BLKWL1 and applying a sensing voltage to the 1_1 th global word line GWL1_1.

[0107] In addition, the control logic (e.g. Figure 2 130) can control peripheral circuits (e.g., Figure 2 120), so that a sensing operation is performed by applying a cutoff voltage to the second block word line BLKWL2 and applying a pass voltage Vpass to the remaining global word lines except the 1_1th global word line GWL1_1.

[0108] As a result, the voltage level of the 1_1th local word line LWL1_1 as the selected word line Selected WL may be set to the sensing voltage level, and the voltage levels of the 1_2nd to 1_nth local word lines LWL1_2 to LWL1_n may be set to the sensing voltage Vpass, and thus a sensing operation may be performed.

[0109] At time t1, the voltage applied to the selected word line Selected WL may be a first read voltage Vread1. The first read voltage Vread1 may be a voltage used to distinguish between an erased state and a programmed state of a selected memory cell connected to the selected word line Selected WL. In other embodiments, the voltage applied to the selected word line Selected WL may be a first verification voltage. The first verification voltage may be a voltage used to determine whether the selected memory cell connected to the selected word line Selected WL has been programmed to a target program state. The first read voltage Vread1 and the first verification voltage may be sensing voltages.

[0110] At time t1, the voltage applied to the unselected word line (Unselected WL) may be a pass voltage Vpass. The pass voltage Vpass may be a voltage for turning on memory cells connected to word lines other than the selected word line (Selected WL). The voltage applied to the unselected word line (Unselected WL) may be maintained at the pass voltage Vpass until the sensing operation is completed. In other words, the pass voltage Vpass may be applied to the unselected word line (Unselected WL) until the first and second read operations or the first and second verify operations are completed.

[0111] At time t1, the voltage applied to the block word line BLKWL may be the on-voltage Vto. The on-voltage Vto may be a voltage for turning on the transfer switches included in the first transfer switch group PSG1 coupled to the block word line BLKWL. At time t1, the voltage applied to the block word line BLKWL may be maintained at the level of the on-voltage Vto until all word lines are discharged after equalization is performed. In other words, the transfer switches included in the first transfer switch group PSG1 coupled to the block word line BLKWL may remain on until all word lines enter a ground state.

[0112] At time t1, a sensing operation may begin when a first sensing voltage is applied to the selected word line (Selected WL) and a pass voltage (Vpass) is applied to the unselected word line (Unselected WL). In an embodiment, the first sensing voltage may be a first read voltage (Vread1) or a first verification voltage. After the sensing operation begins, program data stored in memory cells connected to the selected word line may be sensed via bit lines respectively connected to the memory cells.

[0113] In an embodiment, the data sensed by the bit line may be stored in Figure 2 Page buffer groups (e.g., Figure 2123). The sensed data may be read data or verification data. The read data may be data read through a bit line to read data programmed into the memory cell. The verification data may be data read through a bit line to verify data programmed into the memory cell. The program state of the memory cell may be determined based on the sensed data.

[0114] In an embodiment, the channel potential may be a potential of channels of a plurality of memory cells coupled to any one of a plurality of cell strings coupled to the bit line. Before performing the sensing operation, the channel potential may be 0V.

[0115] At time t1, the channel potential may increase instantaneously or rapidly and then may return to 0V. Specifically, as the sensing operation begins, a sensing voltage may be applied to the selected word line (Selected WL), and a pass voltage (Vpass) may be applied to the unselected word line (Unselected WL). When the sensing voltage and the pass voltage (Vpass) are applied to the selected word line (Selected WL) and the unselected word line (Unselected WL), respectively, channel coupling may occur between the word lines. When channel coupling occurs between the word lines, the channel potential may increase. After a predetermined time has passed, the increased channel potential may return to 0V.

[0116] The channel potential that has returned to 0V can have various levels depending on the programming state of the memory cell. That is, because the plurality of memory cells connected to the cell string can have various programming states, the current flowing through the plurality of memory cells can vary depending on the voltage applied to the word line. As a result, the channel potential can have various values ​​depending on the programming state of the plurality of memory cells connected to the cell string.

[0117] After the sensing operation has terminated, the channel potential may return to 0 V. That is, when the plurality of word lines are discharged, the bit lines may also be discharged, and thus the channel potential may return to 0 V.

[0118] In an embodiment, after the sensing operation has been performed, an equalization operation may be performed. The equalization operation may be an operation that simultaneously discharges multiple word lines connected to the memory block. The multiple word lines connected to the memory block may include a selected word line (Selected WL) and an unselected word line (Unselected WL).

[0119] Assuming that a discharge operation is performed on the word lines without performing an equalization operation, the voltage levels applied to the selected word line (Selected WL) and the unselected word lines (Unselected WL) are different from each other, and therefore, the time points at which the discharge operation will be completed can be different from each other. Therefore, the potential of the selected word line (Selected WL) can be set to the pass voltage (Vpass), so that the discharge of multiple word lines can be completed simultaneously.

[0120] Specifically, after performing a first read operation or a first verify operation, a pass voltage Vpass may be applied to the selected word line Selected WL. After the pass voltage Vpass has been applied to the selected word line Selected WL, the selected word line Selected WL and the unselected word lines Unselected WL may all be discharged simultaneously from the same pass voltage Vpass. That is, when the potential of the selected word line Selected WL is set to the pass voltage Vpass at time t2, and the potentials of all word lines including the selected word line Selected WL are set to the same pass voltage Vpass, all word lines may be discharged simultaneously by the same amount during a common period from time t2 to time t3.

[0121] In embodiments, because the programming states of multiple memory cells connected to a cell string differ from one another, the cutoff time points of the multiple memory cells may vary during bitline discharge. This change in the cutoff time points of the multiple memory cells may cause capacitive coupling between word lines, and due to this capacitive coupling, the channel potential may have a negative value. Consequently, the cutoff time points of the multiple memory cells vary, resulting in negative channel voltage boosting.

[0122] As the channel negative boosting occurs, the channel potential may have a negative value. During the period from time t2 to time t3, the channel potential changes to a negative potential due to the channel negative boosting, and thereafter, the channel potential may return to 0V due to the recovery operation at time t3.

[0123] In embodiments, during a restore operation, the potential of the word line may also increase along with the channel potential due to coupling between the channel and the word line. After the potential of the word line has increased, a considerable amount of time has passed as the potential of the word line increases, and thus the threshold voltage level of the memory cell in the erased state may increase due to retention. In other words, the cell stress on the memory cell in the erased state may increase.

[0124] Furthermore, a difference occurs between the potential levels of the channel and the word line, and thus it is possible to Figure 2The refresh read operation is repeatedly performed in the idle state or ready state of the memory device (e.g., Figure 2 The idle state or ready state of the memory device (e.g., Figure 2 100) is a state in which the operation is waiting to be performed subsequently, that is, a state in which the operation is not performed.

[0125] In an embodiment, as the refresh read operation is repeatedly performed, an uncorrectable error correction code (UECC) failure in which an error in sensed data is uncorrectable may occur.

[0126] Therefore, the present disclosure proposes a method of preventing a phenomenon in which a threshold voltage level of a memory cell is changed by reducing a time during which a potential level of a word line is maintained at a positive value.

[0127] Figure 6 is a graph showing a shift in threshold voltage distribution in an erased state due to an increase in the potential of a word line.

[0128] Reference Figure 6 , illustrates the threshold voltage distribution of the memory cell. Figure 6 In the example, it is assumed that the memory device (e.g. Figure 2 100) performs a programming operation using a single-level cell (SLC) scheme. Therefore, the memory cell can be in an erased state E or a programmed state P.

[0129] In other embodiments, Figure 6 It can also be applied to memory devices (e.g. Figure 2 100) A case where a program operation is performed using a multi-level cell (MLC), a triple-level cell (TLC), or a quad-level cell (QLC) scheme.

[0130] Reference Figure 5 , when the recovery operation corresponding to the negative boosting of the channel is performed at time t3, the potential of the word line may increase together with the channel potential due to coupling between the channel and the word line.

[0131] While the potential of the word line is increasing, the floating of the word line continues, and thus the memory cell may be degraded. In other words, the memory cell may be stuck.

[0132] In an embodiment, due to the retention of the memory cell, the threshold voltage of the memory cell in the erased state E may increase to E'. That is, the stress on the memory cell may increase.

[0133] Furthermore, the refresh read operation is repeatedly performed as the threshold voltage of the memory cell in the erased state E increases. As the refresh read operation is repeated, a UECC failure in which an error in the sensed data is uncorrectable may occur.

[0134] In order to prevent the occurrence of the above-mentioned UECC failure, the following figures describe the memory device (eg, Figure 2 A method for discharging a word line in an idle state or a ready state of 100).

[0135] Figure 7 is a diagram illustrating the potential of a word line changed by discharging the word line after a restore operation.

[0136] Reference Figure 5 and Figure 7 , Figure 7 Illustrated in Figure 5 After the recovery operation corresponding to the negative channel boosting has been performed at time t3, in the memory device (eg, Figure 2 The process of discharging the word line during the idle time or ready time of 100).

[0137] exist Figure 7 Before time t4, the change in voltage applied to each line and the change in channel potential are similar to Figure 5 , and therefore their repeated description will be omitted.

[0138] Reference Figure 5 Due to the recovery operation corresponding to the negative channel boosting performed at time t3, the channel potential can return to 0V at time t4.

[0139] However, as the channel potential increases from a negative value to 0 V again at time t4, the potential of the word line may have a positive value other than the ground voltage due to coupling between the channel and the word line. That is, as the channel potential increases, the potential of the word line may increase together with the channel potential.

[0140] In an embodiment, to reset the increased potential of the word line to 0V, the memory device (eg, Figure 2 100) can discharge the word line in the idle state or the ready state. Figure 2 The idle state or ready state of the memory device (e.g., Figure 2 100) is a state in which a subsequent operation is waiting to be performed, that is, a state in which no operation is performed.

[0141] In detail, after a recovery operation corresponding to negative boosting of a channel has been performed, the word line may be floated to a positive voltage.

[0142] In an embodiment, time passes in a state where the potential of the word line has been increased, and then the memory device (eg, Figure 2 100) can enter the idle state or ready state at time t5.

[0143] Therefore, since the memory device (e.g. Figure 2 100) is in the ready state at time t5, so the memory device (e.g., Figure 2 100) can be connected to the first block word line BLKWL1 by making the transistor (ie, Figure 4 The transistors in the first transfer switch group PSG1 are turned on to discharge the word line.

[0144] In detail, at time t5, the memory device (e.g., Figure 2 The first block word line BLKWL1 may be applied with a positive voltage. Thus, as the transistors in the first transfer switch group PSG1 are turned on, the potentials of the 1_1th to 1_nth local word lines LWL1_1 to LWL1_n may decrease.

[0145] Therefore, during a sensing operation, the memory device (e.g., Figure 2 100) in an idle state or a ready state, discharges a word line that has been floated to a positive voltage after a recovery operation corresponding to a negative channel boost has been performed, thereby preventing or alleviating a phenomenon in which a threshold voltage level of a memory cell is changed.

[0146] Figure 8 It is an example Figure 1 and Figure 2 FIG. 1 is a diagram of a configuration of the block wordline controller 150 .

[0147] Reference Figure 8 , the block word line controller 150 may include an idle state sensor 151 , a voltage controller 153 , and an operation signal generator 155 .

[0148] In an embodiment, the idle state sensor 151 can sense the memory device (eg, Figure 2 100) is in an idle state. The memory device (e.g., Figure 2 100) can be an idle state of a memory device (e.g., Figure 2 100) ready state.

[0149] For example, the idle state sensor 151 may be based on the ready / busy signal RB or a memory device (eg, Figure 2 100) internally generated signal to determine the memory device (e.g., Figure 2 100) is in idle state.

[0150] The idle state sensor 151 may be configured to determine the idle state of the memory device (e.g., Figure 2 Here, the status information STATUS_INF may include information related to the memory device (eg, Figure 2 100) is in an idle state.

[0151] In an embodiment, the voltage controller 153 may control a voltage level to be applied to a block word line. The block word line controlled by the voltage controller 153 may be a word line coupled to a transistor coupled to a local word line and a global word line corresponding to a selected word line.

[0152] Reference Figure 4 and Figure 5 , the selected word line Selected WL is the 1_1th local word line LWL1_1, so the voltage controller 153 can control the voltage level to be applied to the first block word line BLKWL1, which is coupled to the gate of the transistor for coupling the 1_1th local word line LWL1_1 to the 1_1th global word line GWL1_1.

[0153] In an embodiment, when the voltage controller 153 receives the recovery operation completion signal RECC_SIG, the voltage controller 153 may output voltage information VOL_INF including information about the voltage level to be applied to the block word line. Here, the recovery operation completion signal RECC_SIG may be a signal indicating that the recovery operation corresponding to the negative boosting of the channel caused by the discharge of the word line after the equalization operation of setting the potential of the selected word line to the pass voltage level during the sensing operation has been completed.

[0154] That is, in order to lower the increased potential of the word line again after the recovery operation corresponding to the channel negative boosting has been completed, the voltage controller 153 may set a voltage level to be applied to the block word line.

[0155] In an embodiment, the operation signal generator 155 may generate an operation signal OPSIG based on the state information STATUS_INF and the voltage information VOL_INF and may output the operation signal OPSIG. Here, the state information STATUS_INF may be output from the idle state sensor 151 and the voltage information VOL_INF may be output from the voltage controller 153.

[0156] In detail, when the status information STATUS_INF outputted from the idle state sensor 151 indicates that the memory device (eg, Figure 2When the operation signal generator 155 receives voltage information VOL_INF including information on a voltage level to be applied to a block word line from the voltage controller 153, the operation signal generator 155 may output the operation signal OPSIG. Here, the operation signal OPSIG may be a signal indicating a voltage having a level corresponding to the voltage information VOL_INF to be applied to the block word line. For example, the operation signal OPSIG may be output to Figure 2 Voltage generator (e.g., Figure 2 122).

[0157] That is, in a memory device (e.g., Figure 2 After performing the sensing operation in the memory device (e.g., Figure 2 A voltage level that discharges the word line in an idle state of 100) and a voltage having a set level can be applied to the block word line.

[0158] Refer to the following Figure 9 Detailed description of the memory device (e.g., Figure 2 The voltage level applied to the block word line in the idle state of 100).

[0159] Figure 9 is a diagram illustrating voltages applied to block word lines to discharge the word lines.

[0160] Reference Figure 9 , Figure 9 Instruction memory means (eg, Figure 2 The ready / busy signal RB indicating the ready state or the busy state of the first block word line BLKWL1 and the voltage level applied to the 1_1th global word line GWL1_1 are used.

[0161] Reference Figure 4 、 Figure 5 and Figure 9 , the selected word line Selected WL is the 1_1 local word line LWL1_1, so in Figure 9 In the embodiment, the first block word line BLKWL1 may be a word line coupled to a gate of a transistor for coupling the 1_1th local word line LWL1_1 to the 1_1th global word line GWL1_1. Figure 7 and Figure 9 , time t4 Figure 9 The middle may be a time point at which the recovery operation corresponding to the channel negative boosting is completed.

[0162] In an embodiment, before time t4, the memory device (e.g., Figure 2100) is performing a recovery operation corresponding to the channel negative boosting, so the ready / busy signal RB may be in a low state. That is, the ready / busy signal RB may indicate that the memory device (eg, Figure 2 100) is busy.

[0163] Furthermore, since the memory device (e.g. Figure 2 100) is performing a recovery operation before time t4, so a turn-on voltage (eg, Figure 5 That is, for the recovery operation, a voltage for turning on the transistor coupled to the first block word line BLKWL1 may be applied to the first block word line BLKWL1 before time t4.

[0164] Thereafter, the memory device (e.g., Figure 2 100) can be in an idle state.

[0165] Therefore, since the memory device (e.g. Figure 2 100) is in a waiting state in which no operation is performed in an idle state, so the ready / busy signal RB may be in a state indicating that the memory device (eg, Figure 2 In order to reduce the potential of the word line increased by the recovery operation when the ready / busy signal RB is in the high state (i.e., during the first idle time t_IDLE1 after time t4), a potential having a voltage lower than the turn-on voltage (e.g., Figure 5 Here, the voltage level applied to the first block word line BLKWL1 may be changed to a voltage lower than the turn-on voltage (eg, Vto). Figure 5 For example, the voltage applied to the first block word line BLKWL1 during the first idle time t_IDLE1 may be 0V or a voltage having a level close to 0V with respect to the turn-on voltage Vto.

[0166] Because 0V or a voltage having a level close to 0V is applied to the first block word line BLKWL1 during the first idle time t_IDLE1 , charges trapped in transistors coupled to the first block word line BLKWL1 may be released and the potential of the word line may be lowered.

[0167] After the first idle time t_IDLE1 has elapsed, the memory device (eg, Figure 2 100) performs the sensing operation again at time t5, so the ready / busy signal RB can be changed from the high state to indicate that the memory device (eg, Figure 2100) of the busy state of the low state.

[0168] Assume that the memory device (e.g. Figure 2 100) performs a sensing operation at time t5, then the turn-on voltage (eg, Figure 5 A voltage Vto) may be applied to the first block word line BLKWL1, and a sensing voltage or a pass voltage may be applied to the 1_1th global word line GWL1_1.

[0169] Thereafter, at time t6 the memory device (eg, Figure 2 After the sensing operation of 100), the memory device (eg, Figure 2 100) can enter the idle state. When the memory device (e.g., Figure 2 When the ready / busy signal RB is in an idle state, the ready / busy signal RB can be changed from a low state to a high state.

[0170] In order to reduce the potential of the word line increased by the recovery operation when the ready / busy signal RB is in a high state (ie, during the second idle time t_IDLE2 after time t6), a voltage having a higher than on-state voltage (eg, Figure 5 Here, the voltage level applied to the first block word line BLKWL1 may be changed to a voltage lower than the turn-on voltage (eg, Vto). Figure 5 The level of Vto) is within a range of various values.

[0171] That is, since 0V or a voltage having a level close to 0V with respect to the turn-on voltage Vto is applied to the first block word line BLKWL1 again during the second idle time t_IDLE2, charges trapped in transistors coupled to the first block word line BLKWL1 may be released and the potential of the word line may be lowered.

[0172] As a result, in a state where the potential of the word line has floated to a positive voltage level after the sensing operation, the memory device (eg, Figure 2 100) may apply 0V or a voltage having a level close to 0V to the first block word line BLKWL1. A memory device (eg, Figure 2 100) can quickly discharge the word line by applying 0V or a voltage having a level close to 0V with respect to the turn-on voltage Vto to the first block word line BLKWL1.

[0173] Therefore, after the sensing operation, the memory device (e.g., Figure 2 100) can immediately discharge the word line, thereby preventing the threshold voltage of the memory cell in the erased state from increasing.

[0174] Figure 10is a flowchart illustrating the operation of a memory device according to an embodiment of the present disclosure.

[0175] Reference Figure 10 In step S1001, the memory device may perform a sensing operation. For example, when the memory device performs a sensing operation, a sensing voltage may be applied to a selected word line, and a pass voltage may be applied to unselected word lines. The sensing operation may be performed by applying the sensing voltage to the selected word line and applying the pass voltage to the unselected word lines.

[0176] In step S1003, the memory device may discharge the word lines after performing an equalization operation. Specifically, while the memory device is performing a sensing operation, voltages having different levels are applied to the selected word lines and the unselected word lines. Therefore, an equalization operation may be performed to set the potentials of all word lines to the same level after the sensing operation is terminated.

[0177] After the equalization operation, the memory device may discharge all word lines simultaneously, thereby setting the potential of all word lines to 0 V. However, after the equalization operation has been performed, all word lines are discharged simultaneously, so the channel potentials of the memory cells may decrease simultaneously. In other words, negative channel boosting may occur.

[0178] Therefore, in step S1005, the memory device may perform a recovery operation corresponding to the channel negative boosting. The channel potential that has become a negative potential due to the channel negative boosting may increase through the recovery operation and then may return to 0V.

[0179] However, during the recovery operation, due to the coupling between the channel and the word line, the potential of the word line may also increase along with the channel potential. That is, because the potential of the word line may float to a state with a positive voltage value, the memory device may discharge the word line in the idle state.

[0180] In step S1007, it is determined whether the memory device is in an idle state or a ready state. When the memory device is in an idle state or a ready state (in the case of "yes"), the process may proceed to step S1009. The idle state of the memory device means that the memory device is in a state where no operation is being performed while the memory device is waiting for a subsequent operation to be performed after the corresponding operation is completed.

[0181] In step S1009, the memory device may set a voltage level for discharging a word line and apply a voltage having the set level to a block word line. The block word line may be a word line connected to the gate of a transistor connected to the selected word line. In an embodiment, the memory device may apply the voltage having the set level to the block word line for a predetermined time.

[0182] Figure 11This is an example of how Figure 1 FIG. 2 is a diagram of an embodiment of a memory controller 1000 .

[0183] The memory controller 1000 is coupled to a host and a memory device. In response to a request received from the host, the memory controller 1000 can access the memory device. For example, the memory controller 1000 can be configured to control writing, reading, and erasing of the memory device and perform background operations. The memory controller 1000 can provide an interface between the memory device and the host. The memory controller 1000 can run firmware for controlling the memory device.

[0184] Reference Figure 11 , the memory controller 1000 may include a processor 1010 , a memory buffer 1020 , an error correction code (ECC) circuit 1030 , a host interface 1040 , a buffer control circuit 1050 , a memory interface 1060 , and a bus 1070 .

[0185] The bus 1070 may provide a channel between the components of the memory controller 1000 .

[0186] The processor 1010 may control the overall operation of the memory controller 1000 and may perform logic operations. The processor 1010 may communicate with an external host through the host interface 1040 and may also communicate with a memory device through the memory interface 1060. In addition, the processor 1010 may communicate with the memory buffer 1020 through the buffer control circuit 1050. The processor 1010 may control the operation of the storage device by using the memory buffer 1020 as a working memory, a cache memory, or a buffer memory.

[0187] The processor 1010 may perform the function of a flash translation layer (FTL). The processor 1010 may convert a logical block address (LBA) provided by a host into a physical block address (PBA) through the FTL. The FTL may receive the LBA using a mapping table and convert the LBA into the PBA. Examples of address mapping methods performed by the FTL may include various methods depending on the mapping unit. Representative address mapping methods include a page mapping method, a block mapping method, and a hybrid mapping method.

[0188] The processor 1010 may randomize data received from the host. For example, the processor 1010 may use a randomization seed to randomize the data received from the host. The randomized data may be provided to the memory device as data to be stored and may be programmed into the memory cell array.

[0189] The processor 1010 may execute software or firmware to perform randomization or de-randomization operations.

[0190] In an embodiment, the processor 1010 may execute software or firmware to perform randomization and de-randomization operations.

[0191] The memory buffer 1020 may be used as a working memory, a cache memory, or a buffer memory of the processor 1010. The memory buffer 1020 may store codes and commands executed by the processor 1010. The memory buffer 1020 may store data processed by the processor 1010. The memory buffer 1020 may include a static RAM (SRAM) or a dynamic RAM (DRAM).

[0192] The ECC circuit 1030 may perform error correction. The ECC circuit 1030 may perform error correction code (ECC) encoding based on data to be written to the memory device via the memory interface 1060. The ECC-encoded data may be transmitted to the memory device via the memory interface 1060. The ECC circuit 1030 may perform ECC decoding based on data received from the memory device via the memory interface 1060. In an example, the ECC circuit 1030 may be included in the memory interface 1060 as a component of the memory interface 1060.

[0193] The host interface 1040 may communicate with an external host under the control of the processor 1010. The host interface 1040 may perform communication using at least one of various communication methods such as Universal Serial Bus (USB), Serial AT Attachment (SATA), Serial Attached SCSI (SAS), High-Speed ​​Interchip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI-Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), MultiMedia Card (MMC), Embedded MMC (eMMC), Dual Inline Memory Module (DIMM), Registered DIMM (RDIMM), and Load Reduced DIMM (LRDIMM) communication methods.

[0194] The buffer control circuit 1050 may control the memory buffer 1020 under the control of the processor 1010 .

[0195] The memory interface 1060 may communicate with the memory device under the control of the processor 1010. The memory interface 1060 may transmit / receive commands, addresses, and data to / from the memory device through a channel.

[0196] In an embodiment, the memory controller 1000 may not include the memory buffer 1020 and the buffer control circuit 1050 .

[0197] In an embodiment, the processor 1010 may use code to control the operation of the memory controller 1000. The processor 1010 may load code from a nonvolatile memory device (eg, ROM) provided in the memory controller 1000. In an embodiment, the processor 1010 may load code from the memory device through the memory interface 1060.

[0198] In an embodiment, the bus 1070 of the memory controller 1000 can be divided into a control bus and a data bus. The data bus can be configured to transmit data in the memory controller 1000, and the control bus can be configured to transmit control information such as commands or addresses in the memory controller 1000. The data bus and the control bus can be isolated from each other so as not to interfere with or affect each other. The data bus can be connected to the host interface 1040, the buffer control circuit 1050, the ECC circuit 1030, and the memory interface 1060. The control bus can be connected to the host interface 1040, the processor 1010, the buffer control circuit 1050, the memory buffer 1020, and the memory interface 1060.

[0199] Figure 12 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present disclosure is applied.

[0200] Reference Figure 12 , the memory card system 2000 may include a memory controller 2100 , a memory device 2200 , and a connector 2300 .

[0201] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 can access the memory device 2200. For example, the memory controller 2100 can control the read operation, write operation, erase operation and background operation of the memory device 2200. The memory controller 2100 can provide an interface between the memory device 2200 and the host. The memory controller 2100 can run firmware for controlling the memory device 2200. The memory device 2200 can be operated in accordance with the above reference. Figure 1 The memory device described (e.g., Figure 1 100) is achieved in the same way.

[0202] In an embodiment, the memory controller 2100 may include components such as a RAM, a processor, a host interface, a memory interface, and an ECC circuit.

[0203] The memory controller 2100 can communicate with an external device through the connector 2300. The memory controller 2100 can communicate with an external device (e.g., a host) based on a specific communication protocol. In an embodiment, the memory controller 2100 can communicate with an external device through at least one of the following communication protocols: Universal Serial Bus (USB), MultiMediaCard (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI-Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and Non-Volatile Memory Express (NVMe) protocol. In an embodiment, the connector 2300 can be defined by at least one of the above-mentioned various communication protocols.

[0204] In an embodiment, the memory device 2200 can be implemented as any one of various non-volatile memory devices such as: electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM) and spin transfer torque magnetic RAM (STT-MRAM).

[0205] The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association: PCMCIA), a Compact Flash card (CF), a Smart Media Card (SM or SMC), a Memory Stick, a MultiMedia Card (MMC, RS-MMC, MicroMMC, or eMMC), an SD card (SD, MiniSD, MicroSD, or SDHC), or a Universal Flash Storage (UFS).

[0206] In an embodiment, the memory device 2200 may perform a sensing operation. The sensing operation may be a read operation or a verification operation included in a program loop.

[0207] After the memory device 2200 has performed the sensing operation, all word lines may be set to a pass voltage level according to an equalization operation. Thereafter, all word lines may be discharged simultaneously.

[0208] However, when all word lines are discharged simultaneously, the channel potentials of the memory cells may decrease simultaneously. That is, negative channel boosting may occur. When negative channel boosting occurs, the memory device 2200 may perform a recovery operation corresponding to the negative channel boosting.

[0209] However, during the recovery operation of memory device 2200, the potential of the word line may also increase along with the channel potential due to coupling between the channel and the word line. Therefore, in order to discharge the word line, memory device 2200 may apply a voltage having a preset level to the block word line connected to the transistor connected to the selected word line for a preset time in an idle state. Here, the voltage applied to the block word line may be 0V or a voltage having a level close to 0V, and the preset time may be a period of time included in the time when memory device 2200 is in the idle state.

[0210] As a result, a voltage having a preset level is applied to the block word line for a preset time so that charges trapped in transistors coupled to the block word line may be released, and thus the increased potential of the word line may decrease and return to 0V.

[0211] Figure 13 is a block diagram illustrating an example of a solid state drive (SSD) system to which a storage device according to an embodiment of the present disclosure is applied.

[0212] Reference Figure 13 , the SSD system 3000 may include a host 3100 and an SSD 3200. The SSD 3200 may exchange a signal SIG with the host 3100 via a signal connector 3001 and may receive power PWR via a power connector 3002. The SSD 3200 may include an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

[0213] In an embodiment, the SSD controller 3210 may perform the above reference Figure 1 The memory controller described (e.g., Figure 1 200) function.

[0214] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal SIG received from the host 3100. For example, the signal SIG may be a signal based on an interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one of the following interfaces: a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), PCI-Express (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), Wi-Fi, Bluetooth, and a non-volatile memory express (NVMe) interface.

[0215] The auxiliary power supply 3230 can be connected to the host 3100 via the power connector 3002. The auxiliary power supply 3230 can be supplied with power PWR from the host 3100 and can be charged. When the power supply from the host 3100 is unstable, the auxiliary power supply 3230 can provide power to the SSD 3200. In embodiments, the auxiliary power supply 3230 can be located inside or outside the SSD 3200. For example, the auxiliary power supply 3230 can be provided on the motherboard and can provide auxiliary power to the SSD 3200.

[0216] The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 can temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or can temporarily store metadata (e.g., a mapping table) of the flash memories 3221 to 322n. The buffer memory 3240 can include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0217] Each of the plurality of flash memories 3221 to 322n may perform a sensing operation, which may be a read operation or a verification operation included in a program loop.

[0218] After the plurality of flash memories 3221 to 322n have performed a sensing operation, all word lines may be set to a pass voltage level according to an equalization operation. Thereafter, all word lines may be discharged simultaneously.

[0219] However, when all word lines are discharged simultaneously, the channel potentials of the memory cells may decrease simultaneously. That is, negative channel boosting may occur. When negative channel boosting occurs, each of the plurality of flash memories 3221 to 322n may perform a recovery operation corresponding to the negative channel boosting.

[0220] When multiple flash memories 3221 to 322n perform a restore operation, the potential of the word line may also increase along with the channel potential due to coupling between the channel and the word line. Therefore, to discharge the word line, each of the multiple flash memories 3221 to 322n may apply a voltage of a preset level to the block word line connected to the transistor connected to the selected word line for a preset time in an idle state. Here, the voltage applied to the block word line may be 0V or a voltage having a level close to 0V, and the preset time may be a period of time included in the time when the multiple flash memories 3221 to 322n are in the idle state.

[0221] As a result, a voltage having a preset level is applied to the block word line for a preset time so that charges trapped in transistors coupled to the block word line may be released, and thus the increased potential of the word line may decrease and return to 0V.

[0222] Figure 14 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0223] Reference Figure 14 , the user system 4000 may include an application processor 4100 , a memory module 4200 , a network module 4300 , a storage module 4400 , and a user interface 4500 .

[0224] The application processor 4100 may execute components, an operating system (OS), or a user program included in the user system 4000. In an embodiment, the application processor 4100 may include a controller, an interface, a graphic engine, etc. for controlling the components included in the user system 4000. The application processor 4100 may be provided as a system on chip (SoC).

[0225] Memory module 4200 can be used as a main memory, working memory, buffer memory, or cache memory of user system 4000. Memory module 4200 may include volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDRAM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile RAM such as PRAM, ReRAM, MRAM, and FRAM. In an embodiment, application processor 4100 and memory module 4200 may be packaged based on a package-on-package (POP) process and then provided as a single semiconductor package.

[0226] The network module 4300 can communicate with external devices. For example, the network module 4300 can support wireless communications such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi communications. In an embodiment, the network module 4300 can be included in the application processor 4100.

[0227] The storage module 4400 can store data. For example, the storage module 4400 can store data received from the application processor 4100. Alternatively, the storage module 4400 can send the data stored in the storage module 4400 to the application processor 4100. In an embodiment, the storage module 4400 can be implemented as a non-volatile semiconductor memory device such as a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash memory, a NOR flash memory, or a NAND flash memory with a three-dimensional structure. In an embodiment, the storage module 4400 can be provided as a removable storage medium (i.e., a removable drive) such as a memory card or an external drive of the user system 4000.

[0228] In an embodiment, the storage module 4400 may include a plurality of non-volatile memory devices, each of which may be configured as described above with reference to FIG. Figure 2 and Figure 3 The storage module 4400 can be operated in the same manner as described above with reference to the memory device described above. Figure 1 The storage device 50 operates in the same manner as described.

[0229] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or outputting data to an external device. In an embodiment, the user interface 4500 may include user input interfaces such as a keyboard, a keypad, buttons, a touch panel, a touch screen, a touch pad, a touch ball, a camera, a microphone, a gyro sensor, a vibration sensor, and a piezoelectric device. The user interface 4500 may also include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

[0230] In an embodiment, the storage module 4400 may perform a sensing operation. The sensing operation may be a read operation or a verification operation included in a program loop.

[0231] After the memory module 4400 has performed the sensing operation, all word lines may be set to a pass voltage level according to an equalization operation. Thereafter, all word lines may be discharged simultaneously.

[0232] However, when all word lines are discharged simultaneously, the channel potentials of the memory cells may decrease simultaneously. That is, negative channel boosting may occur. When negative channel boosting occurs, the storage module 4400 may perform a recovery operation corresponding to the negative channel boosting.

[0233] However, during the recovery operation of storage module 4400, due to the coupling between the channel and the word line, the potential of the word line may also increase along with the channel potential. Therefore, in order to discharge the word line, storage module 4400 may apply a voltage having a preset level to the block word line connected to the transistor connected to the selected word line for a preset time in an idle state. Here, the voltage applied to the block word line may be 0V or a voltage having a level close to 0V, and the preset time may be a period of time included in the time when storage module 4400 is in the idle state.

[0234] As a result, a voltage having a preset level is applied to the block word line for a preset time so that charges trapped in transistors coupled to the block word line may be released, and thus the increased potential of the word line may decrease and return to 0V.

[0235] According to the present disclosure, the word line is discharged by turning on the transistor on the block word line coupled to the word line for a certain time after a recovery operation corresponding to negative boosting of the channel during a sensing operation, thereby reducing the potential difference between the word line and the channel.

[0236] CROSS-REFERENCE TO RELATED APPLICATIONS

[0237] This application claims priority from Korean Patent Application No. 10-2020-0166854 filed on December 2, 2020, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A memory device, comprising: a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells; a peripheral circuit that performs a sensing operation that senses a selected memory cell coupled to a selected word line selected from among the plurality of word lines; and control logic that controls the peripheral circuit to apply a turn-on voltage to the block word lines coupled to the selected word lines in an idle state or a ready state when the sensing operation is terminated and when potentials of the plurality of word lines increase due to a recovery operation on channels of the plurality of memory cells after the plurality of word lines have been discharged.

2. The memory device of claim 1 , further comprising a transistor coupled to the block word line, wherein The on-voltage is a voltage for turning on the transistor.

3. The memory device according to claim 1, wherein The turn-on voltage has a voltage level lower than a voltage level applied to the block word line during the sensing operation.

4. The memory device according to claim 1, wherein The control logic controls the peripheral circuit to apply the turn-on voltage to the block word line for a reference time interval during the idle state after the sensing operation has terminated.

5. The memory device according to claim 4, wherein The reference time interval is included in a time period corresponding to the idle state. The memory device according to claim 1 , wherein: The control logic controls the peripheral circuit to perform a subsequent sensing operation when the turn-on voltage is applied to the block word line and then discharges potentials of the plurality of word lines.

7. The memory device according to claim 6, wherein: The control logic controls the peripheral circuit to apply the turn-on voltage to a block word line coupled to a word line on which the subsequent sensing operation is performed among the plurality of word lines during the idle state after the subsequent sensing operation has terminated.

8. A memory device, comprising: a memory cell array coupled to a plurality of word lines, wherein each word line is coupled to a plurality of memory cells; a peripheral circuit that performs a sensing operation that senses a selected memory cell coupled to a selected word line selected from among the plurality of word lines; an idle state sensor that determines whether the memory device is in an idle state in which no operation is performed on the memory cell array and generates state information; a voltage controller that generates voltage information for setting a voltage level to be applied to a block word line coupled to the selected word line; and an operation signal generator that generates, based on the state information and the voltage information, an operation signal indicating that a turn-on voltage is to be applied to the block word lines when the sensing operation is terminated and when potentials of the plurality of word lines increase due to a recovery operation on channels of the plurality of memory cells after the plurality of word lines have been discharged.

9. The memory device according to claim 8, wherein The idle state sensor determines whether the memory device is in the idle state based on a ready / busy signal or an internal signal, and generates the state information indicating whether the memory device is in the idle state.

10. The memory device according to claim 8, wherein The voltage controller generates the voltage information upon receiving a recovery operation completion signal indicating that the recovery operation has been completed.

11. The memory device according to claim 8, wherein The voltage controller generates the voltage information to include information about a voltage level lower than a voltage level applied to the block word line during the sensing operation.

12. The memory device according to claim 8, wherein The operation signal generator, when receiving the voltage information from the voltage controller and when the state information indicates the idle state, outputs the operation signal indicating application of the turn-on voltage to the block word line for a reference time interval in the idle state after the sensing operation has terminated.

13. The memory device according to claim 12, wherein: The reference time interval is included in a time period corresponding to the idle state.

14. A method of operating a memory device comprising a memory cell array coupled to a plurality of word lines, wherein: Each word line is coupled to a plurality of memory cells, and the method comprises the following steps: performing a sensing operation that senses a selected memory cell coupled to a selected word line selected from among the plurality of word lines; discharging the plurality of word lines after the sensing operation has been performed; performing a recovery operation on the channels of the plurality of memory cells; After the recovery operation has been performed, determining whether the memory device is in an idle state in which no operation is performed on the plurality of memory cells; and A turn-on voltage is applied to a block word line coupled to the selected word line in the idle state.

15. The method according to claim 14, wherein The step of applying the turn-on voltage includes the step of applying the turn-on voltage to transistors coupled to the block word line.

16. The method according to claim 14, wherein The step of applying the turn-on voltage includes applying a voltage having a lower voltage level than a voltage level applied to the block word line during the sensing operation to the block word line in the idle state.

17. The method according to claim 14, wherein: Applying the turn-on voltage to the block word line includes applying the turn-on voltage to the block word line for a reference time interval in the idle state.

18. The method according to claim 17, wherein The reference time interval is included in a time period corresponding to the idle state.

19. The method according to claim 14, further comprising the steps of: A subsequent sensing operation is performed after the potentials of the plurality of word lines are discharged by applying the turn-on voltage to the block word lines.

20. The method according to claim 19, further comprising the steps of: In an idle state after the subsequent sensing operation has terminated, the turn-on voltage is applied to a block word line coupled to a word line on which the subsequent sensing operation is performed among the plurality of word lines.

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