Semiconductor chip and semiconductor package comprising the same

Abstract

The present invention relates to a semiconductor chip and a semiconductor package comprising the semiconductor chip. A semiconductor chip comprises a chip body comprising a signal input / output circuit, a chip pad structure arranged on a surface of the chip body, the chip pad structure comprising a first chip pad and a second chip pad, the two chip pads having different surface areas, and a chip pad selection circuit arranged in the chip body and electrically connected to the signal input / output circuit and the chip pad structure. The chip pad selection circuit is configured to selectively electrically connect one of the first chip pad and the second chip pad to the signal input / output circuit.

Description

Technical Field

[0001] This disclosure generally relates to packaging technology, and more specifically, to semiconductor chips including chip pads of different surface areas and semiconductor packages including the same. Background Technology

[0002] Today, the semiconductor industry is evolving towards manufacturing lightweight, compact, high-speed, multifunctional, high-performance, and highly reliable semiconductor products at low cost, and semiconductor packaging technology is a crucial part of achieving this goal. Semiconductor packaging technology refers to the techniques used to mount semiconductor chips, which have circuitry formed through wafer fabrication processes, onto a packaging substrate. The packaging substrate ensures electrical connectivity between the semiconductor chip and external electronic devices and protects the semiconductor chip from external environmental influences. Techniques for mounting semiconductor chips onto packaging substrates include methods such as wire bonding of the semiconductor chip and the packaging substrate, and flip-chip bonding of the semiconductor chip and the packaging substrate. Summary of the Invention

[0003] A semiconductor chip according to embodiments of the present disclosure may include: a chip body including signal input / output circuitry; a chip pad structure disposed on the surface of the chip body, the chip pad structure including input / output pad units and control pad units; and a chip pad selection circuit disposed in the chip body and electrically connected to the signal input / output circuitry and the chip pad structure. The input / output pad units include a first chip pad and a second chip pad, the first chip pad and the second chip pad having different surface areas. The chip pad selection circuit is configured to select one of the first chip pad and the second chip pad and is configured to electrically connect one of the first chip pad and the second chip pad to the signal input / output circuitry based on a control signal input from the control pad unit.

[0004] A semiconductor package according to another embodiment of the present disclosure may include a package substrate and a semiconductor chip disposed on the package substrate. The package substrate includes a substrate body and a plurality of chip connection pads disposed on the surface of the substrate body. The semiconductor chip includes a chip body and a chip pad structure disposed on the surface of the chip body, the chip pad structure including a plurality of input / output pad units and at least one control pad unit. The plurality of input / output pad units and at least one control pad unit are configured to correspond to the plurality of chip connection pads respectively. Each of the plurality of input / output pad units includes a first chip pad and a second chip pad configured to be spaced apart from each other, the first chip pad and the second chip pad having different surface areas. One of the first chip pads and the second chip pad is electrically connected to a corresponding chip connection pad among the plurality of chip connection pads. Attached Figure Description

[0005] Figure 1 This is a schematic cross-sectional view of a semiconductor package according to an embodiment of the present disclosure.

[0006] Figure 2 This is a schematic plan view of a packaging substrate according to an embodiment of the present disclosure.

[0007] Figure 3 This is a schematic plan view of a semiconductor chip according to an embodiment of the present disclosure.

[0008] Figure 4 This is a schematic diagram illustrating the parasitic capacitance generated by the chip pads of a semiconductor chip according to an embodiment of the present disclosure.

[0009] Figure 5 This is a circuit diagram of a chip pad selection circuit for a semiconductor chip according to an embodiment of the present disclosure.

[0010] Figure 6 This is a schematic plan view of a semiconductor package according to an embodiment of the present disclosure.

[0011] Figure 7 This is a schematic plan view of a semiconductor chip according to another embodiment of the present disclosure.

[0012] Figure 8 This is an illustrative representation of joining to another embodiment of this application. Figure 7 A plan view of the packaging substrate for a semiconductor chip.

[0013] Figure 9 This is a plan view of a semiconductor package according to another embodiment of the present disclosure.

[0014] Figure 10 This is a schematic circuit diagram illustrating a chip pad selection circuit for a semiconductor chip according to an embodiment of the present disclosure.

[0015] Figure 11 This is a schematic cross-sectional view of a semiconductor chip including a chip pad selection circuit according to an embodiment of the present disclosure. Detailed Implementation

[0016] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the drawings, the dimensions of the components (e.g., the width and thickness of the components) are enlarged to clearly illustrate the components of the various devices. The terms used herein may correspond to words that take into account their functional selection in the embodiments, and the meaning of the terms may be interpreted differently by those skilled in the art to which the embodiments pertain. If explicitly defined in detail, the terms may be interpreted according to the definition. Unless otherwise defined, the terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the embodiments pertain.

[0017] Furthermore, unless clearly used otherwise in the context, the singular form of a word should be understood to include the plural form of the word. It will be understood that the terms “comprising,” “including,” or “having” are intended to indicate the presence of a feature, quantity, step, operation, component, element, part, or combination thereof, and not to exclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, components, elements, parts, or combinations thereof.

[0018] In this specification, the phrase "predetermined direction" may refer to a direction defined in a coordinate system as well as the direction opposite to that direction. As an example, in the xyz coordinate system, the x-direction may encompass directions parallel to the x-direction. That is, the x-direction may refer to both the direction in which the absolute value of the z-axis increases positively along the x-axis from the origin 0 and the direction in which the absolute value of the x-axis increases negatively along the x-axis from the origin 0. The y-direction and z-direction may each be interpreted in substantially the same way in the xyz coordinate system.

[0019] In this specification, in addition to direct bonding from one component to another, bonding between one component and another may include indirect bonding through intermediate material inserted between the two components. As an example, bonding between chip connection pads of a package substrate and chip pads of a semiconductor chip may mean not only direct bonding between chip connection pads and chip pads, but also bonding materials such as bumps or solder are inserted between chip connection pads and chip pads to bond the chip connection pads and chip pads to each other.

[0020] Figure 1 This is a schematic cross-sectional view of a semiconductor package 1 according to an embodiment of the present disclosure. (Refer to...) Figure 1 The semiconductor package 1 may include a package substrate 10 and a semiconductor chip 20 disposed on the package substrate 10. The package substrate 10 and the semiconductor chip 20 may be joined to each other via a conductive connector 230. The conductive connector 230 may include, for example, bumps.

[0021] The packaging substrate 10 may include a substrate body 110 having an upper surface 110S1 and a lower surface 110S2. The packaging substrate 10 may include chip connection pads 120 disposed on the upper surface 110S1 of the substrate body 110. The packaging substrate 10 may include a plurality of connection pads 130 spaced apart from the chip connection pads 120 in a first direction and a second direction (e.g., the x-direction and the z-direction). In one embodiment, the plurality of connection pads 130 may be disposed on the lower surface 110S2 of the substrate body 110. The packaging substrate 10 may include a plurality of connection structures 140 respectively disposed on the plurality of connection pads 130. The plurality of connection structures 140 may include, for example, bumps or solder balls. For example, the plurality of connection structures 140 may be configured to electrically connect to other semiconductor packages or other electronic systems.

[0022] although Figure 1 As not shown in the diagram, in this embodiment, the chip connection pads 120 may be arranged along a third direction (e.g., the y-direction) on the upper surface 110S1 of the substrate body 110. The arrangement of the plurality of chip connection pads 120 will be described later. Figure 2 Description. Additionally, the connection pads 130 may be arranged along a third direction (e.g., the y-direction) on the lower surface 110S2 of the substrate body 110. The arrangement of the plurality of connection pads 130 will be described later. Figure 2 Description. Hereinafter, for ease of description, when two distinct connection pads are selected from among a plurality of connection pads 130, the two selected connection pads are referred to as the first connection pad 130a and the second connection pad 130b, respectively. In this case, among the plurality of connection structures 140, the connection structure in contact with the first connection pad 130a may be referred to as the first connection structure 140a, and the connection structure in contact with the second connection pad 130b may be referred to as the second connection structure 140b.

[0023] Reference Figure 1 Multiple wirings 150 can be disposed on / in the substrate body 110. The first wiring 150a among the multiple wirings 150 can electrically connect the first connection structure 140a to the corresponding chip connection pad 120. The second wiring 150b among the multiple wirings 150 can electrically connect the second connection structure 140b to other chip connection pads 120. Figure 1 (Not shown in the image).

[0024] In this embodiment, the first wiring 150a and the second wiring 150b may have different lengths. Therefore, when an electrical signal is transmitted along the first wiring 150a and the second wiring 150b, different parasitic capacitances can be generated in the first wiring 150a and the second wiring 150b due to the different wiring lengths. (Refer to...) Figure 1The first wiring 150a may include a first outer layer circuit a1 and a first via a2. The second wiring 150b may include a second outer layer circuit b1 and a second via b2. The first outer layer circuit a1 and the second outer layer circuit b1 may be disposed on the upper surface 110S1 of the substrate body 110. The first via a2 and the second via b2 may be disposed in the substrate body 110 to connect the first outer layer circuit a1 and the second outer layer circuit b1 to corresponding first connection pads 130a and second connection pads 130b, respectively. The first outer layer circuit a1 and the second outer layer circuit b1 may have various shapes and lengths. The first via a2 and the second via b2 may be formed to have substantially the same shape and length.

[0025] In the implementation method, such as Figure 1 As shown, the first outer circuit a1 of the first wiring 150a and the second outer circuit b1 of the second wiring 150b can have different lengths along the electrical signal path. Therefore, when an electrical signal is transmitted along the first outer circuit a1 and the second outer circuit b1, different parasitic capacitances can be generated along the first outer circuit a1 and the second outer circuit b1 based on their different lengths.

[0026] exist Figure 1 In some embodiments not shown, the configuration of the multiple wirings 150 can be modified differently. As an example, each of the multiple wirings 150 may also include at least one inner layer circuit within the substrate body 110. The at least one inner layer circuit is electrically connected to the outer layer circuit and connection pads via at least one via. In this case, the magnitude of the parasitic capacitance generated in each of the multiple wirings 150 can vary based on the sum of the lengths of the outer and inner layer circuits.

[0027] Reference Figure 1 The semiconductor chip 20 may include a chip body 210 having a first surface 210S1 and a second surface 210S2, and chip pad units 220 disposed on the first surface 210S1. The chip body 210 may include an internal integrated circuit. In an embodiment, the internal integrated circuit may be disposed in an inner region of the chip body 210. Although Figure 1 As not shown, the chip body 210 may include signal input / output circuitry electrically connected to an internal integrated circuit. Electrical signals processed in the internal integrated circuit can reach the chip pad unit 220 via the signal input / output circuitry. Additionally, electrical signals input through the chip pad unit 220 can be transmitted to the internal integrated circuit via the signal input / output circuitry. The electrical signal transmission between the signal input / output circuitry and the chip pad unit 220 will be described later. Figure 5 describe.

[0028] Chip pad units 220 may be configured to correspond to chip connection pads 120 on the first surface 210S1. Each chip pad unit 220 may include a first chip pad 220a and a second chip pad 220b spaced apart from each other. The first chip pad 220a may have a different surface area than the second chip pad 220b, both of which are formed on the first surface 210S1. One of the first chip pad 220a and the second chip pad 220b may be bonded to the corresponding chip connection pad 120. Bonding may be achieved via a conductive connector 230. The method for determining which chip pad of the first chip pad 220a and the second chip pad 220b shall be bonded to the chip connection pad 120 will be described later. Figure 6 describe.

[0029] One of the first chip pads 220a and the second chip pad 220b, which is to be bonded to the chip connection pad 120, can be used as a bonding pad. Signal input / output circuitry can be electrically connected to the chip connection pad 120 via the bonding pad. (Refer to...) Figure 1 The second chip pad 220b can be used as a bonding pad. The other chip pad, which is not bonded to the chip connection pad 120, between the first chip pad 220a and the second chip pad 220b, can be used as a chip test pad. The chip test pad can be used to connect test equipment for testing the operation of the internal integrated circuit of the semiconductor chip 20 to the internal integrated circuit. In an embodiment, operational tests using the chip test pad can be performed on the semiconductor chip 20 before it is mounted on the package substrate 10.

[0030] although Figure 1 Not shown, a chip pad selection circuit and a signal input / output circuit connected to the first chip pad 220a and the second chip pad 220b may be disposed in the chip body. The chip pad selection circuit may be configured to selectively connect one of the bonding pads and the chip test pads electrically to the signal input / output circuit. Detailed configuration of the chip pad selection circuit will be described later. Figure 5 describe.

[0031] although Figure 1 As not shown, chip pad units 220 may be arranged in multiple ways along a third direction (e.g., the y-direction) on the first surface 210S1 of the chip body 210. Each of the first chip pad 220a and the second chip pad 220b may be arranged along a third direction. The arrangement of the multiple chip pad units 220 will be described later. Figure 3 describe.

[0032] Figure 2 This is a schematic plan view of a packaging substrate according to an embodiment of the present disclosure. Figure 2 It can be Figure 1The diagram shows a plan view of the packaging substrate 10 of the semiconductor package 1.

[0033] Reference Figure 2 Multiple chip connection pads 120 may be disposed on the upper surface 110S1 of the substrate body 110. The multiple chip connection pads 120 may be spaced apart from each other on the upper surface 110S1 of the substrate body 110 along a third direction (e.g., the y-direction). In one embodiment, the multiple chip connection pads 120 may be configured to form columns L1. Alternatively, in another embodiment, the multiple chip connection pads 120 may be arranged in two columns L1 parallel to each other in the y-direction. Multiple connection pads 130 may be disposed on the lower surface 110S2 of the substrate body 110. Although... Figure 2 Not shown in the image. Figure 1 The connection structure 140 can be respectively disposed on the corresponding connection pad 130. For example, as shown... Figure 1 As shown, the first connection pad 130a and the second connection pad 130b can be configured to be adjacent to each other in the x-direction on the lower surface 110S2 of the substrate body 110. The first connection structure 140a can be disposed on the corresponding first connection pad 130a, and the second connection structure 140b can be disposed on the corresponding second connection pad 130b.

[0034] Refer to together Figure 1 and Figure 2 In this embodiment, each first connection structure 140a can be electrically connected to a corresponding chip connection pad among the plurality of chip connection pads 120 via a first connection pad 130a and a first wiring 150a. Each second connection structure 140b can be electrically connected to another corresponding chip connection pad among the plurality of chip connection pads 120 via a second connection pad 130b and a second wiring 150b. One chip connection pad and another chip connection pad can be configured to be adjacent to each other in the y-direction. The first wiring 150a and the second wiring 150b can each have a corresponding first outer layer circuit a1 and a second outer layer circuit b1. In this case, the first outer layer circuit a1 and the second outer layer circuit b1 can have different lengths in the electrical signal path.

[0035] In addition, such as Figure 1 and Figure 2As shown, the first connection pad 130a and the second connection pad 130b can be configured to be adjacent to each other in the x-direction on the lower surface 110S2 of the substrate body 110, such that the first connection structure 140a and the second connection structure 140b can be configured to be adjacent to each other in the x-direction. However, the invention is not limited thereto, and the first connection pad 130a and the second connection pad 130b may not be configured to be adjacent to each other on the lower surface 110S of the substrate body 110. As an example, the first connection pad 130a and the second connection pad 130b may be configured not to face each other in the x-direction or y-direction on the lower surface 110S of the substrate body 110. Therefore, the first connection structure 140a and the second connection structure 140b may not be configured to be adjacent to each other. The configuration of the first connection pad 130a and the second connection pad 130b can be determined by the design configuration of the package substrate 10. As an example, depending on the function and purpose of the semiconductor package, the design configuration may include various arrangement configurations for the connection pads 130, the connection structures 140, and the wiring 150.

[0036] Refer to together Figure 1 and Figure 2 Multiple wirings 150 can be set from multiple connection structures 140 to corresponding chip connection pads 120. Figure 2 For ease of description, a first wiring 150a and a second wiring 150b are shown as examples of multiple wirings 150. Although not shown, wirings other than the first wiring 150a and the second wiring 150b can be respectively disposed between the corresponding connection structure 140 and the chip connection pad 120. In this case, the lengths of the multiple wirings 150 can be different from each other. In this case, as the length of the wiring 150 is shortened, the parasitic capacitance of the semiconductor package 1 generated by the wirings 150 in the substrate body 110 can be reduced during electrical signal transmission processing.

[0037] In the implementation method, refer to Figure 2 The length of the first wiring 150a having the first outer layer circuit a1 can be shorter than the length of the second wiring 150b having the second outer layer circuit b1. In this case, the parasitic capacitance generated by the first wiring 150a can be smaller than the parasitic capacitance generated by the second wiring 150b. Hereinafter, the parasitic capacitance generated by the above wiring will be referred to as "encapsulated parasitic capacitance".

[0038] In embodiments of this disclosure, a configuration is provided to compensate for differences in package parasitic capacitance generated on the electrical signal path of the package substrate 10 for each of the plurality of chip connection pads 120 (or for each of the plurality of connection structures 140) due to the different lengths of the plurality of wirings 150. As described below, when two different chip connection pads 120, respectively connected to first wirings 150a and second wirings 150b of different lengths, are disposed on the upper surface 110S1 of the substrate body 110, the two different chip connection pads 120 can be connected to each other correspondingly with the first chip pads 220a and second chip pads 220b having different surface areas, so that the aforementioned differences in package parasitic capacitance can be canceled out.

[0039] Figure 3 This is a schematic plan view of a semiconductor chip according to an embodiment of the present disclosure. Figure 3 It can be Figure 1 The diagram shows a plan view of the semiconductor chip 20 in the semiconductor package 1.

[0040] Reference Figure 3 Multiple chip pad units 220 may be disposed on a first surface 210S1 of the chip body 210. The multiple chip pad units 220 may be spaced apart from each other along a third direction (e.g., the y-direction). In one embodiment, the multiple chip pad units 220 may be configured to form a column L0. Alternatively, in another embodiment, the multiple chip pad units 220 may be arranged as two columns L0 parallel to each other in the y-direction.

[0041] Each of the plurality of chip pad units 220 may include a first chip pad 220a and a second chip pad 220b configured to be spaced apart from each other in the x-direction. The first chip pad 220a may have a different surface area than the second chip pad 220b. In an embodiment, the first chip pad 220a may have a smaller surface area than the second chip pad 220b.

[0042] Reference Figure 3 Multiple first chip pads 220a can be configured to form a column along the y-direction. Multiple second chip pads 220b can be configured to be spaced apart from the multiple first chip pads 220a and form a column L0 along the y-direction.

[0043] Figure 4 This is a schematic diagram illustrating the parasitic capacitance generated by the chip pads of a semiconductor chip according to an embodiment of the present disclosure. Figure 4 The chip pads 320, the inner circuit layer 340, and the interlayer dielectric layer 330 disposed on the surface of the semiconductor chip are schematically shown.

[0044] Chip pads 320 and inner circuit layers 340 can be conductive layers, and interlayer dielectric layers 330 can be interposed between chip pads 320 and inner circuit layers 340. The parasitic capacitance generated between chip pads 320 and inner circuit layers 340 can be related to the dielectric constant of interlayer dielectric layers 330 and the surface area w of chip pads 320. The parasitic capacitance generated between the chip pad 320 and the inner circuit layer 340 is directly proportional to the thickness "d" of the interlayer dielectric layer 330, and inversely proportional to the thickness "d". Therefore, as the surface area of ​​the chip pad 320 decreases, the parasitic capacitance generated between the chip pad 320 and the inner circuit layer 340 decreases. Hereinafter, the parasitic capacitance generated between the chip pad 320 and the inner circuit layer 340 in the semiconductor chip is referred to as "pad parasitic capacitance".

[0045] Refer to together Figure 3 and Figure 4 When the chip pad with the smaller surface area among the first chip pad 220a and the second chip pad 220b is electrically connected to the corresponding chip connection pad 120, the parasitic capacitance of the semiconductor chip 20 in the semiconductor package 1 can be relatively small. On the other hand, when the chip pad with the larger surface area among the first chip pad 220a and the second chip pad 220b is connected to the corresponding chip connection pad 120, the parasitic capacitance of the semiconductor chip 20 in the semiconductor package 1 can be relatively large. That is, each of the first chip pad 220a and the second chip pad 220b of the semiconductor chip 20 can have a parasitic capacitance proportional to its surface area.

[0046] Figure 5 This is a circuit diagram of a chip pad selection circuit for a semiconductor chip according to an embodiment of the present disclosure. The chip pad selection circuit 240 can be set in... Figure 1 and Figure 3 In the semiconductor chip 20 of the semiconductor package 1.

[0047] Figure 5 The chip pad selection circuit 240 shown can be connected to the signal input / output circuit 201 and the chip pad unit 220 in the chip body 210. In one embodiment, the chip pad selection circuit 240 can be disposed between the signal input / output circuit 201 and the chip pad unit 220 in the chip body 210. The chip pad selection circuit 240 can be disposed within the chip body 210. The chip pad selection circuit 240 can be configured to correspond to each of the plurality of chip pad units 220.

[0048] The chip pad selection circuit 240 can be configured to select one chip pad from the first chip pad 220a and the second chip pad 220b and electrically connect the selected chip pad to the signal input / output circuit 201. As an example, the chip pad selection circuit 240 can be configured to electrically connect one of the first chip pads 220a and the second chip pad 220b to the signal input / output circuit 201, and electrically disconnect the other chip pad from the signal input / output circuit 201. In an embodiment, when performing electrical testing on an internal integrated circuit, the chip pad selection circuit 240 can provide one of the first chip pads 220a and the second chip pad 220b as a chip test pad via electrical connection. When the internal integrated circuit is electrically connected to a package substrate, the chip pad selection circuit 240 can provide the other chip pad from the first chip pad 220a and the second chip pad 220b as a bonding pad via electrical connection.

[0049] The following will refer to Figure 5 The operation of the chip pad selection circuit 240 is illustrated schematically. First, signal information S transmitted from the signal input / output circuit 201 electrically connected to the internal integrated circuit is input to the input buffer 410. The input buffer 410 transmits the signal information S to the first transfer transistor 430 and the second transfer transistor 440. At this time, a separate control signal OPT can be input to the input terminal of the inverter 420 connected to the first transfer transistor 430 and the second transfer transistor 440.

[0050] When the control signal OPT is high, the inverted control signal OPTB output from the inverter turns on the first transfer transistor 430, and the signal information S can be output to the first chip pad 220a through the first buffer 450 and the second buffer 460. The transmission of the signal information is shown as a first signal path R1. In this case, a first transistor 492 can be provided on the first signal path R1 to prevent signal transmission failure. The first transistor 492 can be controlled by the inverted control signal OPTB.

[0051] Furthermore, when the control signal OPT is a "low" level signal, the inverted control signal OPTB output from the inverter 420 turns on the second transfer transistor 440, and the signal information S can be output to the second chip pad 220b through the third buffer 470 and the fourth buffer 480. The transmission of the signal information S is shown as a second signal path R2. In this case, a second transistor 494 can be provided on the second signal path R2 to prevent signal transmission failure. The second transistor 494 can be controlled by the control signal OPT.

[0052] Refer again Figure 5 One of the first chip pad 220a and the second chip pad 220b can be used as a bonding pad. That is, one of the first chip pad 220a and the second chip pad 220b can be bonded to... Figure 1 and Figure 2 The substrate body 110 has corresponding chip connection pads 120. The other of the first chip pad 220a and the second chip pad 220b can be used as a chip test pad. The chip test pad can be used as a pad for testing a test device for the semiconductor chip 20, which is electrically connected to the internal integrated circuit of the semiconductor chip 20.

[0053] In this implementation, the chip pad selection circuit 240 can electrically connect the signal input / output circuit 201 to the chip test pad during testing of the semiconductor chip 20 using a test apparatus. In this case, the signal input / output circuit 201 and the bonding pad can maintain an electrically open circuit state. After the tested semiconductor chip 20 is bonded to the package substrate 10, the chip pad selection circuit 240 can electrically connect the signal input / output circuit 201 to the bonding pad and electrically disconnect the signal input / output circuit 201 from the chip test pad. Therefore, after the semiconductor package 1 is completed, the internal integrated circuit can maintain an electrical connection with the bonding pad and an electrically open circuit with the chip test pad.

[0054] In embodiments of this disclosure, the reference for selecting the bonding pad and the chip test pad among the first chip pad 220a and the second chip pad 220b can be the length of the wiring from the chip connection pad 120 of the package substrate 10 that overlaps with the first chip pad 220a and the second chip pad 220b to the corresponding connection structure, as shown below. Figure 6 Described.

[0055] Figure 6 This is a plan view of a semiconductor package according to an embodiment of the present disclosure. Figure 6 It can be Figure 3 Semiconductor chip 20 is installed Figure 2 A diagram showing the upper surface 110S1 of the packaging substrate 10. Additionally, Figure 6 It can be Figure 1 The diagram shows a plan view of semiconductor package 1.

[0056] Reference Figure 1 , Figure 2 and Figure 6A plurality of chip pad units 220 on the first surface 210S1 of the semiconductor chip 20 may be configured to face and overlap with a plurality of chip connection pads 120 on the upper surface 110S1 of the packaging substrate 10. Each of the plurality of chip pad units 220 may include a first chip pad 220a and a second chip pad 220b configured to be spaced apart from each other in the x-direction and may have different surface areas. (Refer to...) Figure 6 In one embodiment, the first chip pad 220a may have a smaller surface area than the second chip pad 220b. (Refer to...) Figure 1 , Figure 2 and Figure 6 In each of the plurality of chip pad units 220, the first chip pad 220a and the second chip pad 220b can be configured to overlap with the corresponding chip connection pad 120.

[0057] In this embodiment, for each of the plurality of chip pad units 220, the chip connection pad 120 overlapping with one chip pad unit 220 can be electrically connected to the connection structure 140 via wiring 150. In this case, based on the length of the wiring 150 connecting the connection structure 140 to the chip connection pad 120, a bonding pad to be bonded to the chip connection pad 120 can be determined from the first chip pad 220a and the second chip pad 220b of the chip pad unit 220. Additionally, when one of the first chip pad 220a and the second chip pad 220b is determined to be a bonding pad, the other chip pad can be determined to be a chip test pad. The process of determining the bonding pad and the chip test pad can be performed before the semiconductor chip 20 is mounted on the package substrate 10. In this embodiment, operational testing of the internal integrated circuits of the semiconductor chip 20 can be performed using the determined chip test pad, and then, when the semiconductor chip 20 is mounted on the package substrate 10, the bonding pad can be bonded to the chip connection pad 120 of the package substrate 10.

[0058] In the implementation method, refer together Figure 1 , Figure 2 and Figure 6 Two connection structures 140a and 140b can be selected from a plurality of connection structures 140. In an embodiment, the method of selecting the two connection structures 140a and 140b can be determined by the design configuration of the package substrate 10. For example, depending on the function and purpose of the semiconductor package, the design configuration may include various arrangement configurations for connecting pads 130, connection structures 140, and wiring 150. In an embodiment, such as Figure 1 , Figure 2 and Figure 6As shown, two connection structures 140a and 140b adjacent to each other along the x-direction and two connection pads 130a and 130b can be selected. Additionally, two chip connection pads 120 electrically connected to the two connection pads 130a and 130b via wiring 150 can be identified.

[0059] The first connection structure 140a of the two connection structures 140a and 140b can be connected to a corresponding chip connection pad 120 via a first wiring 150a and a first connection pad 130a. The second connection structure 140b of the two connection structures 140a and 140b can be connected to another corresponding chip connection pad 120 via a second wiring 150b and a second connection pad 130b. Figure 1 , Figure 2 and Figure 6 As shown, the length of the first wiring 150a having the first outer layer circuit a1 may be shorter than the length of the second wiring 150b having the second outer layer circuit b1. In this case, a chip connection pad 120 connected to the first wiring 150a can be bonded to the second chip pad 220b with the larger surface area, which is the first chip pad 220a and the second chip pad 220b. Another chip connection pad 120 connected to the second wiring 150b can be bonded to the first chip pad 220a with the smaller surface area, which is the first chip pad 220a and the second chip pad 220b.

[0060] In the first wiring 150a and the second wiring 150b respectively connected to the first connection structure 140a and the second connection structure 140b, the shorter first wiring 150a exhibits a relatively smaller package parasitic capacitance on the signal path compared to the second wiring 150b. In this case, the chip connection pad 120 connected to the first wiring 150a can bond to the second chip pad 220b with a relatively large surface area. Therefore, the signal path from the chip connection pad 120 through the second chip pad 220b to the internal integrated circuit can have a relatively large pad parasitic capacitance. As a result, the signal path from the first connection structure 140a through the first connection pad 130a, the first wiring 150a, the chip connection pad 120, and the second chip pad 220b to the internal integrated circuit can have a relatively small package parasitic capacitance and a relatively large pad parasitic capacitance.

[0061] Furthermore, in the first wiring 150a and the second wiring 150b, the longer second wiring 150b can exhibit a relatively large package parasitic capacitance on the signal path compared to the first wiring 150a. In this case, another chip connection pad 120 connected to the second wiring 150b can be bonded to the first chip pad 220a, which has a relatively small surface area. Therefore, the signal path from the other chip connection pad 120 through the first chip pad 220a to the internal integrated circuit can have a relatively small pad parasitic capacitance. As a result, the signal path from the second connection structure 140b through the second connection pad 130b, the second wiring 150b, the other chip connection pad 120, and the first chip pad 220a to the internal integrated circuit can have a relatively large package parasitic capacitance and a relatively small pad parasitic capacitance.

[0062] Using the method described above, the chip connection pads 120 of the package substrate 10, which are respectively connected to multiple connection structures 140, can be bonded to the chip pad units 220 of the semiconductor chip 20. In embodiments of this disclosure, the difference in package parasitic capacitance generated in the package substrate 10 due to the difference in wiring length between multiple wirings 150 can be offset by the difference in pad parasitic capacitance generated by chip pads of different sizes in the semiconductor chip 20. In other words, the deviation of the sum of the package parasitic capacitance and the pad parasitic capacitance generated in each of the multiple signal paths passing through the multiple chip connection pads 120 of the semiconductor package can be reduced.

[0063] As a result, the deviation of the sum of parasitic capacitances generated in each of the multiple connection structures of the package substrate through the corresponding chip connection pads and the chip pads of the semiconductor chip to the internal integrated circuit of the semiconductor chip can be reduced. Consequently, the electrical reliability of the semiconductor package can be improved by reducing the deviation of the transmission characteristics of the electrical signals generated for each of the multiple connection structures.

[0064] Figure 7 This is a schematic plan view of a semiconductor chip according to another embodiment of the present disclosure. Figure 8 This is an illustrative representation of joining to another embodiment of this disclosure. Figure 7 A plan view of the packaging substrate for a semiconductor chip. Figure 9 This is a plan view of a semiconductor package according to another embodiment of the present disclosure. More specifically, the semiconductor package 2 can be... Figure 7 Semiconductor chip 21 is installed Figure 8 The encapsulation is performed on the encapsulation substrate 11.

[0065] Reference Figure 7 , Figure 8 and Figure 9Semiconductor package 2 can be combined with the above in terms of the configuration of semiconductor chip 21. Figures 1 to 6 The semiconductor package described is different in phase 1. More specifically, Figure 7 The configuration of the chip pad structure 2200 of the semiconductor chip 21 shown may differ from that described above. Figure 3 The configuration of the chip pad unit 220 of the semiconductor chip 20 is described. Figure 7 The chip pad structure 2200 may include a plurality of input / output pad units 2220 and at least one control pad unit 2230 disposed on the surface 210S1 of the chip body 210.

[0066] Multiple input / output pad units 2220 and at least one control pad unit 2230 may be configured to be spaced apart from each other along a third direction (e.g., the y-direction). In one embodiment, the multiple input / output pad units 2220 and at least one control pad unit 2230 may be configured to form a column L2. Alternatively, in one embodiment, the multiple input / output pad units 2220 and at least one control pad unit 2230 may be arranged in two columns L2 parallel to each other in the y-direction. Although... Figure 7 The diagram shows one control pad unit 2230, but this disclosure is not limited thereto, and two or more control pad units 2230 may be provided.

[0067] The configuration of multiple input / output pad units 2220 can be referenced above. Figure 3 The semiconductor chip 20 described has a plurality of chip pad units 220 configured substantially identically. Each of the plurality of input / output pad units 2220 may include a first chip pad 2220a and a second chip pad 2220b configured to be spaced apart from each other in the x-direction. In this case, the first chip pad 2220a may have a different surface area than the second chip pad 2220b. In an embodiment, as Figure 7 As shown, the first chip pad 2220a may have a smaller surface area than the second chip pad 2220b. Multiple first chip pads 2220a may be arranged in a row along the y-direction. Multiple second chip pads 2220b may also be spaced apart from the multiple first chip pads 2220a to form a row along the y-direction. On the other hand, at least one control pad unit 2230 may be a single, inseparable pad.

[0068] Reference Figure 8 The configuration of the packaging substrate 11 can be combined with the above. Figure 1 and Figure 2The configuration of the package substrate 10 described is substantially the same. A plurality of chip connection pads 120 may be disposed on the upper surface 110S1 of the substrate body 110. The plurality of chip connection pads 120 may be arranged in a column L3 along a third direction (e.g., the y-direction). In an embodiment, the plurality of chip connection pads 120 may be arranged in two columns L3 parallel to each other in the y-direction. (See also...) Figure 1 and Figure 8 Multiple connection pads 130 may be disposed on the lower surface 110S2 of the substrate body 110. Similarly, refer to... Figure 1 and Figure 8 , Figure 1 The connection structure 140 can be set on the corresponding connection pad 130.

[0069] Refer to together Figure 1 and Figure 8 In this embodiment, the first connection structure 140a can be electrically connected to a corresponding first chip connection pad 120a among the plurality of chip connection pads 120 via the first connection pad 130a and the first wiring 150a. The second connection structure 140b can be electrically connected to a corresponding second chip connection pad 120b among the plurality of chip connection pads 120 via the second connection pad 130b and the second wiring 150b. A third connection structure (not shown) disposed on the third connection pad 130c can be electrically connected to a corresponding third chip connection pad 120c among the plurality of chip connection pads 120 via the third wiring 150c.

[0070] In an implementation, the first chip connection pad 120a can be configured to be connected to the chip located at... Figure 7 The input / output pad unit 2220 in row A1 corresponds to the second chip connection pad 120b located in the... Figure 7 The input / output pad unit 2220 in row A2 corresponds to this. The third chip connection pad 120c can be configured to be located with the input / output pad unit 2220 in row A2. Figure 7 The control pad unit 2230 in row A3 corresponds to this.

[0071] exist Figure 9 In semiconductor package 2, Figure 7 The chip pad structure 2200 of the semiconductor chip 21 and Figure 8 The plurality of chip connection pads 120 of the packaging substrate 11 can be configured to face each other in the z-direction. In addition, the chip pad structure 2200 of the semiconductor chip 21 can be configured to overlap with the plurality of chip connection pads 120 of the packaging substrate 11 in the z-direction.

[0072] Reference Figure 9 , Figure 8The first chip connection pad 120a can be electrically bonded to one of the first chip pad 2220a and the second chip pad 2220b of the input / output pad unit 2220 located in row A1. Figure 8 The second chip connection pad 120b can be electrically bonded to one of the first chip pad 2220a and the second chip pad 2220b of the input / output pad unit 2220 located in row A2. Figure 8 The third chip connection pad 120c can be electrically bonded to the control pad unit 2230 located in row A3.

[0073] Furthermore, when a control signal is input from an electronic device outside the semiconductor package 2, the control signal can be input from the external electronic device to the third connection pad 130c through the third connection structure of the package substrate 11. The input control signal can be transmitted to the control pad unit 2230 located in row A3 of the semiconductor chip 21 via the third wiring 150c and the third chip connection pad 120c.

[0074] The control signal transmitted to the control pad unit 2230 can be transmitted to a chip pad selection circuit inside the chip body 210 connected to the control pad unit 2230. The chip pad selection circuit can electrically connect one of the first chip pad 2220a and the second chip pad 2220b of the input / output pad unit 2220 to a signal input / output circuit in the chip body 210 based on the control signal. Therefore, the internal integrated circuit of the semiconductor chip 21 can be electrically connected to a chip pad via the signal input / output circuit. The method of selecting a chip pad using the control signal transmitted through the control pad unit 2230 will be described below. Figure 10 and Figure 11 The chip pad selection circuit 245 is described in more detail.

[0075] In one implementation, a control pad unit 2230 may collectively participate in connecting one of the first chip pad 2220a and the second chip pad 2220b to the signal input / output circuitry in each of at least two input / output pad units 2220. As an example, a control signal input to the control pad unit 2230 in row A3 may perform an operation to determine chip pads to be connected together to the signal input / output circuitry 201 in the input / output pad units 2220 in row A1 and in row A2. As another example, a control signal input to the control pad unit 2230 in row A3 may perform an operation to determine chip pads to be connected together to the signal input / output circuitry 201 in each input / output pad unit 2220 located in a single column L2.

[0076] Figure 10This is a schematic circuit diagram illustrating a chip pad selection circuit for a semiconductor chip according to an embodiment of the present disclosure. Figure 11 This is a schematic cross-sectional view of a semiconductor package having a chip pad selection circuit according to an embodiment of the present disclosure. Figure 11 The cross-sectional view can be implemented in a semiconductor chip. Figure 10 A schematic diagram of the circuit. Additionally, Figure 10 and Figure 11 The semiconductor chip 21 with chip pad selection circuit 245 can be applied to Figure 7 and Figure 9 2. Semiconductor package 2. Chip pad selection circuit 245 can be set to... Figure 7 The semiconductor chip 21 is in the chip body 210.

[0077] Reference Figure 10 and Figure 11 The chip pad selection circuit 245 can be connected to the signal input / output circuit 201 in the chip body 210 and the chip pad structure 2200 disposed on the surface 210S1 of the chip body 210. The chip pad selection circuit 245 can be disposed within the chip body 210. The chip pad selection circuit 245 can be configured to... Figure 7 Each of the multiple input / output pad units 2220 corresponds to one of them.

[0078] The chip pad selection circuit 245 can be configured to select one of the first chip pad 2220a and the second chip pad 2220b of the input / output pad unit 2220 and electrically connect the selected chip pad to the signal input / output circuit 201. As an example, the chip pad selection circuit 245 can electrically connect one of the first chip pad 2220a and the second chip pad 2220b to the signal input / output circuit 201, and electrically disconnect the other of the first chip pad 2220a and the second chip pad 2220b from the signal input / output circuit 201. Although not shown, the signal input / output circuit 201 can be electrically connected to an internal integrated circuit disposed in the chip body 210.

[0079] In this embodiment, when performing electrical operation tests on the internal integrated circuit of the semiconductor chip 21, the chip pad selection circuit 245 can provide one of the first chip pad 2220a and the second chip pad 2220b as a chip test pad via electrical connection. Additionally, when the semiconductor chip 21 is mounted on the package substrate 11, the chip pad selection circuit 245 can provide the other of the first chip pad 2220a and the second chip pad 2220b as a bonding pad for bonding the package substrate 11 to the semiconductor chip 21.

[0080] Reference Figure 10The operation of the chip pad selection circuit 245 is illustrated schematically. First, signal information S is transmitted from the signal input / output circuit 201, electrically connected to the internal integrated circuit, to the source terminals of the first switching transistor 2401 and the second switching transistor 2402. As an example, the first switching transistor 2401 may be an n-channel field-effect transistor (NMOS FET), and the second switching transistor 2402 may be a p-channel field-effect transistor (PMOS FET).

[0081] In this configuration, the control signal CS can be input from the control pad unit 2230 of the chip pad structure 2200 to the semiconductor chip 21. The control signal CS can be transmitted from an external electronic device connected to the semiconductor package 2 via the package substrate 11 to the control pad unit 2230. When the control signal CS is at a "high" level, the first switching transistor 2401 is turned on, and the signal information S can be output to the first chip pad 2220a via the first signal path R1a. In this configuration, the second switching transistor 2402 remains off. Additionally, when the control signal CS is at a "high" level, the signal information S input to the first chip pad 2220a can be input to the signal input / output circuit 201 via the turned-on first switching transistor 2401.

[0082] Furthermore, when the control signal CS is at a "low" level, the second switching transistor can be turned on, and the signal information S can be output to the second chip pad 2220b via the second signal path R2a. In this case, the first switching transistor 2401 can remain in the off state. Additionally, when the control signal CS is at a "low" level, the signal information S input to the second chip pad 2220b can be input to the signal input / output circuit 201 via the turned-on second switching transistor 2402.

[0083] Refer again Figure 10 One of the first chip pad 2220a and the second chip pad 2220b can be designated as the chip test pad. Before the semiconductor chip 21 is mounted on the package substrate 11, a test process for the internal integrated circuit of the semiconductor chip 21 can be performed. The chip test pad can be used during the test process as a connection pad provided for electrical connection of a test device to the internal integrated circuit of the semiconductor chip 21. In this case, the test device can also be connected to the control pad unit 2230. The test device can determine the chip test pad among the first chip pad 2220a and the second chip pad 2220b by inputting a control signal CS to the control pad unit 2230.

[0084] Furthermore, the other of the first chip pad 2220a and the second chip pad 2220b can be designated as a bonding pad. After the testing process of the internal integrated circuit is completed, the semiconductor chip 21 can be mounted on the packaging substrate 11. At this time, the bonding pad between the first chip pad 2220a and the second chip pad 2220b can be defined as follows: Figure 9 The corresponding chip connection pads 120 are bonded to the upper surface 110S1 of the substrate body 110.

[0085] After the semiconductor chip 21 is electrically connected to the package substrate 11 via bonding pads, a control signal CS can be provided from an electronic device located outside the semiconductor package 2. In an embodiment, as shown in reference... Figure 9 The control signal CS can be input from the electronic device to the third connection structure of the packaging substrate 11, and the input control signal CS can reach the control pad unit 2230 of the semiconductor chip 21 via the third connection pad 130c, the third wiring 150c, and the third chip connection pad 120c. The control signal CS input from the electronic device to the control pad unit 2230 can determine the bonding pad between the first chip pad 2220a and the second chip pad 2220b. The bonding pad can be a chip pad other than the chip test pad connected to the test device when performing a test process on the internal integrated circuit.

[0086] Figure 11 This is a schematic cross-sectional view of a semiconductor structure having a chip pad selection circuit 245 with a semiconductor chip 21. The semiconductor structure may include a chip body 210 and a chip pad structure 2200. The chip pad structure 2200 may be disposed on a surface 210S1 of the chip body 210. The chip pad structure 2200 may include an input / output pad unit 2220 and a control pad unit 2230. The input / output pad unit 2220 may include a first chip pad 2220a and a second chip pad 2220b spaced apart from each other.

[0087] The chip body 210 may include a chip substrate 2001 and an insulating structure 2010 stacked on the chip substrate 2001. The insulating structure 2010 may include an internal insulating layer 2012 disposed on the upper surface 2001S of the chip substrate 2001 and a passivation layer 2014 disposed on the internal insulating layer 2012. The chip body 210 may include a wiring structure disposed in the insulating structure 2010. The wiring structure may include first to fourth chip wirings “a”, “b”, “c”, and “d”.

[0088] The chip substrate 2001 may be a semiconductor substrate. In one embodiment, the chip substrate 2001 may be doped with a p-type dopant. The chip substrate 2001 may include an N-well region 2001W doped with an n-type dopant, which is the opposite of the p-type dopant. In this case, a plurality of field-effect transistors may be disposed on the chip substrate 2001. The plurality of field-effect transistors may include a first switching transistor 2401 and a second switching transistor 2402 with different channel types. As an example, the first switching transistor 2401 may be an n-channel field-effect transistor, and the second switching transistor 2402 may be a p-channel field-effect transistor.

[0089] The first switching transistor 2401 may include a source region 2401S and a drain region 2401D, both doped with n-type dopant and spaced apart from each other. The first switching transistor 2401 may include a gate dielectric layer 2401N and a gate electrode layer 2401G disposed on the chip substrate 2001 between the source region 2401S and the drain region 2401D. Furthermore, the second switching transistor 2402 may include a source region 2402S and a drain region 2402D, both doped with p-type dopant and spaced apart from each other, in the N-well region 2001W. The second switching transistor 2402 may include a gate dielectric layer 2402N and a gate electrode layer 2402G disposed on the chip substrate 2001 between the source region 2402S and the drain region 2402D.

[0090] Reference Figure 11 The drain region 2401D of the first switching transistor 2401 is electrically connected to the first chip pad 2220a of the input / output pad unit 2220 via a first chip wiring "a". The first chip wiring "a" may include a first circuit layer a2, a second circuit layer a4, a third circuit layer a6, and a fourth circuit layer a8. Additionally, the first chip wiring "a" may include a first contact plug a1 connecting the drain 2401D and the first circuit layer a2 to each other, a first contact via a3 connecting the first circuit layer a2 and the second circuit layer a4 to each other, a second contact via a5 connecting the second circuit layer a4 and the third circuit layer a6 to each other, a third contact via a7 connecting the third circuit layer a6 and the fourth circuit layer a8 to each other, and a redistribution line a9 connecting the fourth circuit layer a8 and the first chip pad 2220a to each other. The redistribution line a9 may be disposed in the passivation layer 2014. The remaining first chip wiring "a" except for the redistribution line a9 may be disposed in the internal insulating layer 2012.

[0091] The drain region 2402D of the second switching transistor 2402 is electrically connected to the second chip pad 2220b of the input / output pad unit 2220 via a second chip wiring "b". The second chip wiring "b" may include a first circuit layer b2, a second circuit layer b4, a third circuit layer b6, and a fourth circuit layer b8. Additionally, the second chip wiring b may include a first contact plug b1 connecting the drain 2402D and the first circuit layer b2 to each other, a first contact via b3 connecting the first circuit layer b2 and the second circuit layer b4 to each other, a second contact via b5 connecting the second circuit layer b4 and the third circuit layer b6 to each other, a third contact via b7 connecting the third circuit layer b6 and the fourth circuit layer b8 to each other, and a redistribution line b9 connecting the fourth circuit layer b8 and the second chip pad 2220b to each other. The redistribution line b9 may be disposed in the passivation layer 2014. The remaining second chip wiring "b" except for the redistribution line b9 may be disposed in the internal insulating layer 2012.

[0092] Furthermore, the gate electrode layer 2401G of the first switching transistor 2401 and the gate electrode layer 2402G of the second switching transistor 2402 can be electrically connected to the control pad unit 2230 via third chip wiring “c”, respectively. That is, the control pad unit 2230 can be jointly connected to the gate electrode layer 2401G of the first switching transistor 2401 and the gate electrode layer 2402G of the second switching transistor 2402, respectively. Each third chip wiring c may include a first circuit layer c2, a second circuit layer c4, and a third circuit layer c6. In addition, the third chip wiring c may include a contact plug c1 connecting the gate electrode layer 2401G of the first switching transistor 2401 and the gate electrode layer 2402G of the second switching transistor 2402 to the first circuit layer c2, a first contact via c3 connecting the first circuit layer c2 and the second circuit layer c4 to each other, a second contact via c5 connecting the second circuit layer c4 and the third circuit layer c6 to each other, and a redistribution line c7 connecting the third circuit layer c6 and the control pad unit 2230 to each other. The redistribution line c7 can be located in the passivation layer 2014. The remaining third chip wiring "c" besides the redistribution line c7 can be located in the inner insulating layer 2012.

[0093] Furthermore, the source region 2401S of the first switching transistor 2401 and the source region 2402S of the second switching transistor 2402 can be electrically connected to a signal input / output circuit (not shown) via a fourth chip wiring "d". The signal input / output circuit can be jointly connected to the source region 2401S of the first switching transistor 2401 and the source region 2402S of the second switching transistor 2402, respectively. Figure 10 The signal input / output circuit 201 in the circuit diagram.

[0094] The fourth chip wiring "d" may include a first circuit layer d2 and a contact plug d1 connecting the first circuit layer d2 and source regions 2401S and 2402S to each other. Although Figure 10 As not shown, the signal input / output circuit may include logic circuitry having multiple switching transistors disposed on the chip substrate 2001. Therefore, the first circuit layer d2 can be electrically connected to the multiple switching transistors disposed on the chip substrate 2001 via other contact plugs (not shown). The fourth chip wiring “d” may be disposed in the inner insulating layer 2012.

[0095] As described above, the chip pad structure 2200 disposed on the surface 210S of the chip body 210 is electrically connected to the first switching transistor 2401 and the second switching transistor 2402 disposed in the chip substrate 2001 via the first to fourth chip wirings "a", "b", "c" and "d". Based on the control signal input to the control pad unit 2230, one of the first switching transistor 2401 and the second switching transistor 2402 can be turned on, so that the signal input / output circuit can be electrically connected to one of the first chip pad 2220a and the second chip pad 2220b.

[0096] In addition, in combination Figures 7 to 11 In the described implementation, the method by which the chip pad selection circuit 245 determines the chip test pad and bonding pad from the first chip pad 220a and the second chip pad 220b based on the control signal CS can be combined with the above. Figure 1 , Figure 2 , Figure 3 and Figure 6 The methods described are essentially the same. That is, by employing a method to reduce the parasitic capacitance deviation of each wiring in the semiconductor package, one of the first chip pad 220a and the second chip pad 220b can be first identified as a bonding pad, and then the other of the first chip pad 220a and the second chip pad 220b can be identified as a chip test pad.

[0097] More specifically, refer to together Figures 7 to 9The following method can be used to determine the bonding pads. A pair of first chip connection pads 120a and second chip connection pads 120b, and a pair of first connection pads 130a and second connection pads 130b can be selected from the package substrate 11. First wiring 150a and second wiring 150b can respectively connect the first chip connection pads 120a and 120b to the first connection pads 130a and 130b. In this case, when the length of the second wiring 150b is relatively long, the second chip connection pad 120b can be determined to bond to the first chip pad 2220a with a relatively smaller surface area among the first chip pads 2220a and 2220b located in row A2 of the semiconductor chip 21. That is, in the input / output pad unit 2220 located in row A2, the first chip pad 2220a can be determined as a bonding pad to bond to the second chip connection pad 120b, and the second chip pad 2220b can be determined as a chip test pad. Furthermore, when the length of the first wiring 150a is relatively short, the first chip connection pad 120a can be determined to bond to the second chip pad 2220b with the relatively larger surface area among the first chip pad 2220a and the second chip pad 2220b located in row A1 of the semiconductor chip 21. That is, in the input / output pad unit 2220 located in row A1, the second chip pad 2220b can be determined to be a bonding pad to bond to the first chip connection pad 120a, and the first chip pad 2220a can be determined to be a chip test pad.

[0098] By applying essentially the same method as described above, the bonding pads of the semiconductor chip 21 to which the plurality of chip connection pads 120 disposed on the packaging substrate 11 are bonded can be determined. Additionally, chip test pads for testing the internal integrated circuits of the semiconductor chip 21 can be determined.

[0099] This teaching has been disclosed in conjunction with some embodiments described above. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and spirit of this disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictively but rather as illustrative. The scope of this teaching is not limited to the foregoing description but is defined by the appended claims, and all different features within the equivalent scope should be interpreted as being included within the inventive concept.

[0100] Cross-reference to related applications

[0101] This application claims priority to Korean Application No. 10-2020-0165149, filed on November 30, 2020, and Korean Application No. 10-2021-0035578, filed on March 18, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: The chip body includes signal input / output circuitry; A chip pad structure is disposed on the surface of the chip body, and the chip pad structure includes input / output pad units and control pad units; and A chip pad selection circuit is disposed in the chip body and electrically connected to the signal input / output circuit and the chip pad structure. The input / output pad unit includes a first chip pad and a second chip pad, which have different surface areas. The chip pad selection circuit selects one of the first and second chip pads based on a control signal input from the control pad unit and electrically connects the selected chip pad to the signal input / output circuit. The chip body includes: Chip substrate; Multiple field-effect transistors are disposed in the chip substrate; An insulating structure disposed on the chip substrate and between the plurality of field-effect transistors and the chip pad structure; and A wiring structure, which is disposed within the insulation structure. The chip pad structure is electrically connected to the plurality of field-effect transistors via the wiring structure, and the plurality of field-effect transistors are connected to the signal input / output circuit. The wiring structure includes: Multiple circuit layers are configured to be spaced apart from each other in a direction perpendicular to the surface of the chip substrate; A contact plug that electrically connects the lowest of the plurality of circuit layers to the chip substrate; Contact vias that connect the plurality of circuit layers to each other; and A redistribution line that electrically connects the topmost of the plurality of circuit layers to the chip pad structure.

2. The semiconductor chip according to claim 1, wherein, The chip pad selection circuit also electrically disconnects the other unselected chip pad from the signal input / output circuit.

3. The semiconductor chip according to claim 1, wherein, Each of the first chip pad and the second chip pad has a surface area and a pad parasitic capacitance proportional to the surface area.

4. The semiconductor chip according to claim 1, wherein, The plurality of field-effect transistors include a first switching transistor and a second switching transistor having different channel types from each other.

5. The semiconductor chip according to claim 4, wherein, One of the first and second switching transistors is an n-channel field-effect transistor, and the other of the first and second switching transistors is a p-channel field-effect transistor.

6. The semiconductor chip according to claim 4, in, The wiring structure includes a first chip wiring, a second chip wiring, a third chip wiring, and a fourth chip wiring, and Specifically, the first chip wiring electrically connects the drain region of the first switching transistor to the first chip pad. The second chip wiring electrically connects the drain region of the second switching transistor to the second chip pad. The third chip wiring electrically connects the gate electrode layer of each of the first and second switching transistors to the control pad unit, and The fourth chip wiring electrically connects the source region of each of the first and second switching transistors to the signal input / output circuit.

7. A semiconductor package comprising: Packaging substrate; as well as A semiconductor chip, which is disposed on the packaging substrate, The packaging substrate includes: Substrate body; and Multiple chip connection pads are disposed on the surface of the substrate body. The semiconductor chip includes: The chip body; and A chip pad structure is disposed on the surface of the chip body. The chip pad structure includes multiple input / output pad units and at least one control pad unit. The plurality of input / output pad units and the at least one control pad unit correspond to the plurality of chip connection pads, respectively. Each of the plurality of input / output pad units includes a first chip pad and a second chip pad spaced apart from each other, the first chip pad and the second chip pad having different surface areas, and Wherein, one of the first chip pads and the second chip pads is electrically connected to the corresponding chip connection pad among the plurality of chip connection pads. The chip body includes: Chip substrate; Multiple field-effect transistors are disposed in the chip substrate; An insulating structure disposed on the chip substrate, the insulating structure being disposed between the plurality of field-effect transistors and the chip pad structure; and A wiring structure, which is disposed within the insulation structure. The chip pad structure is electrically connected to the plurality of field-effect transistors through the wiring structure, and The wiring structure includes: Multiple circuit layers are configured to be spaced apart from each other in a direction perpendicular to the surface of the chip substrate; A contact plug that electrically connects the lowest of the plurality of circuit layers to the chip substrate; Contact vias that connect the plurality of circuit layers to each other; and A redistribution line that electrically connects the topmost of the plurality of circuit layers to the chip pad structure.

8. The semiconductor package according to claim 7, wherein, The semiconductor chip also includes: Signal input / output circuitry, which is disposed within the chip body; and A chip pad selection circuit is provided, which is connected to the signal input / output circuit and the chip pad structure. The chip pad selection circuit electrically connects one of the first chip pads and the second chip pads to the signal input / output circuit based on a control signal input from the at least one control pad unit.

9. The semiconductor package according to claim 7, wherein, The plurality of field-effect transistors include a first switching transistor and a second switching transistor, wherein the first switching transistor and the second switching transistor have different channel types, and In this configuration, one of the first and second switching transistors is an n-channel field-effect transistor, and the other of the first and second switching transistors is a p-channel field-effect transistor.

10. The semiconductor package according to claim 9, in, The wiring structure includes a first chip wiring, a second chip wiring, a third chip wiring, and a fourth chip wiring. Specifically, the first chip wiring electrically connects the drain region of the first switching transistor to the first chip pad of the corresponding input / output pad unit among the plurality of input / output pad units. Specifically, the second chip wiring electrically connects the drain region of the second switching transistor to the second chip pad of the input / output pad unit among the plurality of input / output pad units. The third chip wiring electrically connects the gate electrode layer of each of the first and second switching transistors to the corresponding control pad unit in the at least one control pad unit, and The fourth chip wiring electrically connects the source region of each of the first and second switching transistors to the signal input / output circuit.

11. The semiconductor package of claim 10, wherein, The control signal input to the control pad unit turns on one of the first and second switching transistors.

12. The semiconductor package according to claim 8, in, In the plurality of input / output pad units, one of the first chip pads and the second chip pads is a bonding pad that is electrically connected to a corresponding chip connection pad among the plurality of chip connection pads, and the other chip pad among the first chip pads and the second chip pads is a test pad that is provided to be connected to a test device for testing the internal integrated circuits of the semiconductor chip.

13. The semiconductor package according to claim 12, wherein, The signal input / output circuit is electrically connected to the chip connection pad via the bonding pad.

14. The semiconductor package of claim 7, further comprising: Multiple connection pads are disposed on the lower surface of the substrate body; as well as Multiple wirings electrically connect the multiple chip connection pads to the corresponding connection pads.

15. The semiconductor package according to claim 14, further comprising a first connection structure and a second connection structure, wherein the first connection structure and the second connection structure are respectively disposed on a first connection pad and a second connection pad among the plurality of connection pads. in, The first connection structure is electrically connected to a first chip connection pad among the plurality of chip connection pads via a first wiring, and the second connection structure is electrically connected to a second chip connection pad among the plurality of chip connection pads via a second wiring. Wherein, the length of the first wiring is shorter than the length of the second wiring, and The first chip connection pad is electrically connected to the chip pad with the larger surface area in the first chip pad and the second chip pad of the corresponding chip pad unit in the plurality of chip pad units, and the second chip connection pad is electrically connected to the chip pad with the smaller surface area in the first chip pad and the second chip pad of the corresponding chip pad unit in the plurality of chip pad units.

16. The semiconductor package of claim 15, further comprising a third chip connection structure disposed on a third connection pad among the plurality of connection pads. in, The third chip connection structure is connected to the third chip connection pad among the plurality of chip connection pads, and The third chip connection pad is electrically connected to at least one control pad unit of the semiconductor chip.

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