Semiconductor device

Abstract

The present disclosure relates to a semiconductor device with reduced power consumption. The device includes an n-type well region located on a main surface of a semiconductor body; an element isolation region located on the main surface; first and second active regions located in the n-type well region and surrounded by the element isolation region; an insulating film located on the main surface in the first active region; a semiconductor layer located on the insulating film; a gate electrode layer located on the semiconductor layer by a gate insulating film; p-type source and drain regions formed in the semiconductor layer at two end portions of the gate electrode layer; a dummy gate electrode layer located on the semiconductor layer by the gate insulating film; an n-type semiconductor region located on an n-type well region surface in the second active region; and a power supply wiring coupled with the n-type semiconductor region. The dummy gate electrode layer is electrically floating.

Description

[0001] This application is a divisional application of the application filed on October 26, 2016, with application number 201610947452X and title "Semiconductor Device". Technical Field

[0002] This invention relates to semiconductor devices, and more particularly, to techniques for semiconductor devices having SRAM disposed on an SOI substrate. Background Technology

[0003] Japanese Unexamined Patent Application Publication No. 2009-135140 discloses a semiconductor device including PMOS and NMOS transistors having a thin-film BOX-SOI structure. The semiconductor device has a semiconductor support substrate, an insulating film having a thickness of less than 10 nm, and a semiconductor layer, wherein the PMOS and NMOS transistors are formed in the surface of the semiconductor layer. A well region is located below the semiconductor layer, extending through the insulating film having a thickness of less than 10 nm, and the threshold voltages of the PMOS and NMOS transistors are changed by applying a desired voltage to the well region. Summary of the Invention

[0004] The inventors of this invention have studied a semiconductor device having SRAM memory cells, which include NMOS and PMOS transistors with a thin-film BOX-SOI structure. Each SRAM memory cell includes two PMOS load transistors, two NMOS driver transistors, and two access transistors. The two load transistors are formed in an n-type well region, and the two driver transistors and two access transistors are formed in a p-type well region.

[0005] This SRAM memory cell is arranged in a matrix pattern on a semiconductor substrate along the X and Y directions to configure a memory array, and this memory cell is arranged in a matrix pattern along the X and Y directions.

[0006] P-well and n-well regions extending along the Y-direction are continuously located in multiple memory arrays, and tap regions of desired width extending along the X-direction are located between adjacent memory arrays along the Y-direction. The tap regions are areas that supply power to the p-well and n-well regions, wherein power wiring supplying a first potential to the p-well region and power wiring supplying a second potential to the n-well region extend along the X-direction.

[0007] An SRAM memory cell includes multiple gate electrode layers (gate conductor film, gate conductor strip) that configure gate electrodes for load transistors, driver transistors, and access transistors. In the tap region, no memory cell is disposed, but multiple dummy gate electrode layers are located in the same layers as the gate electrode layers, and these dummy gate electrode layers are coupled to power supply wiring. In other words, a first potential or a second potential is provided to the dummy gate strip.

[0008] However, the inventors of this invention have discovered that leakage current occurs in the region where the dummy gate electrode layer is located in the tap region, making it difficult to reduce the power consumption of the semiconductor device.

[0009] Therefore, there is a need for technologies that can reduce the power consumption of semiconductor devices with SRAM memory cells (which have a thin-film BOX-SOI structure).

[0010] The above and other objects and novel features of the present invention will become clear from the detailed description in the following specification and drawings.

[0011] According to one aspect of the present invention, a semiconductor device is provided, comprising: an n-type well region formed on a main surface of a semiconductor substrate; a device isolation region formed on the main surface of the semiconductor substrate; and a first active region and a second active region located in the n-type well region and surrounded by the device isolation region. The device further comprises: an insulating film formed on the main surface of the semiconductor substrate in the first active region; a semiconductor layer formed on the insulating film; a gate electrode layer formed on the semiconductor layer through the gate insulating film; a p-type source region and a p-type drain region formed in the semiconductor layer at two ends of the gate electrode layer; and a dummy gate electrode layer formed on the semiconductor layer through the gate insulating film. The device further comprises: an n-type semiconductor region formed on the surface of the n-type well region in the second active region; and power wiring coupled to the n-type semiconductor region. The dummy gate electrode layer is electrically floating.

[0012] According to the present invention, the power consumption of semiconductor devices can be reduced. Attached Figure Description

[0013] Figure 1 This is an equivalent circuit diagram showing a storage cell in an SRAM according to a preferred embodiment of the present invention;

[0014] Figure 2 This is a table showing the well region potentials and thresholds for PMOS and NMOS transistors according to embodiments;

[0015] Figure 3 This is a plan view showing the structure of a storage cell of an SRAM according to an embodiment;

[0016] Figure 4This is a plan view showing the structure of a storage cell of an SRAM according to an embodiment;

[0017] Figure 5 This is a plan view showing the structure of a storage cell of an SRAM according to an embodiment;

[0018] Figure 6 It is along Figure 3 A cross-sectional view taken from line AA;

[0019] Figure 7 It is along Figure 3 A cross-sectional view of line BB;

[0020] Figure 8 This is a plan view conceptually illustrating the location of the tap region in the SRAM region according to an embodiment;

[0021] Figure 9 This is a plan view showing the memory array and tap area in the SRAM region according to an embodiment;

[0022] Figure 10 It is along Figure 9 A cross-sectional view taken from line CC;

[0023] Figure 11 It is along Figure 9 A cross-sectional view of line DD;

[0024] Figure 12 This is a cross-sectional view illustrating a comparative example conceived by the inventors of the present invention; and

[0025] Figure 13 This is a cross-sectional view illustrating a comparative example conceived by the inventors of the present invention. Detailed Implementation

[0026] Preferred embodiments of the invention are described below in different sections or separately as needed or for convenience, but the described embodiments are not unrelated unless explicitly indicated otherwise. One embodiment may be a modification, refinement, or supplement to another embodiment, either wholly or in part. In the preferred embodiments described below, when numerical information (numbers, values, quantities, ranges, etc.) of an element is given by a specific number, it is not limited to that specific number unless explicitly specified otherwise or theoretically limited to that specific number; it may be greater than or less than that specific number. In the preferred embodiments described below, constituent elements (including constituent steps) are not necessary unless explicitly specified otherwise or theoretically necessary. Similarly, in the preferred embodiments described below, when a specific form or positional relationship is indicated for an element, it should be interpreted as including forms or positional relationships equivalent to or similar to that specific form or positional relationship, unless explicitly specified otherwise or theoretically limited to that specific form or positional relationship. This also applies to the numerical values ​​and ranges described above.

[0027] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings. In all the drawings illustrating the embodiments, components having similar functions are indicated by similar reference numerals, and repeated descriptions are omitted. For the embodiments described below, the same or similar elements or things will not be described again unless necessary.

[0028] In the accompanying drawings illustrating the embodiments, section lines are omitted even in the cross-sectional views for ease of understanding, and section lines may be used in the plan views for ease of understanding.

[0029] First Embodiment

[0030] The semiconductor device (semiconductor integrated circuit device, semiconductor memory device) according to this embodiment has an SRAM region. The SRAM region includes multiple memory arrays (memory array regions) MA and tap regions TAP located between the memory arrays MA. Each memory array MA includes multiple memory cells MC arranged in a matrix pattern.

[0031] Storage cell circuit structure

[0032] First, the circuit structure of the memory cell MC in the SRAM of the semiconductor device (semiconductor integrated circuit device, semiconductor memory device) according to this embodiment will be described. Figure 1This is an equivalent circuit diagram illustrating a memory cell MC in an SRAM according to this embodiment. The memory cell MC is located at the intersection between a pair of bit lines (bit line BLT, bit line BLB) and a word line WL. The memory cell MC includes a pair of load transistors (load MOS, MOS for load, transistor for load, MISFET for load) QL1 and QL2, a pair of access transistors (access MOS, transistor for access, MISFET for access, transistor for transfer) QT1 and QT2, and a pair of driver transistors (driver MOS, transistor for drive, MISFET for drive) QD1 and QD2.

[0033] Of the six transistors that configure the memory cell MC, the load transistors QL1 and QL2 are p-type (p-channel type) transistors, and the access transistors QT1 and QT2 and the driver transistors QD1 and QD2 are n-type (n-channel type) transistors.

[0034] MISFET is an abbreviation for Metal-Insulator-Semiconductor Field-Effect Transistor, sometimes referred to as MOS. For example, load transistors QL1 and QL2 are called PMOS (PMIS), and access transistors QT1 and QT2, as well as driver transistors QD1 and QD2, are called NMOS (NMIS). Furthermore, in the following description, load transistors, access transistors, and driver transistors may be simply referred to as "transistors". Additionally, each transistor can be simply represented by its reference symbol (QL1, QL2, QT1, QT2, QD1, QD2).

[0035] Of the six transistors in the memory cell MC, QL1 and QD1 are configured as CMOS inverters, and QL2 and QD2 are configured as another CMOS inverter. The input / output terminals (memory nodes VL and VR) of this pair of CMOS inverters are cross-linked to configure a flip-flop circuit as a data memory for storing one bit of data.

[0036] Next, we will describe in detail how the six transistors of the SRAM memory cell MC are coupled to each other.

[0037] QL1 is coupled between the power supply potential line (first potential) Vdd and the memory node VL, and QD1 is coupled between the memory node VL and the ground potential line (GND, 0V, reference potential, second potential below the first potential) VSS, thereby configuring a CMOS inverter, and the gate electrodes of QL1 and QD1 are coupled to the memory node VR.

[0038] QL2 is coupled before the power supply potential line Vdd and the memory node VR, and QD2 is coupled between the memory node VR and the ground potential line VSS, thereby configuring another CMOS inverter, and the gate electrodes of QL2 and QD2 are coupled to the memory node VL.

[0039] QT1 is coupled between bit line BLT and memory node VL, and QT2 is coupled between bit line BLB and memory node VR, and the gate electrodes of QT1 and QT2 are coupled to word line WL.

[0040] In this embodiment, six transistors have a thin-film BOX-SOI structure and are formed above a semiconductor layer SM, which is an SOI layer on an SOI substrate, as described later (see [link to documentation]). Figure 6 and Figure 7 ).

[0041] Furthermore, QL1 and QL2 have back gates positioned beneath the semiconductor layer SM, through the insulating layer BOX. The back gates of QL1 and QL2 are n-well regions (semiconductor regions, back gate regions) NW. QT1 and QD1 have back gates positioned beneath the semiconductor layer SM, through the insulating layer BOX. The back gates of QT1 and QD1 are p-well regions (semiconductor regions, back gate regions) PW1. QT2 and QD2 have back gates positioned beneath the semiconductor layer SM, through the insulating layer BOX. The back gates of QT2 and QD2 are p-well regions (semiconductor regions, back gate regions) PW2. The n-well regions NW are coupled to the power supply wiring VN, and the p-well regions PW1 and PW2 are coupled to the power supply wiring VP. The PMOS and NMOS configured in the memory cells MC have a structure called FD-SOI (fully depleted silicon on insulator), in which the semiconductor layer SM, used as the channel region, is very thin. Furthermore, since the back gates are used to control the threshold values ​​of the PMOS and NMOS, the insulating layer BOX is also very thin.

[0042] Storage operations

[0043] Next, the storage operation of the SRAM's memory cell MC will be described. When the potential of the memory node VL of one CMOS inverter is high (H), QD2 is turned on, and the potential of the memory node VR of the other CMOS inverter is low (L). Therefore, QL1 and QL2 are turned off, thus maintaining the high potential of memory node VL. In other words, the latch circuit of a pair of CMOS inverters cross-linked maintains the state of memory nodes VL and VR, so that data is held while power is applied. This is the idle time (idle state).

[0044] On the other hand, word line WL is coupled to the gate electrodes of QT1 and QT2. When the potential of word line WL is high (H), QT1 and QT2 are turned on, and the trigger circuit is electrically coupled to the bit lines (BLT, BLB), so that the potential states of memory nodes VL and VR (a combination of H and L or a combination of L and H) appear on bit lines BLT and BLB, and data is read as memory cell MC.

[0045] In order to write data into the memory cell, word line WL is high (H), and QT1 and QT2 are turned on to electrically couple the trigger circuit and bit line (BLT, BLB), thereby transferring the data (a combination of H and L or a combination of L and H) of bit lines BLT and BLB to memory nodes VL and VR and storing the data as described above.

[0046] Figure 2 This is a table illustrating the well region potentials and thresholds for PMOS and NMOS according to this embodiment. More specifically, the table shows the potentials (applied voltages) of p-well regions PW1 and PW2, the potentials (applied voltages) of n-well region NW, and the thresholds for PMOS and NMOS during idle and read / write times. In this embodiment, the through current of one CMOS inverter and the other CMOS inverter is reduced by making the thresholds of the PMOS and NMOS of the memory cell MC during the idle time greater than the thresholds during the read / write time.

[0047] This will be explained below, using the case where the potential of the storage node VL of one CMOS inverter is high (H) and the potential of the storage node VR of another CMOS inverter is low (L) as an example.

[0048] like Figure 2 As shown, during the read or write time, a power supply potential Vdd is applied from the power supply line VN to the n-well regions NW, which serve as the back gates of QL1 and QL2 (PMOS), and the threshold values ​​of QL1 and QL2 (PMOS) are set to, for example, 0.25V (absolute value). Furthermore, a ground potential is applied from the power supply line VP to the n-well regions NW1 and NW2, which serve as the back gates of QD1 and QT1 and QD2 and QT2, respectively, and the threshold values ​​of QD1 and QT1 and QD2 and QT2 are set to, for example, 0.25V (absolute value). The read and write speeds are increased by lowering the threshold values ​​of the PMOS and NMOS.

[0049] On the other hand, during idle time, a voltage (Vdd + 2.0)V higher than the supply voltage Vdd is applied from the power supply line VN to the n-well regions NW, which serve as the back gates of QL1 and QL2 (PMOS), and the threshold values ​​of QL1 and QL2 (PMOS) are set to, for example, 0.5V (absolute value). Furthermore, a voltage (VSS - 2.0)V lower than the ground potential VSS is applied from the power supply line VP to the p-well regions PW1 and PW2, which serve as the back gates of QD1 and QT1 and QD2 and QT2, respectively, and the threshold values ​​of QD1 and QT1 and QD2 and QT2 are set to, for example, 0.5V (absolute value).

[0050] In other words, during idle periods, the leakage current of QD1 and QL2 is reduced by increasing their threshold values. For example, leakage current is prevented from flowing to QD1 and QL2 due to noise, etc. Therefore, the power consumption of the SRAM is reduced by decreasing the through current of one CMOS inverter and the other CMOS inverter.

[0051] Storage cell structure

[0052] Figures 3 to 5 This is a plan view showing the structure of the SRAM storage cell MC according to this embodiment. Figure 6 It is along Figure 3 The cross-sectional view of line AA, and Figure 7 It is along Figure 3 The cross-sectional view of line BB.

[0053] Figure 3 The roughly rectangular area surrounded by dashed lines represents a memory cell (MC) for one bit. Figure 3 In this diagram, AcN1, AcP1, AcP2, and AcN2 represent active regions, G1, G2, G3, and G4 represent gate electrode layers, P1a, P1b, P1c, P1d, P1e, P1f, P1g, P1h, P1i, and P1j represent plug conductor layers, SC represents the shared contact conductor layer SC, and M1 represents the first layer wiring M1.

[0054] As shown in the figure, four active regions AcN1, AcP1, AcP2, and AcN2 extending along the Y direction are arranged in the X direction in the aforementioned order. A component isolation region STI is disposed between (surrounding) the active regions AcN1, AcP1, AcP2, and AcN2. In other words, the active regions AcN1, AcP1, AcP2, and AcN2 are demarcated (defined) by the component isolation region STI.

[0055] Active regions AcP1 and AcP2 are adjacent rectangles with the same width in the X direction, extending along the Y direction, and located at the center of the memory cell MC, with a desired spacing between them. Active regions AcN1 and AcN2 are rectangles extending along the Y direction on their longer sides and positioned to sandwich active regions AcP1 and AcP2 along the X direction. Active region AcN1 has a QD1 region with a width greater than the QT1 region along the X direction, and adopts the shape of two rectangles with different shorter side lengths when joined together. Active region AcN2 has the same shape.

[0056] The four gate electrode layers G1 to G4 are positioned in a two-layer (linear) arrangement. The common gate electrode layer G1, which intersects above the active regions AcN1 and AcP1, and the gate electrode layer G4, which intersects above the active region AcN2, extend along the X direction and are located on a virtual line extending along the X direction. The common gate electrode layer G3, which intersects above the active regions AcP2 and AcN1, and the gate electrode layer G2, which intersects above the active region AcN1, extend along the X direction and are located on a virtual line extending along the X direction.

[0057] QD1 is formed at the intersection of the active region AcP1 and the gate electrode layer G1, QD1 is formed at the intersection of the active region AcN1 and the gate electrode layer G1, and QT1 is formed at the intersection of the active region AcN1 and the gate electrode layer G3. QL2 is formed at the intersection of the active region AcP2 and the gate electrode layer G2, QD2 is formed at the intersection of the active region AcN2 and the gate electrode layer G2, and QT2 is formed at the intersection of the active region AcN2 and the gate electrode layer G4.

[0058] Plug conductor layers P1a, P1b, P1c, P1d, P1e, P1f, P1g, P1h, P1i, and P1j, or the shared contact conductor layer SC, are located above the source / drain regions of the six transistors QD1, QT1, QL1, QL2, QT2, and QD2. The plug conductor layers P1a, P1b, P1c, P1d, P1e, P1f, P1g, P1h, P1i, and P1j, or the shared contact conductor layer SC, are plugs (conductor layers) that couple the source / drain regions or gate electrode layers G1 and G2 of transistors QD1, QT1, QL1, QL2, QT2, and QD2 to the first layer wiring M1. The drain region of QL1 and the gate electrode layer G2 are coupled through the shared contact conductor layer SC, and the drain region of QL2 and the gate electrode layer G1 are coupled through the shared contact conductor layer SC.

[0059] The plug conductor layer P1b coupled to the drain regions of QD1 and QT1, and the shared contact conductor layer SC coupled to the drain region D of QL1 and the gate electrode layer G2, are coupled through the first layer wiring M1. Similarly, the plug conductor layer P1g coupled to the drain regions D of QD2 and QT2, and the shared contact conductor layer SC coupled to the drain region D of QL2 and the gate electrode layer G1, are coupled through the first layer wiring M1.

[0060] Figure 4The diagram shows plug conductor layers P2a, P2b, P2c, P2d, P2e, P2f, P2g, and P2h, as well as the second layer wiring M2. Plug conductor layers P2a, P2b, P2c, P2d, P2e, P2f, P2g, and P2h are plugs coupling the first layer wiring M1 and the second layer wiring M2. The second layer wiring M2 is configured with a power potential line Vdd and bit lines BLT and BLB, and the power potential line Vdd and bit lines BLT and BLB extend along the Y direction. The power potential line Vdd, located between bit lines BLT and BLB, is wider than bit lines BLT and BLB.

[0061] like Figure 3 and Figure 4 As is known, the power supply potential line Vdd is coupled to the source region S of QL1 through the plug conductor layer P2a, the first layer wiring M1, and the plug conductor layer P1a. Furthermore, the power supply potential line Vdd is coupled to the source region S of QL2 through the plug conductor layer P2e, the first layer wiring M1, and the plug conductor layer P1f.

[0062] Bit line BLT is coupled to the source region S of QT1 through plug conductor layer P2b, first layer wiring M1, and plug conductor layer P1d. Bit line BLB is coupled to the source region S of QT2 through plug conductor layer P2f, first layer wiring M1, and plug conductor layer P1i.

[0063] Figure 5 The diagram shows a second-layer wiring M2, plug conductor layers P3a, P3b, P3c, and P3d, and a third-layer wiring M3. Plug conductor layers P3a, P3b, P3c, and P3d are plugs coupling the second-layer wiring M2 and the third-layer wiring M3. The third-layer wiring M3 is configured with a word line WL and two ground potential lines VSS, with the word line WL and the two ground potential lines VSS extending parallel to each other in the X-direction. In the Y-direction, the word line WL lies between the two ground potential lines VSS.

[0064] like Figures 3 to 5 As shown, the word line WL is coupled to the gate electrode layer G3 through the plug conductor layer P3a, the second layer wiring M2, the plug conductor layer P2c, the first layer wiring M1, and the plug conductor layer P1e. ​​Furthermore, the word line WL is coupled to the gate electrode layer G4 through the plug conductor layer P3c, the second layer wiring M2, the plug conductor layer P2g, the first layer wiring M1, and the plug conductor layer P1i.

[0065] like Figure 5 As shown, the ground potential line VSS located above the word line WL is coupled to the source region S of QD2 through the plug conductor layer P3d, the second layer wiring M2, the plug conductor layer P2h, the first layer wiring M1, and the plug conductor layer P1h. Furthermore, as... Figure 5As shown, the ground potential line VSS located below the word line WL is coupled to the source region S of QD1 through the plug conductor layer P3b, the second layer wiring M2, the plug conductor layer P2d, the first layer wiring M1, and the plug conductor layer P1c.

[0066] like Figure 6 and Figure 7 As shown, according to this embodiment, the SRAM memory cell MC is formed above the SOI substrate. The SOI substrate has a silicon semiconductor substrate (support substrate, substrate) 1, an insulating layer BOX, and a semiconductor layer (device formation region) SM covering the insulating layer BOX. The semiconductor layer (device formation region) SM is separated by a device isolation region STI. As described above, the active regions AcP1 and AcN1 are demarcated (separated) by the device isolation region STI. For example, the insulating layer BOX is a silicon oxide film (with a thickness of approximately 10 nm) and isolates the semiconductor layer SM from the semiconductor substrate 1 or the p-type well regions PW1, PW2 and the n-type well region NW. The semiconductor layer SM is, for example, a silicon film with a thickness of approximately 10 to 15 nm. The device isolation region STI has a device isolation film as a silicon oxide film (SiO) or a laminate including a silicon nitride film (SiN) and a silicon oxide film (SiO), etc.

[0067] like Figure 6 As shown, the insulating layer BOX is located below the active region (semiconductor layer SM) AcN1, and the p-type well region PW1 is located below the insulating layer BOX. The insulating layer BOX is located below the active region (semiconductor layer SM) AcP1, and the n-type well region NW is located below the insulating layer BOX. The n-type buried well region DNW is located below the p-type well regions PW1 and NW, and above the semiconductor substrate 1. The p-type well regions PW1 and PW2 and the n-type well region NW are formed in the main surface of the semiconductor substrate 1, and the semiconductor layer SM is formed on the main surface of the semiconductor substrate 1 through the insulating film BOX. The active region is disposed on the semiconductor layer SM or the main surface of the semiconductor substrate 1 surrounded by the element isolation region STI.

[0068] Figure 6 The diagram shows QD1 as an NMOS and QL1 as a PMOS. QD1 has the same structure as QT1, QD2, and QT2, and QL1 has the same structure as QL2. Figure 6 As shown, the n-type gate electrode GD1 of QD1 is formed on the semiconductor layer SM in the active region AcN1 via a gate insulating film 2. The gate insulating film 2 is, for example, a 2 nm thick silicon oxynitride film, but alternatively, it can be a silicon oxide film or a high-permeability film (referred to as a high-k film). The gate electrode GD1 is made of a polycrystalline silicon film (polysilicon film) doped with n-type impurities. The gate insulating film 2 is very thin, thinner than the insulating film BOX or the device isolation film.

[0069] The gate electrode QD1 is along the channel length direction of QD1 ( Figure 6 The gate electrode GD1 has opposing sidewalls in the horizontal direction, and an offset spacer OS made of silicon nitride film is formed on the sidewalls, completely covering the sidewalls of the gate electrode GD1. An insulating film 3, which is a silicon oxide film, and a sidewall insulating film SW, which is a silicon nitride film, are formed above the offset spacer OS. The insulating film 3 and the sidewall insulating film SW completely cover the sidewalls of the gate electrode GD1 through the offset spacer OS.

[0070] Along the channel length, an n-type low-concentration semiconductor region NM and an n-type high-concentration semiconductor region NH are formed on both sides of the gate electrode GD1, sandwiched between the gate electrode GD1. The n-type low-concentration semiconductor region NM and the n-type high-concentration semiconductor region NH are the source region S or drain region D of QD1. The n-type high-concentration semiconductor region NH has a higher n-type impurity concentration than the n-type low-concentration semiconductor region NM, and the n-type high-concentration semiconductor region NH is further away from the gate electrode GN1 than the n-type low-concentration semiconductor region NM. The n-type low-concentration semiconductor region NM and the n-type high-concentration semiconductor region NH are in contact with the insulating layer BOX. The n-type high-concentration semiconductor region NH is positioned across the semiconductor layer SM and the epitaxial layer EP formed by selective silicon growth on the semiconductor layer SM.

[0071] A silicon layer (SIL) is formed on the front surface (top surface) of the gate electrode GD1 and the n-type high-concentration semiconductor region NH to reduce the impedance of the source region S, drain region D, and gate electrode GD1 of QD1. The source region S of QD1 is coupled to the first layer wiring M1, which is a conductor, through a plug conductor layer P1c. The plug conductor layer P1c is located in the interlayer insulating film 4 covering QD1. The first layer wiring M1 is formed in wiring trenches in the insulating film 5.

[0072] like Figure 6 As shown, the p-type gate electrode GL1 of QL1 is formed on the semiconductor layer SM in the active region AcP1 via a gate insulating film 2. The gate insulating film 2 is, for example, a 2 nm thick silicon oxynitride film, but alternatively it can be silicon oxide or a high-permeability film (referred to as a high-k film). The gate electrode GL1 is made of a polycrystalline silicon film doped with p-type impurities (polycrystalline silicon film).

[0073] The gate electrode GL1 is along the channel length direction of QL1 ( Figure 6 The gate electrode GL1 has opposing sidewalls in the horizontal direction, and an offset spacer OS made of silicon nitride film is formed on the sidewalls, completely covering the sidewalls of the gate electrode GL1. An insulating film 3, which is a silicon oxide film, and a sidewall insulating film SW, which is a silicon nitride film, are formed on the offset spacer OS. The insulating film 3 and the sidewall insulating film SW completely cover the sidewalls of the gate electrode GL1 through the offset spacer OS.

[0074] Along the channel length, a low-concentration p-type semiconductor region PM and a high-concentration p-type semiconductor region PH are formed on both sides of the gate electrode GL1, sandwiched between them. The low-concentration p-type semiconductor region PM and the high-concentration p-type semiconductor region PH are the source region S or drain region D of QL1. The p-type impurity concentration in the high-concentration p-type semiconductor region PH is higher than that in the low-concentration p-type semiconductor region PM, and the high-concentration p-type semiconductor region PH is farther from the gate electrode GL1 than the low-concentration p-type semiconductor region PM. Both the low-concentration p-type semiconductor region PM and the high-concentration p-type semiconductor region PH are in contact with the insulating layer BOX. The high-concentration p-type semiconductor region PH is positioned across the semiconductor layer SM and an epitaxial layer EP formed on the semiconductor layer SM by selectively growing silicon.

[0075] A silicon layer (SIL) is formed on the front surface (top surface) of the gate electrode GL1 and the p-type high-concentration semiconductor region PH to reduce the impedance of the source region S, drain region D, and gate electrode GL1 of QL1. The source region S of QL1 is coupled to the first layer wiring M1, which is a conductor, through a plug conductor layer P1a. The plug conductor layer P1a is located in the interlayer insulating film 4 covering QL1. The first layer wiring M1 is formed in wiring trenches in the insulating film 5. Figure 3 and Figure 4 It is understandable that the first layer wiring M1 is coupled to the power supply potential line Vdd, which is the second layer wiring M2.

[0076] Here, the silicide layer SIL includes, for example, a cobalt silicide (CoSi) layer, a titanium silicide (TiSi) layer, a nickel silicide (NiSi) layer, and a platinum (Pt) nickel silicide (NiSi) layer.

[0077] The plug conductor layers P1c and P1a have a laminated structure comprising a barrier conductor film such as tungsten nitride (TiW) or titanium nitride (TiN) film and a tungsten (W) dominant body film. Other plug conductor layers P1b, P1d, P1e, P1f, P1g, P1h, P1i, and P1j, as well as the shared contact conductor layer SC, have the same structure as plug conductor layers P1c and P1a.

[0078] The first layer of wiring M1 is a copper wiring with a laminated structure, comprising a barrier conductor film and a copper-based main conductor film covering it. The barrier conductor film is made of tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), or nitrides, or silicon nitride containing any of these elements, or it is a laminated film as a combination of these. The copper-based main conductor film is made of copper (Cu) or copper alloys (copper (Cu) combined with aluminum (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), indium (In), lanthanides, or actinides).

[0079] The interlayer insulating film 4 is a silicon oxide film (SiO), and the insulating film 5 is a silicon oxide film (SiO); however, alternatively, they may be carbon-containing silicon oxide films (SiOC films), nitrogen- and carbon-containing silicon oxide films (SiCON films), or fluorine-containing silicon oxide films (SiOF films), in the form of monolayer films or laminated films.

[0080] Next, as Figure 7 As shown, QT1 is formed on the semiconductor layer SM in the active region AcN1, and QT1 includes a gate electrode GT1. The structure of QT1 is basically the same as that of QD1 described above, and its description is omitted.

[0081] like Figure 7 As shown, the active region AcP1 is adjacent to the active region AcN1 via the element isolation region STI, and the p-type high-concentration semiconductor region PH and the silicide layer SIL are formed on the surface of the active region AcP1. Figure 3 It can be seen that the p-type high-concentration semiconductor region PH is the drain region D of QL1. Furthermore, the gate electrode layer G2 is located above the device isolation region STI and adjacent to the active region AcP1. (As...) Figure 3 and Figure 7 As shown, the shared contact conductor layer SC extends continuously (integrally) from the active region AcP1, where the drain region D of QL1 is located, and is situated above the gate electrode G2. In short, the drain region D of QL1 and the gate electrode layer G2 are coupled through the shared contact conductor layer SC.

[0082] like Figure 7 As shown, the drain region D of QT1 is coupled to the shared contact conductor layer SC through the plug conductor layer P1c and the first layer wiring M1. In other words, as Figure 3 and Figure 7 As shown, the drain region D of QT1, the drain region D of QL1, and the gate electrode layer G2 forming QL2 and QD2 are electrically coupled through the plug conductor layer P1b, the first layer wiring M1, and the shared contact conductor layer SC.

[0083] Tap area

[0084] Figure 8 This is a plan view conceptually illustrating the location of the tap region in the SRAM region according to this embodiment. Figure 9 This is a plan view showing the memory array and tap area in the SRAM region according to this embodiment. Figure 10 It is along Figure 9 The cross-sectional view taken from line CC.

[0085] Figure 11 It is along Figure 9 The cross-sectional view of line DD. Figure 12 and Figure 13 This is a cross-sectional view illustrating a comparative example conceived by the inventors of the present invention. For example... Figure 8 As shown, the tap region TAP is located between adjacent memory arrays along the Y direction (the direction of bit line extension). The n-type well region NW and the p-type well regions PW1 and PW2, located below the memory cell MC, extend along the Y direction and are continuously located in the memory array MA and the tap region TAP, which are adjacent to each other along the Y direction.

[0086] The tapped region TAP extends along the X direction (the direction of word line extension) and has a desired width in the Y direction (the direction of bit line extension). The tapped region TAP is a power region for the n-well region NW and the p-well regions PW1 and PW2, and includes power traces VN and VP extending along the X direction. In the tapped region TAP, the power trace VN extending along the X direction is coupled to the n-well NW extending along the Y direction via a plug conductor layer P1k. Furthermore, in the tapped region TAP, the power trace VP extending along the X direction is coupled to the p-wells PW1 and PW2 extending along the Y direction via a plug conductor layer P3e. The plug conductor layer P1k is structurally connected to... Figure 3 The plug conductor layers P1a, P1b, P1c, P1d, P1e, P1f, P1g, P1h, P1i, and P1j shown are identical, and the plug conductor layer P3e is structurally similar to... Figure 5 The plug conductor layers P3a, P3b, and P3d shown are identical.

[0087] In short, power is supplied from power lines VN and VP to the n-type well region NW and the p-type well regions PW1 and PW2. Figure 2 The potential shown.

[0088] Figure 9 This is a plan view showing adjacent memory arrays MA and the tap region TAP between them, where each memory array MA includes two memory cells MC adjacent to each other along the X direction. The memory cells are as follows... Figure 3 As shown, and this image omits... Figure 4 and Figure 5 The second layer wiring M2 and the third layer wiring M3 are shown.

[0089] like Figure 9 As shown, in the tapped region TAP, the active region AcNT is formed within the n-type well region NW, and the n-type high-concentration semiconductor region NH is formed within the active region AcNT. The silicide layer SIL is formed within the n-type high-concentration semiconductor region NH. Figure 10 As shown, the active region AcNT is formed on the surface of the n-type well region NW, and the insulating layer BOX and the semiconductor layer SM are not present in the active region AcNT. In the tapped region TAP, the active region AcPT is formed in the p-type well regions PW1 and PW2, and the p-type high-concentration semiconductor region PH is formed in the active region AcPT. Furthermore, the silicide layer SIL is formed on the surface of the p-type high-concentration semiconductor region PH. Figure 11 As shown, the active region AcPT is formed on the surface of the p-type well regions PW1 and PW2, and the insulating layer BOX and the semiconductor layer SM are not present in the active region AcPT.

[0090] like Figure 9 As shown, in the tap region TAP, the power supply wiring VN, which is the first layer wiring M1, and the power supply wiring VP, which is the third layer wiring M3, extend along the X direction. The power supply wiring VN is coupled to the n-type high-density semiconductor region NH formed in the active region AcNT through the plug conductor layer P1k and the silicide layer SIL (see [link to diagram]). Figure 10 The power supply wiring VP is coupled to the p-type high-concentration semiconductor region PH formed in the active region AcPT via the plug conductor layer P3e, the second layer wiring M2, the plug conductor layer P2k, the first layer wiring M1, the plug conductor layer P1m, and the silicide layer SIL (see [link to relevant documentation]). Figure 11 ).

[0091] In the tap area TAP, the active areas AcPT and AcNT are arranged alternately along the X direction, and the power wiring VN, which serves as the first layer wiring M1, extends along the X direction to avoid the active area AcPT being arranged to meander along the Y direction.

[0092] like Figure 9 As shown, multiple dummy gate electrode layers (DGs) are formed in the tap region (TAP). Each dummy gate electrode layer (DG) has a rectangular shape extending along the X direction and has the same length in the X direction as the gate electrode layers G1, G2, G3, and G4 of the memory cell MC. In the Y direction, the width of the dummy gate electrode layer (DG) is the same as the width of the gate electrode layers G3 and G4 of the memory cell MC.

[0093] In the upper region of the tapped region TAP, multiple dummy gate electrode layers (DGs) are arranged in rows along the X direction adjacent to the memory array MA (hereinafter referred to as the upper memory array MA) located above the tapped region TAP. Similarly, in the lower region of the tapped region TAP, multiple dummy gate electrode layers (DGs) are arranged in rows along the X direction adjacent to the memory array MA (hereinafter referred to as the lower memory array MA) located below the tapped region TAP. In short, in the tapped region TAP, the dummy gate electrode layers (DGs) are arranged side by side in two rows along the X direction, with the two rows arranged along the Y direction. For convenience, the row of dummy gate electrode layers (DGs) adjacent to the upper memory array MA is called the upper dummy gate group, and the row of dummy gate electrode layers (DGs) adjacent to the lower memory array MA is called the lower dummy gate group. In the Y direction, the active regions AcPT and AcNT are located between the upper dummy gate group and the lower dummy gate group.

[0094] First, the relationship between the memory cells in the upper memory array MA, which is closest to the tap region TAP, and the upper pseudo-gate group will be explained.

[0095] like Figure 9 As shown, the dummy gate electrode layer DG is arranged parallel to the gate electrode layers G1 and G4 in the memory cell MC in such a way that it covers the gate electrode layers G1 and G4 along the Y direction.

[0096] The spacing SP1 between the gate electrode layer G1 and the dummy gate electrode layer DG in the Y direction is equal to the spacing SP2 between the gate electrode layer G1 and the gate electrode layer G3 in the Y direction. Similarly, the spacing between the gate electrode layer G4 and the dummy gate electrode layer DG in the Y direction is equal to the spacing between the gate electrode layer G4 and the gate electrode layer G2 in the Y direction.

[0097] The active regions AcN1, AcP1 and AcN2 in the memory cell MC extend to reach and cross the pseudo gate electrode layer DG in the tap region TAP.

[0098] The pseudo-shared contact conductor layer (DSC) is end-coupled to the pseudo-gate electrode layer (DG). The pseudo-shared contact conductor layer (DSC) is structurally identical to the shared contact conductor layer (SC) in the memory cell (MC).

[0099] The relationship between the memory cells in the lower memory array MA, which is closest to the tap region TAP, and the lower pseudo-gate electrode group is the same as described above, so its description is omitted.

[0100] Figure 10 It is along Figure 9 The cross-sectional view taken from line CC shows, from left to right, the QL1 of the memory cell MC, the dummy gate electrode layer DG in the tap region TAP, and the junction between the power supply wiring VN and the n-type well region NW in the tap region TAP. Figure 10As shown, active regions AcP1 and AcNT are located in the n-type well region NW. The semiconductor layer SM is located above the surface of the n-type well region NW in the active region AcP1 via the insulating layer BOX, and the p-type gate electrode GL1 is formed above the semiconductor layer SM via the gate insulating film 2. The source region S and drain region D are formed at the two ends of the gate electrode GL1 in a manner that sandwiches the gate electrode GL1. The source region S is coupled to the first layer wiring M1 via the plug conductor layer P1a, and as shown... Figure 6 As shown, the source region S is coupled to the power supply potential line Vdd.

[0101] A p-type dummy gate electrode layer DG is formed on a semiconductor layer SM adjacent to the source region S via a gate insulating film 2. The dummy gate electrode layer DG is positioned across the active region AcP1 and the adjacent device isolation region STI. A dummy shared contact conductor layer DSC coupled to the dummy gate electrode layer DG is formed on top of the dummy gate electrode layer DG. However, the upper surface of the dummy shared contact conductor layer DSC is completely covered by the insulating film 5 and is not coupled to wiring such as the first layer wiring M1. For example, as... Figure 9 As shown, the power supply wiring VN does not overlap with the pseudo-shared contact conductor layer DSC. In short, the pseudo-gate electrode layer DG and the pseudo-shared contact conductor layer DSC are electrically floating. Here, "floating" means, for example, that the pseudo-gate electrode layer DG is not physically coupled to the wiring through the conductor layer (or directly). In other words, the pseudo-gate electrode layer DG is not provided with any potential, such as a power supply potential or a ground potential. In short, the periphery of the pseudo-gate electrode layer DG, or the periphery of the pseudo-gate electrode layer DG and the pseudo-shared contact conductor layer DSC coupled thereto, is covered by an insulating film.

[0102] In the active region AcNT, which serves as the junction between the power supply line VN and the n-type well region NW, a high-concentration n-type semiconductor region NH is formed on the surface of the n-type well region NW, and a silicide layer SIL is formed on the surface of the high-concentration n-type semiconductor region NH. The silicide layer SIL on the surface of the high-concentration n-type semiconductor region NH is coupled to the power supply line VN, which serves as the first layer wiring M1, through a plug conductor layer P1k. In short, the potential supplied to the power supply line VN is applied to the n-type well region NW.

[0103] Figure 12 This is a cross-sectional view of a comparative example conceived by the inventors of the present invention, which corresponds to... Figure 10 The cross section. Figure 12 and Figure 10 The difference lies in that the power supply line VN extends above and is coupled to the pseudo-shared contact conductor layer DSC. This means that the pseudo-gate electrode layer DG is not floating, but rather supplied from the power supply line VN to it. Figure 2The potential shown. During idle time, for example, Vdd+2.0 (V) is supplied from the power supply wiring VN to the dummy gate electrode layer DG, and the potential of the source region S of QL1 is Vdd, such that... Figure 12 As shown, a potential difference of 2.0 (V) is generated at point Y of the gate insulating film 2. The inventors of this invention discovered that this potential difference can cause breakdown of the gate insulating film 2 and generate leakage current between the power supply wiring VN and the source region S of QL1, thereby increasing power consumption.

[0104] In this embodiment, such as Figure 10 As shown, the dummy gate electrode layer DG is floating and the potential of the power supply wiring VN is not supplied to it, so that the breakdown of the gate insulating film 2 does not occur and power consumption can be reduced.

[0105] Figure 11 It is along Figure 9 The cross-sectional view taken from line DD shows, from left to right, the QT2 of the memory cell MC, the dummy gate electrode layer DG in the tap region TAP, and the junction between the power supply wiring VP and the p-type well region PW2 in the tap region TAP. Figure 11 As shown, the active regions AcN2 and AcPT are located in the p-type well region PW2. The semiconductor layer SM is located on the surface of the p-type well region PW2 within the active region AcN2 via the insulating layer BOX, and the n-type gate electrode GT2 is formed on the semiconductor layer SM via the gate insulating film 2. The source region S and drain region D are formed at both ends of the gate electrode GT2 in a manner that sandwiches the gate electrode GT2. The source region S is coupled to the first layer wiring M1 via the plug conductor layer P1i, and can be accessed from this... Figure 3 and Figure 4 As can be seen, the source region S is coupled to the bit line BLB.

[0106] like Figure 11 As shown, an n-type dummy gate electrode layer DG is formed adjacent to the source region S on the semiconductor layer SM via a gate insulating film 2. The dummy gate electrode layer DG is positioned across the active region AcN2 and the adjacent device isolation region STI. The upper surface of the dummy gate electrode layer DG is completely covered by the insulating film 5 and is not coupled to wiring such as the first layer wiring M1. For example, as... Figure 9 As shown, the first layer wiring M1 extends from the junction between the power supply wiring VP and the p-type well region PW2 to cover the dummy gate electrode layer DG, but is not coupled to the dummy gate electrode layer DG. In short, the dummy gate electrode layer DG is electrically floating.

[0107] like Figure 11As shown, in the active region AcPT, which serves as the junction between the power supply line VP and the p-type well region PW2, a high-concentration p-type semiconductor region PH is formed on the surface of the p-type well region PW, and a silicide layer SIL is formed on the surface of the high-concentration p-type semiconductor region PH. The silicide layer SIL on the surface of the high-concentration p-type semiconductor region PH is coupled to the power supply line VP, which serves as the third layer wiring, through the plug conductor layer P1m, the first layer wiring M1, the plug conductor layer P2k, the second layer wiring M2, and the plug conductor layer P3e. In short, the potential supplied to the power supply line VP is applied to the p-type well region PW2. The first layer wiring M1, coupled to the p-type well region PW2, extends to be located above and overlaps with the dummy gate electrode layer DG, but is not coupled to the dummy gate electrode layer DG.

[0108] Insulating films 6, 7, 8 and 9 are silicon oxide films (SiO); however, alternatively, they may be carbon-containing silicon oxide films (SiOC films), nitrogen- and carbon-containing silicon oxide films (SiCON films) or fluorine-containing silicon oxide films (SiOF films), in the form of monolayer films or laminated films.

[0109] The via conductor layer P2k and the second wiring layer M2 are integrated. The via conductor layer P2k and the second wiring layer M2 are copper vias and copper wiring fabricated using a damascene method, and have a laminated structure comprising a barrier conductor film and a copper-based main conductor film located thereon. The barrier conductor film is made of tantalum (Ta), titanium (Ti), ruthenium (Ru), tungsten (W), manganese (Mn), or nitrides or silicon nitrides containing any of these elements, or a laminated film of combinations of these elements. The copper-based main conductor film is made of copper (Cu) or copper alloys (copper (Cu) combined with aluminum (Al), magnesium (Mg), titanium (Ti), manganese (Mn), iron (Fe), zinc (Zn), zirconium (Zr), niobium (Nb), molybdenum (Mo), ruthenium (Ru), palladium (Pd), silver (Ag), gold (Au), indium (In), lanthanides, or actinides). The via conductor layer P3e and the third layer wiring M3 are integrated in the same way as the via conductor layer P2k and the second layer wiring M2.

[0110] Figure 13 This is a cross-sectional view of a comparative example conceived by the inventors of this invention, which corresponds to... Figure 11 Cross-sectional view. Figure 13 and Figure 11 The difference lies in that the first layer wiring M1, coupled to the power supply wiring VP, is coupled to the dummy gate conductor layer DG through the plug conductor layer P1n. This indicates that the dummy gate electrode layer DG is not floating but is supplied to it from the power supply wiring VP. Figure 2The potentials shown. During idle periods, for example, VSS-2.0 (V) is supplied from the power supply line VP to the dummy gate electrode layer DG, and the potential of the source region S of QT2 coupled to the bit line BLB is Vdd or VSS, such that... Figure 13 The maximum potential difference of Vdd+2.0 (V) is generated at point Z in the gate insulating film 2. The inventors of this invention have discovered that this potential difference causes leakage current between the power supply wiring VP and the source region S, thereby increasing power consumption.

[0111] like Figure 11 As shown, according to this embodiment, the dummy gate electrode layer DG is floating and the potential of the power supply wiring VP is not supplied to it, so that the breakdown of the gate insulating film 2 does not occur and power consumption can be reduced.

[0112] Because the pseudo-gate electrode layer DG is formed in Figure 9 In the tapped region TAP shown, the processing precision can be increased during the photolithography process to form the gate electrode layers G1 and G4 in the memory cell MC adjacent to the tapped region TAP. Specifically, thinning or similar problems of the gate electrode layers G1 and G4 can be prevented. Therefore, stable electrical characteristics (threshold, source and drain current, etc.) can be achieved in the memory cell MC adjacent to the tapped region TAP.

[0113] The present invention has now been described in detail with reference to preferred embodiments. However, the invention is not limited thereto, and it will be apparent that these details may be modified in various ways without departing from the spirit of the invention.

Claims

1. A semiconductor device, comprising: A semiconductor substrate, including a first well region; An insulating layer is formed on a first portion of the semiconductor substrate and contacts the first well region; A semiconductor layer is formed on the insulating layer; The component isolation region extends into the interior of the first well region in the cross-sectional view; A first gate electrode layer is formed on a first portion of the semiconductor layer via a first gate insulating film; The second gate electrode layer is formed on the second portion of the semiconductor layer via a second gate insulating film, and is also formed on the first portion of the device isolation region; An interlayer insulating film covers the first gate electrode layer, the second gate electrode layer, and a second portion of the element isolation region; A first plug conductor layer is formed in the interlayer insulating film and connected to a third portion of the semiconductor layer; A second plug conductor layer is formed in the interlayer insulating film and is connected to a second portion of the semiconductor substrate; A first wiring is formed on the interlayer insulating film and connected to the first plug conductor layer; as well as The second wiring is formed on the interlayer insulating film and connected to the second plug conductor layer. The second gate electrode layer includes a dummy gate electrode layer that is isolated from the first wiring and the second wiring and electrically floated, and During standby, a first potential is provided to the semiconductor layer via the first plug conductor layer, while a second potential, different from the first potential, is provided to the first well region via the second plug conductor layer.

2. The semiconductor device of claim 1, wherein the dummy gate electrode layer is formed in a tap region different from the memory array region including the memory cell region, for providing the second potential to the first well region.

3. The semiconductor device of claim 1, wherein the first plug conductor layer is connected to a third portion of the semiconductor layer via a first silicide layer, and The second plug conductor layer is connected to a second portion of the semiconductor substrate via a second silicide layer.

4. The semiconductor device of claim 1, wherein a common contact conductor layer is formed in the interlayer insulating film and is formed on a second portion of the second gate electrode layer and the element separation region, and is connected to the second gate electrode layer via a third silicide layer, and The common contact conductor layer is isolated from the first wiring and the second wiring.

5. The semiconductor device of claim 4, wherein the first well region has a first conductivity type, and The third portion of the semiconductor layer has a second conductivity type that is different from the first conductivity type.

6. The semiconductor device of claim 5, wherein the first conductivity type is n-type, and The second conductivity type is p-type.

7. The semiconductor device of claim 6, wherein an n-type second well region is formed between the second plug conductor layer and the first well region.

8. The semiconductor device of claim 5, wherein the third portion of the semiconductor layer comprises an epitaxial layer.

9. A semiconductor device, comprising: A semiconductor substrate, including a first well region; An insulating layer is formed on a first portion of the semiconductor substrate and contacts the first well region; A semiconductor layer is formed on the insulating layer; A first gate electrode layer is formed on the semiconductor layer via a first gate insulating film; The second gate electrode layer is formed on the semiconductor layer via a second gate insulating film; An interlayer insulating film covers the first gate electrode layer and the second gate electrode layer; A first plug conductor layer is formed in the interlayer insulating film and connected to the semiconductor layer; A second plug conductor layer is formed in the interlayer insulating film and is connected to a second portion of the semiconductor substrate; A first wiring is formed on the interlayer insulating film and connected to the first plug conductor layer; and The second wiring is formed on the interlayer insulating film and connected to the second plug conductor layer. The second gate electrode layer is isolated from the first wiring and the second wiring to be electrically floated, and During standby, a first potential is provided to the semiconductor layer via the first plug conductor layer, while a second potential, different from the first potential, is provided to the first well region via the second plug conductor layer.

10. The semiconductor device of claim 9, wherein the second gate electrode layer is formed in a tap region different from the memory array region including the memory cell region for providing the second potential to the first well region.

11. The semiconductor device of claim 9, wherein the first plug conductor layer is connected to the semiconductor layer via a first silicide layer, and The second plug conductor layer is connected to a second portion of the semiconductor substrate via a second silicide layer.

12. The semiconductor device of claim 9, wherein a common contact conductor layer is formed in the interlayer insulating film and is formed on the second gate electrode layer, and is connected to the second gate electrode layer via a third silicide layer. The common contact conductor layer is isolated from the first wiring and the second wiring.

13. The semiconductor device of claim 12, wherein the first well region has a first conductivity type, and The third portion of the semiconductor layer has a second conductivity type that is different from the first conductivity type.

14. The semiconductor device of claim 13, wherein the first conductivity type is n-type, and The second conductivity type is p-type.

15. The semiconductor device of claim 14, wherein an n-type second well region is formed between the second plug conductor layer and the first well region.

16. The semiconductor device of claim 13, wherein the first plug conductor layer is connected to an epitaxial layer formed on the semiconductor layer via a first silicide layer.

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