Array substrate and display panel

Abstract

This application provides an array substrate and a display panel. The display panel includes an array substrate. By aligning at least a portion of the channel portion of the active layer with an ion implantation barrier layer in the array substrate, ions are prevented from being implanted into the channel portion by the ion implantation barrier layer, thereby reducing the effective channel length of the oxide thin film transistor. While keeping the aspect ratio of the oxide thin film transistor unchanged, the width of the channel of the oxide thin film transistor can be reduced, thereby reducing the size of the thin film transistor and improving the aperture ratio of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Technology

[0002] As display panels develop towards larger sizes, higher resolutions, higher frequencies, and self-emissive display modes, increasingly higher requirements are being placed on the mobility and stability of thin-film transistors (TFTs) that control the switching and drive the display. Currently, the amorphous silicon TFT devices commonly used in the display industry have low mobility and low on-state current, which cannot meet the needs of high-end display products. On the other hand, oxide TFTs have a mobility that is 10 to 100 times higher than that of amorphous silicon TFTs, which can meet the needs of new high-end display products. Therefore, oxide TFTs and their display panels are receiving increasing attention from the industry.

[0003] Currently, there are two main types of oxide thin-film transistors (TFTs) in the array substrates of liquid crystal displays (LCDs): etch-stopper layer (ESL) TFTs and back-channel etch (BCE) TFTs. The ESL TFT process requires an additional photomask step to prepare the etch-stopper layer, resulting in higher costs, and the larger TFT size affects the aperture ratio of the display panel. BCE TFTs, on the other hand, suffer from poorer device characteristics and stability due to channel damage from etching and other processes, impacting the production yield and reliability of the display panel.

[0004] In summary, existing display panels suffer from reduced aperture ratio due to the large size of oxide thin-film transistors. Therefore, it is necessary to provide an array substrate and display panel to improve this defect. Summary of the Invention

[0005] This application provides an array substrate and a display panel that can reduce the size of oxide thin-film transistors, thereby increasing the aperture ratio of the display panel.

[0006] This application provides an array substrate, including:

[0007] Substrate;

[0008] An active layer is disposed on the substrate, the material of the active layer including a metal oxide; and

[0009] An ion implantation barrier layer is disposed on the side of the active layer opposite to the substrate;

[0010] The active layer includes a channel portion, and the ion implantation barrier layer is disposed opposite to at least a portion of the channel portion.

[0011] According to one embodiment of this application, the array substrate further includes:

[0012] A gate is disposed on the substrate; and

[0013] A gate insulating layer is disposed between the gate and the active layer;

[0014] The gate's orthogonal projection onto the active layer covers the channel portion.

[0015] According to one embodiment of this application, the array substrate further includes a source electrode and a drain electrode, and the active layer further includes a source electrode contact portion and a drain electrode contact portion, wherein the source electrode is connected to and covers the source electrode contact portion, and the drain electrode is connected to and covers the drain electrode contact portion;

[0016] The orthogonal projection of the gate onto the active layer covers both the source contact and the drain contact.

[0017] According to one embodiment of this application, the active layer further includes a conductor portion, and the ion implantation barrier layer is disposed offset from the conductor portion;

[0018] The ion doping concentrations of the channel portion, the source contact portion, and the drain contact portion are all lower than the ion doping concentration of the conductor portion.

[0019] According to one embodiment of this application, the array substrate includes an etch barrier layer disposed between the active layer and the ion implantation barrier layer.

[0020] According to one embodiment of this application, the ion implantation barrier layer is disposed between the source and the drain, and is spaced apart from the source and the drain;

[0021] The channel portion includes a main channel portion disposed opposite to the ion implantation barrier layer, and the conductor portion is disposed on opposite sides of the main channel portion and connected to the main channel portion.

[0022] According to one embodiment of this application, the source electrode includes a main body portion and an extension portion, the main body portion being connected to and covering a corresponding source electrode contact portion, and the extension portion being connected to the main body portion and extending over the etch barrier layer; and / or

[0023] The drain includes a main body and an extension. The main body is connected to and covers the corresponding drain contact portion, and the extension is connected to the main body and extends over the etch barrier layer.

[0024] According to one embodiment of this application, the channel portion includes a sub-channel portion disposed opposite to the extension portion, and the opposite sides of the sub-channel portion are respectively connected to one of the source contact portion and the drain contact portion, and the conductor portion.

[0025] According to one embodiment of this application, the array substrate further includes a passivation protection layer, which covers the source, the drain, and the active layer;

[0026] The ion implantation barrier layer is disposed on the side of the passivation protection layer opposite to the active layer.

[0027] According to one embodiment of this application, the ion implantation barrier layer is disposed on the passivation protection layer, and the orthogonal projection of the ion implantation barrier layer on the active layer is located between the orthogonal projections of the source and the drain on the active layer, and is offset from the source and the drain.

[0028] According to one embodiment of this application, the ion implantation barrier layer is disposed on the same layer as the source and the drain, and is made of the same material as the source and the drain.

[0029] This application embodiment also provides a display panel, including an array substrate, an opposing substrate, and a liquid crystal layer as described above, wherein the liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0030] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide an array substrate and a display panel. The display panel includes an array substrate, which includes an active layer and an ion implantation barrier layer. The active layer is made of metal oxide. The ion implantation barrier layer is disposed on one side of the active layer. The active layer includes a channel portion. By aligning the ion implantation barrier layer with at least a portion of the channel portion, the ion implantation barrier layer can prevent ions from being implanted into the channel portion during ion implantation, thereby reducing the effective channel length of the oxide thin film transistor. While keeping the aspect ratio of the oxide thin film transistor unchanged, the width of the channel of the oxide thin film transistor can be reduced, thereby reducing the size of the oxide thin film transistor and improving the aperture ratio of the display panel. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1This is a schematic diagram of the structure of the array substrate for related technologies;

[0033] Figure 2 This is a schematic diagram of the structure of the first array substrate provided in the embodiments of this application;

[0034] Figure 3 This is a schematic diagram of the structure of the second array substrate provided in the embodiments of this application;

[0035] Figure 4 This is a schematic diagram of the structure of the third array substrate provided in the embodiments of this application;

[0036] Figure 5 This is a schematic diagram of the structure of the fourth array substrate provided in the embodiments of this application;

[0037] Figure 6 This is a schematic diagram of the structure of the fifth array substrate provided in the embodiments of this application;

[0038] Figure 7 This is a schematic diagram of the structure of the sixth array substrate provided in the embodiments of this application. Detailed Implementation

[0039] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0040] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0041] like Figure 1 As shown, Figure 1 This is a schematic diagram of the structure of an array substrate in related technologies. The array substrate includes an active layer 10, a gate 30, a gate insulating layer 40, a source 50, a drain 60, and an etch barrier layer 70. The channel portion 13 of the active layer 10 overlaps with the etch barrier layer 70. The effective channel length of the oxide thin-film transistor is the length L1 of the channel portion 13. Because the length L1 of the channel portion 13 is relatively long, the size of the thin-film transistor cannot be made smaller, which in turn affects the aperture ratio of the panel.

[0042] In view of this, this application provides an array substrate, such as Figure 2 As shown, Figure 2This is a schematic diagram of the structure of a first array substrate provided in an embodiment of this application. The array substrate includes a substrate 100 and an active layer 10 and an ion implantation barrier layer 20 stacked on the substrate 100. The ion implantation barrier layer 20 is disposed on one side of the active layer 10.

[0043] The active layer 10 is made of a metal oxide. The metal oxide may be any one of indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), or other metal oxides.

[0044] The active layer 10 includes a source contact portion 11, a drain contact portion 12, a channel portion 13, and a conductor portion 14, wherein the channel portion 13 and the conductor portion 14 are both disposed between the source contact portion 11 and the drain contact portion 12.

[0045] The ion implantation barrier layer 20 is aligned with the channel portion 13 such that the orthographic projection of the ion implantation barrier layer 20 on the active layer 10 overlaps with the channel portion 13. The ion implantation barrier layer 20 is offset from the conductor portion 14 such that the orthographic projection of the ion implantation barrier layer 20 on the active layer 10 is offset from the conductor portion 14, thus preventing the ion implantation barrier layer 20 from blocking the conductor portion 14.

[0046] In this embodiment, the material of the ion implantation barrier layer 20 includes metal, so that ions during the ion implantation process cannot penetrate the ion implantation barrier layer 20, thereby ensuring that the channel portion 13 of the active layer 10, which is disposed in opposition to the ion implantation barrier layer 20, maintains its semiconductor properties.

[0047] It should be noted that the side of the active layer 10 where the ion implantation barrier layer 20 is located is the ion implantation direction. In the actual fabrication process of the oxide thin-film transistor, the active layer 10 and the ion implantation barrier layer 20 can be formed sequentially, and then the active layer 10 can be ion implanted. The ion implantation barrier layer 20 can block the channel portion 13 of the active layer 10, preventing ions from being implanted into the channel portion 13, so that the channel portion 13 maintains its semiconductor properties. The areas of the active layer 10 that are not blocked by the ion implantation barrier layer 20 and other metal materials are ion implanted to form the conductor portion 14. The ion doping concentration in the conductor portion 14 is greater than the ion doping concentration in the channel portion 13.

[0048] Compared to existing technologies where only a channel portion 13 is provided between the source contact portion 11 and the drain contact portion 12, the array substrate provided in this embodiment not only has a channel portion 13 between the source contact portion 11 and the drain contact portion 12, but also has a conductor portion 14. With the channel length of the active layer 10 remaining constant, the length L2 of the channel portion 13 is the effective channel length of the oxide thin-film transistor. Combined with... Figure 1 and Figure 2 It can be seen that, Figure 2 The length L2 of the middle channel section 13 is less than Figure 1 The length L1 of the middle channel portion 13 is such that by providing a conductor portion 14 between the source contact portion 11 and the drain contact portion 12, the effective channel length of the oxide thin film transistor can be reduced.

[0049] The on-state current (Ion) of the oxide thin-film transistor is directly proportional to the width-to-length ratio of its channel. With the same channel width-to-length ratio and the same on-state current, if the effective channel length of the oxide thin-film transistor is reduced, its corresponding channel width can also be reduced. This reduces the size of the oxide thin-film transistor, thereby increasing the aperture ratio of the display panel using it. Simultaneously, by placing the channel portion 13 of the active layer 10 below the ion implantation barrier layer 20, the influence of subsequent processes and environmental factors such as light, H2O, H, and O2 on the active layer channel portion can be isolated, improving the stability of the oxide thin-film transistor device.

[0050] like Figure 2 As shown, the array substrate further includes a gate 30 and a gate insulating layer 40. The gate 30 is disposed on the side of the active layer 10 away from the ion implantation barrier layer 20. The gate insulating layer 40 is disposed between the gate 30 and the active layer 10. The orthogonal projection of the gate 30 on the active layer 10 covers the channel portion 13 and the conductor portion 14.

[0051] The array substrate further includes a source electrode 50 and a drain electrode 60. The source electrode 50 is connected to the source contact portion 11 and covers the side of the source contact portion 11 opposite to the gate insulating layer 40. The drain electrode 60 is connected to the drain contact portion 12 and covers the side of the drain contact portion 12 opposite to the gate insulating layer 40. The orthogonal projection of the gate electrode 30 onto the active layer 10 covers the source contact portion 11 and the drain contact portion 12.

[0052] It should be noted that since both the source contact 11 and the drain contact 12 are covered by a metallic material, after the formation of the source 50 and drain 60 during the ion implantation step, neither the source contact 11 nor the drain contact 12 is implanted with ions. The ion doping concentrations of the source contact 11 and the drain contact 12 are lower than the ion doping concentration of the conductor portion 14, making both the source contact 11 and the drain contact 12 semiconductor in nature. By overlapping the gate 30 with the source contact 11 and the drain contact 12 in their thickness direction, when the gate 30 reaches the turn-on voltage, the source contact 11 and the drain contact 12, as well as the channel portion 13, become conductors, thereby turning on the source 50 and the drain 60.

[0053] Furthermore, the array substrate also includes an etch barrier layer 70, which is disposed between the active layer 10 and the ion implantation barrier layer 20.

[0054] like Figure 2 As shown, the oxide thin-film transistor is an ESL-type thin-film transistor, and the etch barrier layer 70 covers the channel portion 13 and the conductor portion 14 of the active layer 10. In the actual fabrication process, the step of forming the etch barrier layer 70 is performed before the steps of forming the source electrode 50 and the drain electrode 60. This protects the active layer 10 from damage caused by the etchant used to form the source electrode 50 and the drain electrode 60, thereby ensuring the electrical performance of the active layer 10.

[0055] Specifically, the material of the etch barrier layer 70 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0056] exist Figure 2 In the embodiment shown, the ion implantation barrier layer 20 is disposed on the side of the etch barrier layer 70 away from the active layer 10, and the ion implantation barrier layer 20 is disposed in the middle region between the source electrode 50 and the drain electrode 60, and is spaced apart from the source electrode 50 and the drain electrode 60.

[0057] The channel portion 13 is aligned with the ion implantation barrier layer 20. The conductor portion 14 is disposed on opposite sides of the channel portion 13, and is offset from the ion implantation barrier layer 20, and is not blocked by the ion implantation barrier layer 20. The conductor portion 14 located on the left side of the channel portion 13 is connected to the source contact portion 11 and the channel portion 13, respectively. The conductor portion 14 located on the right side of the channel portion 13 is connected to the drain contact portion 12 and the channel portion 13, respectively.

[0058] In some other embodiments, the ion implantation barrier layer 20 may also be disposed in any other region between the source 50 and the drain 60, and spaced apart from the source 50 and the drain 60, with the channel portion 13 aligned with the ion implantation barrier layer 20.

[0059] like Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of the second array substrate provided in the embodiments of this application, and its structure is similar to... Figure 2 The structure of the first array substrate shown is roughly the same, except that: the oxide thin film transistor includes a plurality of ion implantation barrier layers 20, all of which are disposed between the source 50 and the drain 60 and are spaced apart from each other.

[0060] The active layer 10 includes a plurality of channel portions 13, each of which is respectively aligned with a plurality of ion implantation barrier layers 20. The portion of adjacent channel portions 13 not covered by the ion implantation barrier layers 20 forms the conductor portion 14. The effective channel length of the oxide thin-film transistor is the sum of the lengths L3 and L4 of two channel portions 13. In practical applications, the number of ion implantation barrier layers 20 disposed between the source 50 and the drain 60 is not limited to one as in the above embodiment, but can also be two, three, or more.

[0061] like Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of the third array substrate provided in the embodiments of this application. Its structure is similar to... Figure 2 The structure of the first array substrate shown is roughly the same, except that: the source electrode 50 includes a main body and an extension, the main body is connected to and covers the corresponding source electrode contact 11, and the extension is connected to the main body and extends to the etch barrier layer 70; and / or the drain electrode 60 includes a main body and an extension, the main body is connected to and covers the corresponding drain electrode contact 12, and the extension is connected to the main body and extends to the etch barrier layer 70.

[0062] The channel portion 13 includes a sub-channel portion disposed opposite to the extension portion, and the opposite sides of the sub-channel portion are respectively connected to one of the source contact portion 11 and the drain contact portion 12, and the conductor portion 14.

[0063] In one embodiment, such as Figure 4As shown, the channel portion 13 includes a main channel portion 131 disposed opposite to the ion implantation barrier layer, and the conductor portion 14 is disposed on opposite sides of the main channel portion 131 and connected to the main channel portion 131.

[0064] The source electrode 50 includes a source body portion 51 that covers and connects to the source contact portion 11, and a source extension portion 52 that extends from the source body portion 51 to the etch barrier layer 70. The drain electrode 60 includes a drain body portion 61 that covers and connects to the drain contact portion 12, and a drain extension portion 62 that extends from the drain body portion 61 to the etch barrier layer 70.

[0065] The channel portion 13 includes two sub-channel portions 132, which are respectively aligned with the source extension portion 52 and the drain extension portion 62. The opposite sides of one sub-channel portion 132 are respectively connected to the source contact portion 11 and the conductor portion 14 near the source contact portion 11, while the opposite sides of the other sub-channel portion 132 are respectively connected to the drain contact portion 12 and the conductor portion 14 near the drain contact portion 12.

[0066] exist Figure 4 In the illustrated embodiment, the effective channel length L of the oxide thin-film transistor is the sum of the length L5 of the main channel portion 131 and the lengths L6 and L7 of the secondary channel portions 132 on both sides. Compared to Figure 1 The array substrate shown, Figure 4 The third array substrate shown can also reduce the effective channel length of the oxide thin film transistor by providing an ion implantation barrier layer 20, a source extension 52, and a drain extension 62.

[0067] In one embodiment, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of the fourth array substrate provided in the embodiments of this application. Its structure is similar to... Figure 4 The structure of the third type of array substrate shown is roughly the same, except that: the array substrate does not have an ion implantation barrier layer 20, but has a source extension portion 52 on the source electrode 50 that extends from the source electrode body portion 51 to the etch barrier layer 70. The channel portion 13 includes only one side channel portion 132, which is aligned with the source extension portion 52. The opposite sides of the side channel portion 132 are connected to the source electrode contact portion 11 and the conductor portion 14.

[0068] In one embodiment, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of the array substrate provided in the embodiments of this application, and its structure is similar to... Figure 5 The fourth type of array substrate shown has a similar structure, but differs in that: the source electrode 50 includes a source body portion 51 covering and connecting the source electrode contact portion 11, and a source extension portion 52 extending from the source body portion 51 to the etch barrier layer 70; the drain electrode 60 includes a drain body portion 61 covering and connecting the drain electrode contact portion 12, and a drain extension portion 62 extending from the drain body portion 61 to the etch barrier layer 70; the channel portion 13 includes only two sub-channel portions 132 respectively aligned with the source extension portion 52 and the drain extension portion 62; the two sub-channel portions 132 are respectively connected to the source electrode contact portion 11 and the drain electrode contact portion 12; and the conductor portion 14 is disposed between the two sub-channel portions 132 and connected to the sub-channel portions 132.

[0069] exist Figures 2 to 6 In the illustrated embodiment, the material of the ion implantation barrier layer 20 can be the same as the material of the source electrode 50 and the drain electrode 60. During the fabrication of the array substrate, the same metal deposition process can be used to simultaneously form the ion implantation barrier layer 20, the source electrode 50, and the drain electrode 60. This reduces the need for a separate photomask step required to form the ion implantation barrier layer 20, thereby lowering production costs.

[0070] In one embodiment, the oxide thin-film transistor can also be a BCE-type thin-film transistor. For example... Figure 7 As shown, Figure 7 This is a schematic diagram of the structure of the sixth array substrate provided in the embodiments of this application. The oxide thin film transistor includes a gate 30, a gate insulating layer 40, an active layer 10, a source 50, a drain 60, a passivation protection layer 80, and an ion implantation barrier layer 20. The passivation protection layer 80 covers the source 50, the drain 60, and the active layer 10. The ion implantation barrier layer 20 is disposed on the side of the passivation protection layer 80 away from the active layer 10.

[0071] The material of the passivation protective layer 80 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0072] The orthographic projection of the ion implantation barrier layer 20 on the active layer 10 is located between the orthographic projections of the source electrode 50 and the drain electrode 60 on the active layer 10, and is offset from the source electrode 50 and the drain electrode 60.

[0073] The active layer 10 includes a channel portion 13, a conductor portion 14, a source contact portion 11, and a drain contact portion 12. The channel portion 13 is aligned with the ion implantation barrier layer 20, and the conductor portion 14 is offset from the ion implantation barrier layer 20.

[0074] The source electrode 50 is connected to the source contact portion 11 and covers the side of the source contact portion 11 away from the gate insulating layer 40. The drain electrode 60 is connected to the drain contact portion 12 and covers the side of the drain contact portion 12 away from the gate insulating layer 40. The two conductor portions 14 are respectively disposed between the source contact portion 11 and the channel portion 13, and between the drain contact portion 12 and the channel portion 13. The length of the channel portion 13 is the effective channel length of the oxide thin film transistor.

[0075] Based on the array substrate provided in the above embodiments of this application, this application also provides a display panel, which is a liquid crystal display panel. The display panel includes an array substrate and a counter substrate disposed opposite each other, and a liquid crystal layer disposed between the array substrate and the counter substrate. The counter substrate can be a color filter substrate. The array substrate can be the array substrate provided in the above embodiments.

[0076] In practical applications, the type of display panel is not limited to the liquid crystal display panel in the above embodiments, but can also be an organic light-emitting diode (OLED) display panel, a mini light-emitting diode (Mini-LED) display panel, or a micro light-emitting diode (Micro-LED) display panel. The display panel may include a light-emitting device layer disposed on the array substrate as provided in the above embodiments. The light-emitting device layer may include multiple light-emitting devices, which may be Micro-LEDs or Mini-LEDs, etc.

[0077] By setting an ion implantation barrier layer within the oxide thin-film transistor on the array substrate, the size of the oxide thin-film transistor can be reduced, the on-state current of the oxide thin-film transistor can be increased, and the stability of the oxide thin-film transistor can be improved. This can prevent insufficient charging of LCD display panels or insufficient brightness of OLED, Mini-LED and Micro-LED.

[0078] Based on the display panel provided in the above embodiments of this application, this application also provides an electronic device, which includes the display panel provided in the above embodiments. The electronic device can be a mobile terminal, such as color electronic paper, color e-book, smartphone, etc. The electronic device can also be a wearable terminal, such as smartwatch, smart bracelet, etc. The electronic device can also be a fixed terminal, such as color electronic billboard, color electronic poster, etc.

[0079] The beneficial effects of this application embodiment are as follows: This application embodiment provides an array substrate and a display panel. The display panel includes an array substrate, which includes an active layer and an ion implantation barrier layer. The active layer is made of metal oxide. The ion implantation barrier layer is disposed on one side of the active layer. The active layer includes a channel portion. By aligning the ion implantation barrier layer with at least a portion of the channel portion, during ion implantation, the ion implantation barrier layer can prevent ions from being implanted into the channel portion, thereby reducing the effective channel length of the oxide thin film transistor, which can increase the on-state current of the oxide thin film transistor. While keeping the aspect ratio of the oxide thin film transistor unchanged, the width of the channel of the oxide thin film transistor can be reduced, thereby reducing the size of the oxide thin film transistor and thus increasing the aperture ratio of the display panel. At the same time, by utilizing the shielding effect of the ion implantation barrier layer on the active layer, the influence of subsequent processes and environmental factors such as light, H2O, H, and O2 on the active layer channel region can also be isolated, improving the stability of the oxide thin film transistor device.

[0080] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; An active layer is disposed on the substrate, and the material of the active layer includes metal oxide; as well as An ion implantation barrier layer is disposed on the side of the active layer opposite to the substrate; The active layer includes a channel portion, and the ion implantation barrier layer is disposed aligned with at least a portion of the channel portion; the array substrate includes an etch barrier layer, which is disposed between the active layer and the ion implantation barrier layer. The active layer further includes a source contact portion, a drain contact portion, and a conductor portion. The conductor portion is disposed between the channel portion and the source contact portion and the drain contact portion. The ion implantation barrier layer is offset from the conductor portion. The ion doping concentration of the channel portion, the source contact portion, and the drain contact portion is lower than the ion doping concentration of the conductor portion.

2. The array substrate as described in claim 1, characterized in that, The array substrate further includes: A gate is disposed on the substrate; and A gate insulating layer is disposed between the gate and the active layer; The gate's orthogonal projection onto the active layer covers the channel portion.

3. The array substrate as described in claim 2, characterized in that, The array substrate further includes a source and a drain, wherein the source is connected to and covers the source contact portion, and the drain is connected to and covers the drain contact portion; The orthogonal projection of the gate onto the active layer covers both the source contact and the drain contact.

4. The array substrate as described in claim 3, characterized in that, The ion implantation barrier layer is disposed between the source and the drain, and is spaced apart from the source and the drain. The channel portion includes a main channel portion disposed opposite to the ion implantation barrier layer, and the conductor portion is disposed on opposite sides of the main channel portion and connected to the main channel portion.

5. The array substrate as described in claim 4, characterized in that, The source electrode includes a main body and an extension, the main body is connected to and covers the corresponding source electrode contact, and the extension is connected to the main body and extends over the etch barrier layer; and / or The drain includes a main body and an extension. The main body is connected to and covers the corresponding drain contact portion, and the extension is connected to the main body and extends over the etch barrier layer.

6. The array substrate as described in claim 5, characterized in that, The channel portion includes a sub-channel portion disposed opposite to the extension portion, and the opposite sides of the sub-channel portion are respectively connected to one of the source contact portion and the drain contact portion, as well as the conductor portion.

7. The array substrate as described in claim 3, characterized in that, The array substrate further includes a passivation protection layer, which covers the source, the drain, and the active layer; The ion implantation barrier layer is disposed on the side of the passivation protection layer opposite to the active layer.

8. The array substrate as claimed in claim 7, characterized in that, The ion implantation barrier layer is disposed on the passivation protection layer. The orthogonal projection of the ion implantation barrier layer on the active layer is located between the orthogonal projections of the source and the drain on the active layer, and is offset from the source and the drain.

9. The array substrate as described in claim 8, characterized in that, The ion implantation barrier layer is disposed on the same layer as the source and the drain, and is made of the same material as the source and the drain.

10. A display panel, characterized in that, It includes an array substrate, a counter substrate, and a liquid crystal layer as described in any one of claims 1 to 9, wherein the liquid crystal layer is disposed between the array substrate and the counter substrate.

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