Intelligent redundant liquid cooling loops for data center cooling systems

Abstract

Disclosed are intelligent redundant liquid-cooled cooling loops for a data center cooling system, particularly systems and methods for cooling a data center. In at least one embodiment, a backup cooling loop having its own fluid source and a liquid-to-liquid heat exchanger is used to alternately cool at least one computing component with an auxiliary cooling loop associated with a primary cooling loop and a cooling facility.

Description

Technical Field

[0001] At least one embodiment relates to cooling systems, including systems and methods for operating such cooling systems. In at least one embodiment, such cooling systems can be used in a data center containing one or more racks or computing servers. Background Art

[0002] Data center cooling systems use fans to circulate air through server components. Some supercomputers or other high-capacity computers may use water or water or other cooling systems instead of air cooling systems to draw heat from the server components or racks in the data center to an area outside the data center. The cooling system may include chillers within the data center area (which may include areas outside the data center itself). In addition, the area outside the data center may include a cooling tower or other external heat exchanger that receives heated coolant from the data center and dissipates heat to the environment (or external cooling medium) through forced air or other means. The cooled coolant is recirculated back to the data center. The chillers and cooling towers together form a cooling facility. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 An exemplary data center cooling system is shown that is subject to the improvements described in at least one embodiment;

[0004] Figure 2 illustrates server-level features associated with an intelligent redundant liquid-cooled cooling loop for a data center liquid cooling system, according to at least one embodiment;

[0005] Figure 3 illustrates rack-level features associated with an intelligent redundant liquid-cooled cooling loop for a data center cooling system, according to at least one embodiment;

[0006] Figure 4 Data center level features associated with intelligent redundant liquid-cooled cooling loops for a data center cooling system are illustrated according to at least one embodiment;

[0007] Figure 5 According to at least one embodiment, Figure 2-4 Methods associated with data center cooling systems;

[0008] Figure 6 A distributed system according to at least one embodiment is shown;

[0009] Figure 7 An exemplary data center is shown in accordance with at least one embodiment;

[0010] Figure 8illustrates a client-server network according to at least one embodiment;

[0011] Figure 9 illustrates a computer network according to at least one embodiment;

[0012] Figure 10A illustrates a networked computer system according to at least one embodiment;

[0013] Figure 10B illustrates a networked computer system according to at least one embodiment;

[0014] Figure 10C illustrates a networked computer system according to at least one embodiment;

[0015] Figure 11 illustrates one or more components of a system environment in which services may be provided as third-party network services according to at least one embodiment;

[0016] Figure 12 illustrates a cloud computing environment according to at least one embodiment;

[0017] Figure 13 illustrates a set of functional abstraction layers provided by a cloud computing environment in accordance with at least one embodiment;

[0018] Figure 14 shows a supercomputer at a chip level according to at least one embodiment;

[0019] Figure 15 illustrates a supercomputer at the rack module level according to at least one embodiment;

[0020] Figure 16 illustrates a supercomputer at the rack level according to at least one embodiment;

[0021] Figure 17 illustrates a supercomputer at an overall system level according to at least one embodiment;

[0022] Figure 18A Inference and / or training logic according to at least one embodiment is shown;

[0023] Figure 18B Inference and / or training logic according to at least one embodiment is shown;

[0024] Figure 19 illustrates the training and deployment of a neural network according to at least one embodiment;

[0025] Figure 20 shows the architecture of a network system according to at least one embodiment;

[0026] Figure 21 shows the architecture of a network system according to at least one embodiment;

[0027] Figure 22 illustrates a control plane protocol stack according to at least one embodiment;

[0028] Figure 23 illustrates a user plane protocol stack according to at least one embodiment;

[0029] Figure 24 Components of a core network according to at least one embodiment are shown;

[0030] Figure 25 Components of a system supporting network functions virtualization (NFV) according to at least one embodiment are shown;

[0031] Figure 26 A processing system according to at least one embodiment is shown;

[0032] Figure 27 A computer system according to at least one embodiment is shown;

[0033] Figure 28 A system according to at least one embodiment is shown;

[0034] Figure 29 An exemplary integrated circuit according to at least one embodiment is shown;

[0035] Figure 30 A computing system according to at least one embodiment is shown;

[0036] Figure 31 An APU is shown according to at least one embodiment;

[0037] Figure 32 A CPU according to at least one embodiment is shown;

[0038] Figure 33 An exemplary accelerator integrated slice is shown in accordance with at least one embodiment;

[0039] Figures 34A-34B An exemplary graphics processor is shown in accordance with at least one embodiment;

[0040] Figure 35A A graphics core according to at least one embodiment is shown;

[0041] Figure 35B GPGPU according to at least one embodiment is shown;

[0042] Figure 36A A parallel processor according to at least one embodiment is shown;

[0043] Figure 36B illustrates a processing cluster according to at least one embodiment;

[0044] Figure 36C A graphics multiprocessor is shown in accordance with at least one embodiment;

[0045] Figure 37 illustrates a software stack for a programming platform according to at least one embodiment;

[0046] Figure 38 According to at least one embodiment, Figure 37 CUDA implementation of the software stack;

[0047] Figure 39 According to at least one embodiment, Figure 37 ROCm implementation of the software stack;

[0048] Figure 40 According to at least one embodiment, Figure 37 OpenCL implementation of the software stack;

[0049] Figure 41 illustrates software supported by a programming platform according to at least one embodiment; and

[0050] Figure 42 According to at least one embodiment, a method for Figures 37-40 Compiled code that is executed on a programming platform. DETAILED DESCRIPTION

[0051] In at least one embodiment, the exemplary data center 100 (e.g. Figure 1), the exemplary data center has an improved cooling system as described herein. In at least one embodiment, numerous specific details are set forth to provide a thorough understanding, but the concepts herein may be practiced without one or more of these specific details. In at least one embodiment, a data center cooling system can respond to sudden high thermal demands caused by varying computational loads in today's computing components. In at least one embodiment, because these demands vary or tend to range from a minimum to a maximum value for different cooling demands, an appropriate cooling system must be used to economically meet these demands. In at least one embodiment, for moderate to high cooling demands, a liquid cooling system can be used. In at least one embodiment, high cooling demands are economically met by localized immersion cooling. In at least one embodiment, these different cooling demands also reflect the different thermal signatures of the data center. In at least one embodiment, the heat generated from these components, servers, and racks is cumulatively referred to as a thermal signature or cooling demand because the cooling demand must fully address the thermal signature.

[0052] In at least one embodiment, a data center liquid cooling system is disclosed. In at least one embodiment, the data center cooling system addresses thermal signatures in associated computing or data center equipment, such as thermal signatures in a graphics processing unit (GPU), a switch, a dual in-line memory module (DIMM), or a central processing unit (CPU). In at least one embodiment, these components may be referred to herein as high heat density computing components. Furthermore, in at least one embodiment, the associated computing device or data center equipment may be a processing card having one or more GPUs, switches, or CPUs thereon. In at least one embodiment, each of the GPUs, switches, and CPUs may be a heating signature of the computing device. In at least one embodiment, the GPU, CPU, or switch may have one or more cores, and each core may be a heating signature.

[0053] In at least one embodiment, a smart redundant liquid-cooled cooling loop provides redundancy for a liquid data center cooling system that utilizes a primary cooling loop to secondary cooling loop architecture. In at least one embodiment, the liquid-cooled cooling loop serves as a backup cooling loop for a secondary cooling loop that is backed up by the primary cooling loop. In at least one embodiment, redundancy can be achieved by a backup cooling loop with its own fluid source and a liquid-to-liquid heat exchanger that uses facility water to cool the backup coolant or secondary coolant stored in the fluid source and then circulates the backup coolant or secondary coolant back to at least one cold plate.

[0054] In at least one embodiment, at least one cold plate is designed to support an auxiliary cooling circuit and a backup cooling circuit. In at least one embodiment, in the event of a failure in the primary cooling circuit, the backup cooling circuit can be engaged to provide immediate and temporary cooling until the failure is resolved. In at least one embodiment, the failure may be that the primary cooling circuit is unable or insufficient to provide adequate heat exchange to the auxiliary cooling circuit. In at least one embodiment, the failure may be such that the auxiliary coolant of the auxiliary cooling circuit is sufficiently cooled by the primary cooling circuit to be effective when re-entering the cold plate for further cooling. In at least one embodiment, the backup cooling circuit is a closed-loop cooling circuit capable of operating independently of the auxiliary and primary cooling circuits. In at least one embodiment, the backup cooling circuit can use a backup coolant instead of the auxiliary coolant. In at least one embodiment, the backup coolant can be a common coolant. In at least one embodiment, the backup coolant or the auxiliary coolant can be cooled by an external liquid source that interfaces with the backup coolant or the auxiliary coolant in a liquid-to-liquid heat exchanger.

[0055] In at least one embodiment, redundant liquid cooling of a data center cooling system can be achieved by providing flow lines, at least one flow controller, at least one liquid-to-liquid heat exchanger, and at least one fluid source. In at least one embodiment, redundant liquid cooling can be achieved for at least one cold plate having a port for auxiliary coolant of an auxiliary cooling circuit. In at least one embodiment, the cold plate can have a separate port for backup coolant of a backup cooling circuit. In at least one embodiment, the at least one flow controller can be activated when a flow or temperature problem is identified in the auxiliary cooling circuit or in a primary cooling circuit associated with the auxiliary cooling circuit. In at least one embodiment, the at least one flow controller enables fluid from the fluid source to flow to the cold plate and back to the fluid source. In at least one embodiment, flow from the fluid source to the cold plate and back to the fluid source occurs through a liquid-to-liquid heat exchanger. In at least one embodiment, the liquid-to-liquid heat exchanger can be located in a separate fluid path to allow heat to dissipate from the fluid source (for the backup coolant or the standby coolant) to the facility fluid. In at least one embodiment, the refrigerant in the condenser unit can be associated with the fluid source to provide cooling via the liquid-to-liquid heat exchanger. In at least one embodiment, the backup cooling circuit enables a local circuit to resolve temporary problems in the primary cooling circuit of the data center.

[0056] In at least one embodiment, a problem addressed in the intelligent redundant liquid-cooled cooling circuit may include a lack of redundancy in a primary cooling circuit. In at least one embodiment, while redundancy may be provided for blockages or leaks in a secondary cooling circuit, another problem addressed in the intelligent redundant liquid-cooled cooling circuit may be providing redundancy in the event of a failure in the primary cooling circuit or a cooling tower associated with the primary cooling circuit. In at least one embodiment, the intelligent redundant liquid-cooled cooling circuit provides an independent, redundant path for a "secondary" secondary coolant (such as via a backup cooling circuit) that is distinct from the secondary cooling circuit and removes heat from the secondary coolant or provides cooling via the backup coolant until normal operation of the primary cooling circuit is restored.

[0057] In at least one embodiment, the Figure 1 An exemplary data center 100 is shown having a cooling system that has undergone the improvements described herein. In at least one embodiment, the data center 100 can be one or more rooms 102 having racks 110 and auxiliary equipment for accommodating one or more servers on one or more server trays. In at least one embodiment, the data center 100 is supported by a cooling tower 104 located outside the data center 100. In at least one embodiment, the cooling tower 104 removes heat from within the data center 100 by acting on a primary cooling loop 106. In at least one embodiment, a cooling distribution unit (CDU) 112 is used between the primary cooling loop 106 and a secondary or secondary cooling loop 108 to enable heat to be extracted from the secondary or secondary cooling loop 108 to the primary cooling loop 106. In at least one embodiment, in one aspect, the secondary cooling loop 108 can be connected to the server trays with various ducting as needed. In at least one embodiment, the loops 106, 108 are shown as line diagrams, but one of ordinary skill in the art will recognize that one or more ducting features may be used. In at least one embodiment, flexible polyvinyl chloride (PVC) tubing can be used with associated piping to move fluid along each provided loop 106, 108. In at least one embodiment, one or more coolant pumps can be used to maintain a pressure differential within the coolant loops 106, 108 to enable coolant movement in response to temperature sensors in various locations, including within the room, within one or more racks 110, and / or within server boxes or server trays within one or more racks 110.

[0058] In at least one embodiment, the coolant in the primary cooling loop 106 and the secondary cooling loop 108 can be at least water and an additive. In at least one embodiment, the additive can be ethylene glycol or propylene glycol. In operation, in at least one embodiment, each of the primary cooling loop and the secondary cooling loop can have its own coolant. In at least one embodiment, the coolant in the secondary cooling loop can be dedicated to the requirements of the components in the server tray or associated rack 110. In at least one embodiment, the CDU 112 is capable of providing complex control over the coolant provided in the coolant loops 106, 108, either independently or simultaneously. In at least one embodiment, the CDU can be adapted to control the flow rate of the coolant so that the coolant is appropriately distributed to absorb the heat generated within the associated rack 110. In at least one embodiment, further flexible tubing 114 is provided from the secondary cooling loop 108 to enter each server tray to provide coolant to the electrical and / or computing components therein.

[0059] In at least one embodiment, the tubing 118 forming part of the auxiliary cooling loop 108 can be referred to as a room manifold. Separately, in at least one embodiment, another tubing 116 can extend from the row manifold tubing 118 and can also be part of the auxiliary cooling loop 108, but can be referred to as a row manifold. In at least one embodiment, the coolant line 114 enters the rack as part of the auxiliary cooling loop 108, but can be referred to as one or more intra-rack rack cooling manifolds. In at least one embodiment, the row manifold 116 extends to all racks along a row in the data center 100. In at least one embodiment, the piping of the auxiliary cooling loop 108, including the coolant manifolds 118, 116, and 114, can be improved by at least one embodiment herein. In at least one embodiment, a chiller 120 can be provided in the primary cooling loop within the data center 102 to support cooling before the cooling tower. In at least one embodiment, for the present disclosure, an additional cooling circuit that may be present in the primary control circuit and provide cooling external to the rack and external to the auxiliary cooling circuit may be used with the primary cooling circuit and distinct from the auxiliary cooling circuit.

[0060] In at least one embodiment, during operation, heat generated within the server trays of a provided rack 110 can be transferred via the flexible tubing of the drain manifold 114 of the auxiliary cooling loop 108 to coolant exiting one or more racks 110. In at least one embodiment, secondary coolant (in the auxiliary cooling loop 108) from the CDU 112, used to cool the provided racks 110, moves toward the one or more racks 110 (via provided tubing). In at least one embodiment, the secondary coolant from the CDU 112 is transferred from one side of the room manifold having tubing 118 to one side of the rack 110 via the drain manifold 116 and passes through one side of the server trays via different tubing 114. In at least one embodiment, the spent or returned secondary coolant (or the exiting secondary coolant that has removed heat from the computing components) exits from the other side of the server trays (such as entering the left side of the rack for the server tray and exiting the right side of the rack after circulating through the server trays or components on the server trays). In at least one embodiment, the spent second coolant exiting the server trays or racks 110 exits a different side of the tubes 114 (such as the outlet side) and moves to the parallel, also outlet side, of the drain manifold 116. In at least one embodiment, the spent second coolant moves from the drain manifold 116 in a parallel portion of the drain manifold 118 and flows in an opposite direction from the incoming second coolant (which may also be refreshed second coolant) and toward the CDU 112.

[0061] In at least one embodiment, the spent second coolant exchanges its heat with the primary coolant in the primary cooling loop 106 via the CDU 112. In at least one embodiment, the spent second coolant can be refreshed (such as relatively cooled compared to the temperature of the spent second coolant stage) and ready to be circulated back through the secondary cooling loop 108 to one or more computing components. In at least one embodiment, various flow and temperature control features in the CDU 112 enable control of the exchange of heat from the spent second coolant or control of the flow of the second coolant into and out of the CDU 112. In at least one embodiment, the CDU 112 can also control the flow of the primary coolant in the primary cooling loop 106.

[0062] In at least one embodiment, Figure 2The illustrated server-level feature 200 can be associated with an intelligent, redundant, liquid-cooled cooling loop for a data center cooling system. In at least one embodiment, the server-level feature 200 includes a server tray or chassis 202. In at least one embodiment, the server tray or chassis 202 includes a server manifold 204 tightly coupled between provided cold plates 210A-D of the server tray or chassis 202 and a rack manifold of a rack housing the server tray or chassis 202. In at least one embodiment, the server tray or chassis 202 includes one or more cold plates 210A-D associated with one or more computing or data center components or devices 220A-D. In at least one embodiment, one or more server-level cooling loops 214A,B can be disposed between the server manifold 204 and the one or more cold plates 210A-D. In at least one embodiment, each server-level cooling loop 214A,B includes an inlet line 210 and an outlet line 212. In at least one embodiment, when the cold plates 210A,B are arranged in series, an intermediate line 216 can be provided. In at least one embodiment, one or more cold plates 210A-D can support various ports and channels for auxiliary coolant for the auxiliary cooling circuit or backup coolant for the backup cooling circuit. In at least one embodiment, the backup cooling circuit can be used to cool and circulate the auxiliary coolant used by the auxiliary cooling circuit. In at least one embodiment, the fluid used for cooling can be provided to the server manifold 204 via provided inlet and outlet lines 206A, 206B.

[0063] In at least one embodiment, the server tray 202 is an immersion-cooled server tray that can be submerged in a fluid. In at least one embodiment, the fluid used to immerse the server tray can be a dielectric engineered fluid that can be used in immersion-cooled servers. In at least one embodiment, a secondary coolant can be used to cool the engineered fluid. In at least one embodiment, the backup coolant can be used to cool the engineered fluid when a primary cooling circuit associated with a secondary cooling circuit that circulates the secondary coolant fails or is failing. Thus, in at least one embodiment, at least one cold plate has ports for both the secondary cooling circuit and the backup cooling circuit and can support activation of the backup cooling circuit in the event of a failure in the primary cooling circuit.

[0064] In at least one embodiment, at least one dual-cooled cold plate 210B; 250 can be configured to operate in conjunction with conventional cold plates 210A, C, and D. In at least one embodiment, the conventional cold plate can be used in conjunction with a backup cooling circuit, such that auxiliary coolant from the auxiliary cooling circuit can be diverted to the fluid source of the backup cooling circuit and cooled using a liquid-to-liquid heat exchanger before being circulated back to the conventional cold plate. In at least one embodiment, the conventional cold plate is adapted to support auxiliary coolant from both the auxiliary cooling circuit and the backup cooling circuit.

[0065] In at least one embodiment, a three-dimensional (3D) enlarged view (cold plate 250) provides internal details of at least some features that may be included in the dual-cooled cold plate 210B. In at least one embodiment, the dual-cooled cold plate 250 has distinct paths 264, 270 for auxiliary coolant for the auxiliary cooling circuit and backup coolant for the backup cooling circuit characterized by a fluid source. In at least one embodiment, the auxiliary or backup coolant may not be dielectric in nature. In at least one embodiment, in the use case of immersion cooling servers, the fluid may be suitable for both cold plate applications and immersion cooling server tray applications, and the fluid may be a dielectric engineered fluid.

[0066] In at least one embodiment, unless otherwise specified, reference to a cold plate and its dual cooling feature is intended to refer to a cold plate capable of supporting at least two types of cooling circuits. In at least one embodiment, both types of cold plates receive fluid for cooling from the same auxiliary cooling circuit and can both support a backup cooling circuit. In at least one embodiment, a standard coolant (such as facility water) can be used in both the auxiliary cooling circuit and the backup cooling circuit, so that the backup cooling circuit can temporarily cool the auxiliary coolant via a liquid-to-liquid heat exchanger during a failure of the primary cooling circuit associated with the auxiliary cooling circuit.

[0067] Thus, in at least one embodiment, the backup coolant can be the same or similar to the auxiliary coolant to avoid issues related to chemical differences and manufacturer requirements of cold plates used in data center cooling systems. In at least one embodiment, the fluid can be used only for cold plates and not for immersion cooling. In at least one embodiment, each type of cold plate receives a different fluid from a respective auxiliary cooling circuit or other cooling circuits that interface with the primary cooling circuit. In at least one embodiment, where different fluids are used with different coolant distribution units (CDUs) for different auxiliary circuits, the backup cooling circuit can be adapted for dual cooling cold plates so that different channels can be used for each backup coolant and the different auxiliary coolants.

[0068] In at least one embodiment, the dual cooling cold plate 250 is adapted to receive two types of fluid (such as auxiliary coolant and backup coolant) and maintain the two types of fluid distinct from one another through its distinct ports 252, 272; 268, 262 and its distinct paths 264, 270. In at least one embodiment, each distinct path is a fluid path. In at least one embodiment, the fluid from the fluid source (such as the backup coolant) and the auxiliary coolant can have the same or similar composition and can be re-stored from the same source in the data center cooling system.

[0069] In at least one embodiment, the dual-cooled cold plate 250 includes ports 252, 272 for receiving fluid into the cold plate 250 and exhausting fluid from the cold plate 250. In at least one embodiment, the dual-cooled cold plate 250 includes ports 268, 262 for receiving auxiliary coolant into the cold plate 250 and exhausting auxiliary coolant from the cold plate 250. In at least one embodiment, the ports 252, 272 can have directional and pressure-controlled valve covers 254, 260. In at least one embodiment, a valve cover can be associated with all provided ports. In at least one embodiment, the provided valve covers 254, 260 are mechanical features of an associated flow controller, which also have corresponding electronic features (such as at least one processor for executing instructions stored in an associated memory and controlling the mechanical features of the associated flow controller).

[0070] In at least one embodiment, each valve is actuable by an electronic feature of an associated flow controller. In at least one embodiment, the electronic and mechanical features of a provided flow controller are integrated. In at least one embodiment, the electronic and mechanical features of a provided flow controller are physically distinct. In at least one embodiment, reference to a flow controller can be one or more provided electronic and mechanical features or a combination thereof, but at least relates to features capable of controlling the flow of coolant or fluid through each cold plate or immersion cooled server tray or box.

[0071] In at least one embodiment, the electronic feature of the provided flow controller receives the control signal and asserts control of the mechanical feature. In at least one embodiment, the electronic feature of the provided flow controller can be an actuator or other electronic component with similar electromechanical features. In at least one embodiment, a flow pump can be used as the flow controller. In at least one embodiment, an impeller, piston, or bellows can be the mechanical feature, and the electronic motor and circuitry form the electronic feature of the provided flow controller.

[0072] In at least one embodiment, the circuitry of the provided flow controller can include a processor, memory, switches, sensors, and other components that collectively comprise the electronic features of the provided flow controller. In at least one embodiment, the provided ports 252, 262, 272, 268 of the provided flow controller are adapted to allow entry or exit of an immersion fluid. In at least one embodiment, the flow controller 280 can be associated with a fluid line 276 (also 256, 274) that allows fluid (such as a backup coolant) to enter and exit the cold plate 210B. In at least one embodiment, other flow controllers can be similarly associated with the coolant lines 210, 216, 212 (also 266, 258) to allow auxiliary coolant to enter or exit the cold plate 210B.

[0073] In at least one embodiment, a fluid (such as a backup coolant) enters the provided fluid lines 276 via dedicated fluid inlet and outlet lines 208A, B. In at least one embodiment, the server manifold 204 and the channels therein (as shown in dashed lines) are adapted to support different paths to the different fluid lines 276 (also 256, 274) and any remaining loops 214A, B associated with the auxiliary coolant inlet and outlet lines 206A, B. In at least one embodiment, there can be multiple manifolds to support the fluid (backup coolant) and the auxiliary coolant, respectively. In at least one embodiment, there can be multiple manifolds to support the inlet and outlet for each fluid and auxiliary coolant. In at least one embodiment, if the fluid is the same or similar to the auxiliary coolant, then flow to the fluid source (such as a backup coolant) via the same fluid path (at least within the cold plate or server tray) is achieved. Figure 3 332 in the tank) and auxiliary coolant drain manifolds (such as Figure 3 At least two different fluids in the row manifold 350).

[0074] In at least one embodiment, the first flow can be to allow a fluid (such as a backup coolant) to flow through one or more of the provided ports 252, 272 and associated pathways 270. In at least one embodiment, the dual-cooled cold plate 250 can have isolated plate sections filled with fluid and / or auxiliary coolant while being kept distinct from one another by gaskets or seals. In at least one embodiment, the second flow can be to allow auxiliary coolant to flow through the provided ports 268, 262 and associated pathways 264.

[0075] In at least one embodiment, flow controllers 278 may be associated with the fluid inlet 276 and outlet sections at the server manifold 204, rather than with the flow controllers 280 provided at each cold plate. In at least one embodiment, the first flow utilizes only backup coolant and may be enabled when a failure is determined to have occurred in the auxiliary cooling loop or the primary cooling loop, rendering the auxiliary coolant ineffective in extracting heat from at least one computing device. In at least one embodiment, the failure may be that the auxiliary coolant is not being adequately cooled by the CDU, and therefore may not be able to extract sufficient heat from at least one computing device through its associated cold plate.

[0076] In at least one embodiment, before backup coolant (or auxiliary coolant) from a fluid source in a backup cooling circuit is used to temporarily address cooling of at least one computing component, the auxiliary coolant from the CDU can be shut down first. In at least one embodiment, the first flow provides redundancy for failures in the auxiliary cooling circuit. In at least one embodiment, when a failure is determined, there is no auxiliary coolant flow from the CDU. In at least one embodiment, auxiliary coolant from the backup cooling circuit can be allowed to enter the cold plate 210B simultaneously with auxiliary coolant from the CDU until a shutdown of the CDU flow is performed to allow corrective action to be taken with respect to the auxiliary cooling circuit or the primary cooling circuit. In at least one embodiment, this represents the first and second flows (auxiliary coolant and backup coolant flows) occurring together.

[0077] In at least one embodiment, Figure 3 The rack-level feature 300 shown can be associated with an intelligent redundant liquid cooling loop for a data center cooling system. In at least one embodiment, the rack-level feature 300 includes a rack 302 having brackets 304, 306 for suspending cooling manifolds 314A, B. In at least one embodiment, the cooling manifolds 314A, B can be provided to connect the server-level feature 200 (and Figure 3 308) and a CDU for the auxiliary cooling circuit (such as Figure 4 The CDUs 362 and 364 may be used to transfer auxiliary coolant or backup coolant between the CDUs 406 and 364, or between the fluid source 332 of the backup cooling circuit of the data center cooling system. In at least one embodiment, different CDUs 362 and 364 may serve different racks. In at least one embodiment, different rack cooling manifolds may be different parts of the auxiliary cooling circuit and the backup cooling circuit.

[0078] In at least one embodiment, rack level features 300 may include a backup cooling circuit supported by a fluid source 332; at least one flow controller 344A, 344B, 346A, 346B; a liquid-liquid heat exchanger 338 and fluid paths 364, 366, 368, 370. In at least one embodiment, a cold plate (such as Figure 2 The flow controller associated with the cooling circuit may be part of at least one flow controller supporting the backup cooling circuit. Figure 2 The flow controller description can be applied to Figure 3 Flow controllers in rack-level features 300. In at least one embodiment, the described flow controllers can be adapted to different flow rates and volumes, allowing them to be used in cold plates or cooling manifolds, depending on the application.

[0079] In at least one embodiment, a backup cooling loop can be associated with at least one computing device 324 and an associated cold plate 326. In at least one embodiment, another fluid path can be implemented for the backup cooling loop via inlet and outlet lines 320, 322 and path 354. In at least one embodiment, the auxiliary cooling loop has a different fluid path that can be implemented via inlet and outlet lines 316, 318. In at least one embodiment, a single fluid path is used with a splitter flow controller between the fluid source 332 and the drain manifold 350 associated with the auxiliary cooling loop. In at least one embodiment, the immersed server tray 352 has lines therein to deliver auxiliary coolant or backup coolant for cooling the immersed fluid.

[0080] In at least one embodiment, a splitter flow controller is capable of routing backup or auxiliary coolant from a single inlet line to two outlet lines. In at least one embodiment, auxiliary coolant from an auxiliary cooling circuit supported by a CDU that interfaces with the primary cooling circuit enters the row manifold 350 for distribution to different racks, such as rack 302. In at least one embodiment, the auxiliary coolant from the row manifold 350 is delivered to the flow controller 310C via the rack inlet lines 310A. In at least one embodiment, by default, the flow controller 310C delivers the auxiliary coolant via the cooling manifold inlet lines 310 to the inlet rack manifold 314A. In at least one embodiment, the auxiliary coolant is delivered to one or more cold plates 326 and exits to the outlet rack manifold 314B via corresponding server outlet lines 318. In at least one embodiment, the auxiliary coolant travels via the cooling manifold outlet lines 312, the flow controller 312C, and the rack outlet lines 312A. In at least one embodiment, the auxiliary coolant enters the same bank of manifolds 350 for circulation back to the CDUs, or enters a different bank of manifolds for circulation back to the CDUs.

[0081] In at least one embodiment, a backup cooling circuit alternates with an auxiliary cooling circuit to provide auxiliary cooling for at least one computing component 324. In at least one embodiment, because the auxiliary cooling circuit can be associated with the primary cooling circuit and the cooling facility, a failure in any of the auxiliary cooling circuit, the primary cooling circuit, the CDU, or the cooling facility may need to be fixed to these respective features. In at least one embodiment, a service level agreement (SLA) may describe the permissible downtime for these respective features. In at least one embodiment, the downtime for these respective features may be factored into the capacity of the fluid source 332 of the retention feature 330. In at least one embodiment, the capacity of the fluid source 332 enables it to accommodate a certain volume of backup coolant or auxiliary coolant and to support cooling during an outage of the auxiliary cooling circuit or the primary cooling circuit (including its components, such as the CDU and cooling tower). In at least one embodiment, the retention feature 330 may be a mobile pallet with wheels to support relocation. In at least one embodiment, the retention feature 330 includes brackets 334 and 336 for suspending the piping and electronics associated with the flow controller and fluid source 332.

[0082] In at least one embodiment, when a failure occurs in the primary cooling circuit, the auxiliary cooling circuit, or the cooling facility, parameters such as flow rate, flow velocity, and the expected temperature of the backup coolant (or auxiliary coolant) can be used to determine the capacity of the fluid source 332. In at least one embodiment, the downtime described in the SLA can be compensated by the parameters implemented for the backup cooling circuit, so that sufficient redundant cooling can be provided by the backup cooling circuit until the failure of any of the primary cooling circuit, the auxiliary cooling circuit, or related components can be repaired.

[0083] In at least one embodiment, in the event of a failure in the primary cooling circuit, the auxiliary cooling circuit, or the cooling facility, at least one processor, upon determining the failure, can cause at least one of the flow controllers 310C, 312C, 344A, 344B, 346A, 346B to simultaneously shut down the auxiliary cooling circuit to at least one rack 302 and engage the backup cooling circuit. In at least one embodiment, the flow controllers 310C, 312C can achieve shutdown of the auxiliary cooling circuit by diverting the flow of auxiliary coolant via line 364 to the backup cooling row manifold 360. In at least one embodiment, entirely separate lines and rack manifolds can be used in conjunction with the backup cooling row manifold 360. In at least one embodiment, the retention feature 330 can be directly associated with one or more racks 302 located near the retention feature 330. In at least one embodiment, the backup cooling row manifold 360 may not be required.

[0084] In at least one embodiment, the backup cooling row manifold 360 is in fluid communication with the retention feature 330 via line 366, which forms a loop with line 364. In at least one embodiment, a refrigerant cooling system or facility water cooling system 362 circulates refrigerant or facility water to extract heat from the backup coolant or auxiliary coolant in the retention feature 330. Thus, in at least one embodiment, refrigerant, facility water, or coolant can be provided from system 362 to cool the liquid in the liquid-to-liquid heat exchanger. In at least one embodiment, the retention feature 330 has a composite or metal body structure. In at least one embodiment, flow controllers 334A, 344B can be provided to circulate the backup coolant or auxiliary coolant to the radiant line 338A of the liquid-to-liquid heat exchanger 338 via line 370. In at least one embodiment, when the auxiliary cooling loop associated with the CDU is active, the backup or auxiliary coolant from the fluid source 332 is retained within the fluid source 332. In at least one embodiment, the backup cooling loop can be identified as active when backup or auxiliary coolant is directed to the racks 302 and cooled in the liquid-to-liquid heat exchanger 338. In at least one embodiment, the refrigerant cooling system or facility-water cooling system 362 can be located external to the data center. In at least one embodiment, the facility water cooling system can be air cooled at a location external to the data center.

[0085] In at least one embodiment, at least one processor can be provided to include one or more neural networks. In at least one embodiment, the one or more neural networks can be enabled to determine a failure in a primary cooling circuit or a secondary cooling circuit, including a failure in a cooling facility or CDU. In at least one embodiment, the at least one processor can be enabled to cause at least one flow controller to enable a backup cooling circuit. In at least one embodiment, at least the diverter flow controllers 310C, 312C initiate a backup cooling circuit with a backup cooling row manifold 360. In at least one embodiment, as the temperature of the backup coolant or secondary coolant in the backup cooling row manifold 360 increases, the flow controllers 346A, 346B of the fluid source 332 can circulate the backup coolant or secondary coolant from the backup cooling row manifold 360 to the fluid source 332 and back to the backup cooling row manifold 360. In at least one embodiment, circulation to the fluid source 332 can reduce the temperature of the backup coolant or auxiliary coolant, either because of thermal stability achieved using the existing backup coolant or auxiliary coolant within the fluid source 332, which is cooler due to isolation from the cooling process or due to cooling enabled by the liquid-to-liquid heat exchanger 338.

[0086] In at least one embodiment, at least one cooling manifold, such as a backup cooling row manifold 360, can be provided in the fluid path of the backup cooling loop to support the flow of backup coolant or fluid from the fluid source 332 via the fluid path to the cold plate 326 of the at least one computing component 324. In at least one embodiment, the fluid path can include multiple sub-loops, such as a rack loop 364, a fluid source loop 366, and liquid-liquid heat exchanger loops 368, 370. In at least one embodiment, the at least one cooling manifold is part of the rack loop 364.

[0087] In at least one embodiment, the cold plate 326 can be adapted to interface with both a backup cooling circuit and an auxiliary cooling circuit such that at least one flow controller can be used to prevent auxiliary coolant from the CDU from reaching the cold plate 326 while still allowing auxiliary coolant within the at least one cooling manifold 360 to flow to the fluid source 332 and circulate back to the cold plate 326 as part of the backup cooling circuit. In at least one embodiment, a liquid-to-liquid heat exchanger 338 can be located within the fluid source circuit 366 fluidly coupled in series with the retention feature 330 such that fluid flows from the backup cooling row manifold 360 to the liquid-to-liquid heat exchanger 338 and then to the fluid source 332 to achieve thermal stabilization before being returned to the backup cooling row manifold 360. In at least one embodiment, the backup coolant or auxiliary coolant can first flow to the fluid source 332 before the liquid-to-liquid heat exchanger 338 and then directly to the backup cooling row manifold 360 for use with the at least one cold plate 326.

[0088] In at least one embodiment, at least one flow controller 310C, 312C (or a valve cover of a flow controller associated with ports 268, 260, such as a valve cover 268, 260) may be used when the outlet temperature of the auxiliary coolant is within a threshold of the inlet temperature of the auxiliary coolant. Figure 2 ) to prevent the auxiliary coolant from reaching the cold plate. In at least one embodiment, a threshold between the inlet temperature and the outlet temperature can indicate that the auxiliary coolant is not being adequately cooled by the primary cooling circuit. In at least one embodiment, insufficient cooling of the auxiliary coolant can indicate a failure in the auxiliary cooling circuit, the primary cooling circuit, or any associated cooling components of these respective cooling circuits. In at least one embodiment, the inlet temperature and the outlet temperature can be associated with the inlet and outlet of the auxiliary coolant relative to the CDU. In at least one embodiment, the temperature can be sensed at the rack 302 or the CDU. In at least one embodiment, a sensor can be associated with the rack or CDU to monitor the temperature of the auxiliary coolant.

[0089] In at least one embodiment, at least one processor may be used to determine that an auxiliary cooling circuit is operating outside a threshold cooling requirement of at least one computing device. In at least one embodiment, the threshold cooling requirement is a specified cooling requirement required for normal operation of the at least one computing device. In at least one embodiment, the indication that the auxiliary cooling circuit is operating outside the threshold may result in a backup cooling circuit being used to meet the threshold cooling requirement of the at least one computing device instead.

[0090] In at least one embodiment, the refrigerant cooling system or facility water cooling system 362 can be located external to the data center in association with the data center cooling system. In at least one embodiment, the refrigerant cooling system or facility water cooling system 362 can be associated with a condenser, compressor, or air cooling to achieve cooling of the liquid in the liquid-to-liquid heat exchanger 338. In at least one embodiment, the liquid used in the liquid-to-liquid heat exchanger can be refrigerant or facility water. In at least one embodiment, the auxiliary coolant can be facility water and can include additives. In at least one embodiment, the liquid from the refrigerant cooling system or facility water cooling system 362 absorbs heat from the auxiliary coolant of the auxiliary cooling loop or from the backup coolant of the backup cooling loop. In at least one embodiment, the refrigerant can be in a vapor phase but transitions to a liquid phase as it extracts heat from the auxiliary coolant or backup coolant in the liquid-to-liquid heat exchanger 338.

[0091] In at least one embodiment, Figure 4 The data center-level features 400 shown may be associated with an intelligent redundant liquid-cooled cooling loop for a data center cooling system. In at least one embodiment, the data center-level features 400 within a data center 402 may include racks 404 for hosting one or more server trays or chassis; one or more CDUs 406 for exchanging heat between a secondary cooling loop 412 and a primary cooling loop 422; one or more drain manifolds 410 for distributing coolant from the CDUs 406; and associated various flow controllers 424; as well as inlet and outlet lines 412, 414, 416, 418.

[0092] In at least one embodiment, a fluid source 420 can be provided within the retention feature to include an auxiliary coolant or backup coolant. In at least one embodiment, the fluid source 420 can be associated with a different row manifold 432 than the cooling manifold 410 otherwise used with the CDU 406. In at least one embodiment, the fluid source 420 may be able to use the same cooling manifold as the CDU 406 when the chemistry between the auxiliary coolants of the CDUs is different or within a chemistry threshold associated with the backup coolant stored in the fluid source 420.

[0093] In at least one embodiment, different row manifolds can be associated with different racks. In at least one embodiment, different coolants can be chemically matched or mismatched with respect to the backup coolant. In at least one embodiment, different fluid sources are provided to different CDUs as a redundancy feature based on the chemical properties of the different auxiliary coolants used with each different provided CDU. In at least one embodiment, in the event of a failure of one available CDU, a specific fluid source 420 and associated piping (cooling manifolds, flow controllers, and fluid paths) can be used to provide backup coolant previously received from the affected CDU. In at least one embodiment, at least one flow controller can be associated with a fluid source and a corresponding CDU. In at least one embodiment, at least one flow controller can be provided to divert auxiliary coolant from the CDU to the fluid source and back to the cold plate, so that the CDU can be repaired to at least one computing device requiring cooling provided by the CDU without downtime.

[0094] In at least one embodiment, when a failure of a respective CDU is determined, a backup coolant or auxiliary coolant that is pre-stored in a fluid source and pre-cooled by a liquid-to-liquid heat exchanger 430 before being supplied to one or more cold plates may be used in a manner similar to that described above. Figure 2 、 Figure 3 In the manner described, thermal and chemical verification is first performed for one or more cold plates. In at least one embodiment, the thermal and / or chemical verification provided from the fluid source 420 can cause the backup coolant to be at an expected temperature (or temperature range) and / or an expected chemical composition (or within a range of chemical properties) that was intended to be provided from the corresponding CDU (before its failure).

[0095] In at least one embodiment, a processor may be provided for monitoring various aspects of a secondary cooling circuit or a primary cooling circuit and for determining when to engage a backup cooling circuit by controlling one or more flow controllers. In at least one embodiment, the processor includes one or more circuits for controlling the one or more flow controllers of the backup cooling circuit. In at least one embodiment, the backup cooling circuit includes a fluid source 420, at least one flow controller 424, a liquid-liquid heat exchanger 430, and fluid paths 436A, 436B. In at least one embodiment, the backup cooling circuit may be associated with at least one computing device. In at least one embodiment, the backup cooling circuit may be enabled by one or more circuits of the processor to cause the at least one flow controller 424 to alternately provide cooling to at least one computing component with the secondary cooling circuits 412, 414. In at least one embodiment, the secondary cooling circuits 412, 414 are associated with the primary cooling circuit 422 and the cooling facility 408.

[0096] In at least one embodiment, the processor includes an output for providing a signal to one or more flow controllers 424. In at least one embodiment, the one or more flow controllers 424 can then divert auxiliary coolant flow from the rack manifold of the rack 404 to the reservoir or fluid source 420, which circulates the auxiliary coolant to the liquid-liquid heat exchanger 430. In at least one embodiment, the one or more flow controllers 424 can redirect backup coolant flow from the fluid source 420 back to the drain manifold or a different drain manifold to cool at least one computing device in the rack 404. In at least one embodiment, the one or more flow controllers 424 can redirect backup coolant from the drain manifold 432 associated with the rack 404 to the reservoir or fluid source 420, which circulates the backup coolant to the liquid-liquid heat exchanger 430. In at least one embodiment, the one or more flow controllers 424 can redirect backup coolant from the fluid source 420 back to the drain manifold 432 for cooling at least one computing device in the rack 404. In at least one embodiment, the backup cooling loop may be supported by a refrigerant cooling system or facility water cooling system 434 that cools the backup coolant or auxiliary coolant in the liquid-to-liquid heat exchanger 430 .

[0097] In at least one embodiment, the processor may include an input for receiving sensor input from a sensor associated with at least one rack. In at least one embodiment, the sensor may be associated with the primary cooling circuit, the secondary cooling circuit, the CDU, a cooling tower, or any row of cooling manifolds associated with the primary cooling circuit and the secondary cooling circuit. In at least one embodiment, the processor may use the sensor input to determine a change in coolant status and control one or more flow controllers to engage the secondary cooling circuit or the backup cooling circuit. In at least one embodiment, the sensor input may be at least one temperature of the secondary coolant in the secondary cooling circuit. In at least one embodiment, when the sensed temperature is above the operating temperature of at least one computing device, it may be determined that the secondary coolant is ineffective in cooling the at least one computing device. In at least one embodiment, this may be due to an issue with the primary cooling circuit not absorbing heat from the secondary cooling circuit. In at least one embodiment, this may be due to a leak or a CDU malfunction. In at least one embodiment, this may be due to a cooling facility malfunction. In at least one embodiment, the primary cooling circuit may be sensed to be above its operating temperature and may be unable to effectively cool the secondary cooling circuit.

[0098] In at least one embodiment, one or more neural networks may be used to receive sensor inputs and infer a change in coolant state. In at least one embodiment, the change in coolant state may be a determination that an auxiliary coolant previously applied at a certain flow rate, fluid volume, and / or inlet temperature was inefficient in cooling at least one computing device. In at least one embodiment, such a determination may be identified based in part on previous ineffective cooling associated with previous flow rates, fluid volumes, and / or inlet temperatures of previous coolants (and their associated chemicals). In at least one embodiment, such a priori information may be used to train a learning model to infer the current flow rate, fluid volume, and / or temperature of the auxiliary coolant. In at least one embodiment, the inference may be that the auxiliary coolant is ineffective in providing coolant, which triggers the processor to cause a flow controller to stop the flow of auxiliary coolant to the auxiliary cooling circuit and engage a backup cooling circuit until the problem with the auxiliary cooling circuit is resolved.

[0099] In at least one embodiment, an input of the processor may be adapted to receive sensor input from a sensor associated with at least one rack. In at least one embodiment, the processor may determine a change in coolant state based in part on a temperature of the auxiliary coolant in the auxiliary coolant loop from the received sensor input. In at least one embodiment, the processor may be capable of controlling one or more flow controllers to enable a backup cooling loop and disable the auxiliary cooling loop.

[0100] In at least one embodiment, the processor includes one or more circuits for controlling one or more flow controllers of a backup cooling circuit. In at least one embodiment, the backup cooling circuit includes a fluid source, at least one flow controller, a liquid-liquid heat exchanger, and a fluid path. In at least one embodiment, the backup cooling circuit can be associated with at least one computing device. In at least one embodiment, one or more circuits can be provided for one or more neural networks to infer changes in coolant status of at least one rack from sensor input associated with at least one rack. In at least one embodiment, the one or more circuits can cause the at least one flow controller to alternately provide cooling to at least one computing component with the auxiliary cooling circuit. In at least one embodiment, the auxiliary cooling circuit can be associated with the primary cooling circuit and the cooling facility, and the backup cooling circuit is a distinct closed-loop cooling system.

[0101] In at least one embodiment, one or more neural networks of the processor may be adapted to receive sensor input. In at least one embodiment, the one or more neural networks may be trained to infer changes in coolant state as part of an analysis of previous sensor input and previous coolant state. In at least one embodiment, one or more circuits of the processor may be adapted to receive sensor input from a sensor associated with at least one rack. In at least one embodiment, the processor may be adapted to determine a change in coolant state based in part on at least one temperature of the auxiliary coolant in the auxiliary coolant circuit from the received sensor input. In at least one embodiment, the processor may be adapted to control one or more flow controllers to enable a backup cooling circuit and disable the auxiliary cooling circuit.

[0102] In at least one embodiment, a processor includes one or more circuits and may be associated with a controller of a backup cooling circuit. In at least one embodiment, the backup cooling circuit includes a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path. In at least one embodiment, the backup cooling circuit may be associated with at least one computing device. In at least one embodiment, the one or more circuits may be adapted to train one or more neural networks to infer changes in coolant status of at least one rack from sensor input associated with at least one rack. In at least one embodiment, the one or more circuits of the processor may cause the at least one flow controller to alternately provide cooling to at least one computing component with an auxiliary cooling circuit associated with the primary cooling circuit and the cooling facility.

[0103] In at least one embodiment, each processor of at least one processor (e.g. Figure 1-4The present invention relates to a neural network having an inference and / or training logic 1815, which may include, but is not limited to, code and / or data storage 1801 for storing forward and / or output weights and / or input / output data, and / or other parameters used to configure neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the training logic 1815 may include or be coupled to code and / or data storage 1801 for storing graph code or other software to control the timing and / or order in which weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into the processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, the code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, code and / or any portion of data storage 1801 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache memory or system memory.

[0104] In at least one embodiment, the reasoning and / or training logic 1815 of at least one processor can be part of a building management system (BMS) for controlling flow controllers at one or more of the server level, the rack level, and the row level. In at least one embodiment, a determination of which flow controllers to engage associated with a backup cooling circuit, fluid source, CDU, cold plate, or cooling manifold can be provided to one or more neural networks of the reasoning and / or training logic 1815 so that the one or more neural networks can infer which flow controllers can be properly engaged or disengaged from the auxiliary cooling circuit or the backup cooling circuit based on the coolant demand of one or more cold plates, servers, or racks. In at least one embodiment, the increase or decrease in coolant flow can be achieved by a flow controller controlled by the reasoning and / or training logic 1815 of at least one processor associated with the control logic associated with the backup cooling circuit.

[0105] In at least one embodiment, at least one processor may be associated with a backup cooling loop and a secondary cooling loop. In at least one embodiment, at least one processor includes control logic, such as inference and / or training logic 1815, and is associated with at least one flow controller. In at least one embodiment, at least one flow controller may have its own corresponding processor or microcontroller. In at least one embodiment, the processor or microcontroller executes instructions sent to it from the control logic. In at least one embodiment, the control logic may be used to determine a change in coolant state, such as a fault in a secondary cooling loop (such as a CDU and cooling manifold) or a primary cooling loop (such as a cooling facility, cooling manifold, and associated CDU). In at least one embodiment, the control logic may cause at least one flow controller to provide a coolant response, such as by engaging a backup cooling loop having a fluid source and a liquid-to-liquid heat exchanger to provide backup coolant or secondary coolant to at least one computing device.

[0106] In at least one embodiment, the control logic may cause a first signal to at least one flow controller to, as part of the coolant response, stop the flow of auxiliary coolant from the auxiliary cooling circuit. In at least one embodiment, the control logic may cause a second signal to at least one flow controller to start the flow of backup coolant from the backup cooling circuit as part of the coolant response. In at least one embodiment, the control logic may receive sensor input from a sensor associated with at least one CDU. In at least one embodiment, the at least one processor may determine a change in coolant state based in part on the sensor input. In at least one embodiment, one or more neural networks of the inference and / or training logic 1815 may be adapted to receive the sensor input and infer the change in coolant state.

[0107] In at least one embodiment, at least one processor may include one or more circuits for one or more neural networks, such as inference and / or training logic 1815. In at least one embodiment, the inference and / or training logic 1815 may be adapted to infer a change in coolant status from sensor input associated with at least one server or at least one rack, such as coolant from a CDU being ineffective or retaining too much heat upon entering the rack. In at least one embodiment, the one or more circuits may be adapted to cause at least one flow controller to provide coolant from a backup cooling circuit in response.

[0108] In at least one embodiment, control logic associated with the one or more circuits can cause a first signal (along with any associated signals) to be sent to at least one flow controller to enable a coolant response. In at least one embodiment, a distributed or integrated architecture is implemented by one or more circuits of at least one processor. In at least one embodiment, a distributed architecture can be supported by differently positioned circuits in the one or more circuits.

[0109] In at least one embodiment, one or more neural networks of the inference and / or training logic 1815 can be adapted to infer an increase or decrease in cooling demand for at least one computing component of at least one server. In at least one embodiment, one or more circuits can be adapted to enable a cooling circuit having a fluid source and a liquid-to-liquid heat exchanger to economically address a decreased cooling demand or to supplement an increased cooling demand of at least one computing component. In at least one embodiment, enabling a cooling circuit represents a coolant response from a backup cooling circuit to preempt a corresponding increase or decrease in cooling demand for at least one computing component of at least one server based in part on a workload being delivered to the at least one computing component.

[0110] In at least one embodiment, at least one processor may be provided that is associated with n backup cooling circuits. In at least one embodiment, the at least one processor includes one or more circuits, such as inference and / or training logic 1815, for training one or more neural networks to make inferences from the provided data. In at least one embodiment, the inference and / or training logic 1815 may infer changes in coolant state from sensor inputs associated with at least one server or at least one rack. In at least one embodiment, inference may be used to enable one or more circuits to cause at least one flow controller of the backup cooling circuit to provide a coolant response. In at least one embodiment, the coolant response may be such that the coolant response from the backup cooling circuit absorbs heat into the backup coolant and exchanges the absorbed heat to refrigerant or facility liquid from a liquid-to-liquid heat exchanger, rather than an auxiliary cooling circuit with a CDU.

[0111] In at least one embodiment, the one or more circuits may be adapted to train one or more neural networks to infer an increase or decrease in cooling demand of at least one computing component of at least one server. In at least one embodiment, the one or more circuits may be adapted to train one or more neural networks to infer that an increase or decrease in flow output from the auxiliary cooling loop is associated with an improper flow of auxiliary coolant due to a CDU failure or a corresponding increase or corresponding decrease in power demand of at least one computing component of at least one server.

[0112] In at least one embodiment, one or more neural networks can be trained to make inferences based on previously correlated thermal signatures or cooling demands from computing devices, servers, or racks, and the cooling capacity or capability indicated by the fluid source of the backup cooling circuit. In at least one embodiment, previous cooling demands satisfied by the backup cooling circuit can be used to enable the one or more neural networks to make similar inferences about similar future cooling demands (taking into account minor changes therein) that can be satisfied by adjusting one or more flow controllers to enable the backup cooling circuit.

[0113] Figure 5 According to at least one embodiment, Figure 2-4 Method 500 is associated with a data center cooling system. In at least one embodiment, method 500 includes step 502 of providing a backup cooling circuit having a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path. In at least one embodiment, step 504 associates the backup cooling circuit with at least one computing device. In at least one embodiment, step 506 provides cooling to at least one computing component from a secondary cooling circuit associated with the primary cooling circuit and a cooling tower.

[0114] In at least one embodiment, step 508 enables monitoring of the auxiliary cooling circuit or the primary cooling circuit. In at least one embodiment, the monitoring of at least the temperature, pressure, flow rate, humidity, and chemical properties (such as using a pH sensor) of the auxiliary coolant in the auxiliary cooling circuit at step 508 can be enabled by one or more sensors. In at least one embodiment, step 510 enables detecting or determining a fault in the auxiliary cooling circuit or a fault in the auxiliary coolant. In at least one embodiment, regarding Figure 2-4 The fault discussed is applicable to the detection or determination processor of step 510. In at least one embodiment, when the fault is determined or preempted, step 512 is executed to provide cooling from the backup cooling circuit instead of the auxiliary cooling circuit associated with the primary cooling circuit and the cooling facility. In at least one embodiment, this enables the correction of the fault in the primary cooling circuit or the auxiliary cooling circuit.

[0115] In at least one embodiment, at least step 510 can be further implemented by providing at least one processor with one or more neural networks and allowing the at least one processor to determine a failure in the primary cooling circuit using the one or more neural networks. In at least one embodiment, step 512 can be performed by causing at least one flow controller to activate a backup cooling circuit using the at least one processor.

[0116] In at least one embodiment, steps 502-506 can be implemented by providing at least one cold plate having ports for an auxiliary cooling circuit and a backup cooling circuit. In at least one embodiment, these steps can be further implemented by activating the backup cooling circuit in the event of a failure in the primary cooling circuit. In at least one embodiment, step 502 is further implemented by at least one cooling manifold of a fluid path that is configured to support flow of backup fluid from a fluid source to the cold plate of at least one computing component via the fluid path. In at least one embodiment, method 500 includes the further step or sub-step of associating at least one flow controller with the cold plate for the backup cooling circuit and the auxiliary cooling circuit. In at least one embodiment, method 500 includes the further step or sub-step of preventing, by the at least one flow controller, auxiliary coolant from a coolant distribution unit (CDU) from reaching the cold plate and allowing auxiliary coolant within the at least one cooling manifold to flow to the fluid source and circulate back to the cold plate as part of the backup cooling circuit.

[0117] In at least one embodiment, method 500 includes the further step or sub-step of preventing the auxiliary coolant from reaching the cold plate by at least one auxiliary flow controller when the outlet temperature of the auxiliary coolant is within a threshold of the inlet temperature of the auxiliary coolant. In at least one embodiment, this reflects that the auxiliary coolant is not being adequately cooled in the CDU associated with the primary cooling loop. In at least one embodiment, this reflects a fault in the primary cooling loop, such as a fault in the CDU or cooling facility or a leak in the primary cooling loop. In at least one embodiment, the inlet temperature and the outlet temperature can be associated with the inlet and outlet of the auxiliary coolant relative to the CDU. In at least one embodiment, method 500 includes the further step or sub-step of determining, by at least one processor, that the auxiliary cooling loop is operating outside a threshold cooling requirement of at least one computing device and causing the backup cooling loop to meet the threshold cooling requirement.

[0118] Servers and Data Centers

[0119] The following figures illustrate, but are not limited to, exemplary network server and data center based systems that may be used to implement at least one embodiment.

[0120] Figure 6 A distributed system 600 is shown in accordance with at least one embodiment. In at least one embodiment, the distributed system 600 includes one or more client computing devices 602, 604, 606, and 608 configured to execute and operate client applications, such as network (web) browsers, proprietary clients, and / or variations thereof, over one or more networks 610. In at least one embodiment, a server 612 can be communicatively coupled to the remote client computing devices 602, 604, 606, and 608 via the network 610.

[0121] In at least one embodiment, the server 612 may be adapted to run one or more services or software applications, such as services and applications that can manage session activity for single sign-on (SSO) access across multiple data centers. In at least one embodiment, the server 612 may also provide other services or software applications that may include both non-virtualized and virtualized environments. In at least one embodiment, these services may be provided to users of the client computing devices 602, 604, 606, and / or 608 as web-based services or cloud services or under a software as a service (SaaS) model. In at least one embodiment, users operating the client computing devices 602, 604, 606, and / or 608 may, in turn, utilize one or more client applications to interact with the server 612 to utilize the services provided by these components.

[0122] In at least one embodiment, the software components 618, 620, and 622 of system 600 are implemented on server 612. In at least one embodiment, one or more components of system 600 and / or the services provided by these components can also be implemented by one or more of client computing devices 602, 604, 606, and / or 608. In at least one embodiment, a user operating a client computing device can then utilize one or more client applications to use the services provided by these components. In at least one embodiment, these components can be implemented in hardware, firmware, software, or a combination thereof. It should be understood that a variety of different system configurations are possible that can differ from the distributed system 600. Therefore, Figure 6 The illustrated embodiment is at least one embodiment of a distributed system for implementing an embodiment system and is not intended to be limiting.

[0123] In at least one embodiment, client computing devices 602, 604, 606, and / or 608 may include different types of computing systems. In at least one embodiment, client computing devices may include portable handheld devices (e.g., Cellular phones, computing tablets, personal digital assistants (PDAs), or wearable devices (e.g., Google head-mounted display), running software (such as Microsoft Windows ) and / or various mobile operating systems (such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS and / or their variants). In at least one embodiment, the device can support different applications, such as different Internet-related applications, email, short message service (SMS) applications, and can use various other communication protocols. In at least one embodiment, the client computing device can also include a general-purpose personal computer, which in at least one embodiment includes a computer running various versions of Microsoft Apple and / or a personal computer and / or laptop computer running Linux operating system.

[0124] In at least one embodiment, the client computing device may be a computer running various commercially available or any workstation computer running any of the UNIX-like operating systems, including but not limited to various GNU / Linux operating systems, such as Google Chrome OS. In at least one embodiment, client computing devices may also include electronic devices capable of communicating over one or more networks 610, such as thin client computers, Internet-enabled gaming systems (e.g., with or without a PC), and gesture input devices for Microsoft Xbox gaming consoles), and / or personal messaging devices. Figure 6 The distributed system 600 in FIG. 6 is shown as having four client computing devices, but any number of client computing devices may be supported. Other devices (such as devices with sensors, etc.) may interact with the server 612 .

[0125] In at least one embodiment, the network 610 in the distributed system 600 can be any type of network capable of supporting data communications using any of a variety of available protocols, including but not limited to TCP / IP (Transmission Control Protocol / Internet Protocol), SNA (Systems Network Architecture), IPX (Internetwork Packet Exchange), AppleTalk, and / or variations thereof. In at least one embodiment, the network 610 can be a local area network (LAN), an Ethernet-based network, a token ring, a wide area network, the Internet, a virtual network, a virtual private network (VPN), an intranet, an extranet, a public switched telephone network (PSTN), an infrared network, a wireless network (e.g., a standard implemented in the Institute of Electrical and Electronics Engineers (IEEE) 802.11 protocol suite), a wireless network, or a combination thereof. and / or any other wireless protocols), and / or any combination of these and / or other networks.

[0126] In at least one embodiment, the server 612 may be comprised of one or more general purpose computers, dedicated server computers (including, in at least one embodiment, PC (personal computer) servers, The server 612 may be composed of a plurality of servers (e.g., servers, mid-range servers, mainframe computers, rack servers, etc.), a server farm, a server cluster, or any other suitable arrangement and / or combination. In at least one embodiment, the server 612 may include one or more virtual machines running virtual operating systems or other computing architectures involving virtualization. In at least one embodiment, one or more flexible logical storage device pools may be virtualized to maintain virtual storage devices for the server. In at least one embodiment, the virtual network may be controlled by the server 612 using software-defined networking. In at least one embodiment, the server 612 may be adapted to run one or more services or software applications.

[0127] In at least one embodiment, the server 612 can run any operating system, and any commercially available server operating system. In at least one embodiment, the server 612 can also run any of a variety of additional server applications and / or mid-tier applications, including HTTP (Hypertext Transfer Protocol) servers, FTP (File Transfer Protocol) servers, CGI (Common Gateway Interface) servers, Server, database server and / or variants thereof.In at least one embodiment, exemplary database servers include, but are not limited to, those commercially available from Oracle, Microsoft, Sybase, IBM (International Business Machines), and / or variants thereof.

[0128] In at least one embodiment, server 612 may include one or more applications for analyzing and consolidating data feeds and / or event updates received from users of client computing devices 602, 604, 606, and 608. In at least one embodiment, data feeds and / or event updates may include, but are not limited to, data received from one or more third-party information sources and continuous data streams. feed, Updates or real-time updates, which may include real-time events related to sensor data applications, financial quoters, network performance measurement tools (e.g., network monitoring and business management applications), clickstream analysis tools, automobile traffic monitoring, and / or changes thereto. In at least one embodiment, server 612 may also include one or more applications for displaying data feeds and / or real-time events via one or more display devices of client computing devices 602, 604, 606, and 608.

[0129] In at least one embodiment, the distributed system 600 may further include one or more databases 614 and 616. In at least one embodiment, the database may provide a mechanism for storing information such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, the databases 614 and 616 may reside in various locations. In at least one embodiment, one or more of the databases 614 and 616 may reside on a non-transitory storage medium local to the server 612 (and / or residing in the server 612). In at least one embodiment, the databases 614 and 616 may be remote from the server 612 and communicate with the server 612 via a network-based connection or a dedicated connection. In at least one embodiment, the databases 614 and 616 may reside in a storage area network (SAN). In at least one embodiment, any necessary files for performing the functions attributed to the server 612 may be appropriately stored locally on the server 612 and / or remotely. In at least one embodiment, the databases 614 and 616 may include relational databases, such as databases suitable for storing, updating, and retrieving data in response to SQL-formatted commands.

[0130] Figure 7 An exemplary data center 700 is shown in accordance with at least one embodiment. In at least one embodiment, data center 700 includes, but is not limited to, a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0131] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any complete positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be servers having one or more of the above-mentioned computing resources.

[0132] In at least one embodiment, the grouped computing resources 714 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. The separate groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs comprising a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0133] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may comprise a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may comprise hardware, software, or some combination thereof.

[0134] In at least one embodiment, Figure 7As shown, framework layer 720 includes, but is not limited to, a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, framework layer 720 may include a framework that supports software 752 of software layer 730 and / or one or more applications 742 of application layer 740. In at least one embodiment, software 752 or applications 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 720 may include, but is not limited to, a free and open source software web application framework, such as Apache Spark™ (hereinafter referred to as "Spark"), which can utilize distributed file system 738 for large-scale data processing (e.g., "big data"). In at least one embodiment, job scheduler 732 may include a Spark driver to facilitate scheduling workloads supported by various layers of data center 700. In at least one embodiment, configuration manager 734 may be capable of configuring different layers, such as software layer 730 and framework layer 720, which includes Spark and a distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 can manage clustered or grouped computing resources that are mapped to or allocated to support the distributed file system 738 and the job scheduler 732. In at least one embodiment, the clustered or grouped computing resources can include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 can coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0135] In at least one embodiment, the software 752 included in the software layer 730 may include software used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. The one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0136] In at least one embodiment, the one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. The one or more types of applications may include, but are not limited to, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.

[0137] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 700 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0138] Figure 8 A client-server network 804 is shown formed by a plurality of interconnected network server computers 802, according to at least one embodiment. In at least one embodiment, each network server computer 802 stores data accessible to the other network server computers 802 and client computers 806 and networks 808 connected to the wide area network 804. In at least one embodiment, the configuration of the client-server network 804 can change over time as client computers 806 and one or more networks 808 are connected and disconnected from the network 804, and as one or more backbone server computers 802 are added to or removed from the network 804. In at least one embodiment, the client-server network includes client computers 806 and networks 808 when such client computers 806 and networks 808 are connected to the network server computers 802. In at least one embodiment, the term "computer" includes any device or machine capable of accepting data, applying a prescribed process to the data, and providing a result of the process.

[0139] In at least one embodiment, the client-server network 804 stores information accessible to the network server computer 802, the remote network 808, and the client computers 806. In at least one embodiment, the network server computer 802 is formed by a mainframe computer, a minicomputer, and / or a microcomputer, each having one or more processors. In at least one embodiment, the server computers 802 are linked together via wired and / or wireless transmission media (such as wires, fiber optic cables), and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, the client computers 806 access the network server computers 802 via similar wired or wireless transmission media. In at least one embodiment, the client computers 806 can be linked to the client-server network 804 using a modem and a standard telephone communication network. In at least one embodiment, alternative carrier systems (such as cable and satellite communication systems) can also be used to link to the client-server network 804. In at least one embodiment, other private or time-shared carrier systems can be used. In at least one embodiment, the network 804 is a global information network, such as the Internet. In at least one embodiment, the network is a private intranet that uses similar protocols to the Internet but with added security measures and restricted access controls.In at least one embodiment, the network 804 is a private or semi-private network that uses a proprietary communication protocol.

[0140] In at least one embodiment, client computer 806 is any end-user computer and may also be a mainframe computer, minicomputer, or microcomputer having one or more microprocessors. In at least one embodiment, server computer 802 may sometimes be used as a client computer to access another server computer 802. In at least one embodiment, remote network 808 may be a local area network, a network added to a wide area network via an independent service provider (ISP) for the Internet, or another group of computers interconnected via a wired or wireless transmission medium with a fixed or time-varying configuration. In at least one embodiment, client computer 806 may be linked to network 804 independently or via remote network 808 and access network 804.

[0141] Figure 9Shown is a computer network 908 of one or more computing machines connected according to at least one embodiment.In at least one embodiment, network 908 can be any type of electrically connected computer group, including for example following network: the Internet, intranet, local area network (LAN), wide area network (WAN) or the interconnection combination of these network types.In at least one embodiment, the connection in network 908 can be a remote modem, Ethernet (IEEE 802.3), token ring (IEEE 802.5), fiber distributed data link interface (FDDI), asynchronous transfer mode (ATM) or any other communication protocol.In at least one embodiment, the computing device linked to the network can be a desktop, server, portable, handheld, set-top box, personal digital assistant (PDA), terminal or any other desired type or configuration.In at least one embodiment, depending on their functionality, the equipment of network connection can widely change aspect processing power, internal memory and other performances.

[0142] In at least one embodiment, communications within the network, as well as communications to and from computing devices connected to the network, can be wired or wireless. In at least one embodiment, network 908 can comprise, at least in part, the worldwide public Internet, which typically connects multiple users according to a client-server model based on the Transmission Control Protocol / Internet Protocol (TCP / IP) specification. In at least one embodiment, client-server networks are the predominant model for communication between two computers. In at least one embodiment, a client computer ("client") issues one or more commands to a server computer ("server"). In at least one embodiment, the server fulfills the client's commands by accessing available network resources and returning information to the client based on the client's commands. In at least one embodiment, client computer systems and network resources residing on network servers are assigned network addresses for identification during communications between elements of the network. In at least one embodiment, communications from other network-connected systems to the server will include the network address of the relevant server / network resource as part of the communication, allowing the appropriate destination of the data / request to be identified as the recipient. In at least one embodiment, when the network 908 comprises the global Internet, the network address is an IP address in TCP / IP format that can, at least in part, route data to an email account, website, or other Internet utility residing on a server. In at least one embodiment, information and services residing on a network server can be made available to a web browser of a client computer via a domain name (e.g., www.site.com) that maps to the IP address of the network server.

[0143] In at least one embodiment, a plurality of clients 902, 904, and 906 are connected to a network 908 via respective communication links. In at least one embodiment, each of these clients can access the network 908 via any desired form of communication, such as via a dial-up modem connection, a cable link, a digital subscriber line (DSL), a wireless or satellite link, or any other form of communication. In at least one embodiment, each client can communicate using any machine (e.g., a personal computer (PC), a workstation, a dedicated terminal, a personal data assistant (PDA), or other similar device) that is compatible with the network 908. In at least one embodiment, the clients 902, 904, and 906 may or may not be located in the same geographic area.

[0144] In at least one embodiment, multiple servers 910, 912, and 914 are connected to a network 918 to serve clients communicating with the network 918. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, the servers include computer-readable data storage media, such as hard drives and RAM memory, that store program instructions and data. In at least one embodiment, servers 910, 912, and 914 run applications that respond to client commands. In at least one embodiment, server 910 may run a web server application that responds to client requests for HTML pages and may also run a mail server application that receives and routes emails. In at least one embodiment, other applications may also run on server 910, such as an FTP server or media server for streaming audio / video data to clients. In at least one embodiment, different servers may be dedicated to performing different tasks. In at least one embodiment, server 910 may be a dedicated web server that manages website-related resources for different users, while server 912 may be dedicated to providing email management. In at least one embodiment, other servers may be dedicated to media (audio, video, etc.), file transfer protocol (FTP), or a combination of any two or more services typically available or provided over a network. In at least one embodiment, each server may be in the same or different location as the other servers. In at least one embodiment, multiple servers may be present to perform mirroring tasks for users, thereby alleviating congestion or minimizing traffic directed to and from a single server. In at least one embodiment, servers 910, 912, 914 are under the control of a web hosting provider in the business of maintaining and delivering third-party content over network 918.

[0145] In at least one embodiment, a web hosting provider delivers services to two different types of clients. In at least one embodiment, one type, which may be referred to as a browser, requests content from servers 910, 912, 914, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which may be referred to as a user, hires the web hosting provider to maintain network resources (such as a website) and make them available to the browser. In at least one embodiment, the user contracts with the web hosting provider to make available the memory space, processor capacity, and communication bandwidth required for the network resources they desire, depending on the amount of server resources they desire to utilize.

[0146] In at least one embodiment, in order for the web hosting provider to serve both clients, an application that manages the network resources hosted by the server must be appropriately configured. In at least one embodiment, the program configuration process involves defining a set of parameters that at least partially control the application's responses to browser requests and also at least partially define the server resources available to a particular user.

[0147] In one embodiment, intranet server 916 communicates with network 908 via a communication link. In at least one embodiment, intranet server 916 communicates with server manager 918. In at least one embodiment, server manager 918 includes a database of application configuration parameters used in servers 910, 912, 914. In at least one embodiment, a user modifies database 920 via intranet 916, and server manager 918 interacts with servers 910, 912, 914 to modify application parameters so that they match the contents of the database. In at least one embodiment, a user logs into intranet 916 by connecting to intranet 916 via computer 902 and entering authentication information such as a username and password.

[0148] In at least one embodiment, when a user wishes to log in to a new service or modify an existing service, the intranet server 916 authenticates the user and provides the user with an interactive screen display / control panel that allows the user to access configuration parameters for a particular application. In at least one embodiment, the user is presented with a plurality of modifiable text boxes that describe aspects of the configuration of the user's website or other network resources. In at least one embodiment, if the user desires to increase the memory space reserved for their website on the server, the user is provided with a field in which the user specifies the desired memory space. In at least one embodiment, in response to receiving this information, the intranet server 916 updates the database 920. In at least one embodiment, the server manager 918 forwards this information to the appropriate server and uses the new parameters during application operation. In at least one embodiment, the intranet server 916 is configured to provide the user with access to configuration parameters for hosted network resources (e.g., web pages, email, FTP sites, media sites, etc.) that the user has contracted with a web hosting service provider.

[0149] Figure 10A A networked computer system 1000A according to at least one embodiment is shown. In at least one embodiment, the networked computer system 1000A includes a plurality of nodes or personal computers ("PCs") 1002, 1018, 1020. In at least one embodiment, the personal computer or node 1002 includes a processor 1014, a memory 1016, a camera 1004, a microphone 1006, a mouse 1008, a speaker 1010, and a monitor 1012. In at least one embodiment, the PCs 1002, 1018, 1020 can each run one or more desktop servers, such as an internal network within a given company, or can be servers of a general-purpose network that is not limited to a particular environment. In at least one embodiment, each PC node of the network has one server, such that each PC node of the network represents a specific network server with a specific network URL address. In at least one embodiment, each server defaults to a default web page for users of that server, which itself can contain embedded URLs pointing to further subpages for that user on that server, or to other servers on the network or to pages on other servers.

[0150] In at least one embodiment, nodes 1002, 1018, 1020 and other nodes of the network are interconnected via a medium 1022. In at least one embodiment, the medium 1022 can be a communication channel such as an Integrated Services Digital Network ("ISDN"). In at least one embodiment, the various nodes of the networked computer system can be connected via various communication media, including a local area network ("LAN"), a plain old telephone line ("POTS") (sometimes referred to as a public switched telephone network ("PSTN")), and / or variations thereof. In at least one embodiment, the various nodes of the network can also constitute computer system users interconnected via a network such as the Internet. In at least one embodiment, each server on the network (operated from a particular node of the network at a given instance) has a unique address or identification within the network, which can be specified according to a URL.

[0151] In at least one embodiment, a plurality of multipoint conferencing units ("MCUs") can thus be used to transmit data to and from various nodes or "endpoints" of a conferencing system. In at least one embodiment, the nodes and / or MCUs can be interconnected via ISDN links or through a local area network ("LAN"), in addition to various other communication media (such as, nodes connected via the Internet). In at least one embodiment, the nodes of a conferencing system can generally be connected directly to a communication medium (such as a LAN) or through an MCU, and the conferencing system can include other nodes or elements, such as routers, servers, and / or variations thereof.

[0152] In at least one embodiment, processor 1014 is a general-purpose programmable processor. In at least one embodiment, the processor of a node of networked computer system 1000A may also be a dedicated video processor. In at least one embodiment, the various peripherals and components of a node (such as those of node 1002) may be different from those of other nodes. In at least one embodiment, node 1018 and node 1020 may be configured to be the same as or different from node 1002. In at least one embodiment, the node may be implemented on any suitable computer system other than a PC system.

[0153] Figure 10B10. A networked computer system 1000B is shown according to at least one embodiment. In at least one embodiment, system 1000B shows a network (such as LAN 1024) that can be used to interconnect various nodes that can communicate with each other. In at least one embodiment, attached to LAN 1024 are multiple nodes, such as PC nodes 1026, 1028, 1030. In at least one embodiment, the nodes can also be connected to the LAN via a network server or other device. In at least one embodiment, system 1000B includes other types of nodes or elements, including routers, servers, and nodes for at least one embodiment.

[0154] Figure 10C A networked computer system 1000C is shown in accordance with at least one embodiment. In at least one embodiment, system 1000C shows a WWW system with communications across a backbone communications network, such as the Internet 1032, which may be used to interconnect various nodes of the network. In at least one embodiment, the WWW is a set of protocols that operate on top of the Internet and allow graphical interface systems to operate on top of it to access information through the Internet. In at least one embodiment, attached to the Internet 1032 in the WWW are multiple nodes, such as PCs 1040, 1042, 1044. In at least one embodiment, the nodes interface with other nodes of the WWW through WWW HTTP servers, such as servers 1034, 1036. In at least one embodiment, PC 1044 may be a PC that forms a node of network 1032, and PC 1044 itself runs its server 1036, although for illustrative purposes only. Figure 10C PC 1044 and server 1036 are shown separately in FIG.

[0155] In at least one embodiment, the WWW is a distributed type of application characterized by WWW HTTP, the protocol of the WWW, which runs on top of the Internet's Transmission Control Protocol / Internet Protocol ("TCP / IP"). In at least one embodiment, the WWW can therefore be characterized by a set of protocols (i.e., HTTP) running on the Internet as its "backbone."

[0156] In at least one embodiment, a web browser is an application running on a node of the network in a WWW-compatible network system that allows users of a particular server or node to view such information and, therefore, to search for graphics and text-based files linked together using hypertext links embedded in documents or files available from servers on a network that understands HTTP. In at least one embodiment, when a user retrieves a given web page from a first server associated with a first node using another server on a network such as the Internet, the retrieved document may have different hypertext links embedded therein, and a local copy of the page is created locally on the retrieving user's machine. In at least one embodiment, when a user clicks on a hypertext link, the locally stored information associated with the selected hypertext link is typically sufficient to allow the user's machine to open a connection over the Internet to the server indicated by the hypertext link.

[0157] In at least one embodiment, more than one user can be coupled to each HTTP server via a LAN (such as LAN 1038, as shown with respect to WWW HTTP server 1034). In at least one embodiment, system 1000C may also include other types of nodes or elements. In at least one embodiment, the WWW HTTP server is an application running on a machine such as a PC. In at least one embodiment, each user can be considered to have a unique "server," as shown with respect to PC 1044. In at least one embodiment, a server can be considered to be a server, such as WWW HTTP server 1034, that provides access to the network for a LAN, or multiple nodes, or multiple LANs. In at least one embodiment, there are multiple users, each with a desktop PC or node on the network, each desktop PC potentially establishing a server for its user. In at least one embodiment, each server is associated with a specific network address or URL that, when accessed, provides a default web page for that user. In at least one embodiment, the web page may contain further links (embedded URLs) pointing to further subpages for that user on that server, or to other servers on the network or to pages on other servers on the network.

[0158] Cloud computing and services

[0159] The following figures illustrate, but are not limited to, exemplary cloud-based systems that can be used to implement at least one embodiment.

[0160] In at least one embodiment, cloud computing is a style of computing in which dynamically scalable and often virtualized resources are provided as services over the Internet. In at least one embodiment, users do not need knowledge, expertise, or control over the technical infrastructure that supports them; the technical infrastructure can be referred to as being "in the cloud." In at least one embodiment, cloud computing combines infrastructure as a service, platform as a service, software as a service, and other variations with a common theme of relying on the Internet to meet users' computing needs. In at least one embodiment, a typical cloud deployment (such as in a private cloud (e.g., an enterprise network)) or a data center (DC) in a public cloud (e.g., the Internet) can consist of thousands of servers (or alternatively, VMs), hundreds of Ethernet, Fibre Channel, or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, the cloud can also consist of network service infrastructure, such as IPsec VPN concentrators, firewalls, load balancers, wide area network (WAN) optimizers, etc. In at least one embodiment, remote subscribers can securely access cloud applications and services by connecting via a VPN tunnel (e.g., an IPsec VPN tunnel).

[0161] In at least one embodiment, cloud computing is a model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be quickly provisioned and released with minimal management effort or service provider interaction.

[0162] In at least one embodiment, cloud computing is characterized by on-demand self-service, where consumers can automatically and unilaterally provision computing capabilities, such as server time and network storage, as needed, without requiring human interaction with each service provider. In at least one embodiment, cloud computing is characterized by broad network access, where capabilities are available over the network and accessed through standard mechanisms that facilitate use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling, where a provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically signed up and reallocated based on consumer demand. In at least one embodiment, there is a sense of location independence, as consumers generally have no control or knowledge of the exact location of the provisioned resources, but may be able to specify the location at a higher level of abstraction (e.g., country, state, or data center).

[0163] In at least one embodiment, resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by rapid elasticity, where capacity can be quickly and elastically provisioned (in some cases automatically) to quickly scale down and quickly released to quickly scale up. In at least one embodiment, the capacity available for provisioning generally appears unlimited to the consumer and can be purchased in any quantity at any time. In at least one embodiment, cloud computing is characterized by metered services, where the cloud system automatically controls and optimizes resource usage by utilizing metering capabilities at some level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage can be monitored, controlled, and reported, thereby providing transparency to both the provider and the consumer of the utilized service.

[0164] In at least one embodiment, cloud computing can be associated with a variety of services. In at least one embodiment, cloud software as a service (SaaS) can refer to a service that provides consumers with the ability to use a provider's applications running on a cloud infrastructure. In at least one embodiment, the applications can be accessed from various client devices through a thin client interface such as a web browser (e.g., web-based email). In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application capabilities, with the possible exception of limited user-specific application configuration settings.

[0165] In at least one embodiment, cloud platform as a service (PaaS) may refer to a service in which the capability provided to the consumer is to deploy consumer-created or acquired applications onto a cloud infrastructure, where these applications are created using programming languages ​​and tools supported by the provider. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, including networks, servers, operating systems, or storage, but does have control over the deployed applications and possibly the configuration of the application hosting environment.

[0166] In at least one embodiment, cloud infrastructure as a service (IaaS) can refer to a service in which the capabilities provided to the consumer are processing, storage, networking, and other basic computing resources upon which the consumer can deploy and run arbitrary software, which may include operating systems and applications. In at least one embodiment, the consumer does not manage or control the underlying cloud infrastructure, but rather has control over the operating system, storage, deployed applications, and possibly limited control over selected networking components (e.g., host firewalls).

[0167] In at least one embodiment, cloud computing can be deployed in different ways. In at least one embodiment, a private cloud may refer to cloud infrastructure that operates only for an organization. In at least one embodiment, a private cloud may be managed by an organization or a third party and may exist on-premises or off-premises. In at least one embodiment, a community cloud may refer to cloud infrastructure shared by several organizations and supporting a specific community with shared concerns (e.g., mission, security requirements, policies, and compliance considerations). In at least one embodiment, a community cloud may be managed by an organization or a third party and may exist on-premises or off-premises. In at least one embodiment, a public cloud may refer to cloud infrastructure that is available to the general public or a large industry group and owned by an organization providing cloud services. In at least one embodiment, a hybrid cloud may refer to a cloud infrastructure that is a composite of two or more clouds (private, community, or public) that remain unique entities but are bound together by standardized or proprietary technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds). In at least one embodiment, a cloud computing environment is service-oriented, focusing on statelessness, low coupling, modularity, and semantic interoperability.

[0168] Figure 11 One or more components of a system environment 1100 are shown, according to at least one embodiment, in which services may be provided as third-party network services. In at least one embodiment, the third-party network may be referred to as a cloud, a cloud network, a cloud computing network, and / or variations thereof. In at least one embodiment, the system environment 1100 includes one or more client computing devices 1104, 1106, and 1108, which can be used by users to interact with a third-party network infrastructure system 1102 that provides the third-party network services (which may be referred to as cloud computing services). In at least one embodiment, the third-party network infrastructure system 1102 may include one or more computers and / or servers.

[0169] It should be understood that Figure 11 The third-party network infrastructure system 1102 depicted in FIG may have other components in addition to those depicted. Further, Figure 11 In at least one embodiment, the third party network infrastructure system 1102 may have Figure 11 More or fewer components may be depicted, two or more components may be combined, or there may be a different configuration or arrangement of components.

[0170] In at least one embodiment, the client computing devices 1104, 1106, and 1108 can be configured to operate a client application, such as a web browser, a proprietary client application, or some other application that can be used by users of the client computing devices to interact with the third-party network infrastructure system 1102 to utilize services provided by the third-party network infrastructure system 1102. Although the exemplary system environment 1100 is shown with three client computing devices, any number of client computing devices can be supported. In at least one embodiment, other devices, such as devices with sensors, can interact with the third-party network infrastructure system 1102. In at least one embodiment, one or more networks 1110 can facilitate communication and data exchange between the client computing devices 1104, 1106, and 1108 and the third-party network infrastructure system 1102.

[0171] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include a host of services available on-demand to users of the third-party network infrastructure system. In at least one embodiment, a variety of services may also be provided, including but not limited to online data storage and backup solutions, web-based email services, hosted office suites and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, the services provided by the third-party network infrastructure system may be dynamically scalable to meet the needs of its users.

[0172] In at least one embodiment, a specific instantiation of a service provided by the third-party network infrastructure system 1102 may be referred to as a "service instance." In at least one embodiment, generally, any service available to a user from a third-party network service provider system via a communication network (such as the Internet) is referred to as a "third-party network service." In at least one embodiment, in a public third-party network environment, the servers and systems that comprise the third-party network service provider system are different from the customer's own on-premises servers and systems. In at least one embodiment, the third-party network service provider system can host applications, and users can subscribe to and use the applications on demand via a communication network (such as the Internet).

[0173] In at least one embodiment, services within a computer network third-party network infrastructure may include protected computer network access to storage, hosted databases, hosted web servers, software applications, or other services provided to users by a third-party network provider. In at least one embodiment, services may include password-protected access to remote storage devices on the third-party network via the Internet. In at least one embodiment, services may include a hosted relational database and scripting language middleware engine based on a web service for private use by networked developers. In at least one embodiment, services may include access to an email software application hosted on a website of a third-party network provider.

[0174] In at least one embodiment, the third-party network infrastructure system 1102 may include a suite of application, middleware, and database service offerings delivered to customers in a self-service, subscription-based, elastically scalable, reliable, highly available, and secure manner. In at least one embodiment, the third-party network infrastructure system 1102 may also provide computing and analytical services related to "big data." In at least one embodiment, the term "big data" is generally used to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize, detect trends, and / or otherwise interact with the data. In at least one embodiment, big data and related applications can be hosted and / or manipulated by the infrastructure system at many levels and at varying scales. In at least one embodiment, dozens, hundreds, or thousands of processors linked in parallel may act on such data to render it or simulate external forces acting on the data or its representation. In at least one embodiment, these data sets may involve structured data (such as structured data organized in a database or otherwise according to a structured model) and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by leveraging the ability of embodiments to focus more (or fewer) computing resources on a target relatively quickly, third-party network infrastructure systems may be better available to perform tasks on large data sets based on demand from businesses, government agencies, research organizations, private individuals, groups of like-minded individuals or organizations, or other entities.

[0175] In at least one embodiment, the third-party network infrastructure system 1102 can be adapted to automatically provision, manage, and track customer subscriptions to services provided by the third-party network infrastructure system 1102. In at least one embodiment, the third-party network infrastructure system 1102 can provide third-party network services via different deployment models. In at least one embodiment, services can be provided under a public third-party network model, in which the third-party network infrastructure system 1102 is owned by the organization selling the third-party network services and makes the services available to the general public or businesses across various industries. In at least one embodiment, services can be provided under a private third-party network model, in which the third-party network infrastructure system 1102 operates solely for a single organization and can provide services to one or more entities within the organization. In at least one embodiment, third-party network services can also be provided under a community third-party network model, in which the third-party network infrastructure system 1102 and the services provided by the third-party network infrastructure system 1102 are shared by several organizations within a related community. In at least one embodiment, third-party network services can also be provided under a hybrid third-party network model, which is a combination of two or more different models.

[0176] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include one or more services provided under the Software as a Service (SaaS) category, the Platform as a Service (PaaS) category, the Infrastructure as a Service (IaaS) category, or other service categories including hybrid services. In at least one embodiment, a customer may subscribe to one or more services provided by the third-party network infrastructure system 1102 via a subscription order. In at least one embodiment, the third-party network infrastructure system 1102 then performs processing to provide the services in the customer's subscription order.

[0177] In at least one embodiment, the services provided by the third-party network infrastructure system 1102 may include, but are not limited to, application services, platform services, and infrastructure services. In at least one embodiment, application services may be provided by the third-party network infrastructure system via a SaaS platform. In at least one embodiment, the SaaS platform may be configured to provide third-party network services that fall under the SaaS category. In at least one embodiment, the SaaS platform may provide the ability to build and deliver a suite of on-demand applications on an integrated development and deployment platform. In at least one embodiment, the SaaS platform may manage and control the underlying software and infrastructure used to provide SaaS services. In at least one embodiment, by utilizing the services provided by the SaaS platform, customers may utilize applications executed on the third-party network infrastructure system. In at least one embodiment, customers may obtain application services without the need to purchase separate licenses and support. In at least one embodiment, a variety of different SaaS services may be provided. In at least one embodiment, this may include, but is not limited to, services that provide solutions for sales performance management, enterprise integration, and business agility for large organizations.

[0178] In at least one embodiment, platform services may be provided by the third-party network infrastructure system 1102 via a PaaS platform. In at least one embodiment, the PaaS platform may be configured to provide third-party network services that fall under the PaaS category. In at least one embodiment, platform services may include, but are not limited to, services that enable organizations to consolidate existing applications onto a shared common architecture, as well as the ability to build new applications that utilize the shared services provided by the platform. In at least one embodiment, the PaaS platform may manage and control the underlying software and infrastructure used to provide the PaaS services. In at least one embodiment, customers may obtain PaaS services provided by the third-party network infrastructure system 1102 without requiring the customer to purchase separate licenses and support.

[0179] In at least one embodiment, by utilizing the services provided by the PaaS platform, customers can adopt programming languages ​​and tools supported by the third-party network infrastructure system and also control the deployed services. In at least one embodiment, the platform services provided by the third-party network infrastructure system may include database third-party network services, middleware third-party network services, and third-party network services. In at least one embodiment, the database third-party network service may support a shared service deployment model that enables organizations to aggregate database resources and provide database as a service to customers in the form of a database third-party network. In at least one embodiment, in the third-party network infrastructure system, the middleware third-party network service can provide customers with a platform to develop and deploy different business applications, and the third-party network service can provide customers with a platform to deploy applications.

[0180] In at least one embodiment, a variety of infrastructure services may be provided by an IaaS platform within a third-party network infrastructure system. In at least one embodiment, the infrastructure services facilitate the management and control of underlying computing resources (such as storage, network, and other basic computing resources) by customers utilizing services provided by SaaS and PaaS platforms.

[0181] In at least one embodiment, the third-party network infrastructure system 1102 may also include infrastructure resources 1130 for providing resources for providing various services to customers of the third-party network infrastructure system. In at least one embodiment, the infrastructure resources 1130 may include a pre-integrated and optimized combination of hardware (such as servers, storage, and networking resources) for executing the services and other resources provided by the PaaS platform and the SaaS platform.

[0182] In at least one embodiment, resources in the third-party network infrastructure system 1102 can be shared by multiple users and dynamically reallocated based on demand. In at least one embodiment, resources can be allocated to users in different time zones. In at least one embodiment, the third-party network infrastructure system 1102 can enable a first group of users in a first time zone to utilize the resources of the third-party network infrastructure system for a specified number of hours, and then enable the reallocation of the same resources to another group of users in a different time zone, thereby maximizing resource utilization.

[0183] In at least one embodiment, a plurality of internal shared services 1132 shared by different components or modules of the third-party network infrastructure system 1102 may be provided to enable services provided by the third-party network infrastructure system 1102. In at least one embodiment, these internal shared services may include, but are not limited to, security and identity services, integration services, enterprise library services, enterprise manager services, virus scanning and whitelisting services, high availability, backup and recovery services, services for enabling third-party network support, email services, notification services, file transfer services, and / or variations thereof.

[0184] In at least one embodiment, the third-party network infrastructure system 1102 can provide comprehensive management of third-party network services (e.g., SaaS, PaaS, and IaaS services) within the third-party network infrastructure system. In at least one embodiment, the third-party network management functionality can include capabilities for provisioning, managing, and tracking customer subscriptions received by the third-party network infrastructure system 1102 and / or variations thereof.

[0185] In at least one embodiment, Figure 11As shown, third-party network management functionality may be provided by one or more modules, such as an order management module 1120, an order coordination module 1122, an order provisioning module 1124, an order management and monitoring module 1126, and an identity management module 1128. In at least one embodiment, these modules may include or be provided using one or more computers and / or servers, which may be general-purpose computers, dedicated server computers, server farms, server clusters, or any other suitable arrangement and / or combination.

[0186] In at least one embodiment, at step 1134, a customer using a client device (such as client computing device 1104, 1106, or 1108) can interact with the third-party network infrastructure system 1102 by requesting one or more services provided by the third-party network infrastructure system 1102 and placing an order for a subscription to the one or more services provided by the third-party network infrastructure system 1102. In at least one embodiment, the customer can access a third-party network user interface (UI), such as third-party network UI 1112, third-party network UI 1114, and / or third-party network UI 1116, and place an order via these UIs. In at least one embodiment, the order information received by the third-party network infrastructure system 1102 in response to the customer placing the order can include information identifying the customer and one or more services provided by the third-party network infrastructure system 1102 to which the customer wishes to subscribe.

[0187] In at least one embodiment, at step 1136, the order information received from the customer can be stored in order database 1118. In at least one embodiment, if this is a new order, a new record can be created for the order. In at least one embodiment, order database 1118 can be one of several databases operated by third-party network infrastructure system 1118 and in conjunction with other system components.

[0188] In at least one embodiment, at step 1138, the order information may be forwarded to order management module 1120, which may be configured to perform billing and accounting functions related to the order, such as verifying the order and, upon verification, booking an order.

[0189] In at least one embodiment, information about the order may be transmitted to an order coordination module 1122 at step 1140. The order coordination module 1122 is configured to coordinate the provisioning of services and resources for the order placed by the customer. In at least one embodiment, the order coordination module 1122 may utilize the services of an order provisioning module 1124 for provisioning. In at least one embodiment, the order coordination module 1122 enables management of the business processes associated with each order and applies business logic to determine whether the order should proceed with provisioning.

[0190] In at least one embodiment, at step 1142, upon receiving an order for a new subscription, the order coordination module 1122 sends a request to the order provisioning module 1124 to allocate resources and configure the resources necessary to fulfill the subscription order. In at least one embodiment, the order provisioning module 1124 implements the allocation of resources for the services ordered by the customer. In at least one embodiment, the order provisioning module 1124 provides a level of abstraction between the third-party network services provided by the third-party network infrastructure system 1100 and the physical implementation layer used to provision the resources for providing the requested services. In at least one embodiment, this enables the order coordination module 1122 to be isolated from implementation details, such as whether services and resources are actually provisioned in real time, or pre-provisioned and allocated / assigned only upon request.

[0191] In at least one embodiment, once the services and resources are provisioned, a notification may be sent to the subscribing client indicating that the requested service is now ready for use, step 1144. In at least one embodiment, information (e.g., a link) may be sent to the client that enables the client to begin using the requested service.

[0192] In at least one embodiment, at step 1146, the customer's subscription order may be managed and tracked by the order management and monitoring module 1126. In at least one embodiment, the order management and monitoring module 1126 may be configured to collect usage statistics regarding the customer's use of the subscription service. In at least one embodiment, statistics may be collected regarding the amount of storage used, the amount of data transferred, the number of users, and the amount and / or changes in system power-up time and system power-down time.

[0193] In at least one embodiment, the third-party network infrastructure system 1100 may include an identity management module 1128 configured to provide identity services, such as access management and authorization services within the third-party network infrastructure system 1100. In at least one embodiment, the identity management module 1128 may control information about customers who wish to utilize services provided by the third-party network infrastructure system 1102. In at least one embodiment, such information may include information authenticating the identities of such customers and information describing which actions those customers are authorized to perform with respect to various system resources (e.g., files, directories, applications, communication ports, memory segments, etc.). In at least one embodiment, the identity management module 1128 may also include managing descriptive information about each customer, as well as information about how and by whom the descriptive information may be accessed and modified.

[0194] Figure 12 A cloud computing environment 1202 is shown in accordance with at least one embodiment. In at least one embodiment, the cloud computing environment 1202 includes one or more computer systems / servers 1204 with which computing devices such as personal digital assistants (PDAs) or cell phones 1206A, desktop computers 1206B, laptop computers 1206C, and / or automobile computer systems 1206N communicate. In at least one embodiment, this allows infrastructure, platforms, and / or software to be provided as a service from the cloud computing environment 1202, so that each client does not need to maintain such resources individually. It should be understood that Figure 12 The types of computing devices 1206A-N shown are intended to be illustrative only, and the cloud computing environment 1202 may communicate with any type of computerized device over any type of network and / or network / addressable connection (eg, using a web browser).

[0195] In at least one embodiment, computer system / server 1204, which may be represented as a cloud computing node, is operable with numerous other general-purpose or special-purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations that may be suitable for use with computer system / server 1204 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the foregoing, and / or variations thereof.

[0196] In at least one embodiment, computer system / server 1204 can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. In at least one embodiment, exemplary computer system / server 1204 can be practiced in a distributed cloud computing environment, where tasks are performed by remote processing devices linked through a communication network. In at least one embodiment, in a distributed cloud computing environment, program modules can be located in both local and remote computer system storage media, including memory storage devices.

[0197] Figure 13 FIG. 1 shows a diagram of a cloud computing environment 1202 ( Figure 12 ) provides a set of functional abstraction layers. It should be understood in advance that Figure 13 The components, layers, and functions shown in are intended to be illustrative only, and the components, layers, and functions may vary.

[0198] In at least one embodiment, the hardware and software layer 1302 includes hardware and software components. In at least one embodiment, the hardware components include mainframes, servers based on various RISC (Reduced Instruction Set Computer) architectures, various computing systems, supercomputing systems, storage devices, networks, networking components, and / or variations thereof. In at least one embodiment, the software components include network application server software, various application server software, various database software, and / or variations thereof.

[0199] In at least one embodiment, the virtualization layer 1304 provides an abstraction layer from which the following exemplary virtual entities can be provided: virtual servers, virtual storage, virtual networks (including virtual private networks), virtual applications, virtual clients, and / or variations thereof.

[0200] In at least one embodiment, the management layer 1306 provides various functions. In at least one embodiment, resource provisioning provides dynamic acquisition of computing resources and other resources for performing tasks within the cloud computing environment. In at least one embodiment, metering provides usage tracking when resources are utilized within the cloud computing environment, as well as billing or invoicing for the consumption of those resources. In at least one embodiment, resources may include application software licenses. In at least one embodiment, security provides authentication for users and tasks, as well as protection of data and other resources. In at least one embodiment, a user interface provides access to the cloud computing environment for both users and system administrators. In at least one embodiment, service level management provides allocation and management of cloud computing resources so that required service levels are met. In at least one embodiment, service level agreement (SLA) management provides pre-placement and acquisition of cloud computing resources in anticipation of future demand for the cloud computing resources according to the SLA.

[0201] In at least one embodiment, workload layer 1308 provides functionality that leverages a cloud computing environment. In at least one embodiment, workloads and functionality that can be provided from this layer include: mapping and navigation, software development and management, educational services, data analysis and processing, transaction processing, and service delivery.

[0202] Supercomputing

[0203] The following figures illustrate, but are not limited to, exemplary supercomputer-based systems that may be used to implement at least one embodiment.

[0204] In at least one embodiment, a supercomputer may refer to a hardware system that exhibits significant parallelism and includes at least one chip, wherein the chips in the system are interconnected by a network and placed in a hierarchically organized housing. In at least one embodiment, a large hardware system that fills a computer room with several racks, each rack containing several boards / rack modules, each board / rack module containing several chips all interconnected by a scalable network is at least one embodiment of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other embodiment of a supercomputer. In at least one embodiment, a single chip that exhibits significant parallelism and includes several hardware components may also be considered a supercomputer because as feature sizes may decrease, the amount of hardware that can be combined in a single chip may also increase.

[0205] Figure 14A chip-level supercomputer according to at least one embodiment is shown. In at least one embodiment, the main computation is performed within a finite state machine (1404) called a thread unit within an FPGA or ASIC chip. In at least one embodiment, a task and synchronization network (1402) connects the finite state machine and is used to dispatch threads and execute operations in the correct order. In at least one embodiment, a memory network (1406, 1410) is used to access multi-level partitioned on-chip cache levels (1408, 1412). In at least one embodiment, a memory controller (1416) and an off-chip memory network (1414) are used to access off-chip memory. In at least one embodiment, an I / O controller (1418) is used for cross-chip communication when the design is not suitable for a single logic chip.

[0206] Figure 15 A supercomputer at the rack module level is shown according to at least one embodiment. In at least one embodiment, within the rack module, there are multiple FPGA or ASIC chips (1502) connected to one or more DRAM units (1504) that constitute the main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its neighboring FPGA / ASIC chips using differential high-speed signaling (1506) using a wide bus on the board. In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high-speed serial communication cable.

[0207] Figure 16 A rack-scale supercomputer is shown in accordance with at least one embodiment. Figure 17 An overall system-level supercomputer according to at least one embodiment is shown. In at least one embodiment, see Figure 16 and Figure 17, between rack modules in a rack and across racks throughout the system, high-speed serial optical or copper cables (1602, 1702) are used to implement a scalable, potentially incomplete, hypercube network. In at least one embodiment, one of the accelerator's FPGA / ASIC chips is connected to a host system (1704) via a PCI-Express connection. In at least one embodiment, the host system includes a host microprocessor (1708) on which the software portion of the application runs, and memory consisting of one or more host memory DRAM cells (1706) that are coherent with the memory on the accelerator. In at least one embodiment, the host system can be a separate module on one of the racks, or can be integrated with one of the modules of the supercomputer. In at least one embodiment, a circular topology of cube connections provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, small groups of FPGA / ASIC chips on a rack module can act as a single hypercube node, increasing the total number of external links per group compared to a single chip. In at least one embodiment, a group includes chips A, B, C, and D on a rack module with an internal wide differential bus connecting A, B, C, and D in a ring organization. In at least one embodiment, there are 12 serial communication cables connecting the rack modules to the outside world. In at least one embodiment, chip A on the rack module connects to serial communication cables 0, 1, and 2. In at least one embodiment, chip B connects to cables 3, 4, and 5. In at least one embodiment, chip C connects to cables 6, 7, and 8. In at least one embodiment, chip D connects to cables 9, 10, and 11. In at least one embodiment, the entire group {A, B, C, D} that makes up the rack modules can form a hypercube node within a supercomputer system, with up to 212 = 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to send a message out on link 4 of the group {A, B, C, D}, the message must first be routed to chip B using the on-board differential wide bus connection. In at least one embodiment, a message arriving on link 4 of the group {A, B, C, D} destined for chip A (i.e., to B) must also first be routed to the correct destination chip (A) within the group {A, B, C, D}. In at least one embodiment, parallel supercomputer systems of other sizes may also be implemented.

[0208] AI

[0209] The following figures illustrate, but are not limited to, exemplary artificial intelligence-based systems that can be used to implement at least one embodiment.

[0210] Figure 18AInference and / or training logic 1815 is shown for performing inference and / or training operations associated with one or more embodiments. Figure 18A and / or Figure 18B Provide details about the inference and / or training logic 1815.

[0211] In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, code and / or data storage 1801 for storing forward and / or output weights and / or input / output data, and / or other parameters used to configure neurons or layers of a neural network being trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, training logic 1815 may include or be coupled to code and / or data storage 1801 for storing graph code or other software to control the timing and / or sequence in which weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weights or other parameter information into a processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, code and / or data storage 1801 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 1801 may be included with other on-chip or off-chip data storage devices, including the processor's L1, L2, or L3 cache memory or system memory.

[0212] In at least one embodiment, any portion of code and / or data storage 1801 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data storage 1801 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or code and / or data storage 1801 is internal or external to a processor, or includes DRAM, SRAM, flash memory, or some other type of storage, may depend on the available storage on-chip versus off-chip, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0213] In at least one embodiment, the inference and / or training logic 1815 may include, but is not limited to, code and / or data storage 1805 for storing backpropagation and / or output weights and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, the code and / or data storage 1805 stores weight parameters and / or input / output data for each layer of a neural network trained or used in conjunction with one or more embodiments during backpropagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, the training logic 1815 may include or be coupled to code and / or data storage 1805 to store graph code or other software to control the timing and / or sequence in which weights and / or other parameter information are loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).

[0214] In at least one embodiment, code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network to which such code corresponds. In at least one embodiment, any portion of code and / or data storage 1805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 1805 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 1805 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, the choice of whether code and / or data storage 1805 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of data used in inference and / or training of the neural network, or some combination of these factors.

[0215] In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 may be separate storage structures. In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 may be a combined storage structure. In at least one embodiment, code and / or data storage 1801 and code and / or data storage 1805 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data storage 1801 and code and / or data storage 1805 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0216] In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 1810 , including integer and / or floating point units, for performing logical and / or mathematical operations based at least in part on or directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values ​​from a layer or neuron within a neural network) stored in activation storage 1820 , which is a function of input / output and / or weight parameter data stored in code and / or data storage 1801 and / or code and / or data storage 1805 . In at least one embodiment, the activations stored in activation storage 1820 are generated based on linear algebra and / or matrix-based math performed by ALU 1810 in response to executing instructions or other code, where weight values ​​stored in code and / or data storage 1805 and / or data storage 1801 are used as operands along with other values ​​such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data storage 1805 or code and / or data storage 1801 or in another storage on or off-chip.

[0217] In at least one embodiment, one or more ALUs 1810 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 1810 may be external to the processor or other hardware logic devices or circuits (e.g., coprocessors) that use them. In at least one embodiment, ALUs 1810 may be included within an execution unit of a processor or otherwise within an ALU bank accessible by an execution unit of a processor, either within the same processor or distributed across different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data storage 1801, code and / or data storage 1805, and activation storage 1820 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits, or in some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage 1820 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. Additionally, inference and / or training code may be stored with other code accessible to the processor or other hardware logic or circuitry and fetched and / or processed using the processor's fetch, decode, schedule, execute, retire, and / or other logic circuitry.

[0218] In at least one embodiment, activation storage 1820 can be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage devices. In at least one embodiment, activation storage 1820 can be completely or partially internal or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether activation storage 1820 is internal or external to the processor, or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in inference and / or training of the neural network, or some combination of these factors.

[0219] In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown in FIG can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the one from Google. Processing unit from Graphcore TM Inference Processing Unit (IPU), or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 18A The inference and / or training logic 1815 shown in FIG may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware such as a field programmable gate array (“FPGA”).

[0220] Figure 18B Inference and / or training logic 1815 is shown in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 1815 may include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values ​​or other information corresponding to one or more neuron layers within a neural network. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be combined with an application specific integrated circuit (ASIC) (such as the one from Google Processing unit from Graphcore TM Inference Processing Unit (IPU), or from Intel (e.g., "Lake Crest") processor. In at least one embodiment, Figure 18B The inference and / or training logic 1815 shown in FIG can be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware such as a field programmable gate array (FPGA). In at least one embodiment, the inference and / or training logic 1815 includes, but is not limited to, code and / or data storage 1801 and code and / or data storage 1805, which can be used to store code (e.g., graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. Figure 18B In at least one embodiment described in

[0065] , each of code and / or data storage 1801 and code and / or data storage 1805 is associated with dedicated computing resources, such as computing hardware 1802 and computing hardware 1806, respectively. In at least one embodiment, each of computing hardware 1802 and computing hardware 1806 includes one or more ALUs that perform mathematical functions (such as linear algebraic functions) solely on the information stored in code and / or data storage 1801 and code and / or data storage 1805, respectively, with the results being stored in activation storage 1820.

[0221] In at least one embodiment, each code and / or data storage 1801 and 1805, and corresponding computational hardware 1802 and 1806, respectively, corresponds to a different layer of a neural network, such that the resulting activations from one storage / computation pair 1801 / 1802 in code and / or data storage 1801 and computational hardware 1802 are provided as input to the next storage / computation pair 1805 / 1806 in code and / or data storage 1805 and computational hardware 1806, mirroring the conceptual organization of the neural network. In at least one embodiment, each of storage / computation pairs 1801 / 1802 and 1805 / 1806 may correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) may be included in the inference and / or training logic 1815, either after or in parallel with storage / computation pairs 1801 / 1802 and 1805 / 1806.

[0222] Figure 19 The training and deployment of a deep neural network according to at least one embodiment is shown. In at least one embodiment, an untrained neural network 1906 is trained using a training dataset 1902. In at least one embodiment, the training framework 1904 is the PyTorch framework, while in other embodiments, the training framework 1904 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks.

[0223] In at least one embodiment, the training framework 1904 trains an untrained neural network 1906 and enables it to be trained using the processing resources described herein to generate a trained neural network 1908. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0224] In at least one embodiment, untrained neural network 1906 is trained using supervised learning, where training dataset 1902 includes inputs paired with expected outputs for the inputs, or where training dataset 1902 includes inputs with known outputs and the outputs of neural network 1906 are manually graded. In at least one embodiment, untrained neural network 1906 is trained in a supervised manner, processing inputs from training dataset 1902 and comparing the resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then backpropagated through untrained neural network 1906. In at least one embodiment, training framework 1904 adjusts the weights that control untrained neural network 1906. In at least one embodiment, training framework 1904 includes tools for monitoring how well untrained neural network 1906 converges toward a model (such as trained neural network 1908) suitable for generating correct answers (such as results 1914) based on input data (such as new dataset 1912). In at least one embodiment, the training framework 1904 repeatedly trains the untrained neural network 1906 while adjusting the weights using a loss function and an adjustment algorithm (such as stochastic gradient descent) to refine the output of the untrained neural network 1906. In at least one embodiment, the training framework 1904 trains the untrained neural network 1906 until the untrained neural network 1906 achieves a desired accuracy. In at least one embodiment, the trained neural network 1908 can then be deployed to implement any number of machine learning operations.

[0225] In at least one embodiment, untrained neural network 1906 is trained using unsupervised learning, wherein untrained neural network 1906 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 1902 will include input data without any associated output data or "ground truth" data. In at least one embodiment, untrained neural network 1906 can learn groupings within training dataset 1902 and can determine how individual inputs relate to untrained dataset 1902. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in trained neural network 1908 that is capable of performing operations useful in reducing the dimensionality of new dataset 1912. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in new dataset 1912 that deviate from the normal pattern of new dataset 1912.

[0226] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1902. In at least one embodiment, the training framework 1904 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1908 to adapt to new datasets 1912 without forgetting the knowledge infused into the trained neural network 1408 during initial training.

[0227] 5G network

[0228] The following figures illustrate, but are not limited to, exemplary 5G network-based systems that may be used to implement at least one embodiment.

[0229] Figure 20 The architecture of a system 2000 for a network according to at least one embodiment is shown. In at least one embodiment, the system 2000 is shown as including user equipment (UE) 2002 and UE 2004. In at least one embodiment, the UEs 2002 and 2004 are shown as smartphones (e.g., handheld touchscreen mobile computing devices that can connect to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as a personal digital assistant (PDA), a pager, a laptop computer, a desktop computer, a wireless handheld device, or any computing device that includes a wireless communication interface.

[0230] In at least one embodiment, any of UE 2002 and UE 2004 may comprise an Internet of Things (IoT) UE, which may include a network access layer designed for low-power IoT applications that utilize short-lived UE connections. In at least one embodiment, the IoT UE may utilize technologies such as machine-to-machine (M2M) or machine-type communication (MTC) for exchanging data with an MTC server or device via a public land mobile network (PLMN), proximity-based services (ProSe), or device-to-device (D2D) communication, a sensor network, or an IoT network. In at least one embodiment, the M2M or MTC data exchange may be machine-initiated data exchange. In at least one embodiment, the IoT network describes interconnected IoT UEs, which may include uniquely identifiable embedded computing devices (within the Internet infrastructure) with short-lived connections. In at least one embodiment, the IoT UE may execute background applications (e.g., keep-alive messages, status updates, etc.) to facilitate connectivity to the IoT network.

[0231] In at least one embodiment, UE 2002 and UE 2004 can be configured to connect (e.g., be communicatively coupled) to a radio access network (RAN) 2016. In at least one embodiment, RAN 2016 can be an evolved universal mobile telecommunications system (UMTS) terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or some other type of RAN. In at least one embodiment, UE 2002 and UE 2004 utilize connection 2012 and connection 2014, respectively, each of which includes a physical communication interface or layer. In at least one embodiment, connections 2012 and 2014 are shown as air interfaces for achieving communicative coupling and can be consistent with a cellular communication protocol, such as a Global System for Mobile Communications (GSM) protocol, a Code Division Multiple Access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a fifth generation (5G) protocol, a New Radio (NR) protocol, and variations thereof.

[0232] In at least one embodiment, the UEs 2002 and 2004 may also directly exchange communication data via a ProSe interface 2006. In at least one embodiment, the ProSe interface 2006 may alternatively be referred to as a side link interface, which includes one or more logical channels, including but not limited to a physical side link control channel (PSCCH), a physical side link shared channel (PSSCH), a physical side link discovery channel (PSDCH), and a physical side link broadcast channel (PSBCH).

[0233] In at least one embodiment, UE 2004 is shown as being configured to access access point (AP) 2010 via connection 2008. In at least one embodiment, connection 2008 may comprise a local wireless connection, such as a connection consistent with any IEEE 802.11 protocol, wherein AP 2010 would include Wi-Fi. In at least one embodiment, AP 2010 is shown connected to the Internet and not to the core network of the wireless system.

[0234] In at least one embodiment, the RAN 2016 may include one or more access nodes that enable connections 2012 and 2014. In at least one embodiment, these access nodes (ANs) may be referred to as base stations (BSs), NodeBs, evolved NodeBs (eNBs), next-generation NodeBs (gNBs), RAN nodes, etc., and may include ground stations (e.g., terrestrial access points) or satellite stations that provide coverage within a geographic area (e.g., a cell). In at least one embodiment, the RAN 2016 may include one or more RAN nodes (e.g., macro RAN nodes 2018) for providing macro cells and one or more RAN nodes (e.g., low power (LP) RAN nodes 2020) for providing femto cells or pico cells (e.g., cells with smaller coverage areas, smaller user capacity, or higher bandwidth than macro cells).

[0235] In at least one embodiment, either of the RAN nodes 2018 and 2020 may terminate the air interface protocol and may be the first point of contact for the UEs 2002 and 2004. In at least one embodiment, either of the RAN nodes 2018 and 2020 may implement various logical functions of the RAN 2016, including but not limited to radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and data packet scheduling and mobility management.

[0236] In at least one embodiment, UE 2002 and UE 2004 may be configured to communicate with each other or with any of RAN node 2018 and RAN node 2020 over a multi-carrier communication channel using orthogonal frequency division multiplexing (OFDM) communication signals according to various communication technologies, such as, but not limited to, orthogonal frequency division multiple access (OFDMA) communication technology (e.g., for downlink communication) or single-carrier frequency division multiple access (SC-FDMA) communication technology (e.g., for uplink and ProSe or sidelink communication), and / or variants thereof. In at least one embodiment, the OFDM signal may include multiple orthogonal subcarriers.

[0237] In at least one embodiment, a downlink resource grid can be used for downlink transmissions from either RAN nodes 2018 and 2020 to UEs 2002 and 2004, while uplink transmissions can utilize similar techniques. In at least one embodiment, the grid can be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, representing the physical resources in the downlink in each time slot. In at least one embodiment, this time-frequency plane representation is common practice in OFDM systems, making it intuitive for radio resource allocation. In at least one embodiment, each column and row of the resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. In at least one embodiment, the duration of the resource grid in the time domain corresponds to a time slot in a radio frame. In at least one embodiment, the smallest time-frequency unit in the resource grid is represented as a resource element. In at least one embodiment, each resource grid includes multiple resource blocks, which describe the mapping of certain physical channels to resource elements. In at least one embodiment, each resource block includes a collection of resource elements. In at least one embodiment, in the frequency domain, this can represent the minimum number of resources that can currently be allocated. In at least one embodiment, there are several different physical downlink channels transmitted using such resource blocks.

[0238] In at least one embodiment, a physical downlink shared channel (PDSCH) can carry user data and higher-layer signaling to UEs 2002 and 2004. In at least one embodiment, a physical downlink control channel (PDCCH) can carry information about, among other things, the transport format and resource allocation associated with the PDSCH channel. In at least one embodiment, it can also inform UEs 2002 and 2004 of the transport format, resource allocation, and HARQ (Hybrid Automatic Repeat Request) information associated with the uplink shared channel. In at least one embodiment, downlink scheduling (allocation of control and shared channel resource blocks to UEs 2002 within a cell) can typically be performed at either RAN node 2018 or 2020 based on channel quality information fed back from either UE 2002 or 2004. In at least one embodiment, downlink resource allocation information can be sent on a PDCCH for (e.g., allocated to) each of UEs 2002 and 2004.

[0239] In at least one embodiment, the PDCCH may use control channel elements (CCEs) to transmit control information. In at least one embodiment, before being mapped to resource elements, the PDCCH complex symbols may first be organized into quadruplets, which may then be permuted using a sub-block interleaver for rate matching. In at least one embodiment, each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements referred to as resource element groups (REGs). In at least one embodiment, four quadrature phase shift keying (QPSK) symbols may be mapped to each REG. In at least one embodiment, one or more CCEs may be used to transmit the PDCCH, depending on the size of the downlink control information (DCI) and the channel conditions. In at least one embodiment, there may be four or more different PDCCH formats (e.g., aggregation levels, L=1, 2, 4, or 8) defined in LTE with different numbers of CCEs.

[0240] In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources may be used for control information transmission. In at least one embodiment, EPDCCH may be transmitted using one or more enhanced control channel elements (ECCEs). In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements referred to as enhanced resource element groups (EREGs). In at least one embodiment, ECCEs may have other numbers of EREGs in some cases.

[0241] In at least one embodiment, the RAN 2016 is shown as being communicatively coupled to a core network (CN) 2038 via an S1 interface 2022. In at least one embodiment, the CN 2038 can be an evolved packet core (EPC) network, a NextGen packet core (NPC) network, or some other type of CN. In at least one embodiment, the S1 interface 2022 is divided into two parts: an S1-U interface 2026, which carries traffic data between the RAN nodes 2018 and 2020 and the serving gateway (S-GW) 2030; and an S1-Mobility Management Entity (MME) interface 2024, which is a signaling interface between the RAN nodes 2018 and 2020 and the MME 2028.

[0242] In at least one embodiment, CN 2038 includes MME 2028, S-GW 2030, Packet Data Network (PDN) Gateway (P-GW) 2034, and Home Subscriber Server (HSS) 2032. In at least one embodiment, MME 2028 can be functionally similar to the control plane of a traditional Serving General Packet Radio Service (GPRS) Support Node (SGSN). In at least one embodiment, MME 2028 can manage mobility aspects of access, such as gateway selection and tracking area list management. In at least one embodiment, HSS 2032 can include a database for network users, including subscription-related information used to support network entities handling communication sessions. In at least one embodiment, CN 2038 can include one or more HSSs 2032, depending on the number of mobile users, device capacity, network organization, etc. In at least one embodiment, HSS 2032 can provide support for routing / roaming, authentication, authorization, naming / addressing resolution, location dependencies, etc.

[0243] In at least one embodiment, the S-GW 2030 may terminate the S1 interface 2022 towards the RAN 2016 and route data packets between the RAN 2016 and the CN 2038. In at least one embodiment, the S-GW 2030 may be the local mobility anchor for inter-RAN node handovers and may also provide an anchor for inter-3GPP mobility. In at least one embodiment, other responsibilities may include lawful interception, charging, and some policy enforcement.

[0244] In at least one embodiment, the P-GW 2034 can terminate the SGi interface toward the PDN. In at least one embodiment, the P-GW 2034 can route data packets between the EPC network 2038 and an external network, such as a network including an application server 2040 (or application function (AF)), via an Internet Protocol (IP) interface 2042. In at least one embodiment, the application server 2040 can be an element that provides applications using IP bearer resources using a core network (e.g., a UMTS packet service (PS) domain, an LTE PS data service, etc.). In at least one embodiment, the P-GW 2034 is shown as being communicatively coupled to the application server 2040 via an IP communication interface 2042. In at least one embodiment, the application server 2040 can also be configured to support one or more communication services (e.g., voice over Internet Protocol (VoIP) sessions, PTT sessions, group communication sessions, social networking services, etc.) for UEs 2002 and 2004 via the CN 2038.

[0245] In at least one embodiment, P-GW 2034 can also be a node for policy enforcement and charging data collection. In at least one embodiment, Policy and Charging Enforcement Function (PCRF) 2036 is the policy and charging control element of CN 2038. In at least one embodiment, in a non-roaming scenario, a single PCRF can exist in the Home Public Land Mobile Network (HPLMN) associated with the UE's Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local traffic breakout, two PCRFs can exist associated with the UE's IP-CAN session: a Home PCRF (H-PCRF) in the HPLMN and a Visited PCRF (V-PCRF) in the Visited Public Land Mobile Network (VPLMN). In at least one embodiment, PCRF 2036 can be communicatively coupled to Application Server 2040 via P-GW 2034. In at least one embodiment, Application Server 2040 can signal PCRF 2036 to indicate a new service flow and select appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, PCRF 2036 can supply this rule to a Policy and Charging Enforcement Function (PCEF) (not shown) with the appropriate Traffic Flow Template (TFT) and QoS Class (QCI) identifier, which initiates the QoS and charging specified by the Application Server 2040.

[0246] Figure 21 The architecture of a system 2100 of a network according to some embodiments is shown. In at least one embodiment, the system 2100 is shown to include a UE 2102, a 5G access node or RAN node (shown as (R)AN node 2108), a user plane function (shown as UPF 2104), a data network (DN 2106), which in at least one embodiment can be an operator service, internet access, or a third-party service, and a 5G core network (5GC) (shown as CN 2110).

[0247] In at least one embodiment, CN 2110 includes an authentication server function (AUSF 2114); a core access and mobility management function (AMF 2112); a session management function (SMF 2118); a network exposure function (NEF 2116); a policy control function (PCF 2122); a network function (NF) repository function (NRF 2120); a unified data management (UDM 2124); and an application function (AF 2126). In at least one embodiment, CN 2110 may also include other elements not shown, such as a structured data storage network function (SDSF), an unstructured data storage network function (UDSF), and variations thereof.

[0248] In at least one embodiment, the UPF 2104 can serve as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point interconnected to the DN 2106, and a branching point supporting multi-homed PDU sessions. In at least one embodiment, the UPF 2104 can also perform packet routing and forwarding, packet inspection, user plane enforcement of policy rules, lawful interception of packets (UP collection), service usage reporting, QoS processing for the user plane (e.g., packet filtering, gating, UL / DL rate enforcement), uplink service validation (e.g., SDF to QoS flow mapping), transport-level packet marking in the uplink and downlink, downlink packet buffering, and downlink data notification triggering. In at least one embodiment, the UPF 2104 can include an uplink classifier to support routing of service flows to the data network. In at least one embodiment, the DN 2106 can represent various network operator services, internet access, or third-party services.

[0249] In at least one embodiment, the AUSF 2114 may store data used for authentication of the UE 2102 and handle authentication-related functions. In at least one embodiment, the AUSF 2114 may facilitate a common authentication framework for various access types.

[0250] In at least one embodiment, the AMF 2112 may be responsible for registration management (e.g., for registering UE 2102, etc.), connection management, reachability management, mobility management, and lawful interception of AMF-related events, as well as access authentication and authorization. In at least one embodiment, the AMF 2112 may provide transport of SM messages for the SMF 2118 and act as a transparent proxy for routing SM messages. In at least one embodiment, the AMF 2112 may also provide UE 2102 with an SMS function (SMSF) ( Figure 21 In at least one embodiment, the AMF 2112 may act as a Security Anchor Function (SEA), which may include interaction with the AUSF 2114 and the UE 2102 and receiving intermediate keys established as a result of the UE 2102 authentication process. In at least one embodiment, where USIM-based authentication is used, the AMF 2112 may retrieve security material from the AUSF 2114. In at least one embodiment, the AMF 2112 may also include a Security Context Management (SCM) function that receives keys from the SEA that it uses to derive access network-specific keys. In addition, in at least one embodiment, the AMF 2112 may be the termination point for the RAN CP interface (N2 reference point), the termination point for NAS (NI) signaling, and perform NAS encryption and integrity protection.

[0251] In at least one embodiment, the AMF 2112 may also support NAS signaling with the UE 2102 over the N3 Interworking Function (IWF) interface. In at least one embodiment, the N3 IWF may be used to provide access to untrusted entities. In at least one embodiment, the N3 IWF may be the termination point for the N2 and N3 interfaces for the control plane and user plane, respectively. Thus, it may handle N2 signaling from the SMF and AMF for PDU sessions and QoS, encapsulate / decapsulate packets for IPSec and N3 tunnels, mark N3 user plane packets in the uplink, and enforce QoS corresponding to the marking of N3 packets, taking into account the QoS requirements associated with such markings received over N2. In at least one embodiment, the N3 IWF may also relay uplink and downlink control plane NAS (NI) signaling between the UE 2102 and the AMF 2112, and relay uplink and downlink user plane packets between the UE 2102 and the UPF 2104. In at least one embodiment, the N3IWF also provides a mechanism for IPsec tunnel establishment with UE 2102.

[0252] In at least one embodiment, the SMF 2118 may be responsible for session management (e.g., session establishment, modification, and release, including tunnel maintenance between the UPF and AN nodes); UE IP address allocation and management (including optional authorization); selection and control of UP functions; configuring traffic steering at the UPF to route traffic to the appropriate destination; interface termination towards the policy control function; policy enforcement and control portion of QoS; lawful interception (for SM events and interface to the LI system); termination of the SM portion of NAS messages; downlink data notification; originator of AN-specific SM information, which is sent to the AN via the AMF on N2; determining the SSC mode for the session. In at least one embodiment, the SMF 2118 may include the following roaming functions: handling local implementation to apply QoS SLAB (VPLMN); charging data collection and charging interface (VPLMN); lawful interception (for SM events in the VPLMN and interface to the LI system); supporting interaction with external DNs to transport signaling for PDU session authorization / authentication by the external DN.

[0253] In at least one embodiment, the NEF 2116 can provide a means for securely exposing services and capabilities provided by 3GPP network functions to third parties, internal exposure / re-exposure, application functions (e.g., AF 2126), edge computing or fog computing systems, and the like. In at least one embodiment, the NEF 2116 can authenticate, authorize, and / or throttle the AF. In at least one embodiment, the NEF 2116 can also convert information exchanged with the AF 2126 and information exchanged with internal network functions. In at least one embodiment, the NEF 2116 can convert between AF service identifiers and internal 5GC information. In at least one embodiment, the NEF 2116 can also receive information from other network functions (NFs) based on their exposed capabilities. In at least one embodiment, this information can be stored in the NEF 2116 as structured data or in a data storage NF using standardized interfaces. In at least one embodiment, the stored information can then be re-exposed by the NEF 2116 to other NFs and AFs and / or used for other purposes, such as analysis.

[0254] In at least one embodiment, the NRF 2120 may support service discovery functionality, receive NF discovery requests from NF instances, and provide information about the discovered NF instances to the NF instances. In at least one embodiment, the NRF 2120 also maintains information about available NF instances and the services they support.

[0255] In at least one embodiment, the PCF 2122 can provide policy rules to the control plane functions to implement them and can also support a unified policy framework to manage network behavior. In at least one embodiment, the PCF 2122 can also implement a front end (FE) for accessing subscription information related to policy decisions in the UDR of the UDM 2124.

[0256] In at least one embodiment, the UDM 2124 can process subscription-related information to support network entities handling communication sessions and can store subscription data for the UE 2102. In at least one embodiment, the UDM 2124 can include two components: an application FE and a user data repository (UDR). In at least one embodiment, the UDM can include a UDM FE, which is responsible for handling credentials, location management, subscription management, and the like. In at least one embodiment, several different front ends can serve the same user in different transactions. In at least one embodiment, the UDM-FE accesses the sub-subscription information stored in the UDR and performs authentication credential processing; user identity processing; access authorization; registration / mobility management; and subscription management. In at least one embodiment, the UDR can interact with the PCF 2122. In at least one embodiment, the UDM 2124 can also support SMS management, where the SMS-FE implements similar application logic as described above.

[0257] In at least one embodiment, the AF 2126 can provide application influence on service routing, access to the Network Capability Exposure (NCE), and interaction with the policy framework for policy control. In at least one embodiment, the NCE can be a mechanism that allows the 5GC and AF 2126 to provide information to each other via the NEF 2116, which can be used for edge computing implementations. In at least one embodiment, network operators and third-party services can be hosted near the UE 2102's attachment access point to achieve efficient service delivery with reduced end-to-end latency and load on the transport network. In at least one embodiment, for edge computing implementations, the 5GC can select a UPF 2104 close to the UE 2102 and perform service steering from the UPF 2104 to the DN 2106 via the N6 interface. In at least one embodiment, this can be based on UE subscription data, UE location, and information provided by the AF 2126. In at least one embodiment, the AF 2126 can influence UPF (re)selection and service routing. In at least one embodiment, based on operator deployment, the network operator may allow the AF 2126 to interact directly with the relevant NFs when the AF 2126 is considered a trusted entity.

[0258] In at least one embodiment, the CN 2110 may include an SMSF, which may be responsible for SMS subscription checking and verification, and relaying SM messages to / from the UE 2102 to / from other entities, such as SMS-GMSC / IWMSC / SMS routers. In at least one embodiment, the SMS may also interact with the AMF 2112 and the UDM 2124 for notification procedures that the UE 2102 is available for SMS delivery (e.g., setting a UE unreachable flag and notifying the UDM 2124 when the UE 2102 is available for SMS).

[0259] In at least one embodiment, the system 2100 may include the following service-based interfaces: Namf: a service-based interface exposed by AMF; Nsmf: a service-based interface exposed by SMF; Nnef: a service-based interface exposed by NEF; Npcf: a service-based interface exposed by PCF; Nudm: a service-based interface exposed by UDM; Naf: a service-based interface exposed by AF; Nnrf: a service-based interface exposed by NRF; and Nausf: a service-based interface exposed by AUSF.

[0260] In at least one embodiment, system 2100 may include the following reference points: N1: a reference point between the UE and the AMF; N2: a reference point between the (R)AN and the AMF; N3: a reference point between the (R)AN and the UPF; N4: a reference point between the SMF and the UPF; and N6: a reference point between the UPF and the data network. In at least one embodiment, there may be more reference points and / or service-based interfaces between NF services within the NF; however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, the NS reference point may be between the PCF and the AF; the N7 reference point may be between the PCF and the SMF; the N11 reference point may be between the AMF and the SMF, and so on. In at least one embodiment, CN 2110 may include an Nx interface, which is an inter-CN interface between the MME and the AMF 2112 to enable interworking between CN 2110 and CN 7221.

[0261] In at least one embodiment, the system 2100 may include multiple RAN nodes (such as (R)AN nodes 2108), wherein an Xn interface is defined between two or more (R)AN nodes 2108 (e.g., gNBs) connected to the 5GC 410, between an (R)AN node 2108 (e.g., gNBs) and an eNB (e.g., macro RAN node) connected to the CN 2110, and / or between two eNBs connected to the CN 2110.

[0262] In at least one embodiment, the Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, the Xn-U may provide non-guaranteed delivery of user plane PDUs and support / provide data forwarding and flow control functions. In at least one embodiment, the Xn-C may provide management and error handling functions, functions for managing the Xn-C interface, and mobility support for UE 2102 in connected mode (e.g., CM-CONNECTED), including functions for managing UE mobility in connected mode between one or more (R)AN nodes 2108. In at least one embodiment, mobility support may include context transfer from an old (source) serving (R)AN node 2108 to a new (target) serving (R)AN node 2108, and control of a user plane tunnel between the old (source) serving (R)AN node 2108 and the new (target) serving (R)AN node 2108.

[0263] In at least one embodiment, the protocol stack of Xn-U may include a transport network layer built on an Internet Protocol (IP) transport layer and a GTP-U layer for carrying user plane PDUs on top of UDP and / or one or more IP layers. In at least one embodiment, the Xn-C protocol stack may include an application layer signaling protocol (referred to as the Xn Application Protocol (Xn-AP)) and a transport network layer built on the SCTP layer. In at least one embodiment, the SCTP layer may be on top of the IP layer. In at least one embodiment, the SCTP layer provides guaranteed delivery of application layer messages. In at least one embodiment, in the transport IP layer, point-to-point transport is used to deliver signaling PDUs. In at least one embodiment, the Xn-U protocol stack and / or the Xn-C protocol stack may be the same or similar to the user plane and / or control plane protocol stacks shown and described herein.

[0264] Figure 22 2004 ), RAN 2016 , and MME 2028 .

[0265] In at least one embodiment, the PHY layer 2202 may send or receive information used by the MAC layer 2204 over one or more air interfaces. In at least one embodiment, the PHY layer 2202 may also perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers (e.g., the RRC layer 2210). In at least one embodiment, the PHY layer 2202 may further perform error detection on transport channels, forward error correction (FEC) encoding / decoding of transport channels, modulation / demodulation of physical channels, interleaving, rate matching, mapping to physical channels, and multiple-input multiple-output (MIMO) antenna processing.

[0266] In at least one embodiment, the MAC layer 2204 may perform mapping between logical channels and transport channels, multiplexing MAC service data units (SDUs) from one or more logical channels onto transport blocks (TBs) to be delivered to the PHY via transport channels, demultiplexing MAC SDUs from transport blocks (TBs) delivered from the PHY via transport channels to one or more logical channels, multiplexing MAC SDUs onto TBs, scheduling information reporting, error correction through hybrid automatic repeat request (HARD), and logical channel prioritization.

[0267] In at least one embodiment, the RLC layer 2206 can operate in multiple operating modes, including transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, the RLC layer 2206 can perform transmission of upper layer protocol data units (PDUs), error correction through automatic repeat request (ARQ) for AM data transmission, and concatenation, segmentation, and reassembly of RLC SDUs for UM and AM data transmission. In at least one embodiment, the RLC layer 2206 can also perform re-segmentation of RLC data PDUs for AM data transmission, reordering of RLC data PDUs for UM and AM data transmission, detection of duplicate data for UM and AM data transmission, discarding RLC SDUs for UM and AM data transmission, detecting protocol errors for AM data transmission, and performing RLC re-establishment.

[0268] In at least one embodiment, the PDCP layer 2208 can perform header compression and decompression of IP data, maintain PDCP sequence numbers (SNs), perform in-sequence delivery of higher layer PDUs when re-establishing lower layers, eliminate duplication of lower layer SDUs when re-establishing lower layers for radio bearers mapped on RLC AM, encrypt and decrypt control plane data, perform integrity protection and integrity verification on control plane data, control timer-based data discard, and perform security operations (e.g., encryption, decryption, integrity protection, integrity verification, etc.).

[0269] In at least one embodiment, the main services and functions of the RRC layer 2210 may include broadcasting of system information (e.g., included in a master information block (MIB) or system information block (SIB) related to the non-access stratum (NAS)), broadcasting of system information related to the access stratum (AS), paging, establishment, maintenance, and release of an RRC connection between a UE and an E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification, and RRC connection release), establishment, configuration, maintenance, and release of point-to-point radio bearers, security functions including key management, inter-radio access technology (RAT) mobility, and measurement configuration for UE measurement reporting. In at least one embodiment, the MIB and SIB may include one or more information elements (IEs), each of which may include a separate data field or data structure.

[0270] In at least one embodiment, the UE 2002 and the RAN 2016 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange control plane data via a protocol stack including a PHY layer 2202, a MAC layer 2204, an RLC layer 2206, a PDCP layer 2208, and an RRC layer 2210.

[0271] In at least one embodiment, the non-access stratum (NAS) protocol (NAS protocol 2212) forms the highest layer of the control plane between the UE 2002 and the MME 2028. In at least one embodiment, the NAS protocol 2212 supports the mobility and session management procedures of the UE 2002 to establish and maintain IP connectivity between the UE 2002 and the P-GW 2034.

[0272] In at least one embodiment, the Si application protocol (Si-AP) layer (Si-AP layer 2222) can support the functionality of the Si interface and include basic procedures (EPs). In at least one embodiment, the EP is the interaction unit between the RAN 2016 and the CN 2028. In at least one embodiment, the S1-AP layer services can include two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling, RAN Information Management (RIM), and configuration transfer.

[0273] In at least one embodiment, a stream control transmission protocol (SCTP) layer (alternatively referred to as a stream control transmission protocol / internet protocol (SCTP / IP) layer) (SCTP layer 2220) may ensure reliable delivery of signaling messages between the RAN 2016 and the MME 2028 based in part on the IP protocol supported by the IP layer 2218. In at least one embodiment, the L2 layer 2216 and the L1 layer 2214 may refer to communication links (e.g., wired or wireless) used by the RAN nodes and the MME to exchange information.

[0274] In at least one embodiment, the RAN 2016 and one or more MMEs 2028 may utilize an S1-MME interface to exchange control plane data via a protocol stack including the L1 layer 2214 , the L2 layer 2216 , the IP layer 2218 , the SCTP layer 2220 , and the Si-AP layer 2222 .

[0275] Figure 23 2 is a diagram of a user plane protocol stack according to at least one embodiment. In at least one embodiment, the user plane 2300 is shown as a communication protocol stack between the UE 2002, the RAN 2016, the S-GW 2030, and the P-GW 2034. In at least one embodiment, the user plane 2300 can utilize the same protocol layers as the control plane 2200. In at least one embodiment, the UE 2002 and the RAN 2016 can utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including a PHY layer 2202, a MAC layer 2204, an RLC layer 2206, and a PDCP layer 2208.

[0276] In at least one embodiment, the General Packet Radio Service (GPRS) Tunneling Protocol (GTP-U) layer for the user plane (GTP-U layer 2304) can be used to carry user data within the GPRS core network and between the radio access network and the core network. In at least one embodiment, the transmitted user data can be packets in any format of IPv4, IPv6 or PPP format. In at least one embodiment, the UDP and IP security (UDP / IP) layer (UDP / IP layer 2302) can provide a checksum for data integrity, port numbers for addressing different functions at the source and destination, and encryption and authentication of selected data streams. In at least one embodiment, the RAN 2016 and the S-GW 2030 can utilize the S1-U interface to exchange user plane data via a protocol stack including the L1 layer 2214, the L2 layer 2216, the UDP / IP layer 2302 and the GTP-U layer 2304. In at least one embodiment, the S-GW 2030 and the P-GW 2034 may utilize an S5 / S8a interface to exchange user plane data via a protocol stack including an L1 layer 2214, an L2 layer 2216, a UDP / IP layer 2302, and a GTP-U layer 2304. In at least one embodiment, as described above with respect to Figure 22 As discussed, the NAS protocol supports the mobility of UE 2002 and session management procedures to establish and maintain IP connectivity between UE 2002 and P-GW 2034 .

[0277] Figure 24 Components 2400 of a core network according to at least one embodiment are shown. In at least one embodiment, the components of CN 2038 can be implemented in one physical node or in separate physical nodes, the separate physical nodes including components for reading and executing instructions from a machine-readable medium or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize any or all of the above-described network node functions via executable instructions stored in one or more computer-readable storage media (described in further detail below). In at least one embodiment, a logical instantiation of CN 2038 can be referred to as a network slice 2402 (e.g., network slice 2402 is shown as including HSS 2032, MME 2028, and S-GW 2030). In at least one embodiment, a logical instantiation of a portion of CN 2038 can be referred to as a network sub-slice 2404 (e.g., network sub-slice 2404 is shown as including P-GW 2034 and PCRF 2036).

[0278] In at least one embodiment, the NFV architecture and infrastructure can be used to virtualize one or more network functions onto physical resources including a combination of industry-standard server hardware, storage hardware, or switches, which may alternatively be performed by dedicated hardware. In at least one embodiment, the NFV system can be used to perform a virtual or reconfigurable implementation of one or more EPC components / functions.

[0279] Figure 25 2 is a block diagram illustrating components of a system 2500 for supporting network function virtualization (NFV) according to at least one embodiment. In at least one embodiment, system 2500 is shown as including a virtualization infrastructure manager (shown as VIM 2502), a network function virtualization infrastructure (shown as NFVI 2504), a VNF manager (shown as VNFM 2506), virtualized network functions (shown as VNF 2508), an element manager (shown as EM 2510), an NFV orchestrator (shown as NFVO 2512), and a network manager (shown as NM 2514).

[0280] In at least one embodiment, the VIM 2502 manages resources of the NFVI 2504. In at least one embodiment, the NFVI 2504 may include physical or virtual resources and applications (including a hypervisor) used to execute the system 2500. In at least one embodiment, the VIM 2502 may utilize the NFVI 2504 to manage the lifecycle of virtual resources (e.g., the creation, maintenance, and teardown of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, faults, and security of VM instances and associated physical resources, and expose VM instances and associated physical resources to other management systems.

[0281] In at least one embodiment, VNFM 2506 can manage VNF 2508. In at least one embodiment, VNF 2508 can be used to perform EPC components / functions. In at least one embodiment, VNFM 2506 can manage the lifecycle of VNF 2508 and track the performance, faults, and security of the virtual aspects of VNF 2508. In at least one embodiment, EM 2510 can track the performance, faults, and security of the functional aspects of VNF 2508. In at least one embodiment, the data tracked from VNFM 2506 and EM 2510 can include, in at least one embodiment, performance measurement (PM) data used by VIM 2502 or NFVI 2504. In at least one embodiment, both VNFM 2506 and EM 2510 can scale up / down the number of VNFs in system 2500.

[0282] In at least one embodiment, the NFVO 2512 can coordinate, authorize, release, and occupy resources of the NFVI 2504 in order to provide the requested service (e.g., to execute an EPC function, component, or slice). In at least one embodiment, the NM 2514 can provide an end-user function package responsible for managing the network, which can include network elements with VNFs, non-virtualized network functions, or both (management of the VNFs can occur via the EM 2510).

[0283] Computer-based systems

[0284] The following figures set forth, but are not limiting of, exemplary computer-based systems that can be used to implement at least one embodiment.

[0285] Figure 26 A processing system 2600 is shown in accordance with at least one embodiment. In at least one embodiment, system 2600 includes one or more processors 2602 and one or more graphics processors 2608, and can be a single-processor desktop system, a multi-processor workstation system, or a server system having a large number of processors 2602 or processor cores 2607. In at least one embodiment, processing system 2600 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0286] In at least one embodiment, the processing system 2600 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console, including a gaming and media console. In at least one embodiment, the processing system 2600 is a mobile phone, a smart phone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2600 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2600 is a television or set-top box device having one or more processors 2602 and a graphical interface generated by one or more graphics processors 2608.

[0287] In at least one embodiment, one or more processors 2602 each include one or more processor cores 2607 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2607 is configured to process a specific instruction set 2609. In at least one embodiment, the instruction set 2609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). In at least one embodiment, multiple processor cores 2607 can each process a different instruction set 2609, which can include instructions that facilitate emulating other instruction sets. In at least one embodiment, the processor cores 2607 can also include other processing devices, such as a digital signal processor (DSP).

[0288] In at least one embodiment, the processor 2602 includes a cache memory (cache) 2604. In at least one embodiment, the processor 2602 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2602. In at least one embodiment, the processor 2602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can share this logic among the processor cores 2607 using known cache coherence techniques. In at least one embodiment, the processor 2602 further includes a register file 2606. The processor 2602 may include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2606 may include general purpose registers or other registers.

[0289] In at least one embodiment, one or more processors 2602 are coupled to one or more interface buses 2610 to transmit communication signals, such as address, data, or control signals, between the processors 2602 and other components in the system 2600. In at least one embodiment, the interface bus 2610 can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface bus 2610 is not limited to a DMI bus and can include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2602 includes an integrated memory controller 2616 and a platform controller hub 2630. In at least one embodiment, the memory controller 2616 facilitates communication between storage devices and other components of the processing system 2600, while the platform controller hub (PCH) 2630 provides connections to input / output (I / O) devices via a local I / O bus.

[0290] In at least one embodiment, the memory device 2620 can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or a device having suitable performance for use as processor memory. In at least one embodiment, the memory device 2620 can be used as system memory for the processing system 2600 to store data 2622 and instructions 2621 for use when one or more processors 2602 execute applications or processes. In at least one embodiment, the memory controller 2616 is also coupled to an optional external graphics processor 2612, which can communicate with one or more graphics processors 2608 in the processor 2602 to perform graphics and media operations. In at least one embodiment, a display device 2611 can be connected to the processor 2602. In at least one embodiment, the display device 2611 can include one or more internal display devices, such as in a mobile electronic device or portable computer device, or an external display device connected via a display interface (such as a DisplayPort). In at least one embodiment, the display device 2611 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0291] In at least one embodiment, the platform controller hub 2630 enables peripheral devices to connect to the storage device 2620 and the processor 2602 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2646, a network controller 2634, a firmware interface 2628, a wireless transceiver 2626, a touch sensor 2625, and a data storage device 2624 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2624 can be connected via a memory interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2625 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2626 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2628 enables communication with the system firmware and, in at least one embodiment, can be a unified extensible firmware interface (UEFI). In at least one embodiment, a network controller 2634 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2610. In at least one embodiment, the audio controller 2646 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2600 includes an optional legacy I / O controller 2640 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the processing system 2600. In at least one embodiment, the platform controller hub 2630 can also be connected to one or more universal serial bus (USB) controllers 2642 that connect input devices such as a keyboard and mouse 2643 combination, a camera 2644, or other USB input devices.

[0292] In at least one embodiment, instances of the memory controller 2616 and the platform controller hub 2630 may be integrated into a discrete external graphics processor, such as the external graphics processor 2612. In at least one embodiment, the platform controller hub 2630 and / or the memory controller 2616 may be external to one or more processors 2602. In at least one embodiment, the processing system 2600 may include the external memory controller 2616 and the platform controller hub 2630, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2602.

[0293] Figure 27A computer system 2700 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 2700 can be a system of interconnected devices and components, a SOC, or some combination thereof. In at least one embodiment, the computer system 2700 is formed by a processor 2702, which can include an execution unit for executing instructions. In at least one embodiment, the computer system 2700 can include, but is not limited to, components such as the processor 2702, which employs an execution unit including logic to execute algorithms for processing data. In at least one embodiment, the computer system 2700 can include a processor such as the Intel® processor available from Intel Corporation of Santa Clara, California. Processor family, XeonTM, XScaleTM and / or StrongARMTM, Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, the computer system 2700 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux in at least one embodiment), embedded software, and / or graphical user interfaces may also be used.

[0294] In at least one embodiment, the computer system 2700 can be used in other devices, such as handheld devices and embedded applications. Some of at least one embodiment of a handheld device include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application can include a microcontroller, a digital signal processor ("DSP"), a SoC, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0295] In at least one embodiment, computer system 2700 may include, but is not limited to, a processor 2702, which may include, but is not limited to, one or more execution units 2708, which may be configured to execute Compute Unified Device Architecture ("CUDA") ( Developed by NVIDIA Corporation of Santa Clara, California) program. In at least one embodiment, a CUDA program is at least a portion of a software application written in the CUDA programming language. In at least one embodiment, computer system 2700 is a single-processor desktop or server system. In at least one embodiment, computer system 2700 may be a multi-processor system. In at least one embodiment, processor 2702 may include, but is not limited to, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor in at least one embodiment. In at least one embodiment, processor 2702 may be coupled to a processor bus 2710 that may transmit data signals between processor 2702 and other components in computer system 2700.

[0296] In at least one embodiment, the processor 2702 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 2704. In at least one embodiment, the processor 2702 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to the processor 2702. In at least one embodiment, the processor 2702 may include a combination of internal and external caches. In at least one embodiment, the register file 2706 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0297] In at least one embodiment, an execution unit 2708, including but not limited to logic for performing integer and floating-point operations, is also located in the processor 2702. The processor 2702 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 2708 may include logic for processing a packed instruction set 2709. In at least one embodiment, by including the packed instruction set 2709 in the instruction set of the general-purpose processor 2702, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data in the general-purpose processor 2702. In at least one embodiment, many multimedia applications may be executed faster and more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations on one data element at a time.

[0298] In at least one embodiment, execution unit 2708 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 2700 may include, but is not limited to, memory 2720. In at least one embodiment, memory 2720 may be implemented as a DRAM device, an SRAM device, a flash memory device, or other storage device. Memory 2720 may store instructions 2719 and / or data 2721 represented by data signals that may be executed by processor 2702.

[0299] In at least one embodiment, the system logic chip can be coupled to the processor bus 2710 and the memory 2720. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 2716, and the processor 2702 can communicate with the MCH 2716 via the processor bus 2710. In at least one embodiment, the MCH 2716 can provide a high-bandwidth memory path 2718 to the memory 2720 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 2716 can initiate data signals between the processor 2702, the memory 2720, and other components in the computer system 2700, and bridge data signals between the processor bus 2710, the memory 2720, and the system I / O 2722. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 2716 may be coupled to the memory 2720 via a high-bandwidth memory path 2718 , and the graphics / video card 2712 may be coupled to the MCH 2716 via an Accelerated Graphics Port (“AGP”) interconnect 2714 .

[0300] In at least one embodiment, the computer system 2700 may use the system I / O 2722 as a proprietary hub interface bus to couple the MCH 2716 to the I / O controller hub ("ICH") 2730. In at least one embodiment, the ICH 2730 may provide direct connectivity to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus used to connect peripheral devices to the memory 2720, chipset, and processor 2702. Examples may include, but are not limited to, an audio controller 2729, a firmware hub ("Flash BIOS") 2728, a wireless transceiver 2726, a data store 2724, a traditional I / O controller 2723 including user input 2725 and a keyboard interface, a serial expansion port 2777 (e.g., USB), and a network controller 2734. The data store 2724 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0301] In at least one embodiment, Figure 27 A system comprising interconnected hardware devices or "chips" is shown. In at least one embodiment, Figure 27 An exemplary SoC may be shown. In at least one embodiment, Figure 27 The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of system 2700 are interconnected using a Compute Express Link (CXL) interconnect.

[0302] Figure 28 A system 2800 is shown in accordance with at least one embodiment. In at least one embodiment, the system 2800 is an electronic device that utilizes a processor 2810. In at least one embodiment, the system 2800 can be, in at least one embodiment but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0303] In at least one embodiment, the system 2800 may include, but is not limited to, a processor 2810 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, the processor 2810 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a USB (versions 1, 2, 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 28 A system is shown that includes interconnected hardware devices or "chips". In at least one embodiment, Figure 28 An exemplary SoC may be shown. In at least one embodiment, Figure 28 The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 28 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0304] In at least one embodiment, Figure 28 The system may include a display 2824, a touch screen 2825, a touchpad 2830, a near field communication unit ("NFC") 2845, a sensor hub 2840, a thermal sensor 2846, an express chipset ("EC") 2835, a trusted platform module ("TPM") 2838, a BIOS / firmware / flash memory ("BIOS, FW Flash") 2822, a DSP 2860, a solid-state disk ("SSD") or a hard disk drive ("HDD") 2820, a wireless local area network unit ("WLAN") 2850, a Bluetooth unit 2852, a wireless wide area network unit ("WWAN") 2856, a global positioning system (GPS) 2855, a camera ("USB 3.0 camera") 2854 (e.g., a USB 3.0 camera), or a low-power double data rate ("LPDDR") memory unit ("LPDDR3") 2815 implemented in at least one embodiment of the LPDDR3 standard. Each of these components may be implemented in any suitable manner.

[0305] In at least one embodiment, other components may be communicatively coupled to processor 2810 via the components discussed above. In at least one embodiment, an accelerometer 2841, an ambient light sensor (“ALS”) 2842, a compass 2843, and a gyroscope 2844 may be communicatively coupled to sensor hub 2840. In at least one embodiment, a thermal sensor 2839, a fan 2837, a keyboard 2846, and a touchpad 2830 may be communicatively coupled to EC 2835. In at least one embodiment, a speaker 2863, an earpiece 2864, and a microphone (“mic”) 2865 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 2864, which in turn may be communicatively coupled to DSP 2860. In at least one embodiment, audio unit 2864 may include, but is not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a SIM card (“SIM”) 2857 may be communicatively coupled to WWAN unit 2856. In at least one embodiment, components such as the WLAN unit 2850 and the Bluetooth unit 2852 and the WWAN unit 2856 may be implemented as a next generation form factor (NGFF).

[0306] Figure 29 An exemplary integrated circuit 2900 according to at least one embodiment is shown. In at least one embodiment, exemplary integrated circuit 2900 is a SoC, which can be manufactured using one or more IP cores. In at least one embodiment, integrated circuit 2900 includes one or more application processors 2905 (e.g., CPUs), at least one graphics processor 2910, and may additionally include an image processor 2915 and / or a video processor 2920, any of which may be modular IP cores. In at least one embodiment, integrated circuit 2900 includes peripheral or bus logic, including a USB controller 2925, a UART controller 2930, an SPI / SDIO controller 2935, and an I2S / I2C controller 2940. In at least one embodiment, integrated circuit 2900 may include a display device 2945 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 2950 and a Mobile Industry Processor Interface (MIPI) display interface 2955. In at least one embodiment, storage may be provided by a flash memory subsystem 2960, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 2965 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 2970 .

[0307] Figure 30A computing system 3000 is shown in accordance with at least one embodiment. In at least one embodiment, computing system 3000 includes a processing subsystem 3001 having one or more processors 3002 and system memory 3004 communicating via an interconnect path that may include a memory hub 3005. In at least one embodiment, memory hub 3005 may be a separate component within a chipset assembly or integrated within one or more processors 3002. In at least one embodiment, memory hub 3005 is coupled to an I / O subsystem 3011 via a communication link 3006. In at least one embodiment, I / O subsystem 3011 includes an I / O hub 3007, which enables computing system 3000 to receive input from one or more input devices 3008. In at least one embodiment, I / O hub 3007 may enable a display controller, included in one or more processors 3002, to provide output to one or more display devices 3010A. In at least one embodiment, the one or more display devices 3010A coupled to the I / O hub 3007 may include local, internal, or embedded display devices.

[0308] In at least one embodiment, the processing subsystem 3001 includes one or more parallel processors 3012 coupled to a memory hub 3005 via a bus or other communication link 3013. In at least one embodiment, the communication link 3013 can be one of many standard-based communication link technologies or protocols, such as, but not limited to, PCIe, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 3012 form a computationally focused parallel or vector processing system that can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 3012 form a graphics processing subsystem that can output pixels to one of one or more display devices 3010A coupled via an I / O hub 3007. In at least one embodiment, the one or more parallel processors 3012 can also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 3010B.

[0309] In at least one embodiment, a system storage unit 3014 can be connected to the I / O hub 3007 to provide a storage mechanism for the computing system 3000. In at least one embodiment, an I / O switch 3016 can be used to provide an interface mechanism to enable connections between the I / O hub 3007 and other components, such as a network adapter 3018 and / or a wireless network adapter 3019 that can be integrated into the platform, as well as various other devices that can be added via one or more add-on devices 3020. In at least one embodiment, the network adapter 3018 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 3019 can include one or more of Wi-Fi, Bluetooth, NFC, or other network devices including one or more radios.

[0310] In at least one embodiment, computing system 3000 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and / or variations thereof, which may also be connected to I / O hub 3007. Figure 30 The communication paths that interconnect the various components in the system can be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocols (e.g., NVLink high-speed interconnect or interconnect protocol).

[0311] In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for graphics and video processing (including video output circuitry in at least one embodiment) and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 3012 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computing system 3000 can be integrated with one or more other system elements on a single integrated circuit. In at least one embodiment, one or more parallel processors 3012, memory hub 3005, processor 3002, and I / O hub 3007 can be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computing system 3000 can be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computing system 3000 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 3011 and display device 3010B are omitted from computing system 3000.

[0312] Processing system

[0313] The following figures illustrate, but are not limited to, exemplary processing systems that can be used to implement at least one embodiment.

[0314] Figure 31 An accelerated processing unit ("APU") 3100 is shown in accordance with at least one embodiment. In at least one embodiment, the APU 3100 was developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the APU 3100 can be configured to execute applications, such as CUDA programs. In at least one embodiment, the APU 3100 includes, but is not limited to, a core complex 3110, a graphics complex 3140, a fabric 3160, an I / O interface 3170, a memory controller 3180, a display controller 3192, and a multimedia engine 3194. In at least one embodiment, the APU 3100 can include, but is not limited to, any combination of any number of core complexes 3110, any number of graphics complexes 3140, any number of display controllers 3192, and any number of multimedia engines 3194. For purposes of illustration, multiple instances of similar objects are referred to herein by reference numerals, where the reference numeral identifies the object and a number in parentheses identifies the desired instance.

[0315] In at least one embodiment, core complex 3110 is a CPU, graphics complex 3140 is a GPU, and APU 3100 is a processing unit that is not limited to integrating 3110 and 3140 onto a single chip. In at least one embodiment, some tasks may be assigned to core complex 3110, while other tasks may be assigned to graphics complex 3140. In at least one embodiment, core complex 3110 is configured to execute primary control software associated with APU 3100, such as an operating system. In at least one embodiment, core complex 3110 is the main processor of APU 3100, controlling and coordinating the operations of the other processors. In at least one embodiment, core complex 3110 issues commands that control the operations of graphics complex 3140. In at least one embodiment, core complex 3110 may be configured to execute host executable code derived from CUDA source code, and graphics complex 3140 may be configured to execute device executable code derived from CUDA source code.

[0316] In at least one embodiment, core complex 3110 includes, but is not limited to, cores 3120(1)-3120(4) and L3 cache 3130. In at least one embodiment, core complex 3110 may include, but is not limited to, any number of cores 3120 and any combination of any number and type of caches. In at least one embodiment, cores 3120 are configured to execute instructions of a particular instruction set architecture ("ISA"). In at least one embodiment, each core 3120 is a CPU core.

[0317] In at least one embodiment, each core 3120 includes, but is not limited to, a fetch / decode unit 3122, an integer execution engine 3124, a floating-point execution engine 3126, and an L2 cache 3128. In at least one embodiment, the fetch / decode unit 3122 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 3124 and the floating-point execution engine 3126. In at least one embodiment, the fetch / decode unit 3122 can simultaneously dispatch one micro-op to the integer execution engine 3124 and another micro-op to the floating-point execution engine 3126. In at least one embodiment, the integer execution engine 3124 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 3126 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3122 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 3124 and the floating-point execution engine 3126.

[0318] In at least one embodiment, each core 3120(i) can access an L2 cache 3128(i) included in the core 3120(i), where i is an integer representing a specific instance of the core 3120. In at least one embodiment, each core 3120 included in a core complex 3110(j) is connected to the other cores 3120 included in the core complex 3110(j) via an L3 cache 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, a core 3120 included in a core complex 3110(j) can access all L3 caches 3130(j) included in the core complex 3110(j), where j is an integer representing a specific instance of the core complex 3110. In at least one embodiment, the L3 cache 3130 can include, but is not limited to, any number of slices.

[0319] In at least one embodiment, graphics complex 3140 can be configured to perform computational operations in a highly parallel manner. In at least one embodiment, graphics complex 3140 is configured to perform graphics pipeline operations, such as draw commands, pixel operations, geometry calculations, and other operations associated with rendering an image to a display. In at least one embodiment, graphics complex 3140 is configured to perform operations that are not graphics-related. In at least one embodiment, graphics complex 3140 is configured to perform both graphics-related operations and graphics-independent operations.

[0320] In at least one embodiment, graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and L2 cache 3142. In at least one embodiment, compute units 3150 share L2 cache 3142. In at least one embodiment, L2 cache 3142 is partitioned. In at least one embodiment, graphics complex 3140 includes, but is not limited to, any number of compute units 3150 and any number (including zero) and type of cache. In at least one embodiment, graphics complex 3140 includes, but is not limited to, any amount of dedicated graphics hardware.

[0321] In at least one embodiment, each compute unit 3150 includes, but is not limited to, any number of SIMD units 3152 and shared memory 3154. In at least one embodiment, each SIMD unit 3152 implements a SIMD architecture and is configured to execute operations in parallel. In at least one embodiment, each compute unit 3150 can execute any number of thread blocks, but each thread block executes on a single compute unit 3150. In at least one embodiment, a thread block includes, but is not limited to, any number of execution threads. In at least one embodiment, a workgroup is a thread block. In at least one embodiment, each SIMD unit 3152 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process different data sets based on a single instruction set. In at least one embodiment, predication can be used to disable one or more threads in a warp. In at least one embodiment, a channel is a thread. In at least one embodiment, a work item is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block can be synchronized and communicated via shared memory 3154.

[0322] In at least one embodiment, fabric 3160 is a system interconnect that facilitates data and control transfers across core complex 3110, graphics complex 3140, I / O interface 3170, memory controller 3180, display controller 3192, and multimedia engine 3194. In at least one embodiment, APU 3100 may include, in addition to or in lieu of fabric 3160, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to APU 3100. In at least one embodiment, I / O interface 3170 represents any number and type of I / O interfaces (e.g., PCI, PCI-Extended ("PCI-X"), PCIe, Gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripheral devices are coupled to I / O interface 3170. In at least one embodiment, peripheral devices coupled to I / O interface 3170 may include, but are not limited to, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, etc.

[0323] In at least one embodiment, display controller AMD92 displays images on one or more display devices, such as liquid crystal display (LCD) devices. In at least one embodiment, multimedia engine 240 includes, but is not limited to, any number and type of multimedia-related circuits, such as video decoders, video encoders, image signal processors, and the like. In at least one embodiment, memory controller 3180 facilitates data transfer between APU 3100 and unified system memory 3190. In at least one embodiment, core complex 3110 and graphics complex 3140 share unified system memory 3190.

[0324] In at least one embodiment, the APU 3100 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3180 and memory devices (e.g., shared memory 3154) that can be dedicated to a component or shared among multiple components. In at least one embodiment, the APU 3100 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 2728, L3 cache 3130, and L2 cache 3142), each of which can be private to a component or shared among any number of components (e.g., core 3120, core complex 3110, SIMD unit 3152, compute unit 3150, and graphics complex 3140).

[0325] Figure 32A CPU 3200 is shown according to at least one embodiment. In at least one embodiment, the CPU 3200 is developed by Advanced Micro Devices, Inc. of Santa Clara, California. In at least one embodiment, the CPU 3200 can be configured to execute application programs. In at least one embodiment, the CPU 3200 is configured to execute host control software, such as an operating system. In at least one embodiment, the CPU 3200 issues commands to control the operation of an external GPU (not shown). In at least one embodiment, the CPU 3200 can be configured to execute host executable code derived from CUDA source code, and the external GPU can be configured to execute device executable code derived from such CUDA source code. In at least one embodiment, the CPU 3200 includes, but is not limited to, any number of core complexes 3210, fabric 3260, I / O interfaces 3270, and memory controller 3280.

[0326] In at least one embodiment, core complex 3210 includes, but is not limited to, cores 3220(1)-3220(4) and L3 cache 3230. In at least one embodiment, core complex 3210 may include, but is not limited to, any number of cores 3220 and any combination of any number and type of caches. In at least one embodiment, cores 3220 are configured to execute instructions of a specific ISA. In at least one embodiment, each core 3220 is a CPU core.

[0327] In at least one embodiment, each core 3220 includes, but is not limited to, a fetch / decode unit 3222, an integer execution engine 3224, a floating-point execution engine 3226, and an L2 cache 3228. In at least one embodiment, the fetch / decode unit 3222 fetches instructions, decodes these instructions, generates micro-ops, and dispatches individual micro-ops to the integer execution engine 3224 and the floating-point execution engine 3226. In at least one embodiment, the fetch / decode unit 3222 can simultaneously dispatch one micro-op to the integer execution engine 3224 and another micro-op to the floating-point execution engine 3226. In at least one embodiment, the integer execution engine 3224 performs, but is not limited to, integer and memory operations. In at least one embodiment, the floating-point engine 3226 performs, but is not limited to, floating-point and vector operations. In at least one embodiment, the fetch-decode unit 3222 dispatches micro-ops to a single execution engine that replaces both the integer execution engine 3224 and the floating-point execution engine 3226.

[0328] In at least one embodiment, each core 3220(i) can access an L2 cache 3228(i) included in the core 3220(i), where i is an integer representing a specific instance of the core 3220. In at least one embodiment, each core 3220 included in a core complex 3210(j) is connected to the other cores 3220 in the core complex 3210(j) via an L3 cache 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, a core 3220 included in a core complex 3210(j) can access all L3 caches 3230(j) included in the core complex 3210(j), where j is an integer representing a specific instance of the core complex 3210. In at least one embodiment, the L3 cache 3230 can include, but is not limited to, any number of slices.

[0329] In at least one embodiment, fabric 3260 is a system interconnect that facilitates data and control transfers across core complexes 3210(1)-3210(N) (where N is an integer greater than zero), I / O interface 3270, and memory controller 3280. In at least one embodiment, CPU 3200 may include, in addition to or in lieu of fabric 3260, but is not limited to, any number and type of system interconnects that facilitate data and control transfers across any number and type of directly or indirectly linked components that may be internal or external to CPU 3200. In at least one embodiment, I / O interface 3270 represents any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interface 3270. In at least one embodiment, peripherals coupled to I / O interface 3270 may include, but are not limited to, a display, a keyboard, a mouse, a printer, a scanner, a joystick or other type of game controller, a media recording device, an external storage device, a network interface card, and the like.

[0330] In at least one embodiment, memory controller 3280 facilitates data transfers between CPU 3200 and system memory 3290. In at least one embodiment, core complex 3210 and graphics complex 3240 share system memory 3290. In at least one embodiment, CPU 3200 implements a memory subsystem that includes, but is not limited to, any number and type of memory controllers 3280 and memory devices that can be dedicated to a component or shared among multiple components. In at least one embodiment, CPU 3200 implements a cache subsystem that includes, but is not limited to, one or more cache memories (e.g., L2 cache 3228 and L3 cache 3230), each of which can be private to a component or shared among any number of components (e.g., core 3220 and core complex 3210).

[0331] Figure 33 An exemplary accelerator integrated slice 3390 according to at least one embodiment is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit. In at least one embodiment, the accelerator integrated circuit provides cache management, memory access, environment management, and interrupt management services on behalf of multiple graphics processing engines in multiple graphics acceleration modules. The graphics processing engines may each include a separate GPU. Optionally, the graphics processing engines may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, the graphics processing engines may be individual GPUs integrated on a common package, line card, or chip.

[0332] The application effective address space 3382 within system memory 3314 stores a process element 3383. In one embodiment, a process element 3383 is stored in response to a GPU call 3381 from an application 3380 executing on processor 3307. The process element 3383 contains the processing state of the corresponding application 3380. The work descriptor (WD) 3384 contained in the process element 3383 can be a single job requested by the application or may contain a pointer to a job queue. In at least one embodiment, the WD 3384 is a pointer to a job request queue in the application effective address space 3382.

[0333] Graphics acceleration module 3346 and / or each graphics processing engine can be shared by all or part of the processes in the system.In at least one embodiment, an infrastructure for establishing a processing state and sending WD 3384 to graphics acceleration module 3346 to start a job in a virtualized environment can be included.

[0334] In at least one embodiment, a dedicated process programming model is implemented. In this model, a single process owns the graphics acceleration module 3346 or individual graphics processing engine. Because the graphics acceleration module 3346 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owning partition, and the operating system initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 3346 is allocated.

[0335] In operation, the WD fetch unit 3391 in the accelerator integrated slice 3390 fetches the next WD 3384, which includes an indication of work to be performed by one or more graphics processing engines of the graphics acceleration module 3346. Data from the WD 3384 can be stored in registers 3345 for use by the memory management unit (MMU) 3339, the interrupt management circuit 3347, and / or the context management circuit 3348, as shown. At least one embodiment of the MMU 3339 includes segment / page roaming circuitry for accessing segment / page tables 3386 within the OS virtual address space 3385. The interrupt management circuit 3347 can process interrupt events (INT) 3392 received from the graphics acceleration module 3346. When executing graph operations, the effective address 3393 generated by the graphics processing engine is converted into a real address by the MMU 3339.

[0336] In one embodiment, the same register set 3345 is replicated for each graphics processing engine and / or graphics acceleration module 3346 and can be initialized by the system hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 3390. Table 1 shows exemplary registers that can be initialized by the hypervisor.

[0337] Table 1 – Registers initialized by the hypervisor

[0338]

[0339]

[0340] Example registers that may be initialized by the operating system are shown in Table 2.

[0341] Table 2 – Registers initialized by the operating system

[0342] 1 Process and thread identifiers 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilization Record Pointer 4 Virtual Address (VA) Segment Table Pointer 5 Permission blocking 6 Job Descriptor

[0343] In one embodiment, each WD 3384 is specific to a particular graphics acceleration module 3346 and / or a particular graphics processing engine. It contains all the information the graphics processing engine needs to do its work or work, or it can be a pointer to a memory location where the application has set up a command queue for work to be done.

[0344] Figures 34A-34B An exemplary graphics processor according to at least one embodiment of the present disclosure is shown. In at least one embodiment, any exemplary graphics processor can be manufactured using one or more IP cores. In addition to the illustrated diagram, in at least one embodiment, other logic and circuitry can be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores. In at least one embodiment, the exemplary graphics processor is used within a SoC.

[0345] Figure 34A An exemplary graphics processor 3410 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 34B An additional exemplary graphics processor 3440 of a SoC integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 34A The graphics processor 3410 is a low power graphics processor core. In at least one embodiment, Figure 34B The graphics processor 3440 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 3410, 3440 can be Figure 5 A variant of the graphics processor 510.

[0346] In at least one embodiment, the graphics processor 3410 includes a vertex processor 3405 and one or more fragment processors 3415A-3415N (e.g., 3415A, 3415B, 3415C, 3415D through 3415N-1 and 3415N). In at least one embodiment, the graphics processor 3410 can execute different shader programs via separate logic, such that the vertex processor 3405 is optimized to perform operations for the vertex shader program, while one or more fragment processors 3415A-3415N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 3405 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the fragment processors 3415A-3415N use the primitives and vertex data generated by the vertex processor 3405 to generate a frame buffer for display on a display device. In at least one embodiment, the fragment processors 3415A-3415N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0347] In at least one embodiment, the graphics processor 3410 additionally includes one or more MMUs 3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B. In at least one embodiment, the one or more MMUs 3420A-3420B provide a mapping of virtual to physical addresses for the graphics processor 3410, including for the vertex processor 3405 and / or the fragment processors 3415A-3415N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in the one or more caches 3425A-3425B. In at least one embodiment, the one or more MMUs 3420A-3420B may synchronize with other MMUs within the system, including with Figure 5 One or more MMUs associated with one or more application processors 505, graphics processor 515, and / or video processor 520 enable each processor 505-520 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 3430A-3430B enable the graphics processor 3410 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0348] In at least one embodiment, graphics processor 3440 includes Figure 34A3420A-3420B, caches 3425A-3425B, and circuit interconnects 3430A-3430B of the graphics processor 3410. In at least one embodiment, the graphics processor 3440 includes one or more shader cores 3455A-3455N (e.g., 3455A, 3455B, 3455C, 3455D, 3455E, 3455F, through 3455N-1 and 3455N) that provide a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 3440 includes an inter-core task manager 3445 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 3455A-3455N and a tiling unit 3458 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize use of internal caches.

[0349] Figure 35A FIG35 shows a graphics core 3500 according to at least one embodiment. In at least one embodiment, the graphics core 3500 may include Figure 24 In at least one embodiment, the graphics core 3500 may be Figure 34B 3455N. In at least one embodiment, graphics core 3500 includes a shared instruction cache 3502, texture units 3518, and cache / shared memory 3520, which are common to execution resources within graphics core 3500. In at least one embodiment, graphics core 3500 may include multiple slices 3501A-3501N or partitions of each core, and a graphics processor may include multiple instances of graphics core 3500. Slices 3501A-3501N may include support logic including local instruction caches 3504A-3504N, thread schedulers 3506A-3506N, thread dispatchers 3508A-3508N, and a set of registers 3510A-3510N. In at least one embodiment, the slices 3501A-3501N may include a set of additional function units (AFUs) 3512A-3512N, floating point units (FPUs) 3514A-3514N, integer arithmetic logic units (ALUs) 3516A-3516N, address calculation units (ACUs) 3513A-3513N, double precision floating point units (DPFPUs) 3515A-3515N, and matrix processing units (MPUs) 3517A-3517N.

[0350] In one embodiment, the FPUs 3514A-3514N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while the DPFPUs 3515A-3515N can perform double-precision (64-bit) floating-point operations. In at least one embodiment, the ALUs 3516A-3516N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed-precision operations. In at least one embodiment, the MPUs 3517A-3517N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, the MPUs 3517A-3517N can perform various matrix operations to accelerate CUDA programs, including enabling support for accelerated general matrix-to-matrix multiplication (GEMM). In at least one embodiment, the AFUs 3512A-3512N can perform additional logical operations not supported by the floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.).

[0351] Figure 35B A general purpose graphics processing unit (GPGPU) 3530 is shown in at least one embodiment. In at least one embodiment, GPGPU 3530 is highly parallel and suitable for deployment on a multi-chip module. In at least one embodiment, GPGPU 3530 can be configured to enable highly parallel computational operations to be performed by an array of GPUs. In at least one embodiment, GPGPU 3530 can be directly linked to other instances of GPGPU 3530 to create a multi-GPU cluster to improve execution time for CUDA programs. In at least one embodiment, GPGPU 3530 includes a host interface 3532 to enable connection to a host processor. In at least one embodiment, host interface 3532 is a PCIe interface. In at least one embodiment, host interface 3532 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 3530 receives commands from the host processor and dispatches execution threads associated with those commands to a set of compute clusters 3536A-3536H using a global scheduler 3534. In at least one embodiment, compute clusters 3536A-3536H share cache memory 3538. In at least one embodiment, cache memory 3538 may serve as a higher level cache for cache memory within compute clusters 3536A-3536H.

[0352] In at least one embodiment, GPGPU 3530 includes memory 3544A-3544B coupled to a compute cluster 3536A-3536H via a set of memory controllers 3542A-3542B. In at least one embodiment, memory 3544A-3544B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0353] In at least one embodiment, computing clusters 3536A-3536H each include a set of graphics cores, such as Figure 35A The graphics core 3500, which may include multiple types of integer and floating-point logic units, can perform computational operations at various precisions, including computations suitable for use with CUDA programs. In at least one embodiment, at least a subset of the floating-point units in each compute cluster 3536A-3536H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0354] In at least one embodiment, multiple instances of GPGPU 3530 can be configured to operate as a compute cluster. In at least one embodiment, compute clusters 3536A-3536H can implement any technically feasible communication technology for synchronization and data exchange. In at least one embodiment, multiple instances of GPGPU 3530 communicate via host interface 3532. In at least one embodiment, GPGPU 3530 includes an I / O hub 3539 that couples GPGPU 3530 to a GPU link 3540, enabling direct connection to other instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 3530. In at least one embodiment, GPU link 3540 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 3530 are located in separate data processing systems and communicate via a network device accessible via host interface 3532. In at least one embodiment, GPU link 3540 may be configured to connect to a host processor, in addition to or in place of host interface 3532. In at least one embodiment, GPGPU 3530 may be configured to execute CUDA programs.

[0355] Figure 36AA parallel processor 3600 in accordance with at least one embodiment is shown. In at least one embodiment, the various components of the parallel processor 3600 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or an FPGA.

[0356] In at least one embodiment, parallel processor 3600 includes parallel processing unit 3602. In at least one embodiment, parallel processing unit 3602 includes an I / O unit 3604 that enables communication with other devices, including other instances of parallel processing unit 3602. In at least one embodiment, I / O unit 3604 can be directly connected to other devices. In at least one embodiment, I / O unit 3604 connects to other devices using a hub or switch interface (e.g., memory hub 605). In at least one embodiment, the connection between memory hub 605 and I / O unit 3604 forms a communication link. In at least one embodiment, I / O unit 3604 is connected to a host interface 3606 and a memory crossbar switch 3616, where host interface 3606 receives commands for performing processing operations and memory crossbar switch 3616 receives commands for performing memory operations.

[0357] In at least one embodiment, when host interface 3606 receives command buffers via I / O unit 3604, host interface 3606 can direct work operations to execute those commands to front end 3608. In at least one embodiment, front end 3608 is coupled to scheduler 3610, which is configured to dispatch commands or other work items to processing array 3612. In at least one embodiment, scheduler 3610 ensures that processing array 3612 is properly configured and in a valid state before dispatching tasks to processing array 3612. In at least one embodiment, scheduler 3610 is implemented by firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 3610 can be configured to perform complex scheduling and work dispatch operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 3612. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 3612 through one of multiple graphics processing doorbells. In at least one embodiment, the workload can then be automatically distributed across the processing array 3612 by scheduler 3610 logic within a microcontroller that includes scheduler 3610.

[0358] In at least one embodiment, processing array 3612 can include up to "N" processing clusters (e.g., cluster 3614A, cluster 3614B, through cluster 3614N). In at least one embodiment, each cluster 3614A-3614N of processing array 3612 can execute a large number of concurrent threads. In at least one embodiment, scheduler 3610 can allocate work to clusters 3614A-3614N of processing array 3612 using various scheduling and / or work distribution algorithms, which can vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling can be handled dynamically by scheduler 3610 or can be partially assisted by compiler logic during the compilation of program logic configured to be executed by processing array 3612. In at least one embodiment, different clusters 3614A-3614N of processing array 3612 can be assigned to process different types of programs or to perform different types of computations.

[0359] In at least one embodiment, processing array 3612 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing array 3612 can be configured to perform general-purpose parallel computing operations. In at least one embodiment, processing array 3612 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0360] In at least one embodiment, processing array 3612 is configured to perform parallel graphics processing operations. In at least one embodiment, processing array 3612 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing array 3612 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit 3602 may transfer data from system memory via I / O unit 3604 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 3622) during processing and then written back to system memory.

[0361] In at least one embodiment, when parallel processing unit 3602 is used to perform graph processing, scheduler 3610 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 3614A-3614N of processing array 3612. In at least one embodiment, portions of processing array 3612 can be configured to perform different types of processing. In at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 3614A-3614N can be stored in a buffer to allow the intermediate data to be transferred between clusters 3614A-3614N for further processing.

[0362] In at least one embodiment, the processing array 3612 can receive processing tasks to be executed via the scheduler 3610, which receives commands defining the processing tasks from the front end 3608. In at least one embodiment, the processing tasks can include an index of the data to be processed, which can include, for example, surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 3610 can be configured to obtain the index corresponding to the task, or can receive the index from the front end 3608. In at least one embodiment, the front end 3608 can be configured to ensure that the processing array 3612 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch buffer, push buffer, etc.).

[0363] In at least one embodiment, each of one or more instances of parallel processing unit 3602 can be coupled to parallel processor memory 3622. In at least one embodiment, parallel processor memory 3622 can be accessed via memory crossbar 3616, which can receive memory requests from processing array 3612 and I / O unit 3604. In at least one embodiment, memory crossbar 3616 can access parallel processor memory 3622 via memory interface 3618. In at least one embodiment, memory interface 3618 can include multiple partition units (e.g., partition unit 3620A, partition unit 3620B, through partition unit 3620N), which can each be coupled to a portion of parallel processor memory 3622 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 3620A-3620N are configured to be equal to the number of memory cells, such that the first partition unit 3620A has a corresponding first memory cell 3624A, the second partition unit 3620B has a corresponding memory cell 3624B, and the Nth partition unit 3620N has a corresponding Nth memory cell 3624N. In at least one embodiment, the number of partition units 3620A-3620N may not be equal to the number of memory devices.

[0364] In at least one embodiment, memory units 3624A-3624N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 3624A-3624N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 3624A-3624N, allowing partition units 3620A-3620N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 3622. In at least one embodiment, local instances of parallel processor memory 3622 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0365] In at least one embodiment, any of the clusters 3614A-3614N of the processing array 3612 can process data to be written to any memory unit 3624A-3624N within the parallel processor memory 3622. In at least one embodiment, the memory crossbar 3616 can be configured to transmit the output of each cluster 3614A-3614N to any partition unit 3620A-3620N or another cluster 3614A-3614N, which can perform other processing operations on the output. In at least one embodiment, each cluster 3614A-3614N can communicate with a memory interface 3618 via the memory crossbar 3616 to read from or write to various external storage devices. In at least one embodiment, memory crossbar switch 3616 has connections to memory interface 3618 for communicating with I / O unit 3604, as well as connections to local instances of parallel processor memory 3622, thereby enabling processing units within different processing clusters 3614A-3614N to communicate with system memory or other memory that is not local to parallel processing unit 3602. In at least one embodiment, memory crossbar switch 3616 may use virtual channels to separate traffic flows between clusters 3614A-3614N and partition units 3620A-3620N.

[0366] In at least one embodiment, multiple instances of parallel processing unit 3602 can be provided on a single plug-in card, or multiple plug-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 3602 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. In at least one embodiment, some instances of parallel processing unit 3602 can include higher precision floating point units relative to other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 3602 or parallel processor 3600 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0367] Figure 36B 3694 is shown in accordance with at least one embodiment. In at least one embodiment, processing cluster 3694 is included within a parallel processing unit. In at least one embodiment, processing cluster 3694 is Figure 36AIn at least one embodiment, processing cluster 3694 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster 3694.

[0368] In at least one embodiment, the operation of the processing cluster 3694 can be controlled by a pipeline manager 3632 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 3632 Figure 36A The scheduler 3610 receives instructions and manages the execution of these instructions by the graphics multiprocessor 3634 and / or the texture unit 3636. In at least one embodiment, the graphics multiprocessor 3634 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within the processing cluster 3694. In at least one embodiment, one or more instances of the graphics multiprocessor 3634 may be included within the processing cluster 3694. In at least one embodiment, the graphics multiprocessor 3634 may process data, and the data crossbar 3640 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 3632 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 3640.

[0369] In at least one embodiment, each graphics multiprocessor 3634 within a processing cluster 3694 may include the same set of function execution logic (e.g., arithmetic logic unit, load store unit (LSU), etc.). In at least one embodiment, the function execution logic may be configured in a pipelined manner, where new instructions may be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0370] In at least one embodiment, instructions transmitted to the processing cluster 3694 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within the graphics multiprocessor 3634. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within the graphics multiprocessor 3634. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop of the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within the graphics multiprocessor 3634. In at least one embodiment, when a thread group includes more threads than the number of processing engines within the graphics multiprocessor 3634, processing can be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on the graphics multiprocessor 3634.

[0371] In at least one embodiment, the graphics multiprocessor 3634 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 3634 can abandon the internal cache and use cache memory within the processing cluster 3694 (e.g., L1 cache 3648). In at least one embodiment, each graphics multiprocessor 3634 can also access a partition unit (e.g., Figure 36A L2 cache within partition units 3620A-3620N) of the graphics multiprocessor 3602 is shared across all processing clusters 3694 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 3634 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 3602 can be used as global memory. In at least one embodiment, processing cluster 3694 includes multiple instances of graphics multiprocessor 3634, which can share common instructions and data, which can be stored in L1 cache 3648.

[0372] In at least one embodiment, each processing cluster 3694 may include an MMU 3645 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 3645 may reside in Figure 36A3618. In at least one embodiment, the MMU 3645 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiles below) and optionally to cache line indices. In at least one embodiment, the MMU 3645 may include a translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 3634 or L1 cache 3648 or processing cluster 3694. In at least one embodiment, the physical addresses are processed to assign surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0373] In at least one embodiment, the processing clusters 3694 can be configured such that each graphics multiprocessor 3634 is coupled to a texture unit 3636 to perform texture mapping operations, which may involve, for example, determining texture sample locations, reading texture data, and filtering the texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 3634, and texture data is retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor 3634 outputs processed tasks to a data crossbar 3640 to provide the processed tasks to another processing cluster 3694 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 3616. In at least one embodiment, a pre-raster operations unit (preROP) 3642 is configured to receive data from the graphics multiprocessor 3634 and direct the data to a ROP unit, which can communicate with a partitioning unit (e.g., a partitioning unit) as described herein. Figure 36A In at least one embodiment, the PreROP 3642 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0374] Figure 36C A graphics multiprocessor 3696 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 3696 is Figure 36B36. In at least one embodiment, the graphics multiprocessor 3696 is coupled to the pipeline manager 3632 of the processing cluster 3694. In at least one embodiment, the graphics multiprocessor 3696 has an execution pipeline that includes, but is not limited to, an instruction cache 3652, an instruction unit 3654, an address mapping unit 3656, a register file 3658, one or more GPGPU cores 3662, and one or more LSUs 3666. The GPGPU cores 3662 and LSUs 3666 are coupled to cache memory 3672 and shared memory 3670 via a memory and cache interconnect 3668.

[0375] In at least one embodiment, the instruction cache 3652 receives a stream of instructions to be executed from the pipeline manager 3632. In at least one embodiment, the instructions are cached in the instruction cache 3652 and dispatched for execution by the instruction unit 3654. In one embodiment, the instruction unit 3654 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within the GPGPU core 3662. In at least one embodiment, the instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, the address mapping unit 3656 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by the LSU 3666.

[0376] In at least one embodiment, register file 3658 provides a set of registers for the functional units of graphics multiprocessor 3696. In at least one embodiment, register file 3658 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 3662, LSU 3666) connected to graphics multiprocessor 3696. In at least one embodiment, register file 3658 is divided between each functional unit such that a dedicated portion of register file 3658 is allocated to each functional unit. In at least one embodiment, register file 3658 is divided between the different thread groups being executed by graphics multiprocessor 3696.

[0377] In at least one embodiment, the GPGPU cores 3662 may each include an FPU and / or ALU for executing instructions of the graphics multiprocessor 3696. The GPGPU cores 3662 may be architecturally similar or the architectures may differ. In at least one embodiment, a first portion of the GPGPU core 3662 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-3608 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 3696 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores 3662 may also include fixed-function or special-function logic.

[0378] In at least one embodiment, the GPGPU core 3662 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 3662 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for a SIMT execution model can be executed by a single SIMD instruction. In at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0379] In at least one embodiment, the memory and cache interconnect 3668 is an interconnect network that connects each functional unit of the graphics multiprocessor 3696 to the register file 3658 and shared memory 3670. In at least one embodiment, the memory and cache interconnect 3668 is a crossbar interconnect that allows the LSU 3666 to implement load and store operations between the shared memory 3670 and the register file 3658. In at least one embodiment, the register file 3658 can operate at the same frequency as the GPGPU core 3662, resulting in very low latency for data transfers between the GPGPU core 3662 and the register file 3658. In at least one embodiment, the shared memory 3670 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 3696. In at least one embodiment, the cache memory 3672 can be used as a data cache to cache texture data communicated between the functional units and the texture unit 3636. In at least one embodiment, the shared memory 3670 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 3672, threads executing on GPGPU core 3662 may also programmatically store data in shared memory.

[0380] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in the WD. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0381] General Computing

[0382] The following figures illustrate, but are not limited to, exemplary software configurations for implementing at least one embodiment in general-purpose computing.

[0383] Figure 37A software stack for a programming platform according to at least one embodiment is shown. In at least one embodiment, a programming platform is a platform for utilizing hardware on a computing system to accelerate computing tasks. In at least one embodiment, a software developer can access the programming platform through libraries, compiler directives, and / or extensions to a programming language. In at least one embodiment, the programming platform can be, but is not limited to, CUDA, Radeon Open Compute Platform ("ROCm"), OpenCL (OpenCL developed by Khronos group), TM ), SYCL, or Intel One API.

[0384] In at least one embodiment, the programming platform's software stack 3700 provides an execution environment for applications 3701. In at least one embodiment, applications 3701 may include any computer software capable of being launched on the software stack 3700. In at least one embodiment, applications 3701 may include, but are not limited to, artificial intelligence ("AI") / machine learning ("ML") applications, high performance computing ("HPC") applications, virtual desktop infrastructure ("VDI"), or data center workloads.

[0385] In at least one embodiment, application 3701 and software stack 3700 run on hardware 3707. In at least one embodiment, hardware 3707 may include one or more GPUs, CPUs, FPGAs, AI engines, and / or other types of computing devices that support programming platforms. In at least one embodiment, for example, using CUDA, software stack 3700 may be vendor-specific and compatible only with devices from a specific vendor. In at least one embodiment, for example, using OpenCL, software stack 3700 can be used with devices from different vendors. In at least one embodiment, hardware 3707 includes a host connected to one or more devices that can be accessed via application programming interface (API) calls to perform computing tasks. In at least one embodiment, compared to the host within hardware 3707, which may include but is not limited to a CPU (but may also include computing devices) and their memory, the devices within hardware 3707 may include but are not limited to GPUs, FPGAs, AI engines, or other computing devices (but may also include a CPU) and their memory.

[0386] In at least one embodiment, the programming platform's software stack 3700 includes, but is not limited to, a plurality of libraries 3703, a runtime 3705, and device kernel drivers 3706. In at least one embodiment, each of the libraries 3703 may include data and programming code that can be used by a computer program and utilized during software development. In at least one embodiment, the libraries 3703 may include, but are not limited to, pre-written code and subroutines, classes, values, type specifications, configuration data, documentation, help data, and / or message templates. In at least one embodiment, the libraries 3703 include functions optimized for execution on one or more types of devices. In at least one embodiment, the libraries 3703 may include, but are not limited to, functions for performing mathematical, deep learning, and / or other types of operations on the devices. In at least one embodiment, the libraries 3803 are associated with corresponding APIs 3802, which may include one or more APIs that expose the functions implemented in the libraries 3803.

[0387] In at least one embodiment, application 3701 is written as source code that is compiled into executable code as follows in conjunction with Figure 42 3701. In at least one embodiment, the executable code of application 3701 can run at least in part on an execution environment provided by software stack 3700. In at least one embodiment, during the execution of application 3701, code that needs to run on the device (as opposed to the host) can be obtained. In this case, in at least one embodiment, runtime 3705 can be called to load and start the necessary code on the device. In at least one embodiment, runtime 3705 can include any technically feasible runtime system capable of supporting the execution of application 3701.

[0388] In at least one embodiment, runtime 3705 is implemented as one or more runtime libraries associated with a corresponding API (shown as API 3704). In at least one embodiment, one or more such runtime libraries may include, but are not limited to, functions for memory management, execution control, device management, error handling, and / or synchronization, among others. In at least one embodiment, memory management functions may include, but are not limited to, functions for allocating, deallocating, and copying device memory, and transferring data between host memory and device memory. In at least one embodiment, execution control functions may include, but are not limited to, functions for launching a function on the device (sometimes referred to as a "kernel" when the function is a global function callable from the host), and functions for setting property values ​​in buffers maintained by the runtime library for a given function to be executed on the device.

[0389] In at least one embodiment, the runtime library and corresponding API 3704 can be implemented in any technically feasible manner. In at least one embodiment, one (or any number of) APIs can expose a low-level set of functions for fine-grained control of a device, while another (or any number of) APIs can expose such a higher-level set of functions. In at least one embodiment, a high-level runtime API can be built on top of the low-level APIs. In at least one embodiment, one or more runtime APIs can be language-specific APIs layered on top of a language-independent runtime API.

[0390] In at least one embodiment, the device kernel driver 3706 is configured to facilitate communication with the underlying device. In at least one embodiment, the device kernel driver 3706 can provide APIs such as API 3704 and / or low-level functions that other software relies on. In at least one embodiment, the device kernel driver 3706 can be configured to compile intermediate representation ("IR") code into binary code at runtime. In at least one embodiment, for CUDA, the device kernel driver 3706 can compile non-hardware-specific parallel thread execution ("PTX") IR code into binary code for a specific target device at runtime (caching the compiled binary code), which is sometimes also referred to as "final" code. In at least one embodiment, doing so can allow the final code to run on a target device that may not have existed when the source code was originally compiled into PTX code. Alternatively, in at least one embodiment, the device source code can be compiled into binary code offline without the device kernel driver 3706 compiling the IR code at runtime.

[0391] Figure 38 According to at least one embodiment, Figure 37 3800. In at least one embodiment, the CUDA software stack 3800, on which the application 3801 can be launched, includes a CUDA library 3803, a CUDA runtime 3805, a CUDA driver 3807, and a device kernel driver 3808. In at least one embodiment, the CUDA software stack 3800 executes on hardware 3809, which may include a CUDA-enabled GPU developed by NVIDIA Corporation of Santa Clara, California.

[0392] In at least one embodiment, the application 3801, the CUDA runtime 3805, and the device kernel driver 3808 can perform similar functions as the application 3701, the runtime 3705, and the device kernel driver 3706, respectively. Figure 373806 . In at least one embodiment, the CUDA driver 3807 includes a library (libcuda.so) that implements the CUDA driver API 3806. In at least one embodiment, similar to the CUDA runtime API 3804 implemented by the CUDA runtime library (cudart), the CUDA driver API 3806 may expose, but is not limited to, functions for memory management, execution control, device management, error handling, synchronization, and / or graphics interoperability. In at least one embodiment, the CUDA driver API 3806 differs from the CUDA runtime API 3804 in that the CUDA runtime API 3804 simplifies device code management by providing implicit initialization, context (similar to process) management, and module (similar to dynamically loaded libraries) management. In contrast to the high-level CUDA runtime API 3804, in at least one embodiment, the CUDA driver API 3806 is a low-level API that provides finer-grained control over the device, particularly with respect to context and module loading. In at least one embodiment, the CUDA driver API 3806 may expose functions for context management that are not exposed by the CUDA runtime API 3804. In at least one embodiment, the CUDA driver API 3806 is also language-independent and supports, for example, OpenCL in addition to the CUDA runtime API 3804. Furthermore, in at least one embodiment, the development libraries, including the CUDA runtime 3805, can be considered separate from the driver components, including the user-mode CUDA driver 3807 and the kernel-mode device driver 3808 (sometimes also referred to as a "display" driver).

[0393] In at least one embodiment, the CUDA libraries 3803 may include, but are not limited to, mathematical libraries, deep learning libraries, parallel algorithm libraries, and / or signal / image / video processing libraries, which can be utilized by parallel computing applications (e.g., application 3801). In at least one embodiment, the CUDA libraries 3803 may include mathematical libraries, such as the cuBLAS library, which is an implementation of the Basic Linear Algebra Subroutines ("BLAS") for performing linear algebra operations; the cuFFT library for computing fast Fourier transforms ("FFTs"), and the cuRAND library for generating random numbers, among others. In at least one embodiment, the CUDA libraries 3803 may include deep learning libraries, such as the cuDNN library for primitives for deep neural networks and the TensorRT platform for high-performance deep learning inference, among others.

[0394] Figure 39 According to at least one embodiment, Figure 373909.

[0395] In at least one embodiment, application 3901 may execute a combination of the above Figure 37 In addition, in at least one embodiment, the language runtime 3903 and the system runtime 3905 can perform functions similar to those described above in conjunction with the application 3701. Figure 37 In at least one embodiment, the language runtime 3903 and the system runtime 3905 differ in that the system runtime 3905 is a language-agnostic runtime that implements the ROCr system runtime API 3904 and leverages the Heterogeneous System Architecture ("HAS") runtime API. In at least one embodiment, the HAS runtime API is a thin user-mode API that exposes interfaces for accessing and interacting with the AMD GPU, including functions for memory management, execution control of kernels dispatched by the architecture, error handling, system and agent information, and runtime initialization and shutdown. In at least one embodiment, compared to the system runtime 3905, the language runtime 3903 is an implementation of a language-specific runtime API 3902 layered on top of the ROCr system runtime API 3904. In at least one embodiment, the language runtime API may include, but is not limited to, a portable heterogeneous compute interface ("HIP") language runtime API, a heterogeneous compute compiler ("HCC") language runtime API, or an OpenCL API, among others. In particular, the HIP language is an extension of the C++ programming language with a functionally similar version of the CUDA mechanism, and in at least one embodiment, the HIP language runtime API includes a Figure 38 Similar functions to the CUDA runtime API 3804 are discussed, such as those used for memory management, execution control, device management, error handling, and synchronization.

[0396] In at least one embodiment, thunk (ROCt) 3907 is an interface that can be used to interact with the underlying ROCm driver 3908. In at least one embodiment, the ROCm driver 3908 is a ROCk driver, which is a combination of the AMDGPU driver and the HAS kernel driver (amdkfd). In at least one embodiment, the AMDGPU driver is a device kernel driver for GPUs developed by AMD that performs the above combined Figure 37 3706. In at least one embodiment, the HAS kernel driver is a driver that allows different types of processors to more efficiently share system resources via hardware features.

[0397] In at least one embodiment, various libraries (not shown) may be included in the ROCm software stack 3900 above the language runtime 3903 and provide Figure 38 The various libraries may include, but are not limited to, math, deep learning, and / or other libraries, such as a hipBLAS library that implements functions similar to CUDA cuBLAS, a rocFFT library similar to CUDA cuFFT for computing FFTs, and the like.

[0398] Figure 40 According to at least one embodiment, Figure 37 4001. In at least one embodiment, the OpenCL software stack 4000, on which the application 4001 can be launched, includes an OpenCL framework 4005, an OpenCL runtime 4006, and a driver 4007. In at least one embodiment, the OpenCL software stack 4000 executes on hardware 3809 that is not vendor-specific. In at least one embodiment, because devices developed by different vendors support OpenCL, specific OpenCL drivers may be required to interoperate with hardware from such vendors.

[0399] In at least one embodiment, the application 4001, the OpenCL runtime 4006, the device kernel driver 4007 and the hardware 4008 can each execute in conjunction with the above Figure 37 Similar functionality is discussed for application 3701, runtime 3705, device kernel driver 3706, and hardware 3707. In at least one embodiment, application 4001 also includes an OpenCL kernel 4002 having code to be executed on the device.

[0400] In at least one embodiment, OpenCL defines a "platform" that allows a host to control devices connected to the host. In at least one embodiment, the OpenCL framework provides a platform layer API and a runtime API, shown as platform API 4003 and runtime API 4005. In at least one embodiment, runtime API 4005 uses contexts to manage the execution of kernels on devices. In at least one embodiment, each identified device can be associated with a respective context, which runtime API 4005 can use to manage the device's command queue, program objects and kernel objects, shared memory objects, etc. In at least one embodiment, platform API 4003 exposes functions that allow device contexts to be used to select and initialize devices, submit work to devices via command queues, and enable data transfer to and from devices. In addition, in at least one embodiment, the OpenCL framework provides various built-in functions (not shown), including mathematical functions, relational functions, image processing functions, etc.

[0401] In at least one embodiment, a compiler 4004 is also included in the OpenCL framework 4005. In at least one embodiment, source code can be compiled offline before executing the application or compiled online during execution of the applica...

Claims

1. A data center cooling system, comprising: A backup cooling loop comprising a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path for continuously flowing a backup coolant along the fluid source loop from at least one cooling manifold to the liquid-to-liquid heat exchanger, the backup cooling loop being associated with at least one computing device and alternatingly providing cooling to the at least one computing device with an auxiliary cooling loop associated with the primary cooling loop and the cooling facility.

2. The data center cooling system of claim 1 , further comprising: At least one processor comprising one or more neural networks is configured to determine a failure of the primary cooling circuit and to cause the at least one flow controller to activate the backup cooling circuit.

3. The data center cooling system of claim 1 , further comprising: At least one cold plate has ports, wherein the ports are used to interface the at least one cold plate with the auxiliary cooling circuit and the backup cooling circuit, the backup cooling circuit being activated upon failure of the primary cooling circuit.

4. The data center cooling system of claim 1 , further comprising: The at least one cooling manifold of the fluid path is configured to support flow of backup coolant from the fluid source to a cold plate of the at least one computing device via the fluid path.

5. The data center cooling system of claim 1 , further comprising: a cold plate adapted to interface with the backup cooling circuit and the auxiliary cooling circuit, the at least one flow controller configured to prevent auxiliary coolant in the auxiliary cooling circuit supported by a coolant distribution unit (CDU) from reaching the cold plate and to allow the auxiliary coolant in the at least one cooling manifold to flow toward the fluid source and be circulated back to the cold plate as part of the backup cooling circuit.

6. The data center cooling system of claim 5, further comprising: The at least one flow controller is configured to prevent the auxiliary coolant from reaching the cold plate when a difference between an outlet temperature of the auxiliary coolant and an inlet temperature of the auxiliary coolant is within a threshold value, wherein the inlet temperature and the outlet temperature are associated with an inlet and an outlet of the auxiliary coolant relative to a CDU, the CDU being disposed between the primary cooling circuit and the auxiliary cooling circuit such that heat is extracted from the auxiliary cooling circuit to the primary cooling circuit, and a difference between the outlet temperature and the inlet temperature being within the threshold value indicates that the auxiliary coolant is not being adequately cooled by the primary cooling circuit.

7. The data center cooling system of claim 1 , further comprising: At least one processor is configured to determine that the operating auxiliary cooling loop cannot meet a threshold cooling demand of the at least one computing device and to cause the backup cooling loop to meet the threshold cooling demand.

8. The data center cooling system of claim 1 , further comprising: A refrigerant cooling system or a facility water cooling system external to the data center associated with the data center cooling system, the refrigerant cooling system or the facility water cooling system capable of cooling a liquid of the liquid-to-liquid heat exchanger for absorbing heat from the auxiliary coolant of the auxiliary cooling loop or from the backup coolant of the backup cooling loop.

9. A processor comprising one or more circuits for controlling one or more flow controllers of a backup cooling circuit, the backup cooling circuit comprising a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path for continuously flowing a backup coolant along a fluid source loop from at least one cooling manifold to the liquid-to-liquid heat exchanger, the backup cooling circuit being associated with at least one computing device and being enabled by the one or more circuits so that the backup cooling circuit alternates with an auxiliary cooling circuit to provide cooling to the at least one computing device, the auxiliary cooling circuit being associated with a primary cooling circuit and a cooling facility.

10. The processor of claim 9, further comprising: The auxiliary cooling circuit further includes an output for providing a signal to the one or more flow controllers, the one or more flow controllers being configured to divert the flow of auxiliary coolant in the auxiliary cooling loop from the rack manifold of the rack to the fluid source, the fluid source circulating the auxiliary coolant to the liquid-liquid heat exchanger, and the one or more flow controllers being configured to enable the flow of the auxiliary coolant from the fluid source back to the rack manifold or back to a different rack manifold used to cool the at least one computing device.

11. The processor of claim 9, further comprising: An input for receiving sensor input from a sensor associated with at least one rack, the processor for determining a change in coolant state based in part on the sensor input, and for controlling the one or more flow controllers to engage the auxiliary cooling circuit or the backup cooling circuit.

12. The processor of claim 11 , further comprising: One or more neural networks for receiving the sensor inputs and inferring changes in the coolant state.

13. The processor of claim 9, further comprising: An input is configured to receive sensor input from a sensor associated with at least one rack, the processor being configured to determine a change in coolant state based in part on a temperature of the auxiliary coolant in the auxiliary cooling circuit from the sensor input, the processor being configured to control the one or more flow controllers to enable the backup cooling circuit and disable the auxiliary cooling circuit.

14. A processor comprising one or more circuits for controlling one or more flow controllers of a backup cooling circuit, the backup cooling circuit comprising a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path for continuously flowing backup coolant along a fluid source loop from at least one cooling manifold to the liquid-to-liquid heat exchanger, the backup cooling circuit being associated with at least one computing device, the one or more circuits for using one or more neural networks to infer changes in coolant status of the at least one rack from sensor input associated with at least one rack, and the one or more circuits for causing the backup cooling circuit to alternately provide cooling to the at least one computing device with an auxiliary cooling circuit associated with a primary cooling circuit and a cooling facility.

15. The processor of claim 14, further comprising: The auxiliary cooling circuit further includes an output for providing a signal to the one or more flow controllers, the one or more flow controllers being configured to divert the flow of auxiliary coolant in the auxiliary cooling loop from the rack manifold of the rack to the fluid source, the fluid source circulating the auxiliary coolant to the liquid-liquid heat exchanger, and the one or more flow controllers being configured to enable the flow of the auxiliary coolant from the fluid source back to the rack manifold or back to a different rack manifold used to cool the at least one computing device.

16. The processor of claim 14, further comprising: An input is configured to receive the sensor input from a sensor associated with the at least one rack, the processor is configured to determine a change in coolant state based in part on the sensor input, and is configured to control the one or more flow controllers to engage the auxiliary cooling circuit or the backup cooling circuit.

17. The processor of claim 16, further comprising: The one or more neural networks are configured to receive the sensor inputs, infer a change in the coolant state, and incorporate the change as part of an analysis of previous sensor inputs and previous coolant states.

18. The processor of claim 14, further comprising: The one or more circuits are configured to receive the sensor input from a sensor associated with the at least one rack, the processor is configured to determine a change in the coolant state based in part on at least one temperature of the auxiliary coolant within the auxiliary cooling circuit from the sensor input, and the processor is configured to control the one or more flow controllers to enable the backup cooling circuit and disable the auxiliary cooling circuit.

19. A processor comprising one or more circuits associated with a controller of a backup cooling loop, the backup cooling loop comprising a fluid source, at least one flow controller, a liquid-to-liquid heat exchanger, and a fluid path for continuously flowing backup coolant along the fluid source loop from at least one cooling manifold to the liquid-to-liquid heat exchanger, the backup cooling loop being associated with at least one computing device, the one or more circuits configured to train one or more neural networks to infer changes in coolant state of at least one rack from sensor input associated with at least one rack, and the one or more circuits configured to cause the backup cooling loop to alternately provide cooling to the at least one computing device with an auxiliary cooling loop associated with a primary cooling loop and a cooling facility.

20. The processor of claim 19, further comprising: The auxiliary cooling circuit further includes an output for providing a signal to one or more flow controllers, the one or more flow controllers being configured to divert the flow of auxiliary coolant in the auxiliary cooling loop from a rack manifold of a rack to the fluid source, the fluid source circulating the auxiliary coolant to the liquid-liquid heat exchanger, and the one or more flow controllers being configured to enable the flow of the auxiliary coolant from the fluid source back to the rack manifold or back to a different rack manifold used to cool the at least one computing device.

21. The processor of claim 19, further comprising: An input is configured to receive the sensor input from a sensor associated with the at least one rack, the processor being configured to determine a change in coolant state based in part on the sensor input, and to control one or more flow controllers to engage the auxiliary cooling circuit or the backup cooling circuit.

22. The processor of claim 21 , further comprising: The one or more neural networks are trained to receive the sensor inputs, infer changes in the coolant state, and analyze the changes as part of an analysis of previous sensor inputs and previous coolant states.

23. The processor of claim 19, further comprising: The one or more circuits are configured to receive the sensor input from a sensor associated with the at least one rack and are configured to determine a change in the coolant state based in part on at least one temperature of the auxiliary coolant within the auxiliary cooling circuit from the sensor input, and the processor is configured to control one or more flow controllers to enable the backup cooling circuit and disable the auxiliary cooling circuit.

24. A method for a data center cooling system, the method comprising: providing a backup cooling circuit including a fluid source, at least one flow controller, a liquid-liquid heat exchanger, and a fluid path for continuously flowing a backup coolant along a fluid source circuit from at least one cooling manifold to the liquid-liquid heat exchanger; associating the backup cooling circuit with at least one computing device; and Cooling is provided to the at least one computing device from the backup cooling circuit instead of an auxiliary cooling circuit associated with the primary cooling circuit and the cooling facility.

25. The method according to claim 24, further comprising: implementing at least one processor including one or more neural networks; determining, by the one or more neural networks, a fault in the primary cooling circuit; as well as The at least one processor causes the at least one flow controller to activate the backup cooling circuit.

26. The method of claim 24, further comprising: providing at least one cold plate having ports for the auxiliary cooling circuit and the backup cooling circuit; as well as The backup cooling circuit is activated when a failure occurs in the primary cooling circuit.

27. The method of claim 24, further comprising: The at least one cooling manifold of the fluid path is enabled to support flow of backup coolant from the fluid source through the fluid path to a cold plate of the at least one computing device.

28. The method of claim 24, further comprising: associating the at least one flow controller with a cold plate applicable to the backup cooling circuit and the auxiliary cooling circuit; preventing, by the at least one flow controller, auxiliary coolant in the auxiliary cooling circuit supported by a coolant distribution unit (CDU) from reaching the cold plate; as well as The auxiliary coolant within the at least one cooling manifold is allowed to flow to the fluid source and circulated back to the cold plate as part of the backup cooling loop.

29. The method according to claim 28, further comprising: Auxiliary coolant is prevented from reaching the cold plate by at least one flow controller when a difference between an outlet temperature of the auxiliary coolant and an inlet temperature of the auxiliary coolant is within a threshold value, wherein the inlet temperature and the outlet temperature are associated with an inlet and an outlet of the auxiliary coolant relative to a CDU, the CDU being disposed between the primary cooling circuit and the auxiliary cooling circuit such that heat is extracted from the auxiliary cooling circuit to the primary cooling circuit, and the difference between the outlet temperature and the inlet temperature being within the threshold value indicates that the auxiliary coolant is not being adequately cooled by the primary cooling circuit.

30. The method of claim 24, further comprising: determining, by at least one processor, that the operating auxiliary cooling loop is unable to meet a threshold cooling demand of the at least one computing device; as well as The backup cooling circuit is caused to meet the threshold cooling demand.

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