Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a JFET region embedded in a first trench provided in one main surface of a device portion of a nitride semiconductor layer, a second trench provided in a peripheral voltage-withstanding portion of the nitride semiconductor layer, and one main surface of the nitride semiconductor layer. An inclination angle of a side surface of the first trench adjacent to a channel portion is smaller than an inclination angle of a side surface of the second trench.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In "Development of Normally-off MOSFET on Homoepitaxial GaN" (Japanese original: ホモエピGaN上ノーマリオフ型MOSFETの開発), Applied Physics, Vol. 86, No. 5, p. 376 (2017), a vertical semiconductor device is disclosed, which includes a nitride semiconductor layer, a source electrode provided on one main surface of the nitride semiconductor layer, and a drain electrode provided on the other main surface of the nitride semiconductor layer. The nitride semiconductor layer has an n-type drift region, an n-type JFET region provided on the drift region, and a p-type body region provided on the drift region and adjacent to the JFET region.

[0003] In such a vertical semiconductor device, as disclosed in International Publication No. 2016 / 104264, grooves are often provided in the peripheral breakdown voltage portion of the nitride semiconductor layer. If such grooves are provided, the electric field concentration near the pn junction interface between the n-type drift region and the p-type body region can be alleviated at the periphery of the element portion. Summary of the Invention

[0004] Technical Problem to be Solved by the Invention

[0005] In the case of manufacturing such a vertical semiconductor device, a p-type body region is epitaxially grown on the n-type drift region, and then, after dry etching a part of the body region, epitaxial growth is performed again to form an n-type JFET region. The reason for adopting such a manufacturing method is that when forming a p-type region in the nitride semiconductor layer, it is difficult to activate the p-type impurities introduced by ion implantation technology. Therefore, in such a semiconductor device, a technique capable of well embedding the JFET region in the groove formed by dry etching a part of the body region is required.

[0006] Moreover, in such a semiconductor device, a technique for further alleviating the electric field concentration near the pn junction interface between the n-type drift region and the p-type body region at the periphery of the element portion and further increasing the breakdown voltage is also required.

[0007] This application specification provides a technique that takes into account both the improvement of the embedding property of the JFET region and the improvement of the breakdown voltage.

[0008] Means for Solving the Technical Problem

[0009] The semiconductor device disclosed in the present specification can have a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer is divided into an element portion and a peripheral withstand voltage portion disposed around the element portion. The source electrode is disposed on one main surface of the nitride semiconductor layer. The drain electrode is disposed on the other main surface of the nitride semiconductor layer. The nitride semiconductor layer can have a drift region of a first conductivity type, a JFET region of the first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type. The drift region is disposed in the element portion and the peripheral withstand voltage portion. The JFET region is disposed in the element portion, disposed on the drift region, and buried in a first groove disposed on the one main surface. The body region is disposed in the element portion, disposed on the drift region, and contiguous to the JFET region. The source region is disposed in the element portion, separated from the JFET region by the body region. The insulating gate portion is disposed in the element portion, opposite to a channel portion of the body region separating the JFET region and the source region. In the peripheral withstand voltage portion of the nitride semiconductor layer, a second groove is disposed on the one main surface of the nitride semiconductor layer. The inclination angle of the side surface of the first groove in which the JFET region is buried is smaller than the inclination angle of the side surface of the second groove.

[0010] In the semiconductor device described above, the inclination angle of the side surface of the first groove in which the JFET region is buried is formed to be small. That is, the JFET region is formed in a tapered shape in which the front end is tapered along the depth direction of the nitride semiconductor layer. Therefore, when the JFET region is formed by epitaxial growth again in the first groove, the JFET region can be well buried in the first groove without forming a void or the like. On the other hand, in the semiconductor device described above, the inclination angle of the side surface of the second groove is formed to be large. If the inclination angle of the side surface of the second groove is large, the electric field concentration around the pn junction interface of the drift region and the body region at the periphery of the element portion is alleviated, and the withstand voltage is improved. In this way, in the semiconductor device described above, the improvement of the burying property of the JFET region and the improvement of the withstand voltage are both achieved.

[0011] The manufacturing method of a semiconductor device disclosed in the present specification can include the following steps: a step of preparing a nitride semiconductor layer, a step of forming a trench, a step of forming a JFET region, a step of forming a source region, and a step of forming an insulating gate portion. In the step of preparing the nitride semiconductor layer, a nitride semiconductor layer in which a drift region of a first conductivity type and a body region of a second conductivity type are stacked and the body region is exposed on one main surface is prepared. In the step of forming the trench, a trench reaching the drift region beyond the body region is formed from the one main surface of the nitride semiconductor layer by a dry etching technique. In the step of forming the trench, a first trench formed in a part of a device portion of the nitride semiconductor layer and a second trench formed in a peripheral withstand voltage portion of the nitride semiconductor layer are formed at the same time. In the step of forming the JFET region, a JFET region of the first conductivity type is formed so as to be buried in the first trench. In the step of forming the source region, a source region of the first conductivity type is formed which is separated from the JFET region by the body region. In the step of forming the insulating gate portion, an insulating gate portion is formed which opposes a channel portion of the body region separating the JFET region and the source region. In the step of forming the trench, the profile of a side surface of the first trench adjacent to the channel portion can be made parallel to an m-plane at the one main surface of the nitride semiconductor layer, the profile of a side surface of the second trench can be made parallel to an a-plane at the one main surface of the nitride semiconductor layer, and the first trench and the second trench can be formed at the same time. Alternatively, in the step of forming the trench, the profile of a side surface of the first trench adjacent to the channel portion can be made parallel to an a-plane at the one main surface of the nitride semiconductor layer, the profile of a side surface of the second trench can be made parallel to an m-plane at the one main surface of the nitride semiconductor layer, and the first trench and the second trench can be formed at the same time.

[0012] In the manufacturing method of a semiconductor device described above, the first trench for burying the JFET region and the second trench of the peripheral withstand voltage portion are formed at the same time. Further, the face orientation of a crystal plane used for forming the first trench is different from the face orientation of a crystal plane used for forming the second trench. Thus, even if the first trench and the second trench are formed at the same time, the inclination angles of the side surface of the first trench and the side surface of the second trench can be made different. Thus, the inclination angles of the side surface of the first trench and the side surface of the second trench can be adjusted according to the characteristics required for the semiconductor device with a small number of steps. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 A schematic cross-sectional view showing a main part of one embodiment of a semiconductor device.

[0014] Figure 2A schematic plan view of the main parts of one embodiment of a semiconductor device.

[0015] Figure 3 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0016] Figure 4 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0017] Figure 5 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0018] Figure 6 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0019] Figure 7 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0020] Figure 8 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0021] Figure 9 This schematic cross-sectional view shows the main parts of a semiconductor device manufacturing process.

[0022] Figure 10 A schematic cross-sectional view of the main parts of one embodiment of a modified semiconductor device. Summary of the Invention

[0024] Hereinafter, a semiconductor device employing the technology disclosed in this specification and a method for manufacturing the same will be described with reference to the accompanying drawings. Furthermore, to aid in understanding the technology disclosed in this specification, the embodiments shown below simplify the basic structure of the semiconductor device; please note that this may differ from the actual form of a semiconductor device.

[0025] Figure 1 The diagram shows a cross-sectional view of the main portion of semiconductor device 1. Semiconductor device 1 includes a nitride semiconductor layer 20 divided into a device portion 20A and a peripheral voltage-resistant portion 20B; a drain electrode 32 disposed to cover the back side of the nitride semiconductor layer 20; a source electrode 34 disposed to cover the surface of the nitride semiconductor layer 20; and an insulated gate portion 36 disposed on a portion of the surface of the nitride semiconductor layer 20. The peripheral voltage-resistant portion 20B is disposed around the device portion 20A, and when viewed in planar view, it is arranged to surround the device portion 20A. The nitride semiconductor layer 20 has n +n-type drain region 21, n-type drift region 22, n-type JFET region 23, p-type body region 24, and n + n-type source region 25.

[0026] The drain region 21 is provided in both the element portion 20A and the peripheral withstand voltage portion 20B, and is disposed at a position exposed on the back surface of the nitride semiconductor layer 20 in ohmic contact with the drain electrode 32. The drain region 21 is gallium nitride (GaN) containing n-type impurities. As will be described later, the drain region 21 is a base substrate for epitaxial growth of the drift region 22 and the body region 24, and is a GaN substrate with a c-plane surface.

[0027] The drift region 22 is provided in both the element portion 20A and the peripheral withstand voltage portion 20B, and is disposed on the surface of the drain region 21 and between the drain region 21 and the JFET region 23 and between the drain region 21 and the body region 24. The drift region 22 is gallium nitride (GaN) containing n-type impurities.

[0028] The JFET region 23 is provided in the element portion 20A, is disposed on the surface of the drift region 22, and has a form protruding from the surface of the drift region 22. The JFET region 23 is buried in the first trench TR1 provided on the surface of the nitride semiconductor layer 20, and has a form tapered to a front end along the thickness direction from the surface of the nitride semiconductor layer 20 toward the drift region 22. The JFET region 23 is gallium nitride (GaN) containing n-type impurities. In this example, the impurity concentration of the JFET region 23 is equal to the impurity concentration of the drift region 22.

[0029] The body region 24 is provided in the element portion 20A, is disposed on the surface of the drift region 22, and is disposed adjacent to the JFET region 23. The body region 24 is disposed at a position exposed on the surface of the nitride semiconductor layer 20 in ohmic contact with the source electrode 34. The body region 24 is gallium nitride (GaN) containing p-type impurities.

[0030] The source region 25 is provided in the element portion 20A, is disposed on the surface of the body region 24, and is separated from the JFET region 23 by the body region 24. The source region 25 is disposed at a position exposed on the surface of the nitride semiconductor layer 20 in ohmic contact with the source electrode 34. The source region 25 is gallium nitride (GaN) containing n-type impurities.

[0031] The insulating gate portion 36 is provided in the element portion 20A, is disposed on a portion of the surface of the nitride semiconductor layer 20, and has a gate insulating film 36a of silicon oxide and a gate electrode 36b of polycrystal silicon. The gate electrode 36b opposes the channel portion 24a of the body region 24 separating the JFET region 23 and the source region 25 and the JFET region 23 with the gate insulating film 36a interposed therebetween.

[0032] In the peripheral voltage withstand portion 20B of the nitride semiconductor layer 20, a second trench TR2 is provided on the surface of the nitride semiconductor layer 20. The second trench TR2 has a depth that extends from the surface of the nitride semiconductor layer 20 through the body region 24 to the drift region 22. Therefore, the pn junction interface between the drift region 22 and the body region 24 is exposed on the side of the second trench TR2. As a result, the electric field concentration near the pn junction interface between the drift region 22 and the body region 24 at the periphery of the device portion 20A is mitigated.

[0033] Figure 2 The diagram schematically shows a plan view of the main parts of semiconductor device 1. Additionally, Figure 2 The cross-sectional view corresponding to the I-I line is Figure 1 A cross-sectional view of the main parts. For example... Figure 2 As shown, the JFET region 23 has a shape extending along the y-direction when viewed in planar view of the nitride semiconductor layer 20. For example, in a practical semiconductor device, multiple JFET regions 23 extending along the y-direction are arranged in a strip-like configuration in the device section 20A. The source region 25 is arranged separately from the JFET region 23 in the x-direction. The channel portion 24a of the body region 24 is located between the source region 25 and the JFET region 23.

[0034] As described above, the JFET region 23 has a shape that extends along the y-direction when the nitride semiconductor layer 20 is viewed in a plane. Therefore, the first trench TR1 in which the JFET region 23 is buried has a side surface (also referred to as the short side surface) that extends along the y-direction when the nitride semiconductor layer 20 is viewed in a plane, and this side surface is adjacent to the channel portion 24a. In the semiconductor device 1, the outline 11 of the first trench TR1 adjacent to the channel portion 24a exposed on the surface of the nitride semiconductor layer 20 is set to be parallel to the m-plane. Furthermore, in the semiconductor device 1, the outline 12 of the side surface of the second trench TR2 provided in the peripheral withstand voltage portion 20B exposed on the surface of the nitride semiconductor layer 20 is set to be parallel to the a-plane. Therefore, the outline 12 of the second trench TR2 is hexagonal when the nitride semiconductor layer 20 is viewed in a plane. Thus, in the semiconductor device 1, different crystal plane orientations are used for the side surface of the first trench TR1 adjacent to the channel portion 24a and the side surface of the second trench TR2.

[0035] Next, the operation of semiconductor device 1 will be explained. In use, a positive voltage is applied to the drain electrode 32, and the source electrode 34 is grounded. If a positive voltage higher than the gate threshold voltage is applied to the gate electrode 36b, an inversion layer is formed in the channel portion 24a of the body region 24 that separates the JFET region 23 and the source region 25, and semiconductor device 1 is turned on. At this time, electrons flow from the source region 25 to the JFET region 23 via the inversion layer. The electrons flowing into the JFET region 23 flow longitudinally through the JFET region 23 and tend towards the drain electrode 32. Thus, the drain electrode 32 and the source electrode 34 are turned on. If the gate electrode 36b is grounded, the inversion layer disappears, and semiconductor device 1 is turned off.

[0036] like Figure 1 As shown, in semiconductor device 1, if the tilt angle of the side of the first trench TR1, in which the JFET region 23 is embedded, adjacent to the channel portion 24a is set as θ1, and the tilt angle of the side of the second trench TR2, which is disposed in the peripheral withstand voltage portion 20B, is set as θ2, then the relationship θ1 < θ2 holds. The tilt angle θ1 of the side of the first trench TR1 is in the range of 70 to 80°. The tilt angle θ2 of the side of the second trench TR2 is approximately 90°, in the range of 85 to 90°.

[0037] In semiconductor device 1, the tilt angle θ1 of the side of the first trench TR1 adjacent to the channel portion 24a is small, that is, the JFET region 23 is formed into a tapered shape that tapers at the front end along the depth direction of the nitride semiconductor layer 20. Therefore, as will be described later, when the JFET region 23 is formed by epitaxial growth again in the first trench TR1, the JFET region 23 can be well embedded in the first trench TR1 without forming voids or the like.

[0038] On the other hand, in semiconductor device 1, the tilt angle θ2 of the side of the second trench TR2 is formed to be relatively large. If the tilt angle θ2 of the side of the second trench T2 is relatively large, the electric field concentration near the pn junction interface between the drift region 22 and the bulk region 24 at the periphery of the element section 20A is mitigated, and the breakdown voltage is improved. In this way, both the improved embedding capability of the JFET region 23 and the improved breakdown voltage can be achieved in semiconductor device 1.

[0039] (Semiconductor device manufacturing method)

[0040] Next, the manufacturing method of semiconductor device 1 will be described. First, as follows... Figure 3 As shown, using epitaxial growth technology, an n-type GaN drift region 22 and a p-type GaN bulk region 24 are sequentially stacked from the surface of the drain region 21 of the GaN substrate to prepare a nitride semiconductor layer 20. Furthermore, in the nitride semiconductor layer 20, the predetermined formation ranges of the first trench TR1, the second trench TR2, and the source region 25 are indicated by dashed lines.

[0041] Next, as shown in FIG. 4, a mask 42 is patterned on the surface of the nitride semiconductor layer 20 by a photolithography technique. In the mask 42, an opening 42a is formed at a position corresponding to the first trench TRl, and an opening 42b is formed at a position corresponding to the second trench TR2. The side surface 111 of the mask 42, which delimits the opening 42a and which is adjacent to the channel region 24a, is parallel to the m-plane of the nitride semiconductor layer 20. Also, the side surface 112 of the mask 42, which delimits the opening 42b, is parallel to the a-plane of the nitride semiconductor layer 20. Figure 4

[0042] Next, as shown in FIG. 5, the first trench TRl and the second trench TR2 are formed by a dry etching technique so as to pass through the body region 24 from the surface of the nitride semiconductor layer 20 to the drift region 22. In this dry etching process, the side surfaces of the first trench TRl and the second trench TR2 are formed so as to have different inclination angles. The reason why the side surfaces are formed so as to have different inclination angles will be described later. Figure 5

[0043] The dry etching process is performed by an inductively coupled plasma reactive ion etching device (ICP-RIE device). As an example, the pressure is 1.0 Pa, the etching gas is SiCl4and Cl2, and the temperature of the stage is 180°C. In the ICP-RIE device, the antenna power for forming the plasma and the bias power for forming a potential difference between the plasma and the nitride semiconductor layer 20 can be independently controlled. If the antenna power is increased, the effect of isotropic etching tends to be stronger. If the bias power is increased, the effect of anisotropic etching tends to be stronger. Also, the strength of the tendency to become isotropic etching and anisotropic etching depends on the plane orientation of the crystal plane of the nitride semiconductor layer 20. Thus, in this dry etching process, by controlling the combination of the power ratio of the antenna power / bias power and the plane orientation of the crystal plane, the inclination angle of the side surfaces of the trenches TRl, TR2 formed can be adjusted.

[0044] In this dry etching process, it has been confirmed that if the side surface of the first trench TRl is the m-plane, the side surface of the second trench TR2 is the a-plane, and the power ratio of the antenna power / bias power is controlled to be in the range of 4.3 to 6.9, the side surface of the first trench TRl is processed to be inclined, and the side surface of the second trench TR2 is processed to be substantially perpendicular, resulting in a relationship in which the inclination angle of the side surface of the first trench TRl is smaller than the inclination angle of the side surface of the second trench TR2.

[0045] Next, as shown in FIG. 6, the first trench TRl and the second trench TR2 are formed by a dry etching technique so as to pass through the body region 24 from the surface of the nitride semiconductor layer 20 to the drift region 22. In this dry etching process, the side surfaces of the first trench TRl and the second trench TR2 are formed so as to have different inclination angles. The reason why the side surfaces are formed so as to have different inclination angles will be described later. Figure 6 ​​As shown, n-type GaN is epitaxially grown again within the first trench TR1 using epitaxial growth technology to form the JFET region 23. The first trench TR1 is formed into a tapered shape that tapers at the front end along the depth direction of the nitride semiconductor layer 20. Therefore, the JFET region 23 can be well embedded within the first trench TR1 without forming voids or the like.

[0046] Next, as Figure 7 As shown, the JFET region 23, which is formed on the surface of the bulk region 24, is removed using CMP (Chemical Mechanical Polishing) technology, thus exposing the surface of the bulk region 24.

[0047] Next, as Figure 8 As shown, using ion implantation technology, n-type impurities are introduced into a portion of the surface of bulk region 24 to form source region 25.

[0048] Next, as Figure 9 As shown, a gate insulating film 36a and a gate electrode 36b are locally formed on the surface of the nitride semiconductor layer 20, forming an insulating gate portion 36. Then, by forming films of the drain electrode 32 and the source electrode 34, the semiconductor device 1 is completed.

[0049] According to the manufacturing method described above, a first trench TR1 for burying the JFET region 23 and a second trench TR2 for the peripheral voltage withstand portion 20B are formed simultaneously. Furthermore, the crystal plane used to form the first trench TR1 has an m-plane orientation, and the crystal plane used to form the second trench TR2 has an a-plane orientation; their plane orientations are different. Therefore, even though the first trench TR1 and the second trench TR2 are formed simultaneously, the tilt angles of the side surfaces of the first trench TR1 and the second trench TR2 can be different. Thus, the tilt angles of the side surfaces of the first trench TR1 and the second trench TR2 can be adjusted according to the characteristics required by the semiconductor device 1 with fewer processing steps.

[0050] If the orientation of the crystal plane used to form the first groove TR1 is set as plane a, and the orientation of the crystal plane used to form the second groove TR2 is set as plane m, then it is possible to manufacture... Figure 10 The semiconductor device 2 shown is described. In this semiconductor device 2, since the tilt angle of the side surface of the first trench TR1 adjacent to the channel portion 24a is formed to be relatively large, the electric field concentration in the JFET region 23 is mitigated. On the other hand, since the tilt angle of the side surface of the second trench TR2 is formed to be relatively small, field plate electrodes and the like can be well formed on the side surface of the second trench TR2.

[0051] The following summarizes the technical features disclosed in this specification. In addition, the technical elements described below are independent technical elements, and each alone or in various combinations exhibits technical usefulness, and are not limited to the combinations recited in the claims at the time of filing.

[0052] The semiconductor device disclosed in this specification can have a nitride semiconductor layer, a source electrode, a drain electrode, and an insulating gate portion. The nitride semiconductor layer is divided into an element portion and a peripheral withstand voltage portion disposed around the element portion. The source electrode is disposed so as to cover one main surface of the nitride semiconductor layer. The drain electrode is disposed so as to cover the other main surface of the nitride semiconductor layer. The nitride semiconductor layer can have a drift region of a first conductivity type, a JFET region of the first conductivity type, a body region of a second conductivity type, and a source region of the first conductivity type. The drift region is disposed in the element portion and the peripheral withstand voltage portion. The JFET region is disposed in the element portion, is disposed on the drift region, and is buried in a first groove provided in the one main surface. The body region is disposed in the element portion, is disposed on the drift region, and is adjacent to the JFET region. The source region is disposed in the element portion, is separated from the JFET region by the body region. The insulating gate portion is disposed in the element portion, and opposes a channel portion of the body region that separates the JFET region and the source region. In the peripheral withstand voltage portion of the nitride semiconductor layer, a second groove is provided in the one main surface of the nitride semiconductor layer. The inclination angle of the side surface of the first groove adjacent to the channel portion is smaller than the inclination angle of the side surface of the second groove.

[0053] In the semiconductor device, the inclination angle of the side surface of the second groove can be substantially 90°. In this semiconductor device, the electric field concentration around the pn junction interface between the drift region and the body region is well relaxed, and the withstand voltage is improved.

[0054] In the semiconductor device, the profile of the side surface of the first groove adjacent to the channel portion, which is exposed at the one main surface of the nitride semiconductor layer, can be parallel with respect to the m-plane. Further, in the semiconductor device, the profile of the side surface of the second groove, which is exposed at the one main surface of the nitride semiconductor layer, can be parallel with respect to the a-plane. When the first groove and the second groove are formed at the same time, the inclination angle of the side surface of the first groove can be formed to be smaller, and the inclination angle of the side surface of the second groove can be formed to be larger.

[0055] In the semiconductor device, the pn junction interface between the drift region and the body region can be exposed at the side surface of the second groove. In this semiconductor device, the electric field concentration around the pn junction interface between the drift region and the body region is well relaxed, and the withstand voltage is improved.

[0056] The manufacturing method of the semiconductor device disclosed in the present specification can include a step of preparing a nitride semiconductor layer, a step of forming a trench, a step of forming a JFET region, a step of forming a source region, and a step of forming an insulating gate portion. In the step of preparing the nitride semiconductor layer, a nitride semiconductor layer in which a drift region of a first conductivity type and a body region of a second conductivity type are stacked and the body region is exposed at one main surface is prepared. In the step of forming the trench, a trench reaching the drift region beyond the body region is formed from the one main surface of the nitride semiconductor layer by a dry etching technique. In the step of forming the trench, a first trench formed in a part of an element portion of the nitride semiconductor layer and a second trench formed in a peripheral withstand voltage portion of the nitride semiconductor layer are formed at the same time. In the step of forming the JFET region, a JFET region of the first conductivity type is formed so as to be buried in the first trench. In the step of forming the source region, a source region of the first conductivity type is formed which is separated from the JFET region by the body region. In the step of forming the insulating gate portion, an insulating gate portion is formed which opposes a channel portion of the body region separating the JFET region and the source region. In the step of forming the trench, a profile of a side surface of the first trench adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an m plane, and a profile of a side surface of the second trench exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an a plane, and the first trench and the second trench can be formed at the same time. Alternatively, in the step of forming the trench, a profile of a side surface of the first trench adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an a plane, and a profile of a side surface of the second trench exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an m plane, and the first trench and the second trench can be formed at the same time.

[0057] In the step of forming the trench of the manufacturing method, a profile of the side surface of the first trench adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an m plane, and a profile of the side surface of the second trench exposed at the one main surface of the nitride semiconductor layer can be made parallel with respect to an a plane, and the first trench and the second trench can be formed at the same time. According to the manufacturing method, the side surface of the first trench can be formed with a smaller inclination angle, and the side surface of the second trench can be formed with a larger inclination angle.

[0058] In the step of forming the trench of the manufacturing method, a power ratio of an antenna power / bias power can be 4.3 or more and 6.9 or less. According to the manufacturing method, the side surface of the first trench can be formed with a smaller inclination angle, and the side surface of the second trench can be formed with a larger inclination angle.

[0059] The above detailed description sets forth numerous specific details about the application. However, these specifics are only intended to illustrate the application. They are not intended to limit the scope of the claims. The technology recited in the claims encompasses all of the variations and modifications of the specific examples described above. Also, the technical elements described in the specification or drawings can be used alone or in various combinations, and are not limited to the combinations recited in the claims at the time of filing. Also, the technology described in the specification or drawings can achieve multiple objectives, and achieving one of the objectives itself has technical usefulness.

Claims

1. A semiconductor device characterized by comprising: a nitride semiconductor layer divided into an element portion and a peripheral withstand voltage portion disposed around the element portion; a source electrode disposed on one main surface of the nitride semiconductor layer; a drain electrode disposed on the other main surface of the nitride semiconductor layer; and an insulating gate portion, the nitride semiconductor layer having: a drift region of a first conductivity type disposed in the element portion and the peripheral withstand voltage portion; a JFET region of the first conductivity type disposed in the element portion, disposed on the drift region, and buried in a first trench formed on the one main surface; a body region of a second conductivity type disposed in the element portion, disposed on the drift region, and adjacent to the JFET region; and a source region of the first conductivity type disposed in the element portion, separated from the JFET region by the body region, the insulating gate portion disposed in the element portion, opposing a channel portion of the body region separating the JFET region and the source region, a second trench formed on the one main surface of the nitride semiconductor layer in the peripheral withstand voltage portion, a side surface of the first trench adjacent to the channel portion having a smaller inclination angle than a side surface of the second trench, the side surface of the first trench adjacent to the channel portion being exposed on the one main surface of the nitride semiconductor layer in a profile parallel to an m-plane, and the side surface of the second trench being exposed on the one main surface of the nitride semiconductor layer in a profile parallel to an a-plane.

2. The semiconductor device according to claim 1, characterized in that the inclination angle of the side surface of the second trench is substantially 90°.

3. The semiconductor device according to claim 1 or 2, characterized in that a pn junction interface of the drift region and the body region is exposed on the side surface of the second trench.

4. A method of manufacturing a semiconductor device characterized by comprising: a process of preparing a nitride semiconductor layer in which a drift region of a first conductivity type and a body region of a second conductivity type are laminated and the body region is exposed on one main surface of the nitride semiconductor layer; a process of forming a trench, in which a trench reaching the drift region beyond the body region is formed from the one main surface of the nitride semiconductor layer by a dry etching technique, and in which a first trench formed in a part of an element portion of the nitride semiconductor layer and a second trench formed in a peripheral withstand voltage portion of the nitride semiconductor layer are simultaneously formed; a process of forming a JFET region of the first conductivity type in a manner of being buried in the first trench; a process of forming a source region of the first conductivity type separated from the JFET region by the body region; and a process of forming an insulating gate portion opposing a channel portion of the body region separating the JFET region and the source region, in which one of the following processes is performed in the process of forming a trench: ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ the profile of the side surface of the first groove adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer is made parallel to the m-plane, the profile of the side surface of the second groove exposed at the one main surface of the nitride semiconductor layer is made parallel to the a-plane, and the first groove and the second groove are formed simultaneously; the profile of the side surface of the first groove adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer is made parallel to the a-plane, the profile of the side surface of the second groove exposed at the one main surface of the nitride semiconductor layer is made parallel to the m-plane, and the first groove and the second groove are formed simultaneously.

5. The method for manufacturing a semiconductor device according to claim 4, wherein in the groove forming step, the profile of the side surface of the first groove adjacent to the channel portion exposed at the one main surface of the nitride semiconductor layer is made parallel to the m-plane, the profile of the side surface of the second groove exposed at the one main surface of the nitride semiconductor layer is made parallel to the a-plane, and the first groove and the second groove are formed simultaneously.

6. The method for manufacturing a semiconductor device according to claim 5, wherein in the groove forming step, the power ratio of the antenna power / bias power is 4.3 or more and 6.9 or less.

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