An oscillator circuit

Abstract

The application provides an oscillator circuit, relates to the technical field of electronics, and is used for improving the performance of an oscillator. The oscillator circuit comprises an amplifier, a first transconductance amplifier and a second transconductance amplifier; a resonator comprising a capacitive element and an inductive element, the capacitive element comprising a first capacitor and a second capacitor, and the inductive element comprising a tapped inductor, the tapped inductor comprising a first inductive segment and a second inductive segment, and the first inductive segment and the second inductive segment being coupled through a first capacitor; the first inductive segment comprising a first terminal and a second terminal; the second inductive segment comprising a third terminal and a fourth terminal; the first terminal and the second terminal being coupled to the input end and the output end of the first transconductance amplifier respectively; the third terminal and the fourth terminal being coupled to the input end and the output end of the second transconductance amplifier respectively; and the first terminal and the fourth terminal being coupled through the second capacitor.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electronics, and in particular to an oscillator circuit. BACKGROUND

[0002] With the development of cellular, wireless local area network (WLAN), satellite communication, global positioning system (GPS) and other wireless communication systems, the demand for products with small size, low cost and high frequency is also increasing. In this regard, voltage controlled oscillator (VCO) plays a key role in communication systems, providing the required periodic signal for timing in digital circuits and frequency conversion in radio frequency (RF) circuits. VCO can be implemented as a separate module that is separate from other circuits or integrated into an application specific integrated circuit (ASIC) for use in devices such as, but not limited to, mobile phones, base stations, and almost every communication device. With the increase of RF frequency and the decrease of power supply voltage, it is increasingly difficult to design a VCO that meets both the system noise and power requirements and the product demand for small size, low cost and high frequency.

[0003] The noise performance of an LC resonant VCO is directly related to its signal power, which is proportional to the energy stored in the resonant inductor-capacitor (LC) tank circuit. In traditional VCO design, the energy stored in the LC circuit is proportional to the size of the inductor and the square of the power supply voltage of the amplifier in the VCO. With the reduction of the geometry of semiconductor devices, the power supply voltage of the amplifier also needs to be reduced. In order to compensate for the voltage drop, the size of the inductor used in the LC tank circuit must also be reduced, so that the noise performance of the VCO remains unchanged. Increasing the required frequency also requires reducing the size of the inductor. However, reducing the size of the inductor is extremely challenging, because as the size of the inductor continues to decrease, the quality factor (Q) of the inductor also decreases, further increasing the thermal noise of the VCO. SUMMARY

[0004] The present application provides an oscillator circuit for improving the performance of an oscillator. To achieve the above object, the present application adopts the following technical solution:

[0005] In a first aspect, an oscillator circuit is provided, comprising: an amplifier comprising a first transconductance amplifier and a second transconductance amplifier; a resonator comprising a capacitive element and an inductive element, the capacitive element comprising a first capacitor and a second capacitor, the inductive element comprising a tapped inductor, the tapped inductor comprising a first inductive segment and a second inductive segment, the first inductive segment and the second inductive segment being coupled by the first capacitor; the first inductive segment comprising a first terminal and a second terminal; the second inductive segment comprising a third terminal and a fourth terminal; the first terminal and the second terminal being coupled to an input terminal and an output terminal of the first transconductance amplifier, respectively; the third terminal and the fourth terminal being coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively; the first terminal and the fourth terminal being coupled by the second capacitor. In the above technical solution, the first transconductance amplifier and the first inductive segment can serve as a single-ended three-point oscillation oscillator, the second transconductance amplifier and the second inductive segment can serve as another single-ended three-point oscillation oscillator, and the two single-ended three-point oscillation oscillators can be coupled together by the first capacitor and the second capacitor, so as to reduce the phase noise of the oscillator circuit and improve the performance of the oscillator circuit.

[0006] In a possible implementation of the first aspect, the tapped inductor comprises a plurality of conductive segments, and the plurality of conductive segments form an 8-shaped physical loop in a manner of layer-crossing. In the above possible implementation, the tapped inductor is composed of two half-loop circuits with opposite magnetic field directions, and the induced currents generated by the two opposite magnetic fields are offset when the two half-loop circuits are disturbed by a magnetic field, so that the tapped inductor has good anti-interference performance.

[0007] In a possible implementation of the first aspect, the plurality of conductive segments are routed on a top metal layer and a sub-top metal layer, or a top metal layer and a redistribution layer. Optionally, the plurality of conductive segments of the 8-shaped physical loop 401 are divided into a non-crossing portion and two crossing portions when being routed, and the non-crossing portion and one of the two crossing portions can be routed on the top metal layer, and the other crossing portion can be routed on the sub-top metal layer or the redistribution layer. In the above possible implementation, the interference of other elements in the oscillator circuit on the tapped inductor can be reduced.

[0008] In a possible implementation of the first aspect, the first terminal and the fourth terminal are two output terminals of the tapped inductor, and the second terminal and the third terminal are two tap terminals of the tapped inductor. In the above possible implementation, the positions of the second terminal and the third terminal can be changed to adjust the power consumption, output amplitude and phase noise of the oscillator circuit, so as to improve the performance of the oscillator circuit.

[0009] In a possible implementation of the first aspect, the second terminal and the third terminal correspond to two tap segments which are arranged in the middle of the tapped inductor. When the physical loop is arranged in the top metal layer and the next metal layer of the sub-top metal layer, the part of the two tap segments which does not overlap with the physical loop can be arranged in the top metal layer, and the overlapping part can be arranged in the next metal layer of the sub-top metal layer; when the physical loop is arranged in the top metal layer and the rewiring layer, the part of the two tap segments which does not overlap with the physical loop can be arranged in the top metal layer, and the overlapping part can be arranged in the sub-top metal layer. In the possible implementation, the inductive current of the two symmetrical halves of the tapped inductor can be offset by arranging the two tap segments in the middle of the tapped inductor, thereby improving the performance of the oscillator circuit.

[0010] In a possible implementation of the first aspect, the input voltage of the amplifier exceeds the power supply voltage of the amplifier. In the possible implementation, when the input voltage exceeds the power supply voltage, the gain of the oscillator circuit can be improved, and the power requirement of the oscillator circuit is reduced.

[0011] In a possible implementation of the first aspect, the first transconductance amplifier and the second transconductance amplifier each include an NMOS transistor and a PMOS transistor; the source of the NMOS transistor is coupled to a positive power supply rail, the gate of the NMOS transistor and the gate of the PMOS transistor are coupled as an input terminal, the drain of the NMOS transistor and the drain of the PMOS transistor are coupled as an output terminal, and the source of the PMOS transistor is coupled to a ground terminal. In the possible implementation, the first transconductance amplifier and the second transconductance amplifier form negative resistance through cross positive feedback, which can offset the loss of the tank formed by the resonator, thereby improving the performance of the oscillator circuit; in addition, the input impedance and the output impedance of the first transconductance amplifier and the second transconductance amplifier are different, and by adjusting the ratio of the input impedance and the output impedance, the oscillator circuit can work in a linear region, thereby making the oscillator circuit have better phase noise.

[0012] In a second aspect, a non-transitory computer readable medium for use with a computer having software for creating integrated circuits is provided. The computer readable medium has one or more computer readable data structures stored thereon, the one or more computer readable data structures having photomask data for fabricating an oscillator circuit, the oscillator circuit comprising: an amplifier comprising a first transconductance amplifier and a second transconductance amplifier; a resonator comprising a capacitive element and an inductive element, the capacitive element comprising a first capacitor and a second capacitor, the inductive element comprising a tapped inductor, the tapped inductor comprising a first inductive segment and a second inductive segment, the first inductive segment and the second inductive segment coupled by the first capacitor; the first inductive segment comprising a first terminal and a second terminal; the second inductive segment comprising a third terminal and a fourth terminal; the first terminal and the second terminal coupled to an input terminal and an output terminal of the first transconductance amplifier, respectively; the third terminal and the fourth terminal coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively; the first terminal and the fourth terminal coupled by the second capacitor.

[0013] In a possible implementation form of the second aspect, the tapped inductor comprises a plurality of conductive segments, the plurality of conductive segments form an 8-shaped physical loop by layer-crossing.

[0014] In a possible implementation form of the second aspect, the plurality of conductive segments are routed on a top metal layer and a sub-top metal layer, or a top metal layer and a rewiring layer.

[0015] In a possible implementation form of the second aspect, the first terminal and the fourth terminal are two output terminals of the tapped inductor, and the second terminal and the third terminal are two tap terminals of the tapped inductor.

[0016] In a possible implementation form of the second aspect, the second terminal and the third terminal correspond to two tap segments routed in the middle of the tapped inductor.

[0017] In a possible implementation form of the second aspect, an input voltage of the amplifier exceeds a power supply voltage of the amplifier.

[0018] In a possible implementation form of the second aspect, the first transconductance amplifier and the second transconductance amplifier each comprise: an NMOS transistor and a PMOS transistor; wherein a source of the NMOS transistor is coupled to a positive power supply rail, a gate of the NMOS transistor and the PMOS transistor is coupled as an input terminal, a drain of the NMOS transistor and the PMOS transistor is coupled as an output terminal, and a source of the PMOS transistor is coupled to a ground terminal.

[0019] It can be understood that any of the above provided non-transitory computer readable medium for use with a computer includes the oscillator circuit provided above, and therefore, the beneficial effects achievable by the non-transitory computer readable medium for use with a computer can refer to the beneficial effects of the oscillator circuit provided above, which will not be described herein again. Attached Figure Description

[0020] Figure 1 A schematic diagram of a differential LC energy storage circuit provided in an embodiment of this application;

[0021] Figure 2 An example layout of a first differential tapped inductor provided in the embodiments of this application;

[0022] Figure 3 This application provides a first differential tapped LC energy storage circuit for embodiments of the present application.

[0023] Figure 4 This is an example layout of a second differential tapped inductor provided in an embodiment of this application;

[0024] Figure 5 This application provides a second differential tapped LC energy storage circuit.

[0025] Figure 6 A schematic diagram of a first type of differential VCO provided for embodiments of this application;

[0026] Figure 7 A schematic diagram of a second type of differential VCO provided in an embodiment of this application;

[0027] Figure 8 A schematic diagram of a third type of differential VCO provided in an embodiment of this application;

[0028] Figure 9 A schematic diagram of the fourth type of differential VCO provided in the embodiments of this application;

[0029] Figure 10 A design flowchart of an ASIC provided for an embodiment of this application;

[0030] Figure 11 This is an illustrative example of a computing device provided for embodiments of this application. Detailed Implementation

[0031] The following sections will discuss the fabrication and use of various embodiments in detail. However, it should be understood that many applicable inventive concepts provided in this application can be implemented in a variety of specific environments. The specific embodiments discussed are merely illustrative of specific ways of implementing and using this description and technology, and do not limit the scope of this application.

[0032] Unless otherwise defined, all technical terms used herein have the same meaning as commonly known to one of ordinary skill in the art.

[0033] Circuits or other components can be described as or said to be “configured to” perform one or more tasks. In this context, “configured to” is used to mean that the circuit / component includes at least one structural component (e.g., circuitry) that performs the task(s). As such, the term “configured to” is specifically intended to encompass a structural circuit / component that is active or passive (i.e., having mechanical motion) to operate in a certain manner. If a structural component that is active or passive is recited without the “configured to” language, only a structural component that is active is assumed. Thus, assuming no “configured to” language is recited, a structural component is only active unless expressly recited as passive. The term “configured to” is specifically intended not to invoke 35 U.S.C. 112(f) unless the term “configured to” is specifically used in conjunction with the phrases “to perform X” or “to perform the function of Y,” where X is a function and Y is a device or apparatus that is recited.

[0034] In this specification, references to “an embodiment,” “one embodiment,” “a specific embodiment,” or “a particular embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases “in one embodiment,” “in an embodiment,” or “in a specific embodiment” in various places in the specification are not necessarily referring to the same embodiment. Further, many of the embodiments are described in terms of particular examples, which should not be construed as limiting. In addition, the specific features, structures, or characteristics of a particular embodiment can be combined in any suitable manner with features, structures, or characteristics of one or more other embodiments. It will be appreciated that, in light of the teachings herein, the specific embodiments described herein will adapt to a wide variety of alternative designs and implementations.

[0035] Figure 1 A schematic diagram of an LC tank circuit 100 including a parasitic resistance R c and R l , for use in a differential voltage controlled oscillator (VCO), can also be referred to as an LC resonant circuit, an LC resonator, or a resonator, among others. The VCO amplifier provides current to the input impedance of the LC tank circuit 100, and the voltage generated by the LC tank circuit 100 through the LC circuit is equal to the voltage at the amplifier input. In a conventional single inductor VCO (e.g., Pierce configuration), the amplifier drives an impedance Z2(ω o ), and the voltage at the amplifier input is represented as the voltage through Z2(ω o ).

[0036] In this application, a single inductor is tapped (e.g., divided into at least two parts) according to a factor K. The amplifier drives an inductor tap defined by an impedance Z1(ω o ), and the voltage at the amplifier input is from through an impedance Z2(ω o) defined inductor taps. In theory, inductor sections KL and (1-K) / 2*L can be considered as separate inductors due to their small inductance and very high frequency. However, due to physical size requirements and mutual coupling, separate inductors are impractical.

[0037] Since the input and output of the amplifier are at different points of the LC tank 100 (i.e. Z2 and Z1), the input voltage to the amplifier in the VCO can be much larger than the output voltage of the amplifier as determined by the voltage divider of the tapped inductor. This arrangement has many advantages.

[0038] The HCI voltage limit of the amplifier is only at the output. This supports the input signal to exceed the power supply voltage limit of the amplifier. Since the input voltage represents the energy stored in the LC tank 100, the VCO noise is lower compared to a VCO with a traditional resonator for the same total inductance, because the LC tank 100 voltage is higher. Furthermore, the inductor does not have to be reduced in size to meet the noise requirements, resulting in a higher inductor Q when integrated into an integrated circuit (e.g. as part of an ASIC).

[0039] Since the voltage into the amplifier exceeds the power supply rail, the gain of the amplifier is higher for a given power consumption. The output current of the amplifier is the product of the input voltage across Z2 and its transconductance g m . Since the input voltage is increased, the amplifier has more gain for the same current. This reduces the power requirements of the system.

[0040] From Figure 1 and the following equations (1) to (5), the impedance at Z1 (ω o ) in the LC tank 100 is lower than the impedance at Z2 (ω o ) by a factor of K 2 Under large signal conditions, the linearity of the amplifier is determined by the linearity of its output, not its input. The low impedance at the output of the VCO reduces the flicker noise mixing with the non-linearity of the VCO, improving the spectral utilization of the sidebands near it. Those skilled in the art will recognize that flicker noise at baseband is a type of electronic noise with a 1 / ω density spectrum but mixed via non-linear elements, which produces the 1 / ω 3 part of the VCO single sideband phase noise.

[0041] The resonance value and ω o L = X o (1)

[0042]

[0043]

[0044]

[0045]

[0046] Where: ω o It is the oscillation frequency (radians per second);

[0047] L is inductance;

[0048] C is the capacitor;

[0049] R l It is the parasitic resistance of the inductor;

[0050] R c It is the parasitic resistance of the capacitor;

[0051] K is a constant that relates Z1 and Z2;

[0052] X o The resonant frequency is ω o The reactance of inductor L.

[0053] For reference Figure 2 This illustrates an application of the principles of this application for LC energy storage circuits (e.g., Figure 1 An example layout of a differential tapped inductor 200 integrated into an integrated circuit (LC energy storage circuit shown). Figure 3 A schematic diagram of a differential tapped LC energy storage circuit 302 is shown, including... Figure 2 The equivalent inductance 200' of the tapped inductor 200 coupled in parallel with capacitor C is shown. Note that... Figure 2 The segments V1-V5a, V2-V5a, V3-V5b, V4-V5b, and V5a-V5b correspond to respectively Figure 3 The diagram shows inductors L1, L2, L3, L4, and L5.

[0054] The differential tapped inductor 200 includes one or more conductive segments (e.g., V1-V5a, V4-V5b, and V5a-V5b) constituting a physical loop 201. As used herein, the term "physical loop" refers to a closed or nearly closed geometry having common or adjacent start and end points and including at least one distinct convex portion, wherein the convex portion defines an internal space (e.g., a ring-shaped polygon or a segment of a ring-shaped polygon) within the convex portion. Therefore, a physical loop differs from an "electrical loop," which typically represents a closed path of any shape through which current may flow.

[0055] The physical loop 201 is preferably symmetrical, as shown in FIG. 2, and is generally octagonal in shape when in the inductor 200. Those skilled in the art will recognize that the physical loop 201 can include other symmetrical and non-symmetrical shapes (e.g., rectangular, square, hexagonal, etc.) without departing from the scope of the present application. The inductor 200 taps segments V2-V5a and V3-V5b at V5a and V5b through electrical connections to form electrical loops (L2 and L3) that are disposed within the interior space formed by the physical loop 21 (including LI, L5, and L4).

[0056] The capacitive element C of the tapped LC tank circuit 302 can be embodied as a PMOS varactor diode, an NMOS varactor diode, a metal-insulator-metal (MIM) device, or any other suitable capacitive element. In a silicon process, two types of varactor diodes can be used, namely a reverse-biased pn-junction type diode or a MOS capacitor varactor diode. The MOS capacitor varactor diode can be constructed from a MOS transistor with the drain, source, and body terminals coupled together and the capacitance adjusted based on the voltage applied between the body and gate terminals. Those skilled in the art will recognize that other alternative elements for the capacitive element C of the LC tank circuit can be used without departing from the scope of the present application.

[0057] The quality factor (Q) of the tapped LC tank circuit 302 is dependent on the inductor 200 having a low resistance. The series resistance is minimized by using a thick / wide metallization process, such as but not limited to aluminum, copper, gold, or other suitable material, to minimize the resistance of the inductor 200. The inductor 200 is preferably constructed from a high dielectric substrate material such as silicon, gallium arsenide, or other suitable material. Surface micromachining techniques can be used to create an air gap between the inductor and the substrate to further improve the dielectric properties.

[0058] The inductor tap segments V2-V5a and V3-V5b (L2 and L3) are coupled to the amplifier output and are not part of the LC tank circuit. Therefore, their parasitic resistance is not as significant as the parasitic resistance of the inductor segments LI, L4, and L5. Therefore, segments L2 and L3 can be constructed using a thinner metal material as shown in FIG. 3. Figure 2

[0059] ​A practical problem involved when using multiple inductors (e.g., L1 to L5) is the mutual inductance in any connection from the amplifier output to the taps V5a and V5b. The inductor current in the LC energy storage circuit is typically much higher than the current supplied by the amplifier according to the circuit factor Q. When the mutual inductance is high, the induced current from the LC energy storage circuit becomes high enough in the leads from the amplifier output to the taps that the input impedance to the taps becomes so high that the amplifier cannot supply any current. To overcome this problem, the tap segments V2-V5a (L2) and V3-V5b (L3) are guided upwards in the middle of inductor 200 (e.g., ...). Figure 2 As shown in the figure, the induced currents from the two symmetrical halves of the inductor 200 cancel each other out.

[0060] The tap positions V5a and V5b on the metal can be adjusted to change power consumption, VCO output swing, and phase noise performance. This can be used for fine-tuning the metal design, as shown in V5a' and V5b'. To minimize parasitic effects on the substrate, the substrate can be doped with additives to have high resistivity, and / or the distance between the metal layer and the substrate can be increased through etching or micromachining.

[0061] Furthermore, in combination Figure 2 ,like Figure 4 As shown in the embodiments of this application, another example layout for a differential tapped inductor 400 integrated onto an integrated circuit is also illustrated. Figure 4 In this design, the tapped inductor 400 is divided into two inductor segments (i.e., a first inductor segment and a second inductor segment), which are coupled together by a first capacitor C1. Each of the first and second inductor segments can be a separate three-terminal tapped inductor, i.e., an inductor with two output terminals and one tap terminal; for example, each inductor segment can be a wound coil with two output terminals and one tap terminal. Figure 4 In the first inductor, V1-V5a, V5a-V5c, and V5a-V2 can be included. V1 and V5c can be the two output terminals of the first inductor, and V2 can be the tap terminal of the first inductor. The second inductor can be included, V4-V5b, V5b-V5d, and V5b-V3. V4 and V5d can be the two output terminals of the second inductor, and V2 can be the tap terminal of the second inductor.

[0062] Figure 5 It shows Figure 4 A schematic diagram of the corresponding differential tapped LC energy storage circuit 502, including Figure 4 The equivalent inductance 400' of the tapped inductor 400 coupled in parallel with the second capacitor C2 is shown. Note that... Figure 4 Segments V1-V5a in the middle correspond to Figure 5 In the schematic diagram, inductors L1, V2-V5a correspond toFigure 5 inductor L2 in the schematic diagram of FIG. 1, V3-V5b correspond to Figure 5 inductor L3 in the schematic diagram of FIG. 1, V4-V5b correspond to Figure 5 inductor L4 in the schematic diagram of FIG. 1, V5a-V5c correspond to Figure 5 L5a in the schematic diagram of FIG. 1, V5b-V5d correspond to Figure 5 L5b in the schematic diagram of FIG. 1.

[0063] The differential-tapped inductor 400 includes one or more conductive segments (e.g., V1-V5b, V4-V5b, V5a-V5c, and V5b-V5d) that form a physical loop 401 in the shape of an 8. The "8" here can be understood as including two loop or near-loop (e.g., polygon) geometries that form an 8, and that are each axisymmetric, and that can be closed or open. Each of the conductive segments here can be understood as an inductor with two terminals, e.g., as a coil with two terminals.

[0064] In practice, the conductive segments that form the physical loop 401 can be routed through layer jumps, and can form a physical loop in the shape of an 8. Optionally, the conductive segments can be routed on a top metal layer and a next-top metal layer, or on a top metal layer and a redistribution layer (RDL). For example, the physical loop 401 in the shape of an 8 can be divided into a non-crossing portion and two crossing portions, the non-crossing portion and one of the two crossing portions can be routed on a top metal layer, and the other of the two crossing portions can be routed on a next-top metal layer or a redistribution layer, to Figure 4 For example, the two crossing portions can include P0-P1 and P2-P3, and the non-crossing portion includes the rest of the physical loop 401. When the physical loop 401 is routed on a top metal layer and a next-top metal layer, the portions of the two tap segments that do not overlap the physical loop 401 can be routed on the top metal layer, and the overlapping portions can be routed on the next metal layer of the next-top metal layer. When the physical loop 401 is routed on a top metal layer and a redistribution layer, the portions of the two tap segments that do not overlap the physical loop 401 can be routed on the top metal layer, and the overlapping portions can be routed on the next-top metal layer. Of course, the conductive segments can be routed on other metal layers, which are not limited by the embodiments of the present application.

[0065] It should be noted that integrated circuit chips (also known as dies) typically contain multiple metal layers. Metal layers closer to the substrate can be called lower metal layers, and those farther from the substrate can be called higher metal layers. The top metal layer can be the higher metal layer furthest from the substrate, and the second-to-top metal layer can be the metal layer below the top metal layer. The redistribution layer is located between the integrated circuit chip and the package; specifically, this redistribution layer can be an aluminum layer.

[0066] Currently, to improve communication quality, communication devices typically use Multiple Input Multiple Output (MIMO) operating modes, which means multiple oscillators need to operate simultaneously. However, current communication device chips are trending towards smaller sizes. Therefore, when multiple oscillators operate simultaneously, if two or more oscillators have the same frequency or a secondary frequency relationship, interference will occur between these oscillators, thus degrading their performance. Figure 4 The tapped inductor 400 shown consists of two half-figure-eight loops with opposite magnetic field directions. When these two opposite magnetic fields are disturbed by the magnetic field, the induced currents generated cancel each other out, thus providing excellent anti-interference performance.

[0067] It should be noted that, corresponding Figure 2 and Figure 3 The relevant descriptions also apply to Figure 4 and Figure 5 The embodiments of this application will not be described in detail here.

[0068] Figure 6 A schematic diagram of the differential VCO 600 implemented according to the principles of this application is shown. (Reference) Figure 6 The amplifier comprises a first transconductance amplifier including a PMOS transistor 604 and an NMOS transistor 608, and a second transconductance amplifier including a PMOS transistor 606 and an NMOS transistor 610. The sources of PMOS transistors 604 and 606 are coupled to the positive power rail (VDD), and their gates are coupled to the gates of NMOS transistors 608 and 610. The gates of PMOS transistors 604 and 608 are coupled to tap V1 of the differential tapped LC energy storage circuit 502. The gates of PMOS transistors 606 and 610 are coupled to tap V4 of the differential tapped LC energy storage circuit 502. The sources of NMOS transistors 608 and 610 are coupled to the negative power rail (ground), and their drains are coupled to the drains of PMOS transistors 604 and 606.

[0069] The taps V2 and V3 of the tapped LC tank 502 are coupled to the commonly coupled drains of the PMOS 604 and NMOS 608 and the commonly coupled drains of the PMOS 606 and NMOS 610.

[0070] For example, referring to Figure 7 , a circuit schematic of an exemplary class AB oscillator using a tapped LC tank 302 implemented in accordance with the principles of the present application is shown. In Figure 7 , the amplifier includes two amplification pairs, i.e., a first amplification pair gm1 (may also be referred to as a first transconductance amplifier) and a second amplification pair gm2 (may also be referred to as a second transconductance amplifier), both of which include a PMOS and a NMOS, the sources of the PMOS in gm1 and gm2 are coupled to a positive supply rail (VDD), and the sources of the NMOS in gm1 and gm2 are coupled to a negative supply rail (ground). The gates A of the PMOS and the NMOS in gm1 are coupled to the tap V1 of the tapped LC tank 302, and the drains B of the PMOS and the NMOS in gm1 are coupled to the tap V2 of the differential tapped LC tank 302; the gates C of the PMOS and the NMOS in gm2 are coupled to the tap V4 of the differential tapped LC tank 302, and the drains D of the PMOS and the NMOS in gm2 are coupled to the tap V3 of the differential tapped LC tank 302.

[0071] It should be noted that the equivalent inductances L1-L5 in the tapped LC tank 302 can be designed by using the inductances L11-L14 shown in Figure 7 , which are exemplary only and do not limit the embodiments of the present application.

[0072] In Figure 7 , L11-L14 and C1 form a tank for an oscillator in parallel, and the first amplification pair gm1 and the second amplification pair gm2 form a negative resistance through cross feedback to offset the loss of the tank to form a class AB mode oscillator. For the first amplification pair gm1, the amplitudes of the AC signals seen at the gate A and the drain B are not the same, because L11 and L13 will make the impedance seen at B smaller than the impedance seen at A. According to small-signal linear analysis, the ratio is approximately (L14+L11+L12) / (L11+L12+L13+L14). Therefore, by selecting different ratios of L3 and L4 to improve the size of the impedance seen at the drain B of the first amplification pair gm1, the first amplification pair gm1 can be made to work in the linear region of the class AB mode. Compared with the conventional CMOS oscillator, Figure 7The gate of the class AB oscillator with the inductive feedback has a larger oscillation amplitude, which reduces the nonlinearity of the drain, and thus has better phase noise.

[0073] For example, referring to Figure 8 , a circuit schematic diagram of an example class AB oscillator using a tapped LC tank 502 implemented according to the principles of the present application is shown. In Figure 8 , the amplifier includes two pairs of amplification tubes, i.e., a first pair of amplification tubes gm1 and a second pair of amplification tubes gm2, which are consistent with the above-described gm1 and gm2 in Figure 7 . For details, refer to the related description in Figure 7 . The embodiments of the present application will not be described here again.

[0074] In the differential tapped LC tank 502, the equivalent inductance L1-L5b can be designed by the inductance shown in L21-L24 in Figure 8 . L21-L24 are only examples and do not limit the embodiments of the present application. In addition, Figure 8 , the class AB oscillator with inductive feedback is consistent with the class AB oscillator shown in Figure 7 , and also has better phase noise. For details, refer to the related description in Figure 7 .

[0075] In addition, in order to reduce the phase noise of the oscillator, the two oscillators can be coupled together by a transformer or a capacitor. The power coupling method halves the signal-to-noise ratio of the VCO output, thereby achieving the effect of optimizing noise by 3dB. In Figure 8 , the middle tap of the inductor L22 is coupled to the output stage of the first pair of amplification tubes gm1, so that gm1, L21 and L22 form a single-ended three-point oscillation VCO circuit. Similarly, the middle tap of the inductor L24 is coupled to the output stage of the second pair of amplification tubes gm2, so that gm2, L23 and L24 form another symmetric single-ended three-point oscillation VCO circuit. Coupling the two VCOs together with a first capacitor C1 and a second capacitor C2 can double the equivalent inductance and halve the equivalent capacitance, thereby doubling the signal energy and reducing the phase noise by 3dB.

[0076] Since the 8-shaped inductor has the characteristic of anti-interference, L21-L24 in Figure 8 are set as 8-shaped physical loops, which can make L21-L24 form magnetic fields in opposite directions to achieve the purpose of anti-interference. For example, as shown in Figure 9 , when designed as an 8 shape, L21 and L24 can beFigure 8 The positions of L22 and L24 are swapped, and then L1 and L3 are set as one half of the figure-eight, and L2 and L4 are set as the other half of the figure-eight, thus obtaining a figure-eight physical loop.

[0077] Modern integrated circuit design and manufacturing are typically automated using Electronic Design Automation (EDA) tools. Example tools can be found from companies such as, but not limited to, Synopsys, Cadence, and Mentor Graphics. Details of these EDA tools are not required in this application.

[0078] For reference Figure 10 This illustrates a simplified general-purpose ASIC design flow for producing an ASIC with embodiments of this application using an electronic design analysis (EDA) tool. At step 1000, a functional design for the ASIC is created that may include a VCO having a tapped inductor according to the principles of this application.

[0079] In practice, for these ASIC digital systems, functional designs are typically represented by writing Register Transfer Level (RTL) code in a Hardware Descriptive Language (HDL), such as, but not limited to, VHDL or Verilog. Functional verification (behavioral simulation) is then preferably performed on the HDL data structures to ensure the RTL design conforms to the logic specifications. Alternatively, a schematic capture program can be used to capture a schematic diagram of the digital logic.

[0080] For practical analog ASICs (such as VCOs with tapped inductors as described in this application), the analog functional design is typically presented by capturing a schematic using a schematic capture program. The output of the schematic capture program is then converted (synthesized) into a gate / transistor-level netlist data structure.

[0081] In step 1002, the data structure is simulated using a simulation program within integrated circuits emphasis (SPICE). In step 1004, the data structure obtained from step 1002 is instantiated using its geometric representation, and the physical layout of the ASIC is performed.

[0082] The first step in the physical layout is typically a so-called "floorplan", in which the total area on the integrated circuit chip is allocated, and the input / output (I / O) pins are defined. Hard cores (e.g., arrays, analog blocks, inductors, etc.) are placed within the total area based on design constraints (e.g., trace length, timing, etc.). Clock routing (often referred to as a clock tree) is placed, and connections between gate / analog blocks are guided. When all elements are placed, global and detailed routing is run to connect all elements together. Post-routing optimization is preferably performed to improve performance (timing closure), noise (signal integrity), and yield. Modifications to the layout are made, where possible, while staying consistent with the design rules specified by the selected in-house or external semiconductor foundry, thereby improving production efficiency. Such modifications can include adding extra vias or dummy metal / diffusion / poly layers.

[0083] At step 1006, the physical design is verified. Design rule checking (DRC) is performed to determine whether the physical layout of the ASIC meets a set of recommended parameters, i.e., the design rules of the foundry. Design rules are a set of parameters provided by the foundry for a particular semiconductor manufacturing process. The design rules specify certain geometric and connectivity constraints to ensure that there is sufficient margin to account for variability in the semiconductor manufacturing process, thereby ensuring that the ASIC functions properly. Layout versus schematic (LVS) checking is preferably performed to verify that the physical layout corresponds to the original schematic or circuit diagram of the design. Then, full simulation is preferably performed to ensure that the layout phase was completed correctly.

[0084] After the layout is verified at step 1006, the mask generation design data, typically in the form of a GDSII data structure, is referred to as "tape-out" for the preparation of photomasks at step 1008. The GDSII data structure is transmitted from the circuit designer to the photomask vendor / manufacturer or directly to the semiconductor foundry over a communication medium (e.g., memory or network).

[0085] At step 1010, the photomasks are created and used to manufacture the ASIC according to the principles of the present application.

[0086] Some of the techniques described herein can be implemented by software stored on one or more computer-readable media and executed on a computer. The selected techniques can be executed on a single computer or on a computer network that is networked to another computer or multiple computers. For clarity, only those aspects of the tools or computers that are pertinent to understanding the disclosed techniques are described. Well-known details of the products can be omitted.

[0087] Figure 11 shown for practicing Figure 11of the design flow of the computing device 1101. As shown Figure 11 The computing device 1101 includes a computing unit 1103 having a processing unit 1105 and a system memory 1107. The processing unit 1105 can be any type of programmable electronic device for executing software instructions, but is typically a microprocessor. The system memory 1107 can include both read-only memory (ROM) 1109 and random access memory (RAM) 1111. As is well understood by those of ordinary skill in the art, both the read-only memory 1109 and the random access memory 1111 can store software instructions for execution by the processing unit 1105.

[0088] The processing unit 1105 and the system memory 1107 are connected, either directly or indirectly, through a bus 1113 or alternative communication structure, to one or more peripheral devices. For example, the processing unit 1105 or the system memory 1107 can be directly or indirectly connected to one or more additional storage devices 1115. The storage devices 1115 can include “hard” disk drives, solid state disk drives, optical disk drives, and removable disk drives, among others. The processing unit 1105 and the system memory 1107 can also be directly or indirectly connected to one or more input devices 1117 and one or more output devices 1119. The input devices 1117 can include a keyboard, a pointing device (such as a mouse, a touchpad, a stylus, a navigation ball, or a joystick), a scanner, a camera, a microphone, and the like. The output devices 1119 can include a display device, a printer, and a speaker, among others. For various examples of the computing device 1101, one or more of the peripheral devices 1115-1119 can be internally housed with the computing unit 1103. Alternatively, one or more of the peripheral devices 1115-1519 can be external to the housing of the computing unit 1103 and connected to the bus 1113 through a Universal Serial Bus (USB) jack or a digital visual interface (DVI) jack, among others.

[0089] In some embodiments, the computing unit 1103 can also be directly or indirectly connected to one or more network interface cards (NICs) 1121 for communicating with other devices on a network. The network interface card 1121 converts data and control signals from the computing unit 1103 into network messages, and vice versa. Moreover, the network interface card 1121 can use any suitable connection agent (or combination of agents) for connecting to a network, including a wireless transceiver, a modem, or an Ethernet connection, among others.

[0090] It should be appreciated that the computing device 1101 is only shown as an example and is not limiting. One or more computing devices can be used to implement embodiments of the present application, including Figure 11 alternative combinations of components, including components not shown in the Figure 11 example computing device 1101. For example, embodiments of the present application can be implemented using a multi-processor computer, multiple single and / or multi-processor computers arranged in a network, or some combination thereof.

[0091] In one embodiment, in an oscillation circuit having a resonant device and an amplification device, the amplification device includes a first transconductance amplifier and a second transconductance amplifier, the resonant device includes an inductive element and a capacitive element, the capacitive element includes a first capacitor and a second capacitor, the inductive element includes a tapped inductor, the tapped inductor includes a first inductive segment and a second inductive segment, the first inductive segment and the second inductive segment are coupled by a first capacitance, the first inductive segment includes a first terminal and a second terminal, the second inductive segment includes a third terminal and a fourth terminal, the first terminal and the second terminal are coupled to an input terminal and an output terminal of the first transconductance amplifier, respectively, the third terminal and the fourth terminal are coupled to an input terminal and an output terminal of the second transconductance amplifier, respectively, and the first terminal and the fourth terminal are coupled by the second capacitor. In one embodiment, the tapped inductor includes a plurality of conductive segments, the plurality of conductive segments form an eight-shaped physical loop by a layer-jumping crossing manner.

[0092] In another embodiment, a computer device includes a storage device for storing computer instructions having photomask data device for fabricating an oscillator including a resonator device and an amplification device. The amplification device includes a first transconductance amplifier and a second transconductance amplifier; the resonator device includes a capacitive element and an inductive element, the capacitive element including a first capacitor and a second capacitor, the inductive element including a tapped inductor, the tapped inductor including a first inductive segment and a second inductive segment, the first inductive segment and the second inductive segment coupled by a first capacitance; the first inductive segment includes a first terminal and a second terminal; the second inductive segment includes a third terminal and a fourth terminal; the first terminal and the second terminal are coupled to an input terminal and an output terminal, respectively, of the first transconductance amplifier; the third terminal and the fourth terminal are coupled to an input terminal and an output terminal, respectively, of the second transconductance amplifier; the first terminal and the fourth terminal are coupled by the second capacitor.

[0093] In yet another embodiment, a place and route device includes logic for defining or allocating a total area on an integrated circuit and for defining input / output (I / O) pins. The place and route device includes hard core (e.g., array, analog block, inductor, etc.) placement devices for placing within the total area based on design constraints (e.g., trace length, timing, etc.). Clock routing placement devices (often referred to as clock trees) are used to place clock trees and connections between the clock trees and the guide grid / analogue blocks. Global and detailed routing devices are used to design connections to connect all elements together.

[0094] A physical design verification device including a design rule check device is used to verify that the physical design of a circuit (e.g., ASIC) meets one or more design rules. The design rules specify certain geometric and connectivity constraints to ensure that there is sufficient margin to account for variability in the semiconductor manufacturing process to ensure that the ASIC functions properly. A layout versus schematic (LVS) device is used to verify that the physical layout corresponds to the original schematic or circuit diagram of the design. A simulation device is used to perform a full simulation to ensure that the layout phase was completed correctly.

[0095] A tapeout device is used to generate mask generation design data, typically in the form of a GDSII data structure, for use in preparing photomasks. The GDSII data structure is transmitted from the circuit designer to a photomask vendor / fabricator or directly to a semiconductor foundry over a communication medium (e.g., memory or network). A photomask creation device creates photomasks for fabricating an ASIC in accordance with the principles of the present application. In other features, it is to be understood that the above-described devices are used as appropriate to produce resonator devices and amplification devices as described and claimed herein.

[0096] Some of the techniques described herein can be implemented by software stored on one or more computer-readable storage media and executed on a computer. The selected techniques can be executed on a single computer or on a computer network that is networked with other computers. For clarity, only those aspects of the tools or computers that are pertinent to understanding the disclosed techniques are described. Well-known details of the products can be omitted.

[0097] Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. Examples of computer-readable storage media include read-only memory (ROM), random-access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, optical media such as CD-ROMs, and digital versatile disks (DVDs).

[0098] While this application has been described with respect to certain embodiments and generally associated methods, alterations and permutations of these embodiments and methods will be apparent to those skilled in the art. In particular, it should be noted that while this application has been described in the context of CMOS amplifiers, those skilled in the art will recognize that applications to PMOS and NMOS amplifiers, bipolar amplifiers, and other suitable topologies without departing from the scope of this application. This application is applicable to nearly all communication systems. For example, this application can be used in cellular transceivers, two-way radio communications, Wi-Fi applications, satellite receivers, and any application that uses a voltage controlled oscillator.

[0099] It should be noted that the embodiments of the present application and the drawings are only examples, and each MOS tube in any embodiment or drawing can be a single MOS tube that meets the required starting gain or required on-current, or can be a MOS tube combination that meets the required starting gain or required on-current by parallel combination of multiple MOS tubes, that is, the sum of the starting gain of each MOS tube in the multiple MOS tubes is greater than or equal to the required starting gain; each capacitor in the embodiments of the present application can be a capacitor that meets the required capacitance value, or can be a capacitor combination that meets the required capacitance value by parallel or series combination of multiple capacitors, that is, the capacitance value corresponding to the series or parallel combination of the multiple capacitors is equal to the required capacitance value; each inductance in the embodiments of the present application can be an inductance that meets the required inductance value, or can be an inductance combination that meets the required inductance value by series or parallel combination of multiple inductances; each resistance in the embodiments of the present application can be a resistance that meets the required resistance value, or can be a resistance combination that meets the required resistance value by parallel or series combination of multiple resistances, that is, the resistance value corresponding to the series or parallel combination of the multiple resistances is equal to the required resistance value.

[0100] Finally, it should be noted that the above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto, and any change or replacement within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An oscillator circuit, characterized in that, include: The amplifier includes a first transconductance amplifier (gm) and a second transconductance amplifier (gm); A resonator includes a capacitive element and an inductive element. The capacitive element includes a first capacitor and a second capacitor. The inductive element includes a tapped inductor, which includes a first inductor segment and a second inductor segment. The first inductor segment includes a first terminal, a second terminal, and a fifth terminal; The second inductor segment includes a third terminal, a fourth terminal, and a sixth terminal; The first terminal and the fourth terminal are the two output terminals of the tapped inductor, and the second terminal and the third terminal are the two tap terminals of the tapped inductor; The first terminal is coupled to the input terminal of the first transconductance amplifier, and the second terminal is coupled to the output terminal of the first transconductance amplifier; The fourth terminal is coupled to the input terminal of the second transconductance amplifier, and the third terminal is coupled to the output terminal of the second transconductance amplifier; The first terminal and the fourth terminal are coupled through the second capacitor; The fifth terminal and the sixth terminal are coupled through the first capacitor.

2. The circuit according to claim 1, characterized in that, The tapped inductor includes multiple conductive segments, which form a figure-eight physical loop through a jump-over crossover.

3. The circuit according to claim 2, characterized in that, The plurality of conductive segments are respectively wired to the top metal layer and the second-to-top metal layer, or to the top metal layer and the rewiring layer.

4. The circuit according to claim 1, characterized in that, The two tap segments corresponding to the second terminal and the third terminal are wired in the middle of the tapped inductor.

5. The circuit according to any one of claims 1-4, characterized in that, The input voltage of the amplifier exceeds the power supply voltage of the amplifier.

6. The circuit according to any one of claims 1-4, characterized in that, Both the first transconductance amplifier and the second transconductance amplifier include: an NMOS transistor and a PMOS transistor; The source of the NMOS transistor is coupled to the positive power rail, the gates of the NMOS transistor and the PMOS transistor are coupled to form the input terminal, the drains of the NMOS transistor and the PMOS transistor are coupled to form the output terminal, and the source of the PMOS transistor is coupled to the ground terminal.

7. A non-transitory computer-readable medium for use with a computer, characterized in that, The computer has software for creating integrated circuits, and the computer-readable medium stores one or more computer-readable data structures, the one or more computer-readable data structures having photomask data for manufacturing an oscillator circuit, the oscillator circuit comprising: The amplifier includes a first transconductance amplifier (gm) and a second transconductance amplifier (gm). A resonator includes a capacitive element and an inductive element. The capacitive element includes a first capacitor and a second capacitor. The inductive element includes a tapped inductor, which includes a first inductor segment and a second inductor segment. The first inductor segment includes a first terminal, a second terminal, and a fifth terminal; The second inductor segment includes a third terminal, a fourth terminal, and a sixth terminal; The first terminal and the fourth terminal are the two output terminals of the tapped inductor, and the second terminal and the third terminal are the two tap terminals of the tapped inductor; The first terminal is coupled to the input terminal of the first transconductance amplifier, and the second terminal is coupled to the output terminal of the first transconductance amplifier; The fourth terminal is coupled to the input terminal of the second transconductance amplifier, and the third terminal is coupled to the output terminal of the second transconductance amplifier; The first terminal and the fourth terminal are coupled through the second capacitor; the fifth terminal and the sixth terminal are coupled through the first capacitor.

8. The computer-readable medium according to claim 7, characterized in that, The tapped inductor includes multiple conductive segments, which form a figure-eight physical loop through a jump-over crossover.

9. The computer-readable medium according to claim 8, characterized in that, The plurality of conductive segments are respectively wired to the top metal layer and the second-to-top metal layer, or to the top metal layer and the rewiring layer.

10. The computer-readable medium according to claim 7, characterized in that, The two tap segments corresponding to the second terminal and the third terminal are wired in the middle of the tapped inductor.

11. The computer-readable medium according to any one of claims 7-10, characterized in that, The input voltage of the amplifier exceeds the power supply voltage of the amplifier.

12. The computer-readable medium according to any one of claims 7-10, characterized in that, Both the first transconductance amplifier and the second transconductance amplifier include: an NMOS transistor and a PMOS transistor; The source of the NMOS transistor is coupled to the positive power rail, the gates of the NMOS transistor and the PMOS transistor are coupled to form the input terminal, the drains of the NMOS transistor and the PMOS transistor are coupled to form the output terminal, and the source of the PMOS transistor is coupled to the ground terminal.

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