Memory controller physical interface with differential loopback testing

Abstract

The present invention provides a system, device and method for loopback test technology of a memory controller. The memory controller may include a loopback test circuit, which may include: a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller; an inverter coupled to the output of the input buffer; and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to a second data output from the memory controller.

Description

Technical Field

[0001] The present disclosure relates to memory controller interfaces, and more particularly to electrical test circuits and methods for DDR5 controller Phy in system-on-chip (SoC) applications. Background Art

[0002] In recent years, the rapid growth of data centers, cloud computing, and artificial intelligence applications has stimulated the growing demand for memory bandwidth and double data rate (DDR) interface speeds. In 2018, the first generation of commercial double data rate type six synchronous graphics random access memory (GDDR6) devices for computer systems increased the speed of memory devices from 8Gb / s to 10-14Gb / s. The introduction of the DDR5 specification in late 2019 revolutionized the computing world with faster, higher capacity, and more powerful DDR5 DRAM devices. To support the higher speeds of DDR5 DRAM devices up to 6400MT / s, a series of new features were introduced, including decision feedback equalizer (DFE) and internal VREFCA.

[0003] Although the new loopback test capability is mandatory only for DDR5 DRAM devices, some DDR5 controllers have also taken advantage of the new protocol and implemented similar loopback functions in the DDR5 controller Phy. However, the existing DDR5 loopback function is purposefully designed and scaled down for DRAM devices with maximum simplification and friendly implementation, but is not optimized for the DDR5 controller Phy in terms of performance and reliability. First, the output test signal is a single-ended signal, which greatly reduces the speed performance and reliability of high-speed transmission through the test channel. As a result, the test speed is reduced to half or a quarter of the input traffic, and only a portion of the received data signal is looped back for comparison. Second, the existing loopback scheme can only test the receiver circuit and the DFE circuit, but not the read FIFO circuit and the entire transmitter circuit of the DDR5 controller Phy. Therefore, there is a need in the art for a better scheme that provides maximum speed performance and reliability and also achieves more complete coverage including the read FIFO and transmitter circuits. Summary of the invention

[0004] The present disclosure provides a system and method for loopback testing of a memory controller. In various embodiments, a memory controller with a double data rate (DDR) interface may include a loopback test circuit. The loopback test circuit may include two data paths. The first data path may loop back the DQ signal after the received data signal (DQ signal) passes through an input buffer (e.g., a first-in, first-out (FIFO) buffer). The first data path may include a first multiplexer coupled to the output of the input buffer, so that the DQ signal can be multiplexed with the data output from the memory controller. The Dq signal can be sent from the first multiplexer to a first output buffer (e.g., a write FIFO buffer). The second data path may include an inverter coupled to the output of the input buffer to invert the DQ signal and pass the inverted DQ signal to a second multiplexer, wherein the inverted DQ signal can be multiplexed with another data output from the memory controller. Then, the inverted DQ can be sent from the second multiplexer to a second output buffer. The looped back DQ signal and the inverted DQ signal can be transmitted by two output drivers of the memory controller interface in the form of fully differential signals (e.g., to an external test instrument). In some embodiments, the memory controller can be a DDR5 controller within a system on chip (SoC).

[0005] In an exemplary embodiment, a memory controller is provided that may include a loopback test circuit. The loopback test circuit may include a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to a second data output from the memory controller.

[0006] In another exemplary embodiment, a physical interface for a memory controller is provided. The physical interface may include a loopback test circuit, which may include a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to a second data output from the memory controller.

[0007] In yet another exemplary embodiment, a method for generating a differential loopback signal for a memory controller is provided. The method may include receiving an input data signal, generating an inverted data signal by inverting the input data signal, passing the input data signal through a first multiplexer, passing the inverted data signal through a second multiplexer, and outputting the input data signal and the inverted data signal as a differential signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A memory controller with a loopback test circuit according to an embodiment of the present disclosure is schematically shown.

[0009] Figure 2 is a flow chart of a process for generating a loopback test signal for a memory controller according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0010] Now, specific embodiments according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various figures are represented by the same reference numerals.

[0011] Figure 1 A memory controller 100 with a loopback test circuit 132 according to one embodiment of the present disclosure is schematically shown. The memory controller 100 may include an input 102 for receiving a data input signal, a receiver 104 coupled to the input 102, a decision feedback equalizer (DFE) 106 coupled to the receiver 104, and an input buffer 108 coupled to the output of the DFE 106. The input 102 may generally be referred to as a DQ pin, and the received data input signal may be referred to as a DQ signal. In one embodiment, the input buffer 108 may be implemented as a first-in-first-out (FIFO) buffer and is referred to as a read FIFO buffer or simply a read FIFO. In addition, the input 102, the receiver 104, the DFE 106, and the input buffer 108 may form an input data path. In one embodiment, the input data path may be part of a physical interface (PHY) of the memory controller 100. In some embodiments, the memory controller 100 may be a fifth generation double data rate (DDR5) memory controller, and in at least one embodiment, the memory controller 100 may be a DDR5 memory controller in a system on chip (SoC).

[0012] The memory controller 100 may also include a loopback test circuit 132, which may be configured to generate a loopback test signal for the DQ signal. The loopback test circuit 132 may include an inverter 110, a first multiplexer 112, and a second multiplexer 114. The inverter 110 may be coupled to the output of the input buffer 108 to generate an inverted signal for the DQ signal. The first multiplexer 112 may have a first input coupled to the output of the input buffer 108 and a second input coupled to the first data output from the memory controller 100. The second multiplexer 114 may have a first input coupled to the output of the inverter 110 and a second input coupled to the second data output from the memory controller 100. The first multiplexer 112 and the second multiplexer 114 may both be controlled by a flow control signal. The flow control signal may determine whether a signal from the first input or the second input of the first multiplexer 112 and the second multiplexer 114 may pass.

[0013] The memory controller 100 may also include a first output buffer 116, a first serializer 118, a first output driver 120, and a first output terminal 122. The first output buffer 116 may have an input coupled to the output of the first multiplexer 112 and an output coupled to the first serializer 118. The first output driver 120 may be coupled to the output of the serializer 118 and configured to drive the signal output from the multiplexer 112 on the first output terminal 122. The memory controller 100 may also include a second output buffer 124, a second serializer 126, a second output driver 128, and a second output terminal 130. The second output buffer 124 may have an input coupled to the output of the second multiplexer 114 and an output coupled to the second serializer 126. The second output driver 128 may be coupled to the output of the second serializer 126 and configured to drive the signal output from the second multiplexer 114 on the second output terminal 130.

[0014] In one implementation example, the original loopback data (e.g., DQ signal) may be sent to one of the output buffers (e.g., the first output buffer 116), and the inverted loopback data (e.g., the inverted DQ signal) may be sent to the other output buffer (e.g., the second output buffer 124). The loopback signal from the first output buffer 116 may be sent to the first output driver 120 (via the first serializer 118), and the inverted loopback signal from the second output buffer 124 may be sent to the second output driver 128 (via the second serializer 126). Because the signals of the first output driver 120 and the second output driver 128 are fully complementary to each other, a fully differential signal may be formed between the output terminals 122 and 130. In one embodiment, the output terminal 122 may be referred to as the positive terminal of the loopback DQ signal, and the output terminal 130 may be referred to as the negative terminal of the loopback DQ signal.

[0015] In some embodiments, each of the first output buffer 116 and the second output buffer 124 may be implemented as a first-in-first-out (FIFO) buffer and is referred to as a write FIFO buffer or simply a write FIFO. In addition, the first output buffer 116, the first serializer 118, the first output driver 120, and the first output terminal 122 may form a first output data path; the second output buffer 124, the second serializer 126, the second output driver 128, and the second output terminal 130 may form a second output data path. In some embodiments, the first output data path and the second output data path may be part of a physical interface (PHY) of the memory controller 100.

[0016] In some embodiments, the loopback test circuit 132 may also be part of a physical interface (PHY) of the memory controller 100. In these embodiments, the physical interface (PHY) may include an input data path, first and second output data paths, and the loopback test circuit 132.

[0017] In some other embodiments, the loopback test circuit 132 can be implemented as glue logic between the physical interface of the memory controller 100 and other circuits of the memory controller 100. In these embodiments, the loopback data stream and test circuit including the multiplexer can be implemented outside the physical interface (PHY). The input data from the PHY can be looped back to the multiplexer inside the glue logic. The output data from the memory controller can be multiplexed with the loopback data before being sent to the output buffer of the memory controller PHY. The benefit of this embodiment is that the macros of the memory controller PHY and the memory controller can remain unchanged, and the implementation cost and difficulty of the loopback test circuit can be optimized to a minimum.

[0018] In yet other embodiments, the loopback test circuit 132 may be implemented as part of the circuitry of the memory controller 100 .

[0019] Figure 2 2 is a flow chart of a process 200 for generating a loopback test signal for a memory controller according to one embodiment of the present disclosure. In block 202, an input data signal may be received. For example, a receiver 104 coupled to an input terminal 102 of a memory controller 100 may generate an input data signal by comparing a signal received by the input terminal 102 with a reference voltage Vref. An input data path of the memory controller 100 may further process the received input data signal (e.g., through a DFE 106 and input to an input buffer 108). In block 204, an inverted data signal may be generated by inverting the input data signal. For example, the received input data signal may be sent to an inverter 110, and the inverter 110 may generate an inverted data signal by inverting the received input data signal.

[0020] In block 206, the input data signal may pass through the first multiplexer. In block 208, the inverted data signal may pass through the second multiplexer. For example, the received input data signal may be sent to the first multiplexer 112, and the inverted data signal generated by the inverter 110 may be sent to the second multiplexer 114. The first multiplexer 112 and the second multiplexer 114 may be controlled by a flow control signal to pass the loopback test signal or to pass the data output from the memory controller 100. In process 200, the flow control signal may cause the first multiplexer 112 and the second multiplexer 114 to pass the loopback test signal (e.g., the input data signal and the inverted data signal).

[0021] In block 210, the input data signal and the inverted data signal may be output as differential signals. For example, the received input data signal and the inverted data signal may be passed through first and second output buffers, respectively, and driven out at corresponding output terminals 122 and 130. The two loopback test signals may be fully complementary and form a complete differential signal to be sent to an external test instrument.

[0022] Embodiments of the present disclosure may provide fully differential signals for loopback testing. Fully differential signals may provide maximum speed performance and reliability. In contrast, existing loopback testing techniques use single-ended signals, reduce the test speed to half or a quarter of the input traffic, and only loop back a portion of the received DQ for comparison. In addition, embodiments of the present disclosure include not only a receiver circuit and a DFE circuit, but also a read FIFO circuit of a memory controller PHY and the entire transmitter circuit.

[0023] In one exemplary embodiment, a memory controller is provided that may include a loopback test circuit. The loopback test circuit may include a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to a second data output from the memory controller.

[0024] In one embodiment, the memory controller may further include a physical interface coupled to the loopback test circuit. The physical interface may include a first driver configured to drive an output data signal from the input buffer and a second driver configured to drive an output inverted data signal from the output of the inverter. The data signal may be a received data signal, and the inverted data signal may be a received data signal inverted by the inverter. Furthermore, the data signal and the inverted data signal may form a differential signal driven and output by the first driver and the second driver.

[0025] In one embodiment, the physical interface may further include: a decision feedback equalizer (DFE) having an output coupled to an input of a receiver and coupled to an input of an input buffer, a first output buffer coupled to the output of a first multiplexer, a first serializer coupled between the output of the first output buffer and the input of the first driver, a second output buffer coupled to the output of the second multiplexer, and a second serializer coupled between the output of the second output buffer and the input of the second driver.

[0026] In one embodiment, each of the first output buffer and the second output buffer may be a first-in-first-out (FIFO) buffer.

[0027] In one embodiment, the loopback test circuit may be part of a physical interface. The physical interface may also include a first driver configured to drive an output data signal from the input buffer and a second driver configured to drive an output inverted data signal from the output of the inverter. The data signal may be a received data signal, and the inverted data signal may be a received data signal inverted by the inverter. The data signal and the inverted data signal may form a differential signal driven output by the first driver and the second driver.

[0028] In one embodiment, the physical interface may further include: a decision feedback equalizer (DFE) having an output coupled to an input of a receiver and coupled to an input of an input buffer, a first output buffer coupled to the output of a first multiplexer, a first serializer coupled between the output of the first output buffer and the input of the first driver, a second output buffer coupled to the output of the second multiplexer, and a second serializer coupled between the output of the second output buffer and the input of the second driver.

[0029] In one embodiment, each of the first output buffer and the second output buffer may be a first-in-first-out (FIFO) buffer.

[0030] In one embodiment, the input buffer may be a first-in-first-out (FIFO) buffer.

[0031] In another exemplary embodiment, a physical interface for a memory controller is provided. The physical interface may include a loopback test circuit, which may include a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to a second data output from the memory controller.

[0032] In one embodiment, the physical interface may further include a first driver configured to drive an output data signal from the input buffer and a second driver configured to drive an output inverted data signal from the output of the inverter. The data signal may be a received data signal, and the inverted data signal may be a received data signal inverted by the inverter. Furthermore, the data signal and the inverted data signal may form a differential signal driven and output by the first driver and the second driver.

[0033] In one embodiment, the physical interface may further include a decision feedback equalizer (DFE) having an output coupled to an input of a receiver and coupled to an input of an input buffer, a first output buffer coupled to the output of a first multiplexer, a first serializer coupled between the output of the first output buffer and the input of the first driver, a second output buffer coupled to the output of the second multiplexer, and a second serializer coupled between the output of the second output buffer and the input of the second driver.

[0034] In one embodiment, each of the first output buffer and the second output buffer may be a first-in-first-out (FIFO) buffer.

[0035] In one embodiment, the input buffer may be a first-in-first-out (FIFO) buffer.

[0036] In yet another exemplary embodiment, a method for generating a differential loopback signal for a memory controller is provided. The method may include receiving an input data signal, generating an inverted data signal by inverting the input data signal, passing the input data signal through a first multiplexer, passing the inverted data signal through a second multiplexer, and outputting the input data signal and the inverted data signal as a differential signal.

[0037] In one embodiment, the method may further include passing the input data signal through a decision feedback equalizer (DFE) and an input buffer before sending the input data signal to an inverter to generate the inverted data signal and the first multiplexer.

[0038] In one embodiment, the first multiplexer may have a first input coupled to the output of the input buffer and a second input coupled to a first data output from the memory controller, and the second multiplexer may have a first input coupled to the output of an inverter and a second input coupled to a second data output from the memory controller.

[0039] In one embodiment, the input buffer may be a first-in-first-out (FIFO) buffer.

[0040] In one embodiment, the memory controller may include a physical interface including a first driver configured to drive an output input data signal and a second driver configured to drive an output inverted data signal. The input data signal and the inverted data signal may form a differential signal driven and output by the first driver and the second driver.

[0041] In one embodiment, the physical interface may also include a first output buffer coupled to the output of the first multiplexer, a first serializer coupled between the output of the first output buffer and the input of the first driver, a second output buffer coupled to the output of the second multiplexer, and a second serializer coupled between the output of the second output buffer and the input of the second driver.

[0042] In one embodiment, each of the first output buffer and the second output buffer may be a first-in-first-out (FIFO) buffer.

[0043] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the appended claims.

Claims

1. A memory controller, characterized in that: include: A loopback test circuit, comprising: a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, wherein the input buffer has an input coupled to an output of a decision feedback equalizer to receive an input data signal passing through the feedback equalizer, and the first multiplexer allows either the first data signal from the memory controller or the input data signal from the input buffer to pass through: an inverter coupled to an output of the input buffer to generate an inverted data signal of an input data signal passing through the feedback equalizer and the input buffer; as well as a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to the second data output from the memory controller, wherein the second multiplexer allows either the second data signal from the memory controller or the inverted data signal to pass therethrough.

2. The memory controller according to claim 1, wherein: It also includes a physical interface coupled to the loopback test circuit, the physical interface including: a first driver, which is configured to drive an output data signal from the input buffer; and a second driver, which is configured to drive an output inverted data signal from the output of the inverter, wherein the data signal is a received data signal, the inverted data signal is the received data signal inverted by the inverter, and the data signal and the inverted data signal form a differential signal driven output by the first driver and the second driver.

3. The memory controller according to claim 2, characterized in that: The physical interface further comprises: the decision feedback equalizer (DFE) having an input coupled to the receiver; a first output buffer coupled to an output of the first multiplexer; a first serializer coupled between an output of the first output buffer and an input of the first driver; a second output buffer coupled to an output of the second multiplexer; and A second serializer is coupled between the output of the second output buffer and the input of the second driver.

4. The memory controller according to claim 3, characterized in that: Each of the first output buffer and the second output buffer is a first-in-first-out (FIFO) buffer.

5. The memory controller according to claim 1, wherein: The loopback test circuit is part of a physical interface, which also includes: a first driver, which is configured to drive an output data signal from the input buffer; and a second driver, which is configured to drive an output inverted data signal from the output of the inverter, wherein the data signal is a received data signal, the inverted data signal is the received data signal inverted by the inverter, and the data signal and the inverted data signal form a differential signal driven output by the first driver and the second driver.

6. The memory controller according to claim 5, characterized in that: The physical interface further comprises: the decision feedback equalizer (DFE) having an input coupled to the receiver; a first output buffer coupled to an output of the first multiplexer; a first serializer coupled between an output of the first output buffer and an input of the first driver; a second output buffer coupled to an output of the second multiplexer; and A second serializer is coupled between the output of the second output buffer and the input of the second driver.

7. The memory controller according to claim 3, characterized in that: Each of the first output buffer and the second output buffer is a first-in-first-out (FIFO) buffer.

8. The memory controller according to claim 1, wherein: The input buffer is a first-in-first-out (FIFO) buffer.

9. A physical interface for a memory controller, characterized in that: include: A loopback test circuit, comprising: a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, wherein the input buffer has an input coupled to an output of a decision feedback equalizer to receive an input data signal passing through the feedback equalizer, and the first multiplexer allows either the first data signal from the memory controller or the input data signal from the input buffer to pass through: an inverter coupled to an output of the input buffer to generate an inverted data signal of an input data signal passing through the feedback equalizer and the input buffer; and a second multiplexer having a first input coupled to the output of the inverter and a second input coupled to the second data output from the memory controller, wherein the second multiplexer allows either the second data signal from the memory controller or the inverted data signal to pass therethrough.

10. The physical interface according to claim 9, characterized in that: Also includes: a first driver configured to drive an output data signal from the input buffer; and a second driver configured to drive an output of an inverted data signal from the output of the inverter, wherein the data signal is a received data signal, the inverted data signal is the received data signal inverted by the inverter, and the data signal and the inverted data signal form a differential signal driven and output by the first driver and the second driver.

11. The physical interface according to claim 10, characterized in that: Also includes: the decision feedback equalizer (DFE) having an input coupled to the receiver; a first output buffer coupled to an output of the first multiplexer; a first serializer coupled between an output of the first output buffer and an input of the first driver; a second output buffer coupled to an output of the second multiplexer; as well as A second serializer is coupled between the output of the second output buffer and the input of the second driver.

12. The physical interface according to claim 11, characterized in that: Each of the first output buffer and the second output buffer is a first-in-first-out (FIFO) buffer.

13. The physical interface according to claim 9, characterized in that: The input buffer is a first-in-first-out (FIFO) buffer.

14. A method for a memory controller to generate a differential loopback signal, characterized in that: include: receiving an input data signal at a receiver of the memory controller; Passing the input data signal through a decision feedback equalizer (DFE) and an input buffer; generating an inverted data signal at an inverter by inverting an input data signal received through the decision feedback equalizer and the input buffer; Passing the input data signal received by the decision feedback equalizer and the input buffer through a first multiplexer; passing the inverted data signal through a second multiplexer; as well as The input data signal and the inverted data signal are output as a differential signal.

15. The method according to claim 14, characterized in that The first multiplexer has a first input coupled to the output of the input buffer and a second input coupled to a first data output from the memory controller, and the second multiplexer has a first input coupled to the output of an inverter and a second input coupled to a second data output from the memory controller.

16. The method according to claim 15, characterized in that The input buffer is a first-in-first-out (FIFO) buffer.

17. The method according to claim 14, characterized in that The memory controller includes a physical interface, which includes a first driver configured to drive and output the input data signal and a second driver configured to drive and output the inverted data signal, and the input data signal and the inverted data signal form a differential signal driven and output by the first driver and the second driver.

18. The method according to claim 17, characterized in that The physical interface also includes: a first output buffer coupled to an output of the first multiplexer; a first serializer coupled between an output of the first output buffer and an input of the first driver; a second output buffer coupled to an output of the second multiplexer; and A second serializer is coupled between the output of the second output buffer and the input of the second driver.

19. The method according to claim 18, characterized in that Each of the first output buffer and the second output buffer is a first-in-first-out (FIFO) buffer.

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