Side-to-side adjacent memory cell interference mitigation

Abstract

This invention is entitled "Two-Side Neighbor Memory Cell Disturb Suppression." This invention discloses techniques for two-side neighbor memory cell disturb suppression in a non-volatile storage system. During a read of a target memory cell, the storage system applies a read reference voltage of a suitable magnitude to a target word line to compensate for a disturbance from a neighbor cell on a second unselected word line on the other side of the target word line, while applying a read pass voltage of a suitable magnitude to a first unselected word line adjacent to the target word line to compensate for a disturbance from a neighbor cell on the first unselected word line. The read pass voltage can compensate for a disturbance due to charge added when programming a cell on the first unselected word line after programming the target cell. The read reference voltage can compensate for a disturbance due to charge movement in the vicinity of the target cell caused by charge stored in a cell on the second unselected word line.

Description

Technical Field

[0001] This disclosure relates in general to the field of semiconductor devices, and more specifically to interference suppression between adjacent memory cells on both sides. Background Technology

[0002] The robust growth in demand for portable consumer electronics devices has driven the need for high-capacity storage devices. Non-volatile semiconductor memory devices (also referred to herein as "non-volatile memory systems" or "non-volatile memory systems"), such as flash memory, are widely used to meet the increasing demands for storing and exchanging digital information. Their portability, versatility, and rugged design, along with their high reliability and large capacity, make these memory devices ideal for use in a variety of host electronic devices, including, for example, digital cameras, digital music players, video game controllers, PDAs, cellular phones, and desktop, laptop, and notebook computers. Typically, host electronic devices provide power to non-volatile memory systems.

[0003] Non-volatile semiconductor memory devices contain non-volatile memory cells that can be programmed to store data. Typically, memory cells are programmed with multiple data states. Using a greater number of data states allows each memory cell to store more bits. For example, four data states can be used to store two bits per memory cell, eight data states can be used to store three bits per memory cell, 16 data states can be used to store four bits per memory cell, and so on. To read data back from a memory cell, a read reference voltage is typically used to determine which data state the memory cell is currently in.

[0004] In addition to the capacity increases resulting from multi-state memory architectures, consumers have seen significant advantages due to the historically stable reduction in the physical size of memory cells. Smaller memory cells can be stacked more densely on a given die area, allowing users to access more memory capacity at the same price as older memory technologies. To achieve the advantage of higher memory capacity with a fixed die size, these smaller memory cells must be stacked more tightly together. However, doing so can lead to greater interference between adjacent memory cells on the target memory cell.

[0005] Once a memory cell is programmed, it is crucial to be able to reread its programming state with high reliability. However, due to factors including interference from neighboring memory cells, the sensed programming state may sometimes differ from the expected programming state. This interference from neighboring memory cells increases if smaller memory cells are stacked more closely together. Summary of the Invention

[0006] A memory device is provided, comprising: control circuitry configured to be connected to: a first non-volatile memory cell connected to a first word line, a second non-volatile memory cell connected to a second word line adjacent to the first word line, and a third non-volatile memory cell connected to a third word line adjacent to the first word line, the control circuitry being configured to: apply two or more read reference voltages to the first word line, and apply two or more read pass voltages to the second word line for each of the two or more read reference voltages, wherein the two or more read reference voltages are associated with the same data state; and sense each corresponding first memory cell based on a combination of a first voltage from the two or more read reference voltages and a second voltage from the two or more read pass voltages to determine a condition of the corresponding first memory cell, the first voltage depending on the state of an adjacent cell on the third word line, and the second voltage depending on the state of an adjacent cell on the second word line. Attached Figure Description

[0007] Elements with similar numbers refer to common components in different attached drawings.

[0008] Figure 1A It is a block diagram of one implementation of a storage system connected to the host.

[0009] Figure 1B This is a block diagram of one implementation scheme of the front-end processor circuit.

[0010] Figure 2A This is a block diagram of one implementation scheme for the back-end processor circuit.

[0011] Figure 2B This is a block diagram of one implementation scheme of a memory package.

[0012] Figure 3A This is a functional block diagram of one implementation scheme for a memory die.

[0013] Figure 3B This is a functional block diagram of one implementation of an integrated memory component.

[0014] Figure 4A A side view depicts one embodiment of an integrated memory assembly stacked on a substrate.

[0015] Figure 4B A side view depicts one embodiment of an integrated memory assembly stacked on a substrate.

[0016] Figure 5 This is a perspective view as part of an exemplary embodiment of a monolithic three-dimensional memory array that may include a memory structure.

[0017] Figure 6A This is a block diagram illustrating an exemplary organization of memory structures.

[0018] Figure 6B It is a block diagram depicting a top view of a portion of a block from a memory structure.

[0019] Figure 6C A portion of one embodiment of a three-dimensional memory structure is depicted, showing along... Figure 6B A sectional view of line AA.

[0020] Figure 6D Depicting Figure 6C A cross-sectional view of region 629, which includes a portion of vertical column 632.

[0021] Figure 7 This is a flowchart describing one implementation of the process for programming a NAND string of memory cells organized into an array.

[0022] Figure 8A An exemplary threshold voltage distribution for a memory array is shown when each memory cell stores three bits of data.

[0023] Figure 8B Describing for Figure 8A An implementation of multi-stage programming with three examples per unit.

[0024] Figure 9 The threshold Vt distribution of one implementation of fuzzy-fine programming is depicted.

[0025] Figure 10 It is a flowchart that provides further details on programming memory cell blocks using a fuzzy-fine programming process.

[0026] Figure 11 The concepts of NWI and lateral DR are explained graphically.

[0027] Figure 12A The Vt distribution is depicted to show the effect of lateral DR.

[0028] Figure 12B The Vt distribution of the memory cell is shown to further explain NWI.

[0029] Figure 13 An implementation scheme is described in which a flowchart depicts the process of suppressing interference between adjacent memory cells on both sides.

[0030] Figure 14 An implementation scheme is described, which describes the process of sensing adjacent memory cells and storing state information.

[0031] Figure 15 A timing diagram of the voltage applied to the word line in one embodiment of the process is depicted.

[0032] Figures 16A to 16D It is a combination of Figure 15 Flowcharts for the implementation schemes of the four scenarios discussed.

[0033] Figure 17 This is a flowchart of an implementation scheme for determining and using LLR to simultaneously suppress interference between adjacent cells on both sides. Detailed Implementation

[0034] The technology of the present invention will now be described with reference to the accompanying drawings, which, in various embodiments, relate to interference suppression between adjacent memory cells in a non-volatile memory system. The basic memory cell in a non-volatile memory system is a memory cell. A memory cell can be programmed into a data state by storing charge in it. For example, the threshold voltage of a NAND memory cell can be set to a target level by programming charge into a charge storage region such as a charge trapping layer. The amount of charge stored in the charge trapping layer establishes the threshold voltage (Vt) of the memory cell.

[0035] Due to the charges associated with one or more adjacent memory cells, a real and / or apparent offset of Vt associated with the target memory cell may occur. To account for the real and / or apparent offset of Vt, different compensations may be applied based on the different possible conditions of adjacent cells on either side of the target memory cell. In this document, "adjacent memory cell" means a cell directly adjacent to the target memory cell. In some embodiments, the target memory cell and two adjacent memory cells are located on the same NAND string. In some embodiments, the target memory cell is connected to a target word line, one adjacent cell is connected to a first adjacent word line, and another adjacent cell is connected to a second adjacent word line. In this document, "adjacent word line" means a word line directly adjacent to the target word line. In some embodiments, memory cells are programmed sequentially via word lines. Therefore, the programming order may be, for example, WLn-1, WLn, WLn+1, etc. For the purposes of discussion, WLn may be referred to as the target word line.

[0036] In some cases, programming adjacent memory cells after programming the target memory cell can alter the apparent Vt of the target memory cell. This interference is referred to herein as near-word line interference (NWI). When adjacent cells are programmed, NWI can shift the apparent Vt of the target memory cell due to the electric field introduced by the charge trapping layer injected into the adjacent cells.

[0037] In some cases, the charge stored on adjacent memory cells can alter the actual Vt of the target memory cell. This interference may be referred to herein as lateral data retention (lateral DR). Lateral DR is the offset of trapped electrons or holes from cell to cell or from cell to the region between cells. This offset occurs within the charge trapping layer because electrons and holes can move around within a small area within the charge trapping layer. Lateral DR depends on the amount of charge stored in the charge trapping layer of the adjacent memory cells. More charge (and therefore a higher Vt) results in greater interference with the target memory cell.

[0038] One implementation of the storage system compensates for both NWI and lateral DR. In one implementation, compensation for NWI applies to adjacent memory cells programmed after the target memory cell to be read is programmed. In another implementation, compensation for lateral DR applies to adjacent memory cells programmed before the target memory cell is programmed. Therefore, when reading a memory cell connected to a target word line, the storage system compensates for the NWI of adjacent cells connected to a first adjacent word line and compensates for the lateral DR of adjacent cells connected to a second adjacent word line.

[0039] One embodiment of the memory system compensates for lateral DR by applying a read reference voltage of appropriate magnitude to the target word line and for non-volatile memory (NWI) by applying a read pass voltage of appropriate magnitude to the aforementioned first adjacent word line. In one embodiment, the amount of compensation for lateral DR depends on the data state of the adjacent memory cell. When the adjacent cell has more stored charge, a larger compensation for lateral DR can be applied, which may correspond to a higher Vt. In one embodiment, the amount of compensation for NWI depends on the data state of the adjacent memory cell. When the adjacent cell is programmed after the target cell has been programmed, a larger compensation for NWI can be applied.

[0040] The combined NWI compensation and lateral DR compensation improve the Vt margin. The combined NWI compensation and lateral DR compensation reduce the bit error rate (BER). NWI compensation is particularly useful for adjacent memory cells programmed after the target cell has been programmed. However, NWI compensation may be less useful for adjacent memory cells programmed before the target cell has been programmed. Therefore, in this embodiment, NWI compensation is applied only to the aforementioned first adjacent word line. Furthermore, the lateral DR compensation applied to the target word line is based on the data state of adjacent cells on the aforementioned second adjacent word line.

[0041] It should be understood that the invention can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the invention to those skilled in the art. In fact, the invention is intended to cover alternatives, modifications, and equivalents of these embodiments, all of which are included within the scope and spirit of the invention as defined by the appended claims. Furthermore, numerous specific details are set forth in the following detailed description of the invention in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without such specific details.

[0042] Figures 1A to 6D An example of a storage system that can be used to implement the techniques disclosed herein is described.

[0043] Figure 1AThis is a block diagram of one embodiment of a storage system 100 connected to host 120. The storage system 100 can implement the techniques disclosed herein. Many different types of storage systems can be used with the techniques disclosed herein. An exemplary storage system is a solid-state drive (“SSD”); however, other types of storage systems may also be used. The storage system 100 includes a memory controller 102, a memory package 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. The memory controller 102 includes a front-end processor circuitry (FEP) 110 and one or more back-end processor circuitry (BEP) 112. In one embodiment, the FEP circuitry 110 is implemented on an ASIC. In one embodiment, each BEP circuitry 112 is implemented on a separate ASIC. The ASICs for each of the BEP circuitry 112 and the FEP circuitry 110 are implemented on the same semiconductor, such that the memory controller 102 is fabricated as a system-on-a-chip (“SoC”). Both the FEP 110 and the BEP 112 include their own processors. In one implementation, FEP 110 and BEP 112 operate in a master-slave configuration, where FEP 110 is the master device and each BEP 112 is a slave device. For example, FEP circuit 110 implements a flash translation layer that performs memory management (e.g., garbage collection, wear leveling, etc.), logic-to-physical address translation, communication with the host, DRAM (local volatile memory) management, and overall operation management of SSDs (or other non-volatile memory systems). BEP circuit 112 manages memory operations within memory package 104 based on requests from FEP circuit 110. For example, BEP circuit 112 can perform read, erase, and program processes. Additionally, BEP circuit 112 can perform buffer management, set specific voltage levels required by FEP circuit 110, perform error correction (ECC), control the switching mode interface to the memory package, etc. In one implementation, each BEP circuit 112 is responsible for its own set of memory packages. Memory controller 102 is an example of control circuitry.

[0044] In one embodiment, there are multiple memory packages 104. Each memory package 104 may include one or more memory dies. In one embodiment, each memory die in the memory package 104 utilizes NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package 104 may include other types of memory; for example, the memory package may include phase-change memory (PCM) memory.

[0045] In one embodiment, the memory controller 102 communicates with the host 120 using an interface 130 that implements NVM Express (NVMe) via PCI Express (PCIe). To operate in conjunction with the storage system 100, the host 120 includes a host processor 122, host memory 124, and a PCIe interface 126 that communicate via a bus 128. The host memory 124 is the host's physical memory and can be DRAM, SRAM, non-volatile memory, or another type of storage device. The host 120 is external to and separate from the storage system 100. In one embodiment, the storage system 100 is embedded within the host 120.

[0046] Figure 1B This is a block diagram of one implementation scheme of FEP circuit 110. Figure 1B A PCIe interface 150 communicating with a host 120 and a host processor 152 communicating with the PCIe interface are shown. The host processor 152 can be any type of processor known in the art suitable for implementation. The host processor 152 communicates with a network on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, typically between cores in a SoC. NOCs can span synchronous and asynchronous clock domains or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and cross-switch interconnects. Compared to other designs, NOCs improve the scalability of SoCs and the power efficiency of complex SoCs. The wires and links of a NOC are shared by many signals. High parallelism is achieved because all links in a NOC can operate simultaneously on different data packets. Therefore, as the complexity of integrated subsystems increases, NOCs offer enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and DRAM controller 162. The DRAM controller 162 operates and communicates with the DRAM (e.g., DRAM 106). SRAM 160 is the local RAM used by the memory processor 156. The memory processor 156 runs the FEP circuitry and performs various memory operations. Two PCIe interfaces, 164 and 166, also communicate with the NOC. Figure 1B In one embodiment, the memory controller 102 includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0047] Figure 2A This is a block diagram of one implementation scheme of BEP circuit 112. Figure 2A A diagram is shown for communicating with FEP circuit 110 (e.g., with...). Figure 1B The PCIe interface 200 communicates with one of the PCIe interfaces 164 and 166. The PCIe interface 200 communicates with two NOCs 202 and 204. In one implementation, the two NOCs may be combined into a single large NOC. Each NOC (202 / 204) is connected to SRAM (230 / 260), buffers (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256).

[0048] ECC engines 226 / 256 are used to perform error correction, as is known in the art. Herein, ECC engines 226 / 256 may be referred to as the controller ECC engine. XOR engines 224 / 254 are used to perform XOR operations on data, enabling data to be combined and stored in a recoverable manner in the event of programming errors. In one implementation, XOR engines 224 / 254 are capable of recovering data that could not be decoded using ECC engines 226 / 256.

[0049] Data path controller 222 is connected to memory interface 228 for communicating with the integrated memory component via four channels. Therefore, top NOC 202 is associated with memory interface 228 for the four channels used to communicate with the integrated memory component, and bottom NOC 204 is associated with memory interface 258 for the four additional channels used to communicate with the integrated memory component. In one embodiment, each memory interface 228 / 258 includes four switching mode interfaces (TM interfaces), four buffers, and four schedulers. One scheduler, buffer, and TM interface exist for each of the channels. The processor can be any standard processor known in the art. Data path controller 222 / 252 can be a processor, FPGA, microprocessor, or other type of controller. XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuitry referred to as hardware accelerators. In other embodiments, XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The scheduler, buffers, and TM interfaces are hardware circuitry. In other embodiments, the memory interface (circuit for communicating with the memory die) can be... Figure 2A The different structures are depicted. Additionally, they have the same... Figure 1B and Figure 2A Controllers with different architectures can also be used with the techniques described in this article.

[0050] Figure 2B This is a block diagram of one embodiment of a memory package 104 including multiple memory dies 300 connected to a memory bus (data lines and chip enable lines) 322. The memory bus 322 is connected to a switching mode interface 228 for communication with the TM interface of the BEP circuit 112 (see, for example...). Figure 2A In some implementations, the memory package may include a small controller connected to the memory bus and the TM interface. In summary, the memory package 104 may have eight or 16 memory dies; however, other numbers of memory dies may also be implemented. The techniques described herein are not limited to any particular number of memory dies.

[0051] Figure 3A This is a functional block diagram of one implementation scheme of the memory die 300. Figure 2B Each of one or more memory dies 300 can be implemented as Figure 3A The memory die 300. Figure 3A The components depicted are circuits. In one embodiment, each memory die 300 includes a memory structure 326, control circuitry 310, read / write circuitry 328, and decoders 324 / 332, all of which are circuits. The memory structure 326 is addressable via word lines through row decoder 324 and via bit lines through column decoder 332. The read / write circuitry 328 includes a plurality of sense blocks 340 (which include SB1, SB2, ..., SBp (sensor circuitry)) and allows one (or more) data pages of a plurality of memory cells to be read or programmed in parallel. In one embodiment, each sense block includes a sense amplifier and a set of latches connected to the bit lines. The latches store data to be written and / or data that has been read. The sense block includes a bit line driver.

[0052] Commands and data are transmitted between controller 102 and memory die 300 via memory controller interface 315 (also referred to as the “communication interface”). Memory controller interface 315 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 315 include a switching mode interface and an Open NAND Flash Interface (ONFI). Other I / O interfaces may also be used. For example, memory controller interface 315 may implement a switching mode interface connected to the switching mode interface of memory interface 228 / 258 of memory controller 102. In one embodiment, memory controller interface 315 includes a set of input and / or output (I / O) pins connected to memory bus 322. In one embodiment, memory bus 322 is connected to memory controller 102 as part of the switching mode interface.

[0053] Control circuitry 310 cooperates with read / write circuitry 328 to perform memory operations (e.g., write, read, erase, etc.) on memory structure 326. In one embodiment, control circuitry 310 includes state machine 312, on-chip address decoder 314, power control 316, memory controller interface 315, and memory area 318. State machine 312 provides die-level control of memory operations. In one embodiment, state machine 312 may be software-programmable. In other embodiments, state machine 312 does not use software and is implemented entirely in hardware (e.g., electronic circuitry). In some embodiments, state machine 312 may be replaced by a microcontroller or microprocessor. In one embodiment, control circuitry 310 includes buffers such as registers, ROM fuses, and other storage devices for storing default values ​​such as base voltage and other parameters. Default values ​​and other parameters may be stored in areas of memory structure 326 (e.g., structure parameter storage device 326a). These default values ​​may be updated from time to time.

[0054] The on-chip address decoder 314 provides an address interface between the address used by the controller 102 and the hardware address used by the decoders 324 and 332. The power control 316 controls the power and voltage supplied to the word lines and bit lines during memory operations. The power control 316 may include a charge pump for generating voltage.

[0055] Storage area 318 can be used to store parameters for operating memory structure 326. Storage area 318 may include volatile or non-volatile memory. In some embodiments, parameters include a read reference voltage. In one embodiment, storage area 318 contains a lookup table associating SW with BER. Memory structure 326 has storage area 326a, which may also contain a copy of the parameters for operating memory structure 326. In some embodiments, when memory die 300 is powered on, parameters are copied from storage area 326a to storage area 318.

[0056] For the purposes of this document, control circuitry 310, either alone or in combination with read / write circuitry 328 and decoders 324 / 332, includes control circuitry connected to memory structure 326. Control circuitry is circuitry that performs the functions described below in the flowcharts. In other embodiments, control circuitry may consist solely of controller 102 (or other controllers), which is circuitry combined with software (e.g., firmware) to perform the functions described below in the flowcharts. In one embodiment, control circuitry is a controller, where the controller is circuitry that does not use hardware. In another alternative, control circuitry includes controller 102 and control circuitry 310, which perform the functions described below in the flowcharts. In another embodiment, control circuitry, either alone or in combination with controller 102, includes state machine 312 (and / or microcontroller and / or microprocessor). In another alternative, control circuitry includes controller 102, control circuitry 310, read / write circuitry 328, and decoders 324 / 332, which perform the functions described below in the flowcharts. In other embodiments, control circuitry includes one or more circuits operating non-volatile memory.

[0057] In one embodiment, memory structure 326 includes a monolithic three-dimensional memory array of non-volatile memory cells, wherein multiple memory stages are formed over a single substrate such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of the memory cell array, having an active region disposed over a silicon (or other type) substrate. In one example, the non-volatile memory cells of memory structure 326 include vertical NAND strings with charge-trapping material, such as those described, for example, in U.S. Patent 9,721,662, the entire contents of which are incorporated herein by reference. In another embodiment, memory structure 326 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells utilizing floating gates, such as those described, for example, in U.S. Patent 9,082,502, the entire contents of which are incorporated herein by reference. Other types of memory cells (e.g., NOR flash memory) may also be used.

[0058] The exact type of memory array architecture or memory cell included in memory structure 326 is not limited to the examples described above. Many different types of memory array architecture or memory cell technologies can be used to form memory structure 326. Implementing the new embodiments claimed herein does not require a specific non-volatile memory technology. Other examples of technologies suitable for memory cells in memory structure 326 include ReRAM memory, magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), phase-change memory (e.g., PCM), etc. Examples of suitable technologies for the architecture of memory structure 326 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, etc.

[0059] An example of ReRAM, or PCMRAM, or crosspoint memory includes reversible resistive switching elements arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0060] Magnetoresistive RAM (MRAM) stores data using magnetic storage elements. Each element consists of two ferromagnetic plates, each of which remains magnetized, separated by a thin insulating layer. One of the plates is a permanent magnet set to a specific polarity; the magnetization of the other plate can be changed to match the magnetization of an external magnetic field to store memory. The storage device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell is located between a pair of write lines arranged perpendicular to each other, parallel to the cell, one above and one below. When current passes through them, an induced magnetic field is generated.

[0061] Phase change memory (PCM) utilizes the unique properties of chalcogenide glasses. One implementation uses a Ge2Sb2Te5 alloy to achieve a phase change by electrically heating the phase change material. The programming dose is an electrical pulse of varying amplitude and / or length, resulting in different resistance values ​​in the phase change material.

[0062] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, but encompass many related memory structures within the technical essence and scope described herein and as understood by those skilled in the art.

[0063] Figure 3B A functional block diagram of one embodiment of an integrated memory assembly 306 is depicted. The integrated memory assembly 306 can be used in a memory package 104 within a memory system 100. In one embodiment, the integrated memory assembly 306 includes two types of semiconductor dies (or more simply, "dies"). A memory structure die 302 includes a memory structure 326. The memory structure 326 may contain non-volatile memory cells. A control die 304 includes control circuitry 310. In some embodiments, the control die 304 is configured to connect to the memory structure 326 within the memory structure die 302. For example, the control circuitry 310 is configured to connect to the non-volatile memory cells within the memory structure 326 within the memory structure die 302. In some embodiments, the memory structure die 302 and the control die 304 are coupled together. The control circuitry 310 includes a state machine 312, an address decoder 314, a power control 316, a memory controller interface 315, a memory area 318, and an ECC engine 330. The memory area may store parameters, such as a read reference voltage. The control circuit 310 also includes a read / write circuit 328. In another embodiment, a portion of the read / write circuit 328 is located on the control die 304, and a portion of the read / write circuit 328 is located on the memory structure die 302. As used herein, the term "appendix" may include, but is not limited to, memory die 300, control die 304, memory package 104, memory system 100, memory controller 102, or host system 120 including memory system 100.

[0064] ECC engine 330 is configured to decode and correct codewords. Hereinafter, ECC engine 330 may be referred to as an on-die ECC engine. In one embodiment, on-die ECC engine 330 is configured to encode data bits from memory controller 102 into codewords containing data bits and parity bits. The control circuitry stores this codeword in memory structure 326. In one embodiment, on-die ECC engine 330 is configured to decode codewords read back from memory structure 326.

[0065] Any subset of the components in the control circuitry 310 of the control die 304 can be considered as control circuitry. In another alternative, control circuitry includes controller 102 and control circuitry 310 of the control die 304, performing the functions described below in the flowchart. Control circuitry may consist only of hardware or a combination of hardware and software (including firmware). For example, a firmware-programmed controller is an example of control circuitry. Control circuitry may include a processor, PGA (Programmable Gate Array), FPGA (Field Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), integrated circuit, or other types of circuitry.

[0066] Passage 352 is a pathway between one or more components in control circuitry 310 and the memory structure on memory structure die 302. The pathway can be used to provide or receive signals (e.g., voltage, current). The pathway includes conductive paths. The pathway may include, but is not limited to, one or more of bonding pads, metal interconnects, vias, transistors, conductive materials, and other materials that can transmit or carry electrical signals. The pathway can be used to provide a read reference voltage from power control 316 to selected word lines connected to memory cells being read in memory structure 326.

[0067] In one embodiment, the integrated memory component 306 includes a set of input and / or output (I / O) pins connected to a memory bus 322. The memory bus 322 is depicted as being connected to a memory controller interface 315.

[0068] In some embodiments, the integrated memory component 306 contains more than one control die 304 and more than one memory structure die 302. In some embodiments, the integrated memory component 306 includes a stack of multiple control dies 304 and multiple memory structure dies 302. Figure 4A A side view of one embodiment of an integrated memory assembly 306 (e.g., a stack including control dies 304 and memory structure dies 302) stacked on a substrate 402 is depicted. The integrated memory assembly 306 has three control dies 304 and three memory structure dies 302. In some embodiments, there are more than three memory structure dies 302 and more than three control dies 304.

[0069] Each control die 304 is attached (e.g., bonded) to at least one memory die in the memory die 302. Some of the bonding pads 470, 474 are depicted. There may be more bonding pads. The space between the two bondsed dies 302, 304 is filled with a solid layer 448, which may be formed of epoxy resin or other resins or polymers. The solid layer 448 protects the electrical connection between the dies 302, 304 and further secures the dies together. Various materials can be used as the solid layer 448, but in this embodiment, the material may be Hysol epoxy resin from Henkel Corporation, which has offices in California, USA.

[0070] The integrated memory component 306 may be stacked, for example, in a stepped offset manner, such that the bonding pads at each stage are not covered and can be reached from above. Wire connections 406, attached to the bonding pads, connect the control die 304 to the substrate 402. Multiple such wire connections may be formed over the width of each control die 304 (i.e., formed to...). Figure 4A (on the page).

[0071] A through-silicon via (TSV) 412 for memory die can be used to route signals through memory structure die 302. A through-silicon via (TSV) 414 for control die 304 can be used to route signals through control die 304. TSVs 412 and 414 can be formed before, during, or after the formation of integrated circuits in semiconductor dies 302 and 304. TSVs can be formed by etching holes through the wafer. These holes can then be lined with a barrier to prevent metal diffusion. The barrier layer can in turn be lined with a seed layer, and the seed layer can be plated with an electrical conductor, such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can be used.

[0072] Solder balls 408 may optionally be attached to contact pads 410 on the lower surface of substrate 402. Solder balls 408 may be used to electrically and mechanically couple integrated memory assembly 306 to host devices such as printed circuit boards. Solder balls 408 may be omitted if integrated memory assembly 306 will be used as an LGA package. Solder balls 408 may form part of the interface between integrated memory assembly 306 and memory controller 102.

[0073] Figure 4BA side view of one embodiment of an integrated memory assembly 306 stacked on a substrate 402 is depicted. The integrated memory assembly 306 has three control dies 304 and three memory structure dies 302. In some embodiments, there are more than three memory structure dies 302 and more than three control dies 304. In this example, each control die 304 is bonded to at least one memory structure die 302. Optionally, a control die 304 may be bonded to two memory structure dies 302.

[0074] Some of the bonding pads 470 and 474 are depicted. There may be more bonding pads. The space between the two joined dies 302 and 304 is filled with a solid layer 448, which may be formed of epoxy resin or other resins or polymers. Figure 4A Compared to the examples in, Figure 4B The integrated memory component 306 has no stepped offset. A through-silicon via (TSV) 412 can be used to route signals through the memory structure die 302. A through-silicon via (TSV) 414 can be used to route signals through the control die 304.

[0075] Solder balls 408 may optionally be attached to contact pads 410 on the lower surface of substrate 402. Solder balls 408 may be used to electrically and mechanically couple integrated memory assembly 306 to host devices such as printed circuit boards. Solder balls 408 may be omitted if integrated memory assembly 306 will be used as an LGA package.

[0076] As briefly discussed above, the control die 304 and the memory structure die 302 can be bonded together. Bonding pads on each die 302, 304 can be used to bond the two dies together. In some embodiments, in a so-called Cu-Cu bonding process, the bonding pads are bonded directly to each other without solder or other additional material. In the Cu-Cu bonding process, the bonding pads are controlled to be highly flat and formed in a highly controlled environment that is essentially free of environmental particles that would otherwise deposit on the bonding pads and prevent a tight bond. Under these properly controlled conditions, the bonding pads are aligned and pressed against each other to form a bond based on surface tension. This bond can be formed at room temperature, although heat can also be applied. In embodiments using Cu-Cu bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other at a pitch of 5 μm to 5 μm. Although this process is referred to herein as Cu-Cu bonding, the term can also be applied when the bonding pads are formed from materials other than copper.

[0077] When the area of ​​the bonding pads is small, it can be difficult to bond semiconductor dies together. The size and spacing of the bonding pads can be further reduced by providing a film layer on the surface of the semiconductor die, including the bonding pads. The film layer is disposed around the bonding pads. When the dies are placed together, the bonding pads can bond to each other, and the film layers on the individual dies can bond to each other. This bonding technique can be called hybrid bonding. In embodiments using hybrid bonding, the bonding pads can be approximately 5 μm square and spaced apart from each other with a pitch of 1 μm to 5 μm. Bonding techniques can be used to provide bonding pads with even smaller sizes and pitches.

[0078] Some embodiments may include a membrane on the surfaces of dies 302 and 304. If such a membrane is not initially provided, the space between the dies may be underfilled with epoxy resin or other resins or polymers. The underfill material may be applied as a liquid and then allowed to harden into a solid layer. This underfilling step protects the electrical connection between dies 302 and 304 and further secures the dies together. Various materials can be used as underfill materials, but in this embodiment, the underfill material may be Hysol epoxy resin from Henkel, a company with offices in California, USA.

[0079] Figure 5 This is a perspective view as part of an exemplary embodiment of a monolithic three-dimensional memory array that may include a memory structure 326 comprising a plurality of non-volatile memory cells. For example, Figure 5 A portion of a block including memory is shown. The depicted structure includes a set of bit lines BL above a stack of alternating dielectric and conductive layers, with vertical columns of material extending through the dielectric and conductive layers. For illustrative purposes, one dielectric layer is labeled D, and one conductive layer (also referred to as a word line layer) is labeled W. The word line layer contains one or more word lines connected to memory cells. For example, word lines may be connected to the control gate of a memory cell. The number of alternating dielectric and conductive layers can vary based on specific implementation requirements. One set of embodiments includes 108-304 alternating dielectric and conductive layers. An example embodiment includes 96 data word line layers, 8 select layers, 6 dummy word line layers, and 110 dielectric layers. More or fewer than 108-304 layers may also be used. In one embodiment, the alternating dielectric and conductive layers are divided into four “finger” or sub-blocks by local interconnects LI. Figure 5 Two finger-like portions and two local interconnects LI are shown. The source line layer SL lies beneath alternating dielectric and word line layers. Vertical column material (also called memory vias) is formed within a stack of alternating dielectric and conductive layers. For example, one of the vertical column / memory vias is labeled MH. Note that in... Figure 5In the diagram, the dielectric layers are depicted as a perspective view, allowing the reader to see the memory holes positioned within the stack of alternating dielectric and conductive layers. In one embodiment, NAND strings are formed by filling vertical columns / memory holes with a material including a charge-trapping material to create vertical columns of memory cells. Each memory cell can store one or more data bits. See below for reference. Figures 6A to 6D More details are provided regarding the 3D monolithic memory architecture 326.

[0080] Figure 6A This is a block diagram illustrating an exemplary organization of memory structure 326, which is divided into two planes 602 and 604. Each plane is then divided into M blocks. In one example, each plane has approximately 2000 blocks. However, different numbers of blocks and planes can also be used. In one embodiment, for a two-plane memory, the block IDs typically cause even-numbered blocks to belong to one plane and odd-numbered blocks to belong to the other; thus, plane 602 includes blocks 0, 2, 4, 6… while plane 604 includes blocks 1, 3, 5, 7… In one embodiment, the block of memory cells is an erase unit. That is, all memory cells in a block are erased together. In other embodiments, memory cells may be grouped into blocks for other reasons, such as to organize memory structure 326 to enable signaling and selection circuitry.

[0081] Figures 6B to 6D An exemplary 3D NAND structure is depicted. Figure 6B It is a block diagram depicting a top view of a portion of a block from memory structure 326. Figure 6B The part of the block depicted in the middle corresponds to Figure 6A Part 606 in block 2. From Figure 6B It can be seen from this that Figure 6B The block depicted extends along a direction of 633. In one embodiment, the memory array will have 60 layers. Other embodiments have fewer or more than 60 layers. However, Figure 6B Only the top layer is shown.

[0082] Figure 6B Multiple circles representing vertical columns are depicted. Each column in the vertical column includes multiple selection transistors and multiple memory cells. In one implementation, each vertical column implements a NAND string. For example, Figure 6B Vertical columns 622, 632, 642, and 652 are depicted. Vertical column 622 implements NAND string 682. Vertical column 632 implements NAND string 684. Vertical column 642 implements NAND string 686. Vertical column 652 implements NAND string 688. More details about the vertical columns are provided below. Due to... Figure 6BThe block depicted extends in the direction of arrow 633 and in the direction of arrow 633, therefore the block includes more than Figure 6B More vertical columns are depicted in the text.

[0083] Figure 6B A set of bit lines 615 is also depicted, including bit lines 611, 612, 613, 614, ..., 619. Figure 6B Twenty-four bit lines are shown because only a portion of the block is depicted. It is envisioned that more than twenty-four bit lines connect to the vertical columns of the block. Each circle representing a vertical column has an "x" to indicate its connection to a bit line. For example, bit line 614 connects to vertical columns 622, 632, 642, and 652.

[0084] Figure 6B The block depicted includes a set of local interconnects 662, 664, 666, 668, and 669 that connect the various layers to source lines below the vertical columns. Local interconnects 662, 664, 666, 668, and 669 also divide each layer of the block into four regions; for example, Figure 6B The top layer depicted is divided into regions 620, 630, 640, and 650, which are referred to as fingers or sub-blocks. In the layer of the memory cells implemented in the block, these four regions are called word line sub-blocks, and they are separated by local interconnects. In one embodiment, word line sub-blocks located on a common level of the block are connected together at the ends of the block to form a single word line. In another embodiment, word line sub-blocks located on the same level are not connected together. In an exemplary embodiment, bit lines are connected to only one vertical column in each of regions 620, 630, 640, and 650. In this embodiment, each block has sixteen active columns, and each bit line is connected to four rows in each block. In one embodiment, all four rows connected to the common bit line are connected to the same word line (via different word line sub-blocks connected together on the same level); therefore, the system uses source-side select lines and drain-side select lines to select one (or another subset) of the four to be performed on memory operations (programming, verification, reading, and / or erasing).

[0085] although Figure 6B The illustration shows four vertical columns per region within a block, four regions, and sixteen vertical columns, but these exact numbers are exemplary implementations. Other implementations may include more or fewer regions per block, more or fewer vertical columns per region, and more or fewer vertical columns per block.

[0086] Figure 6B It is also shown that the vertical columns are staggered. In other embodiments, different staggering patterns may be used. In some embodiments, the vertical columns are not staggered.

[0087] Figure 6C A portion of one embodiment of a three-dimensional memory structure 326 is depicted, showing along... Figure 6B The sectional view of line AA. This sectional view cuts through vertical columns 632 and 634 and region 630 (see [reference]). Figure 6B ). Figure 6C The structure includes four drain-side select layers SGD0, SGD1, SGD2, and SGD3; four source-side select layers SGS0, SGS1, SGS2, and SGS3; four dummy word line layers DD0, DD1, DS0, and DS1; and forty-eight data word line layers WLL0 to WLL47 for connecting to data memory cells. Other embodiments may implement more or fewer than four drain-side select layers, more or fewer than four source-side select layers, more or fewer than four dummy word line layers, and more or fewer than forty-eight word line layers (e.g., 96 word line layers). Vertical columns 632 and 634 are depicted as protruding through the drain-side select layers, source-side select layers, dummy word line layers, and word line layers. In one embodiment, each vertical column includes a NAND string. For example, vertical column 632 includes NAND string 684. Below the vertical columns and the layers listed below are a substrate 101, an insulating film 654 on the substrate, and source lines SL. The vertically arranged 632 NAND strings have a source terminal at the bottom of the stack and a drain terminal at the top of the stack. Figure 6B Consistent Figure 6C A vertical column 632 connected to bit line 614 via connector 617 is shown. Local interconnects 664 and 666 are also depicted.

[0088] For ease of reference, the drain-side selection layers SGD0, SGD1, SGD2, and SGD3; the source-side selection layers SGS0, SGS1, SGS2, and SGS3; the dummy word line layers DD0, DD1, DS0, and DS1; and the word line layers WLL0-WLL47 are collectively referred to as conductive layers. In one embodiment, the conductive layers are made of a combination of TiN and tungsten. In other embodiments, other materials can be used to form the conductive layers, such as doped polysilicon, metals (such as tungsten or metal silicides). In some embodiments, the different conductive layers can be formed of different materials. Between the conductive layers are dielectric layers DL0 to DL59. For example, dielectric layer DL49 is above word line layer WLL43 and below word line layer WLL44. In one embodiment, the dielectric layers are made of SiO2. In other embodiments, other dielectric materials can be used to form the dielectric layers.

[0089] Non-volatile memory cells are formed along vertical columns that extend through alternating conductive and dielectric layers in the stack. In one embodiment, the memory cells are arranged within a NAND string. Word line layers WLL0 to WLL47 are connected to the memory cells (also referred to as data memory cells). Dummy word line layers DD0, DD1, DS0, and DS1 are connected to dummy memory cells. Dummy memory cells do not store user data, while data memory cells are eligible to store user data. Drain-side select layers SGD0, SGD1, SGD2, and SGD3 are used to electrically connect and disconnect the NAND string from the bit lines. Source-side select layers SGS0, SGS1, SGS2, and SGS3 are used to electrically connect and disconnect the NAND string from the source line SL.

[0090] In some implementations, word lines are read sequentially, meaning they are read from low to high (e.g., WLL0 to WLL47) or from high to low (e.g., WLL47 to WLL0). When reading sequentially, it is not necessary to read the entire set of word lines. This document discloses techniques for compensating for interference caused by adjacent memory cells on the target memory cell during sequential reads.

[0091] In some implementations, reading a single word line is broken down into reading sub-blocks separately. See again Figure 6B The block is divided into four sub-blocks 620, 630, 640, and 650. Therefore, four sub-blocks on one word line layer can be read before reading four sub-blocks on adjacent word line layers. In some implementations, data status information is used to provide compensation on a sub-block basis. For example, for each of the four sub-blocks 620 to 650, data status information of the memory cell at WLL35 is retained. Then, when reading sub-block 620 of WLL36, the data status information of sub-block 620 at WLL35 is used to compensate for interference from adjacent memory cells in sub-block 620 at WLL35; when reading sub-block 630 of WLL36, the data status information of sub-block 630 at WLL35 is used to compensate for interference from adjacent memory cells in sub-block 620 at WLL35, and so on.

[0092] Figure 6D Depicting Figure 6CA cross-sectional view of region 629, including a portion of vertical column 632. In one embodiment, the vertical column is circular and comprises four layers; however, in other embodiments, it may comprise more or fewer than four layers, and other shapes may be used. In one embodiment, vertical column 632 includes an inner core layer 670 made of a dielectric such as SiO2. Other materials may also be used. Surrounding the inner core 670 is a polysilicon channel 671. Materials other than polysilicon may also be used. Note that channel 671 is connected to a bit line. Surrounding the channel 671 is a tunneling dielectric 672. In one embodiment, tunneling dielectric 672 has an ONO structure. Surrounding tunneling dielectric 672 is a charge trapping layer 673, such as, for example, silicon nitride. Other memory materials and structures may also be used. The techniques described herein are not limited to any particular material or structure.

[0093] Figure 6D Dielectric layers DLL49, DLL50, DLL51, DLL52, and DLL53 are depicted, as well as word line layers WLL43, WLL44, WLL45, WLL46, and WLL47. Each word line layer includes a word line region 676 surrounded by an aluminum oxide layer 677, which is surrounded by a barrier oxide (SiO2) layer 678. The physical interaction between the word line layers and the vertical column forms a memory cell. Thus, in one embodiment, the memory cell includes a channel 671, a tunneling dielectric 672, a charge trapping layer 673, a barrier oxide layer 678, an aluminum oxide layer 677, and a word line region 676. For example, word line layer WLL47 and a portion of vertical column 632 constitute memory cell MC1. Word line layer WLL46 and a portion of vertical column 632 constitute memory cell MC2. Word line layer WLL45 and a portion of vertical column 632 constitute memory cell MC3. A portion of word line layer WLL44 and vertical column 632 constitutes memory cell MC4. A portion of word line layer WLL43 and vertical column 632 constitutes memory cell MC5. In other architectures, memory cells may have different structures; however, a memory cell will still be a storage cell.

[0094] It should be noted that the charge trapping layer 673 may extend from one end of the NAND string to the other, and is therefore referred to herein as a continuous charge trapping layer. When a memory cell is programmed, electrons are stored in a portion of the charge trapping layer 673 associated with the memory cell. In response to an appropriate voltage on the word line region 676, these electrons are attracted from the channel 671 into the charge trapping layer 673 through the tunneling dielectric 672. The Vt of the memory cell increases proportionally to the amount of stored charge. In one embodiment, programming is achieved by electrons tunneling into the charge trapping layer via Fowler-Nordheim tunneling. During an erase operation, electrons return to the channel or holes are injected into the charge trapping layer to recombine with electrons. In one embodiment, erasure is achieved using hole injection into the charge trapping layer via a physical mechanism such as gate-induced drain leakage (GIDL).

[0095] Figure 7 This is a flowchart describing one implementation of a process 700 for programming a NAND string of memory cells. Figure 7 The process can be executed in the direction of state machine 312. In an exemplary embodiment, the above-described control circuitry 310 (and read / write circuitry 328 and decoders 332 / 324) are used on memory die 300 for execution. Figure 7 The process. In one exemplary embodiment, the control circuit 310 described above is used to execute via the integrated memory component 306. Figure 7 The process comprises multiple cycles, each cycle including a programming phase (e.g., steps 704-708) and a verification phase (e.g., steps 710-718).

[0096] In many implementations, the amplitude of the programmed pulse increases by a predetermined step size with each successive pulse. Figure 7 In step 702, the programming voltage (Vpgm) is initialized to the initial amplitude (e.g., about 12V to 16V, or another suitable level), and the programming counter PC maintained by state machine 312 is initialized to 1.

[0097] In one implementation, a set of memory cells selected for programming (referred to herein as selected memory cells) are programmed simultaneously and all connected to the same word line (selected word line). Other memory cells not selected for programming (unselected memory cells) may also be connected to the selected word line. That is, the selected word line will also be connected to memory cells that should be disabled for programming. Furthermore, when the memory cells reach their intended target data state, they will be disabled for further programming. These NAND strings (e.g., unselected NAND strings) boost their channels to disable programming; these strings include the memory cells to be disabled for programming connected to the selected word line. When the channel has a boosted voltage, the voltage difference between the channel and the word line is insufficient to induce programming. To aid the boost, in step 704, the memory system precharges the channel of the NAND string that includes the memory cells connected to the selected word line to be disabled for programming.

[0098] In one implementation, step 704 marks the start of a programming operation. In some implementations, different groups of memory cells are programmed simultaneously. For example, programming of memory cells in different memory structures 326 can be performed concurrently. In some implementations, the start of concurrent programming operations (e.g., step 704) is interleaved, such that step 704 occurs at different times for different memory structures 326.

[0099] In step 706, a NAND string including a memory cell connected to the selected word line to be disabled for programming is boosted in its channel to disable programming. Such a NAND string is referred to herein as an "unselected NAND string". In one embodiment, the unselected word line receives one or more boost voltages (e.g., about 7 to 11 volts) to perform a boost scheme. A programming disable voltage is applied to the bit line coupled to the unselected NAND string.

[0100] In step 708, a programming pulse of the programming signal Vpgm is applied to the selected word line (the word line selected for programming). In one embodiment, if a memory cell on the NAND string is to be programmed, the corresponding bit line is biased at the programming enable voltage. In this document, such a NAND string is referred to as the "selected NAND string".

[0101] In step 708, programming pulses are simultaneously applied to all memory cells connected to the selected word line, such that all memory cells connected to the selected word line are programmed simultaneously (unless they are disabled for programming). That is, they are programmed at the same time or during an overlap period (both are considered simultaneous). In this way, all memory cells connected to the selected word line will have their Vt changes simultaneously, unless they are disabled for programming.

[0102] In step 710, the memory cell that has reached its target state is locked and cannot be further programmed. Step 710 may include performing verification at one or more verification reference levels. In one embodiment, the verification process is performed by testing whether the threshold voltage of the memory cell selected for programming has reached the appropriate verification reference voltage.

[0103] In step 710, after the memory cell has been verified (by the test of Vt) that the memory cell has reached its target state, the memory cell can be locked.

[0104] If, in step 712, it is determined that all memory cells have reached their target threshold voltage (pass), the programming process is complete and successful because all selected memory cells have been programmed and verified to their target state. In step 714, a "pass" status is reported. Otherwise, if it is determined in 712 that not all memory cells have reached their target threshold voltage (failure), the programming process continues to step 716.

[0105] In step 716, the memory system counts the number of memory cells that have not yet reached their corresponding target Vt distribution. That is, the system counts the number of memory cells that have not yet reached their target state. This counting can be performed by state machine 312, memory controller 102, or other logic. In one implementation, each sensing block in the sensing block stores the state (pass / fail) of its corresponding cell. In one implementation, there is a total count that reflects the total number of currently programmed memory cells for which the last verification step has failed. In another implementation, a separate count is maintained for each data state.

[0106] In step 718, it is determined whether the count from step 716 is less than or equal to a predetermined limit. In one embodiment, the predetermined limit is the number of bits that can be corrected by error correction codes (ECC) during the page read process of a memory cell. If the number of failed cells is less than or equal to the predetermined limit, the programming process can stop and a "pass" status is reported in step 714. In this case, enough memory cells have been correctly programmed so that ECC can be used during the read process to correct any remaining memory cells that have not yet been fully programmed. In some embodiments, the predetermined limit used in step 718 is lower than the number of bits that can be corrected by error correction codes (ECC) during the read process to allow for future / additional errors. The predetermined limit can be a fraction (proportional or non-proportional) of the number of bits that can be corrected by ECC during the page read process of a memory cell when programming fewer than all memory cells of a page, or when comparing counts of only one data state (or fewer than all states). In some embodiments, the limit is not predetermined. Instead, it varies based on the number of errors already counted for the page, the number of program erase cycles performed, or other criteria.

[0107] If the number of failed memory cells is not less than a predetermined limit, the programming process continues at step 720 and the programming counter PC is checked against the programming limit value (PL). Examples of programming limit values ​​include 1, 12, 16, 19, and 30; however, other values ​​can be used. If the programming counter PC is not less than the programming limit value PL, the programming process is considered to have failed and a "failure" status is reported in step 724. If the programming counter PC is less than the programming limit value PL, the process continues at step 722, during which the programming counter PC is incremented by 1, and the programming voltage Vpgm is stepped to the next amplitude. For example, the next pulse will have an amplitude one step larger than the previous pulse (e.g., a step size of 0.1 volts to 1.0 volts). After step 722, the process loops back to step 704, and another programming pulse is applied to the selected word line, causing execution to... Figure 7 Another iteration of the programming process (steps 704-722).

[0108] At the end of a successful programming process, the threshold voltage of the memory cell should, where appropriate, be within one or more distributions of the threshold voltages of the memory cells used for programming or within the distribution of the threshold voltages of the erased memory cells. Figure 8A An exemplary Vt distribution for a memory array is shown when each memory cell stores three bits of data. However, other implementations may use other data capacities per memory cell (e.g., one, two, four, or five bits of data per memory cell). Figure 8AEight Vt distributions are shown, corresponding to eight data states. The first Vt distribution S0 represents an erased memory cell. State S0 may be referred to herein as the erase state (Er state). The other seven Vt distributions S1 to S7 represent programmed memory cells and are therefore also referred to as programmed states. Each Vt distribution (data state) corresponds to a predetermined set of data bits. The specific relationship between the data programmed into the memory cell and the Vt level of that cell depends on the data encoding scheme adopted by that cell. In one implementation, Gray code allocation is used to assign data values ​​to the Vt range such that if the memory's Vt is incorrectly offset to its adjacent physical state, only one bit will be affected.

[0109] Figure 8A Eight Vt distributions 802 to 816 are shown. Distribution 802 corresponds to state S0; distribution 804 corresponds to state S1; distribution 806 corresponds to state S2; distribution 808 corresponds to state S3; distribution 810 corresponds to state S4; distribution 812 corresponds to state S5; distribution 814 corresponds to state S6; and distribution 816 corresponds to state S7. Figure 8A Seven read reference voltages, Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7, are also shown for reading data from memory cells. By testing (e.g., performing a sensing operation) whether Vt of a given memory cell is higher or lower than the seven read reference voltages, the system can determine the data state (i.e., S0, S1, S2, S3…) of the memory cell. In some embodiments, lateral DR interference is suppressed by the amplitude of the read reference voltages.

[0110] Figure 8ASeven verification reference voltages, Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7, are also shown. In some embodiments, when a memory cell is programmed to data state S1, the system tests whether the memory cell has a Vt greater than or equal to Vv1. When a memory cell is programmed to data state S2, the system tests whether the memory cell has a threshold voltage greater than or equal to Vv2. When a memory cell is programmed to data state S3, the system determines whether the memory cell has a Vt greater than or equal to Vv3. When a memory cell is programmed to data state S4, the system tests whether the memory cell has a Vt greater than or equal to Vv4. When a memory cell is programmed to data state S5, the system tests whether the memory cell has a Vt greater than or equal to Vv5. When a memory cell is programmed to data state S6, the system tests whether the memory cell has a Vt greater than or equal to Vv6. When a memory cell is programmed to data state S7, the system tests whether these memory cells have a Vt greater than or equal to Vv7. The programming state (e.g., S1) verified by the lowest amplitude reference voltage (e.g., Vv1) is referred to herein as the "lowest programming state". The programming state (e.g., S7) verified by the highest amplitude reference voltage (e.g., Vv7) is referred to herein as the "highest programming state".

[0111] Figure 8A Also shown is Vev (for "erase verification voltage"), which is the voltage level used to test whether a memory cell has been correctly erased. As depicted in Figure 8, the erased memory cell should have a Vt value lower than Vev. Generally, during verification and read operations, a selected word line is connected to a voltage whose level is specific to each read operation (see, for example, [reference needed]). Figure 8A The read comparison levels Vr1, Vr2, Vr3, Vr4, Vr5, Vr6, and Vr7) or verification operation (e.g., see...) Figure 8AThe verification target levels (Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, and Vv7) are specified to determine whether the Vt of the relevant memory cell has reached this level. After the word line voltage is applied, the conduction current of the memory cell is measured to determine whether the memory cell is turned on (conducted current) in response to the voltage applied to the word line. If the conduction current is measured to be greater than a certain value, then it is assumed that the memory cell is turned on and the voltage applied to the word line is greater than the Vt of the memory cell. If the conduction current is not measured to be greater than a certain value, then it is assumed that the memory cell is not turned on and the voltage applied to the word line is not greater than the Vt of the memory cell. During the read or verification process, unselected memory cells are provided with one or more read pass voltages (also known as bypass voltages) at their control gate, causing these memory cells to conduct current as if they were being operated through the gate (e.g., conducting current regardless of whether these memory cells are being programmed or erased).

[0112] There are many methods to measure the conduction current of a memory cell during a read or verification operation. In one example, the conduction current of the memory cell is measured as the rate at which the memory cell discharges or charges a dedicated capacitor in a sense amplifier. In another example, the conduction current of a selected memory cell allows (or does not allow) the NAND string of the memory cell to discharge to the corresponding bit line. The voltage on the bit line is measured after a certain period of time to see if it has discharged. It should be noted that the techniques described herein can be used in conjunction with various methods known in the art for verification / reading. Other read and verification techniques known in the art can also be used.

[0113] In one implementation, known as full-sequence programming, memory cells can be directly programmed from an erase state S0 to any of the programming data states S1 through S7. For example, a group of memory cells to be programmed can be erased first, leaving all memory cells in the group in an erase state S0. Then, a programming process is used to directly program the memory cells into data states S1, S2, S3, S4, S5, S6, and / or S7. For example, while some memory cells are being programmed from data state S0 to data state S1, other memory cells are being programmed from data state S0 to data state S2 and / or from data state S0 to data state S3, and so on. In some implementations, data states S1 through S7 can overlap, where the controller 102 relies on error correction to identify the correct data being stored.

[0114] In addition to full-sequence programming, the techniques described in this article can also be used with other types of programming, including but not limited to multi-level programming / multi-phase programming. Figure 8B Describing for Figure 8AOne implementation of a multi-stage programming approach using a three-bit per cell example. Initially, all memory cells are erased to an erase Vt distribution 820. In the first stage, all memory cells ending in any of data states S4 through S7 are programmed to an intermediate state S4 / S7 with an S4 / S7'Vt distribution 832. The upper tail of the S4 / S7'Vt distribution 832 should not be higher than the upper tail of the final S4Vt distribution 810. A reference voltage Vint_S4 / S7 is used for verification during the first stage. Memory cells ending in any of data states S0 through S3 are not programmed in the first stage, as indicated by remarking the erase Vt distribution 820 to an S0 / S3'Vt distribution 830.

[0115] In the second stage, memory cells ending in data state S2 or S3 are programmed from S0 / S3'Vt distribution 830 to S2 / S3"Vt distribution 842. Memory cells ending in S0 or S1 do not need to be programmed in the second stage, as indicated by relabeling S0 / S3'Vt distribution 830 to S0 / S1"Vt distribution 840. Also in the second stage, memory cells ending in data state S6 or S6 are programmed from S4 / S7'Vt distribution 832 to S6 / S7"Vt distribution 846. Memory cells ending in S4 or S5 do not need to be programmed in the second stage, as indicated by relabeling S4 / S6'Vt distribution 832 to S4 / S5"Vt distribution 844.

[0116] In the third stage, memory cells are programmed from S0 / S1”Vt distribution 840 to S1Vt distribution 804. Memory cells ending with S0 are not programmed in the third stage, as indicated by relabeling S0 / S1”Vt distribution 840 as S0Vt distribution 802. In the third stage, memory cells are programmed from S2 / S3”Vt distribution 842 to S3Vt distribution 808. Memory cells ending with S2 do not need to be programmed in the third stage, as indicated by relabeling S2 / S3”Vt distribution 842 as S2Vt distribution 806. In the third stage, memory cells are programmed from S4 / S5”Vt distribution 844 to S5Vt distribution 812. Memory cells ending with S4 do not need to be programmed in the third stage, as indicated by relabeling S4 / S5”Vt distribution 844 as S4Vt distribution 810. In the third stage, the memory cell is programmed from S6 / S7”Vt distribution 846 to S7Vt distribution 816. Memory cells ending with S6 are not programmed in the third stage, as indicated by remarking S6 / S7”Vt distribution 846 to S6Vt distribution 814.

[0117] In one implementation, the first page is programmed in a first phase, the second page in a second phase, and the third page in a third phase. Throughout this document, once a page has been programmed into a set of memory cells, the memory cells can be retrieved. Therefore, the intermediate states associated with multi-phase programming are referred to herein as programming states.

[0118] As mentioned above, some implementations include multi-stage phase programming. One type of multi-stage phase programming includes fuzzy phases and fine-grained phases, which is referred to herein as fuzzy-fine-grained programming. Figure 9 The threshold Vt distribution of one implementation of fuzzy-fine programming is depicted. Distribution 902 represents the erase state after the erase operation but before fuzzy-fine programming begins.

[0119] Fuzzy distributions 910 to 924 are Vt distributions following the fuzzy phase. Fuzzy verification levels Vv2', Vv4', Vv6', Vv8', Vv10', Vv12', and Vv14' are depicted as adjacent to the corresponding distributions 910 to 924. Figure 9 The arrows in the diagram indicate that memory cells can be programmed from erase state distribution 902 to one of fuzzy distributions S2' to S14'. During the fuzzy phase, memory cells with a final data state of S2 or S3 are programmed to the fuzzy S2' state, as shown in distribution 912. Memory cells with a final data state of S4 or S5 are programmed to the fuzzy S4' state, as shown in distribution 914. Memory cells with a final data state of S6 or S7 are programmed to the fuzzy S6' state, as shown in distribution 916. Memory cells with a final data state of S8 or S9 are programmed to the fuzzy S8' state, as shown in distribution 918. Memory cells with a final data state of S10 or S11 are programmed to the fuzzy S10' state, as shown in distribution 920. Memory cells with a final data state of S12 or S13 are programmed to the fuzzy S12' state, as shown in distribution 922. Memory cells with a final data state of S14 or S15 are programmed to a fuzzy S14' state, as shown in distribution 924. Memory cells remaining in S0 or with a final state of S1 do not receive any programming during the fuzzy phase, as shown in distribution 910.

[0120] The fine Vt distributions 930 to 945 are the Vt distributions following the fine stage. The fine Vt distributions can also be referred to as the final data state. In contrast, the fuzzy Vt distributions can be referred to as intermediate data states. Fine verification levels Vv1, Vv2, Vv3, Vv4, Vv5, Vv6, Vv7, Vv8, Vv9, Vv10, Vv11, Vv12, Vv13, Vv14, and Vv15 are depicted as adjacent to the corresponding fine distributions 930 to 945. Read reference levels Vv1, Vr2, Vr3, Vr4, Vr5, Vr6, Vr7, Vr8, Vr9, Vr10, Vr11, Vr12, Vr13, Vr14, and Vr15 are shown between fine distributions 930 and 945. Figure 9 The arrows in the diagram illustrate that memory cells can be programmed from one of the fuzzy Vt distributions to one of the fine Vt distributions. For example, a memory cell in the fuzzy Vt distribution S2'912 can be programmed into either the fine Vt distribution S2'932 or the fine Vt distribution S3'933. Similar programming can be used for memory cells that are to be programmed into other final states.

[0121] Figure 10 This is a flowchart providing further details on programming a block of memory cells using a fuzzy-fine programming process. This process can be used to program blocks containing NAND strings. Step 1002 includes erasing the block of memory cells. After step 1002, the Vt distribution for each WL can resemble Vt distribution 902.

[0122] Step 1004 includes setting the WL number (WLn) to 0. Step 1006 includes programming the memory cells on WLn to an ambiguous state. After the first iteration of step 1006, the Vt distribution of WL0 can be similar to... Figure 9 The Vt distribution in the range is from 910 to 924.

[0123] Step 1008 involves programming the memory cells on WLn+1 into fuzzy states. After the first iteration of step 1008, the Vt distribution of WL1 can be similar to... Figure 9 The Vt distribution in the range is from 910 to 924.

[0124] Step 1010 involves programming the memory cells on WLn into fine states. After the first iteration of step 1010, the Vt distribution of WL0 can be similar to... Figure 9 The Vt distribution is from 930 to 945. Step 1012 includes incrementing the WL number. Step 1014 determines whether this is the last WL to be programmed. If not, control proceeds to step 1008.

[0125] During the second iteration, step 1008 includes programming the memory cells on WL2 to a fuzzy state. During the second iteration, step 1010 includes programming the memory cells on WL1 to a fine state. Therefore, it should be noted that during the first iteration of step 1010, the memory cells on WL0 were programmed to a fine state (this follows the programming of the memory cells on WL1 to a fuzzy state in the first iteration of step 1008). However, programming the memory cells on WL1 to a fine state in the second iteration of step 1010 causes interference to the memory cells on WL0. That is, programming the memory cells on WL1 to a fine state in the second iteration of step 1010 adds charge to the charge trapping layer 673 of the memory cells on WL1. This additional charge can alter the apparent Vt of the memory cells on WL0. In this document, this is referred to as NWI.

[0126] During the second iteration, step 1012 includes incrementing the WL number to 2. The process continues programming more word lines until it is determined in step 1014 that this is the last WL. In step 1016, the last WL in the block is programmed into a fine state.

[0127] It should be noted that process 1000 describes the sequential order, where word lines are programmed from low to high numbers (or from the source end of the NAND string to the drain end, which can also be referred to as programming from the source line to the bit line). In another implementation, word lines are programmed sequentially from high WL numbers to low WL numbers (or from the drain end of the NAND string to the source end). When programming from high WL numbers to low WL numbers, the NWI of the memory cell on WLn occurs when WLn-1 is programmed. In other words, WLn-1 is programmed after WLn.

[0128] The NWI effect is most pronounced when the memory cell adjacent to the target memory cell is programmed after the target memory cell, although its effect can be observed in other cases as well. The charge, or a portion of the charge, placed on the charge storage region of the adjacent memory cell will be effectively coupled to the target memory cell via electric field coupling, resulting in an apparent shift in the Vt of the target memory cell. The apparent Vt of the memory cell can be shifted to a degree after programming such that it will not turn on and off (conduct) under the applied read reference voltage, which is expected of a memory cell in a memory state intended for programming.

[0129] Figure 11 The possible interpretations of both NWI and lateral DR are illustrated graphically. Figure 11 It depicts a target character line WLn and two adjacent character lines WLn-1 and WLn+1. Figure 6DA simplified view. For the purposes of discussion, it will be assumed that the programming order is WLn-1, WLn, WLn+1. Figure 11 The memory hole MH is depicted, which includes an inner core layer 670, a channel layer 671, a tunneling dielectric layer 672, a charge trapping layer 673, and a barrier layer 678.

[0130] First, we will discuss possible interpretations of NWI. As a result of programming the adjacent memory cells connected to WLn+1, an electric field can be introduced by adding charge to the memory cells on WLn+1. Note that some charge may already exist on the memory cells on WLn+1; in this case, the charge changes due to the new charge added to the memory cells on WLn+1. This electric field has an effect on Vt of the target cell on WLn. This effect can be described by capacitive coupling, as depicted by the coupling component r1.

[0131] Significantly, the magnitude of the coupling component r1 will depend on factors such as the distance between WLn and WLn+1. It should be noted that this distance can vary between blocks, or even between NAND strings within the same block. In some implementations, when reading a target cell on WLn, compensation for the NWI is achieved by applying an appropriate read-through voltage to WLn+1, which automatically compensates for such coupling differences. The effect of this compensation, applied to WLn+1, can depend on the distance between WLn and WLn+1.

[0132] Furthermore, since NWI may occur due to programming WLn+1 after programming WLn, the compensation amount can depend on the amount of programming of adjacent memory cells on WLn+1 received after the programming of the target memory cell is completed. For example, if WLn+1 is executed after the fine pass to WLn is completed. Figure 9 The fine-pass fuzzy-fine programming illustrated here means that the amount of compensation for NWI can depend on whether the adjacent memory cells on WLn+1 are programmed to an even state (e.g., S0, S2, etc.) or an odd state (e.g., S1, S3, etc.). In one implementation, if the adjacent memory cells on WLn+1 are programmed to an odd state, a larger compensation is used. This is because, as shown in the reference... Figure 9 In the fine-grained state, the Vt of adjacent memory cells in odd-numbered state cells increases more than that in even-numbered state cells. In other words, odd-numbered state cells receive more programming during the fine-grained phase.

[0133] Refer again Figure 11The adjacent memory cells connected to WLn-1 are programmed before the target memory cell is programmed. Therefore, NWI is less important in terms of its effect on the target memory cell. However, the lateral DR of adjacent memory cells on WLn-1 has a significant effect on the target memory cell. One possible explanation for the lateral DR is that it is at least partly attributed to the movement of electrons and / or holes in the charge trapping layer 673. Figure 11 Examples of possible electron and hole movements are depicted in the charge trapping layer 673. Double arrows indicate possible movements in the lateral direction. The direction of movement can depend on the amount of charge stored in the target cell and adjacent cells on WLn-1. It should be noted that this charge movement can occur over a relatively long period of time. Therefore, this is referred to as the data retention (DR) problem.

[0134] In some implementations, lateral DR is compensated by applying an appropriate read reference voltage to WLn when reading a target cell on WLn. Since lateral DR may occur at least in part due to the amount of charge stored on adjacent memory cells on WLn-1, the amount of lateral DR compensation can directly depend on the amount of charge stored on adjacent memory cells on WLn-1. However, it should be noted that applying an appropriate read reference voltage to WLn may suppress other types of adjacent cell interference. Therefore, the compensation applied to WLn is not limited to compensating for lateral DR.

[0135] Figure 12A The Vt distributions are depicted to illustrate the effect of lateral DR. Distributions 1202 and 1204 are Vt distributions for two data states. For the purposes of discussion, these will be referred to as "state i" and "state i+1". These can be, for example, states S6 and S7. Specifically, Vt distribution 1202 represents the entire group of cells for data state i, while Vt distribution 1204 represents the entire group of cells for data state i+1. For the purposes of discussion, memory cells are connected to the target word line (WLn).

[0136] Vt distributions 1206 and 1208 represent the Vt distributions of the target cell having neighboring cells on WLn-1 in an erased state (e.g., S0). Specifically, Vt distribution 1206 represents those cells from Vt distribution 1202 having neighboring cells on WLn in an erased state. Similarly, Vt distribution 1208 represents those cells from Vt distribution 1204 having neighboring cells on WLn in an erased state. Therefore, in this example, neighboring cells in an erased state can effectively pull down the Vt of the target cell. (See again...) Figure 11This change can be attributed to electrons moving away from the target cell toward neighboring cells on WLn-1, or holes moving away from neighboring cells on WLn-1 toward the target cell. This effect is not limited to low Vt states where neighboring cells are erased.

[0137] Vt distributions 1210 and 1212 represent the Vt distributions of target cells having neighboring cells on WLn-1 in the highest Vt state (e.g., S15). Specifically, Vt distribution 1210 represents those target cells from Vt distribution 1202 having neighboring cells on WLn in the highest Vt state. Similarly, Vt distribution 1212 represents those target cells from Vt distribution 1204 having neighboring cells on WLn in the highest Vt state. Therefore, in this example, neighboring cells in the highest Vt state can effectively pull up the Vt of the target cell. (See again...) Figure 11 This change can be attributed to electrons moving away from neighboring cells on WLn-1 and towards the target cell, or holes moving away from the target cell and towards neighboring cells on WLn-1. This effect is not limited to neighboring cells being in the highest Vt state (e.g., S15). Note that the scale of the horizontal axis is logarithmic. Additionally, note that the cell numbers for Vt distributions 1206, 1208, 1210, and 1212 are normalized so that the peak values ​​for each distribution from 1202 to 1212 are the same.

[0138] Several read reference voltages are depicted on the horizontal (Vt) axis. The default read reference voltage Vr_def is depicted between distributions 1202 and 1204. The low Vt read reference voltage Vr_low_Vt is depicted between distributions 1206 and 1208. The high Vt read reference voltage Vr_high_Vt is depicted between distributions 1210 and 1212. In one implementation, Vr_low_Vt is used to read the target cell if the adjacent cell on WLn-1 has a low Vt. If the adjacent cell on WLn-1 has a high Vt, Vr_high_Vt is used to read the target cell. If Vr_def is used to perform the read, the BER will be higher than if other read reference voltages are used. The definitions of low Vt and high Vt are flexible. In one implementation, adjacent cells are read at one-bit resolution, where low Vt is the lowest half of the data state and high Vt is the highest half of the data state. If each cell stores four bits, low Vt can be S0 to S7 and high Vt can be S8 to S15.

[0139] In one implementation, adjacent cells are read at a two-bit resolution, in which case four read reference voltages can be used. If each cell stores four bits, the cells can be divided into four groups using two bits: S0 to S3, S4 to S7, S8 to S11, and S12 to S15. In another implementation, adjacent cells are read at a three-bit resolution, in which case eight read reference voltages can be used. If each cell stores four bits, the cells can be divided into eight groups using three bits: S0 to S1, S2 to S3, S4 to S5, S6 to S7, S8 to S9, S10 to S11, S12 to S13, and S14 to S15.

[0140] Figure 12B The Vt distribution of memory cells is illustrated to further explain NWI. This example considers the case where each memory cell stores two bits. Solid curves 1226, 1230, 1234, and 1238 show the Vt distribution before adjacent cells on WLn+1 are programmed. Dashed curves 1228, 1232, 1236, and 1240 show the Vt distribution after adjacent cells on WLn+1 are programmed. Each distribution can be broadened due to the addition of negative charge to memory cells on adjacent word lines. Due to electrostatic charge coupling, the negative charge of a later-programmed memory cell on WLn+1 will increase the apparent Vt of memory cells on the same NAND string on WLn.

[0141] Distributions 1230 and 1232 represent cells in state S1 of the selected word line WLn before and after programming the adjacent word line WLn+1, respectively. Distributions 1234 and 1236 represent cells in state S2 of WLn before and after programming WLn+1, respectively. Distributions 1238 and 1240 represent cells in state S3 of WLn after programming WLn+1, respectively. Because the distributions are widened, memory cells may be read incorrectly. Memory cells at the upper end of each distribution may have an apparent Vt higher than the corresponding read comparison point. For example, when a reference voltage Vr2 is applied, some memory cells programmed to state S1 may not be sufficiently turned on due to the offset of their apparent Vt. These cells may be read incorrectly as in state S2, resulting in read errors.

[0142] Therefore, the NWI effect occurs due to the asymmetry in the charge environment experienced by the cell between the time it is programmed and the time it is read. More specifically, during the programming of the cell on word line WLn, at least some of the memory cells on WLn+1 are not yet fully programmed and have significantly less charge than they would have when fully programmed. Thus, the cell on WLn is programmed under such conditions. Later, the cell on WLn+1 is programmed, and now some of its charge storage elements are programmed to have more negative charge. When the cell on WLn is read, these negative charges now present a more negative charge environment. The effect is as if the cell on WLn were programmed to have more negative charge; that is, the cell appears to be programmed to have a higher Vt.

[0143] In one implementation, when reading WLn, compensation for NWI is provided based on WLn+1 to which the read pass voltage is applied. Therefore, NWI compensation takes into account the condition of adjacent memory cells on WLn+1. Compensation is achieved by biasing adjacent word lines WLn+1, such that the resulting coupling cancels out the effects of programming WLn+1, thereby reducing or eliminating errors during reading of the selected word line WLn.

[0144] Figure 13 One embodiment of a process 1300 for suppressing interference from adjacent memory cells is illustrated in the flowchart. In some embodiments, the memory cells are located on a NAND string, where target cells are those selected for reading. For a given target cell on a NAND string, interference from adjacent cells on the NAND string is suppressed. In one embodiment, process 1300 is used to compensate for NWI on one side of the target cell (e.g., WLn+1) and lateral DR on the other side of the target cell (e.g., WLn-1). However, process 1300 is not limited to compensating for NWI on one side of the target cell and lateral DR on the other side of the target cell. In other words, process 1300 can suppress other types of adjacent memory cell interference. Process 1300 can be executed by control circuitry, which may include one or more of control circuitry 310, read / write circuitry 328, and / or memory controller 102. In some embodiments, process 1300 is initiated after a failure to decode data stored in the target cell. However, if a high BER is expected, process 1300 can be initiated proactively (i.e., before decoding failure).

[0145] Step 1302 includes setting the read reference voltage (Vcgr) to an initial amplitude. The read reference voltage will be applied to the target word line (WLn). This read reference voltage is used to distinguish between two data states. For example, Vcgr can be any of Vr1 to Vr15 (see [link to relevant documentation]). Figure 9Note that process 1300 covers a read at one read reference level. Process 1300 can be repeated for other read reference levels. Due to the memory cells on adjacent word lines, the magnitude of Vcgr will vary during process 1300 to provide different amounts of compensation for lateral DR. For illustration, WLn-1 will be referred to as the adjacent word line with the memory cell that causes the lateral DR problem.

[0146] Step 1304 includes setting the read pass voltage (VreadX) of the adjacent word line to an initial amplitude. The amplitude of VreadX will vary during process 1300 due to the memory cells on the adjacent word lines to provide different amounts of compensation for the NWI. For illustration, WLn+1 will be referred to as the adjacent word line to which VreadX is applied. Note that in process 1300, it is assumed that the WL programming order is from lower numbered word lines to higher numbered word lines. Therefore, WLn+1 is programmed after WLn. In another embodiment, the WL programming order is reversed (from higher numbered word lines to lower numbered word lines), in which case VreadX is applied to WLn-1. Furthermore, in the case of reversed WL programming order, the amplitude of Vcgr is selected to compensate for lateral DR caused by memory cells on WLn+1.

[0147] Step 1306 includes applying Vcgr to WLn, which is the word line connected to the target memory cell to be read. Step 1308 includes applying VreadX to WLn+1. Note that other read pass voltages are typically applied to other unselected word lines. Also note that VreadX is applied to WLn+1, while Vcgr is applied to WLn.

[0148] Step 1310 includes sensing the memory cells connected to WLn. Sensing occurs when VreadX is applied to WLn+1 and when Vcgr is applied to WLn. In some embodiments, all memory cells on WLn are sensed in step 1310, although the results for some memory cells may be discarded as described in step 1312. In cases where the sensing results would be discarded in step 1312, one option is to simply skip sensing those cells in step 1310.

[0149] Step 1312 includes storing the results of the memory cell based on the data state of adjacent memory cells. In some embodiments, the relevant adjacent cells for each target cell are two directly adjacent cells on the same NAND string. Step 1312 will be performed multiple times, wherein different combinations of Vcgr and VreadX are applied to WLn and WLn+1, respectively. At some point during process 1300, the sensing results associated with one combination of Vcgr and VreadX are stored (e.g., stored in a latch) for each target cell.

[0150] Prior to process 1300, information about the state of adjacent cells can be recorded (e.g., stored in a latch or some other storage device). For example, for each target cell, the first state information of the upper adjacent cell of WLn-1 and the second state information of the adjacent cell of WLn+1 can be recorded. This state information does not need to specify the exact state and can be recorded at a lower resolution. For example, if each cell stores four bits, the state information of each adjacent cell can be one, two, three, or four bits. This state information can be used to determine which combination of Vcgr and VreadX is relevant for each target cell.

[0151] Step 1314 involves determining whether another VreadX needs to be applied to WLn+1. If so, VreadX is set to the next amplitude in step 1316. Then, VreadX is applied to WLn+1 in step 1308. Note that the voltage at WLn can remain unchanged. Next, steps 1310 and 1312 are performed to sense the cell and store the results based on the state of adjacent cells.

[0152] Step 1314 is another determination of whether there is another VreadX to be applied to WLn+1. Assuming it does not exist, step 1318 includes determining whether there is another Vcgr to be applied to WLn. If so, Vcgr is set to the next amplitude in step 1320. Control then proceeds to step 1304, where VreadX is again set to the initial amplitude. Next, steps 1306 through 1314 are performed again as described above, but with the updated amplitude of Vcgr. Thus, multiple values ​​of VreadX can be applied to WLn+1 with the updated amplitude of Vcgr. After all values ​​of VreadX have been applied to WLn+1 with the updated amplitude of Vcgr, step 1318 includes determining whether there are any additional values ​​of Vcgr to be applied to WLn. If so, steps 1304 through 1314 are performed again. If not, the process ends.

[0153] Before executing process 1300, adjacent memory cells are read to determine information about the state of the adjacent cells. It is not necessary to determine a specific data state. For example, if each memory cell stores four bits, it may be sufficient to determine whether the cell has a low Vt (e.g., S0 to S7) or a high Vt (e.g., S8 to S15).

[0154] Figure 14One embodiment of a process 1400 for sensing adjacent memory cells and storing state information is described. Process 1400 may be executed prior to process 1300, such that the state information is available in step 1312. Step 1402 includes sensing memory cells on WLn-1. In some embodiments, process 1400 is executed in response to a data decoding failure stored on the target WL. However, LA information and / or DLA information stored in process 1400 may be stored without being triggered by such a decoding failure.

[0155] Step 1402 includes sensing memory cells on WLn-1. In step 1402, the cells may be sensed at the same "resolution" as the data stored therein or at a lower resolution. An example of a memory cell storing four bits per cell will be discussed for illustrative purposes. Reference Figure 9 For example, memory cells can be sensed at Vr8 to obtain one-bit resolution. Alternatively, memory cells can be sensed at Vr4, Vr8, and Vr12 to obtain two-bit resolution. Alternatively, memory cells can be sensed at Vr2, Vr4, Vr6, Vr8, Vr10, Vr12, and Vr14 to obtain three-bit resolution. Alternatively, memory cells can be sensed at each of Vr1 through Vr15 to obtain four-bit resolution.

[0156] Step 1404 includes storing “LA information”. The LA information is used to compensate for interference (e.g., lateral DR) caused by memory cells on WLn to memory cells on WLn-1. This LA information will be used to determine which Vcgr should be applied to each corresponding target cell on WLn. Recall that in process 1300, each Vcgr is applied to WLn, where a sensing result of a combination of a Vcgr and a VreadX is recorded for each target cell. Based on the sensing in step 1402, the LA information has one or more bits of resolution.

[0157] Step 1406 includes sensing memory cells on WLn+1. Cells may be sensed at the same "resolution" as the data stored therein or at a lower resolution. Cells on WLn+1 may be sensed at the same or a different resolution than cells on WLn-1 (in step 1402).

[0158] Step 1408 includes storing “DLA” information. The DLA information is used to compensate for interference (e.g., NWI) caused by memory cells on WLn to memory cells on WLn+1. This DLA information will be used to determine which VreadX should be applied to each corresponding target cell on WLn. In process 1300, each VreadX is applied to WLn+1, where a Vcgr and a VreadX sensing result are recorded for each target cell.

[0159] The following example illustrates which DLA information can be stored for two different programming schemes. (Reference) Figure 9 A fine-grained programming phase can be performed on WLn+1 after WLn's programming is complete. Therefore, the DLA information can specify the memory cells on WLn+1 whose charge increases the most during the fine-grained phase. (Reference) Figure 9 This will be the memory cell in an odd-numbered state (S1, S3, S5, etc.). Therefore, for a single-bit resolution, the DLA information specifies whether adjacent cells on a given NAND string are programmed to be in an odd-numbered or even-numbered state. (See reference) Figure 8B In the three-stage programming scheme, the memory cells that receive the most programming in the third stage are those in odd-numbered states (S1, S3, S5, S7). Therefore, for a single-bit resolution, the DLA information can specify whether adjacent cells on a given NAND string are programmed to an odd-numbered or even-numbered state. The partitioning of a single-bit DLA will not always be between odd and even states. As described herein, in some implementations, the partitioning is based on the amount of charge added to adjacent cells after programming is completed on the target cell.

[0160] In process 1400, LA information and DLA information can be stored at one-bit resolution or multiple-bit resolution. LA information and DLA information can be stored at the same resolution or different resolutions. In one embodiment, DLA information is stored at one-bit resolution, and LA information is stored at multiple-bit resolution.

[0161] Figure 15 A timing diagram depicting the voltage applied to the word line in one embodiment of process 1300 is shown. Four combinations of Vcgr and VreadX exist. WLn+1 receives VreadX or VreadX + ΔVDLA. In one embodiment, VreadX is the uncompensated nominal read pass voltage. In another embodiment, the uncompensated nominal read pass voltage has the same magnitude as the read pass voltage used during programming verification. Compensation for NWI can be provided by adding ΔVDLA to VreadX. In some embodiments, when VreadX + ΔVDLA is applied to WLn+1, the Vt of the memory cell on WLn will appear lower (relative to applying VreadX to WLn+1). WLn receives Vcgr or Vcgr + ΔVLA. In one embodiment, Vcgr is the uncompensated nominal read pass voltage. Compensation for lateral DR can be provided by adding ΔVLA to Vcgr. Other unselected word lines receive Vread without compensation for interference from adjacent cells.

[0162] Memory cells are sensed at the times depicted on the line marked "Sensing". Therefore, for each combination of VreadX and Vcgr, a memory cell is sensed once. The first time a memory cell is sensed (corresponding to Vcgr, VreadX), neither DLA nor LA compensation is provided. The second time a memory cell is sensed (corresponding to Vcgr, VreadX + ΔVDLA), DLA compensation is provided, but LA compensation is not. The third time a memory cell is sensed (corresponding to Vcgr + ΔVLA, VreadX), neither DLA compensation nor LA compensation is provided. The fourth time a memory cell is sensed (corresponding to Vcgr + ΔVLA, VreadX + ΔVDLA), both DLA and LA compensation are provided.

[0163] Figures 16A to 16D It is a combination of Figure 15 Flowcharts for the implementation schemes of the four scenarios discussed. Figure 16A The scenario depicts the case where DLA compensation and LA compensation are not provided. Step 1602 includes applying Vcgr to WLn. Step 1604 includes applying VreadX to WLn+1. Step 1606 includes applying Vread to other unselected word lines. Step 1608 includes sensing memory cells on WLn. Step 1610 includes storing the result of making the memory cells have no DLA compensation or LA compensation.

[0164] Figure 16B The case where DLA compensation is provided but LA compensation is not is described. Step 1622 includes applying Vcgr to WLn. Step 1624 includes applying VreadX+ΔVDLA to WLn+1. Step 1626 includes applying Vread to other unselected word lines. Step 1628 includes sensing memory cells on WLn. Step 1630 includes storing the result of giving the memory cells DLA compensation but not LA compensation.

[0165] Figure 16C The case where DLA compensation is provided but LA compensation is not is described. Step 1642 includes applying Vcgr+ΔVLA to WLn. Step 1644 includes applying VreadX to WLn+1. Step 1646 includes applying Vread to other unselected word lines. Step 1648 includes sensing memory cells on WLn. Step 1650 includes storing the result so that the memory cells have LA compensation but no DLA compensation.

[0166] Figure 16DThe scenario depicts the application of both DLA compensation and LA compensation. Step 1662 includes applying Vcgr+ΔVLA to WLn. Step 1664 includes applying VreadX+ΔVDLA to WLn+1. Step 1666 includes applying Vread to other unselected word lines. Step 1668 includes sensing memory cells on WLn. Step 1670 includes storing the result of providing both DLA compensation and LA compensation to the memory cells.

[0167] and Figure 15 and Figures 16A to 16D This describes a one-bit resolution for both DLA and LA compensation, and multiple-bit resolutions can be used for both DLA and / or LA compensation. In one implementation, multiple-bit resolution is used for LA compensation, in which case the modifications will be... Figure 15 This can be achieved by using, for example, four different amplitudes of the read reference voltage applied to WLn. Figure 15 Consistently, for each read reference voltage, two values ​​of the read voltage (VreadX, VreadX+ΔVDLA) are applied to WLn+1. In this example, the target cell will be sensed eight times, with one of the sensing results used for each target cell.

[0168] In some implementations, the log-likelihood ratio (LLR) is determined based on the sensed memory cells while suppressing interference between adjacent cells on both sides. LLR is the ratio of the probability of a bit being 0 to the probability of a bit being 1. A positive LLR indicates that the probability of the bit being estimated as 0 is greater than 1. A negative LLR indicates that the probability of the bit being estimated as 1 is greater than 0. The absolute value of the LLR indicates the certainty of the estimate.

[0169] When both NWI and lateral DR are compensated, LLR can be determined for the sensed memory cells. Figure 17 This is a flowchart of one implementation of the process 1700 for determining and using LLR while suppressing interference between adjacent units on both sides. Before performing process 1700, process 1400 can be executed to record LA information and DLA information.

[0170] Step 1702 includes sending the status of the memory cells for each sensing operation to the memory controller 102. Step 1702 may include target memory cells for sensing various combinations of Vcgr and VreadX, as described herein. The status information may include bits for each combination of Vcgr and VreadX. Alternatively, for each combination of Vcgr and VreadX, it may include multiple bits representing the quantization type of Vt of the cell. This group of target memory cells collectively stores a codeword.

[0171] Step 1704 includes sending LA information and DLA information to memory controller 102. As described above, this information can be collected during execution process 1400.

[0172] Step 1706 includes determining the LLR of the bits stored within the cell based on the state of the read cell (e.g., whether it reads Vt or quantizes Vt or the Vt bin index) and LA and DLA information. As described above, LLR is the ratio of the probability of a bit being 0 to the probability of a bit being 1 (in a codeword). In contrast to the embodiment described in process 1300, where a specific read outcome corresponding to one of the Vcgr and VreadX combinations is selected for each cell (making a "hard" decision), in process 1700, the different read outcomes for each cell (corresponding to different Vcgr and VreadX combinations) are weighted in a "soft" manner to produce a "soft" LLR metric.

[0173] Step 1708 involves decoding the codeword using an LLR. The LLR is used as input to the soft decision decoder.

[0174] In view of the foregoing, it can be seen that the first embodiment includes an apparatus comprising control circuitry configured to be connected to: a first non-volatile memory cell connected to a first word line, a second non-volatile memory cell connected to a second word line adjacent to the first word line, and a third non-volatile memory cell connected to a third word line adjacent to the first word line. The control circuitry is configured to apply two or more read reference voltages to the first word line, and to apply two or more read pass voltages to the second word line for each of the two or more read reference voltages, wherein the two or more read reference voltages are associated with the same data state. The control circuitry is configured to determine a condition of each corresponding first memory cell based on a combination of a first voltage from the two or more read reference voltages and a second voltage from the two or more read pass voltages, the first voltage depending on the state of adjacent cells on the third word line, and the second voltage depending on the state of adjacent cells on the second word line.

[0175] In the second embodiment, and to advance the first embodiment, the two or more read reference voltages include a compensated read reference voltage that compensates for interference to the first memory cell caused by charges stored on adjacent memory cells connected to the third word line. The two or more read pass voltages include a compensated read pass voltage that compensates for interference to the first memory cell caused by programming adjacent memory cells connected to the second word line. The control circuit applies the compensated read reference voltage to the first word line while simultaneously applying the compensated read pass voltage to the second word line.

[0176] In a third embodiment, and to advance the first or second embodiment, the control circuit is further configured to complete the programming of the second memory cell after the programming of the first memory cell is completed. At least one of two or more read-through voltages compensates for interference to the first memory cell caused by completing the programming of the second memory cell after the programming of the first memory cell is completed.

[0177] In the fourth embodiment, and to advance any of the first to third embodiments, the control circuitry is further configured to complete the programming of the first memory cell after the programming of the third memory cell is completed. The two or more read reference voltages include at least one voltage that compensates for interference to the first memory cell caused by the charge stored in the third memory cell.

[0178] In a fifth embodiment, and to advance any of the first to fourth embodiments, the control circuitry is further configured to sense third memory cells to determine the state of each third memory cell at a first resolution. Each of two or more read reference voltages corresponds to a state at the first resolution.

[0179] In the sixth embodiment, and to advance the fifth embodiment, the control circuit is further configured to sense the second memory cells to determine the state of each second memory cell at the second resolution. Each of the two or more read-through voltages corresponds to the state at the second resolution.

[0180] In the seventh embodiment, and to advance the fifth embodiment, a read reference voltage that provides the maximum compensation among two or more read reference voltages is applied in conjunction with a third memory cell having the highest threshold voltage. A read pass voltage that provides the maximum compensation among two or more read pass voltages is applied in conjunction with a second memory cell programmed during the final programming stage.

[0181] In the eighth embodiment, and to further any of the first to seventh embodiments, the control circuit is further configured to select the log-likelihood ratio (LLR) for decoding codewords stored in the first memory cells. This selection is based on the states of adjacent cells of each corresponding first memory cell on the third word line and the states of adjacent cells of each corresponding first memory cell on the second word line, and also on sensing the first memory cells using two or more read reference voltages applied to the first word line and two or more read pass voltages applied to the second word line. The value output for each corresponding first memory cell is based on decoding the codeword.

[0182] In the ninth embodiment, and to advance any of the first through eighth embodiments, the first, second, and third memory cells are arranged as NAND strings. Each NAND string includes a continuous charge trapping layer. One of two or more read reference voltages compensates for interference caused to the selected cell of the first memory cell on the selected NAND string by charges in the continuous charge trapping layer of the first unselected cell of the third memory cell stored on the selected NAND string. One of two or more read pass voltages compensates for interference caused to the selected first memory cell by charges in the continuous charge trapping layer of the second unselected cell of the second memory cell programmed into the selected NAND string.

[0183] One embodiment includes a method of operating a non-volatile memory device. The method includes applying a read reference voltage to a first word line, the read reference voltage compensating for interference caused to the first memory cell connected to the first word line by charge from a second memory cell stored on a second word line adjacent to a first side of the first word line. The method includes applying a read pass voltage to a third word line, the read pass voltage compensating for interference caused to the first memory cell by programming a third memory cell on the third word line. The third word line is adjacent to a second side of the first word line. The method includes sensing the first memory cell in response to applying the read reference voltage to the first word line while simultaneously applying the read pass voltage to the third word line. The method includes storing the result of sensing a subset of the first memory cells, the subset receiving compensation for interference caused by charge from an adjacent memory cell connected to the second word line, and receiving compensation for interference caused by programming an adjacent memory cell connected to the third word line.

[0184] One embodiment includes a non-volatile memory system comprising a plurality of NAND strings having non-volatile memory cells, and control circuitry communicating with the NAND strings. The control circuitry is configured to apply a read reference voltage to selected memory cells on selected NAND strings, the read reference voltage compensating for interference to the selected NAND strings caused by charge on a first unselected memory cell adjacent to one side of the selected memory cell. The control circuitry is configured to simultaneously apply a read pass voltage to a second unselected memory cell adjacent to the other side of the selected memory cell on the selected NAND strings, wherein the read pass voltage compensates for interference to the selected memory cell caused by programming the second unselected memory cell. The control circuitry is configured to sense the selected memory cell simultaneously with applying the read reference voltage to the selected memory cell and simultaneously with applying the read pass voltage to the second unselected memory cell. The control circuitry is configured to determine the state of the selected memory cell based on the sensed selected memory cell.

[0185] The specific embodiments of the invention described above have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best elucidate the principles of the invention and its practical application, thereby enabling others skilled in the art to best use the invention with various modifications suitable for the contemplated particular purpose in various embodiments. The scope of the invention is intended to be defined by the appended claims.

Claims

1. A memory device comprising: a control circuit configured to be connected to: a first non-volatile memory cell connected to a first word line, a second non-volatile memory cell connected to a second word line adjacent to the first word line, and a third non-volatile memory cell connected to a third word line adjacent to the first word line, the control circuit configured to: apply two or more read reference voltages to the first word line, and for each of the two or more read reference voltages, apply two or more read pass voltages to the second word line, wherein the two or more read reference voltages are associated with a same data state; and determine a condition of each respective first memory cell based on sensing the respective first memory cell for a combination of a first voltage from the two or more read reference voltages and a second voltage from the two or more read pass voltages, the first voltage dependent on a state of an adjacent cell on the third word line, the second voltage dependent on a state of an adjacent cell on the second word line.

2. The memory device of claim 1, wherein: the two or more read reference voltages include a compensation read reference voltage that compensates for interference from a charge stored on an adjacent memory cell connected to the third word line on the first non-volatile memory cell; and the two or more read pass voltages include a compensation read pass voltage that compensates for interference on the first non-volatile memory cell from programming an adjacent memory cell connected to the second word line, wherein the control circuit applies the compensation read reference voltage to the first word line while the control circuit applies the compensation read pass voltage to the second word line.

3. The memory device of claim 1, wherein the control circuit is further configured to: complete programming of the second non-volatile memory cell after completing programming of the first non-volatile memory cell, wherein at least one voltage of the two or more read pass voltages compensates for interference on the first non-volatile memory cell from completing the programming of the second non-volatile memory cell after completing the programming of the first non-volatile memory cell.

4. The memory device of claim 1, wherein the control circuit is further configured to: complete programming of the first non-volatile memory cell after completing programming of the third non-volatile memory cell, wherein the two or more read reference voltages include at least one voltage that compensates for interference on the first non-volatile memory cell from a charge stored in the third non-volatile memory cell.

5. The memory device of claim 1, wherein the control circuit is further configured to: sensing the third non-volatile memory cells to determine a state of each third non-volatile memory cell at a first resolution, wherein each voltage of the two or more read reference voltages corresponds to a state at the first resolution.

6. The memory device of claim 5, wherein the control circuit is further configured to: sense the second non-volatile memory cells to determine a state of each second non-volatile memory cell at a second resolution, wherein each voltage of the two or more read pass voltages corresponds to a state at the second resolution.

7. The memory device of claim 6, wherein: the read reference voltage of the two or more read reference voltages that provides the greatest compensation is applied in conjunction with the third non-volatile memory cell having the highest threshold voltage; and the read pass voltage of the two or more read pass voltages that provides the greatest compensation is applied in conjunction with the second non-volatile memory cell programmed at the final programming stage.

8. The memory device of claim 1, wherein the control circuit is further configured to: select a log likelihood ratio (LLR) for decoding a codeword stored in the first non-volatile memory cells, the selection based on states of neighboring cells of each respective first memory cell on the third word line and states of neighboring cells of each respective first memory cell on the second word line, and further based on sensing the first non-volatile memory cells with the two or more read reference voltages applied to the first word line and with the two or more read pass voltages applied to the second word line, wherein a value output for each respective first memory cell is based on decoding the codeword.

9. The memory device of claim 1, wherein: the first non-volatile memory cells, the second non-volatile memory cells, and the third non-volatile memory cells are arranged as NAND strings, each NAND string including successive charge-trapping layers; one voltage of the two or more read reference voltages compensates for interference caused by charge in the successive charge-trapping layers from a first unselected cell of the third non-volatile memory cells stored on a selected NAND string to a selected cell of the first non-volatile memory cells on the selected NAND string; and one voltage of the two or more read pass voltages compensates for interference caused by charge in the successive charge-trapping layers from a second unselected cell of the second non-volatile memory cells programmed onto a selected NAND string to a selected first non-volatile memory cell.

10. A method of operating a non-volatile storage device, the method comprising: applying a read reference voltage to a first word line, the read reference voltage compensating for interference caused by charge from a second memory cell stored on a second word line adjacent to a first side of the first word line to a first memory cell connected to the first word line; applying a read pass voltage to a third word line, the read pass voltage compensating for interference with the first memory cell caused by programming a third memory cell on the third word line, the third word line being adjacent to a second side of the first word line; sensing the first memory cell in response to applying the read reference voltage to the first word line while applying the read pass voltage to the third word line; and storing results of sensing a subset of the first memory cells, the subset receiving compensation for interference from a charge stored on an adjacent memory cell connected to the second word line and receiving compensation for interference caused by programming an adjacent memory cell connected to the third word line.

11. The method of claim 10, further comprising: verifying completion of programming of the first memory cell before verifying completion of programming of the third memory cell.

12. The method of claim 11, further comprising: verifying completion of programming of the second memory cell before verifying completion of programming of the first memory cell.

13. The method of claim 10, further comprising: performing a first foggy-fine programming operation first foggy phase on the first memory cell before performing a second foggy-fine programming operation second foggy phase on the third memory cell; and performing the first foggy-fine programming operation first fine phase on the first memory cell before performing the second foggy-fine programming operation second fine phase on the third memory cell, wherein the read pass voltage applied to the third word line compensates for interference with the first memory cell caused by performing the second foggy-fine programming operation second fine phase on the third memory cell.

14. The method of claim 10, further comprising: sensing the second memory cell; based on sensing the second memory cell, storing first information for each respective first memory cell, the first information specifying whether the respective first memory cell is to receive compensation for interference from an adjacent memory cell connected to the second word line; sensing the third memory cell; based on sensing the third memory cell, storing second information for each respective first memory cell, the second information specifying whether the respective first memory cell is to receive compensation for interference from an adjacent memory cell connected to the third word line; and determining the subset of the first memory cells using the first information and the second information.

15. A non-volatile storage system, comprising: a plurality of NAND strings, the plurality of NAND strings including non-volatile memory cells; and control circuitry in communication with the NAND strings, the control circuitry configured to: ​ applying a read reference voltage to a selected memory cell on a selected NAND string, the read reference voltage compensating for interference with the selected NAND string from charge stored on a first unselected memory cell adjacent one side of the selected memory cell on the selected NAND string; applying a read pass voltage to a second unselected memory cell adjacent another side of the selected memory cell on the selected NAND string while applying the read reference voltage to the selected memory cell, wherein the read pass voltage compensates for interference with the selected memory cell resulting from programming the second unselected memory cell; sensing the selected memory cell while applying the read reference voltage to the selected memory cell and while applying the read pass voltage to the second unselected memory cell; and determining a state of the selected memory cell based on sensing the selected memory cell.

16. The non- volatile storage system of claim 15, wherein the control circuitry is further configured to: program the first unselected memory cell to its final data state; and after programming the first unselected memory cell to its final data state, program the selected memory cell to its final data state.

17. The non- volatile storage system of claim 16, wherein the control circuitry is further configured to: after programming the selected memory cell to its final data state, program the second unselected memory cell to its final data state.

18. The non- volatile storage system of claim 16, wherein the control circuitry is further configured to: sense the first unselected memory cell; based on sensing the first unselected memory cell, store first information specifying an amount of compensation the selected memory cell is to receive from interference from the first unselected memory cell; sense the second unselected memory cell; based on sensing the second unselected memory cell, store second information specifying an amount of compensation the selected memory cell is to receive from interference from the second unselected memory cell; and use the first information and the second information to determine a magnitude of the read pass voltage and a magnitude of the read reference voltage for which the selected memory cell is to be sensed to determine the data state of the selected memory cell.

19. The non- volatile storage system of claim 15, wherein: the plurality of NAND strings each include a charge trapping layer; and the control circuitry is configured to program the memory cells by adding charge to the charge trapping layer, wherein the control circuitry completes programming of the second unselected memory cell after completing programming of the selected memory cell.

20. The non- volatile storage system of claim 15, wherein the control circuitry is further configured to: ​ selecting a log likelihood ratio (LLR) for a codeword stored in a selected memory cell in the plurality of NAND strings, the selection based on states of first unselected cells on one side of the selected memory cell and states of second unselected cells on another side of the selected memory cell, and based on sensing the selected memory cell while applying the read reference voltage to the selected memory cell and while applying the read pass voltage to the second unselected memory cells.

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