Semiconductor memory devices and their operation methods

Abstract

A semiconductor memory device includes a memory block and control logic. The memory block includes a plurality of memory cells. The control logic controls peripheral circuitry to perform a read operation on a selected memory cell among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuitry to float a common source line coupled to the memory block during at least a portion of the bit line precharge operation, during which the voltages of the plurality of bit lines coupled to the memory block increase.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0168782, filed with the Korean Intellectual Property Office on December 4, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] One or more embodiments described herein relate to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0004] Semiconductor memory devices can be formed with either a two-dimensional or three-dimensional structure. When formed in a two-dimensional structure, strings are arranged horizontally on a semiconductor substrate. When formed in a three-dimensional structure, strings are stacked vertically on a semiconductor substrate. Compared to two-dimensional memory devices, three-dimensional memory devices offer greater integration and have therefore attracted attention. Summary of the Invention

[0005] One or more embodiments described herein provide semiconductor memory devices capable of reducing power consumption during read or verification operations.

[0006] One or more embodiments described herein provide a method of operating such a semiconductor memory device.

[0007] According to one embodiment of this disclosure, a semiconductor memory device includes a memory block and control logic. The memory block includes a plurality of memory cells. The control logic controls peripheral circuitry to perform a read operation on a selected memory cell among the plurality of memory cells. The read operation includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuitry to float a common source line coupled to the memory block during at least a portion of the bit line precharge operation period.

[0008] In one embodiment, during a bit line precharge operation, control logic can be configured to control peripheral circuitry to: increase the voltage of multiple bit lines to a predetermined precharge voltage, and apply a shutdown voltage to drain select lines and source select lines coupled to the memory block.

[0009] In one embodiment, during the evaluation operation, the control logic can be configured to control the peripheral circuitry to: apply a read voltage to a selected word line coupled to a selected memory cell, apply a pass voltage to an unselected word line, and apply an on voltage to a drain select line and a source select line coupled to a memory block.

[0010] In one embodiment, the control logic can be configured to control the peripheral circuitry to apply a reference voltage to the common source line during evaluation operations.

[0011] In one embodiment, during sensing operation, the control logic can be configured to control peripheral circuitry to temporarily store information indicating whether a selected memory cell is switched on.

[0012] In one embodiment, the control logic can be configured to control the peripheral circuitry to float the common source line during at least a portion of the sensing operation period.

[0013] According to another embodiment of this disclosure, a semiconductor memory device includes a memory block and control logic. The memory block includes a plurality of memory cells. The control logic controls peripheral circuitry to perform a plurality of read operations on selected memory cells among the plurality of memory cells. Each of the plurality of read operations includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuitry to float a common source line coupled to the memory block during at least a portion of a time period including a sensing operation of a first read operation and a bit line precharge operation of a second read operation following the first read operation.

[0014] In one embodiment, during the sensing operation of the first read operation, the control logic can be configured to control peripheral circuitry to temporarily store information indicating whether the memory cell selected as the target of the first read operation is turned on.

[0015] In one embodiment, during the bit-line precharge operation of the second read operation, the control logic can be configured to control the peripheral circuitry to: increase the voltage of multiple bit lines to a predetermined precharge voltage, and apply a shutdown voltage to the drain select line and source select line coupled to the memory block.

[0016] In one embodiment, during the evaluation operation of the first read operation, the control logic may be configured to control the peripheral circuitry to: apply a read voltage to a first selected word line coupled to a first memory cell selected as the target of the first read operation; apply a pass voltage to unselected word lines other than the first selected word line; apply an on voltage to drain select lines and source select lines coupled to the memory block; and apply a reference voltage to a common source line.

[0017] In one embodiment, during the evaluation operation of the second read operation, the control logic may be configured to control the peripheral circuitry to: apply a read voltage to a second selected word line coupled to a second memory cell selected as the target of the second read operation; apply a pass voltage to unselected word lines other than the second selected word line; apply an on voltage to drain select lines and source select lines coupled to the memory block; and apply a reference voltage to a common source line.

[0018] According to another embodiment of this disclosure, a method of operating a semiconductor memory device includes performing a read operation on selected memory cells among a plurality of memory cells. The read operation includes: pre-charging a voltage on a bit line coupled to a memory block including the selected memory cell; applying a read voltage to a selected word line coupled to the selected memory cell in a word line coupled to the memory block, and applying a read voltage to unselected word lines in the word line other than the selected word line; and temporarily storing information indicating whether the selected memory cell is turned on based on the voltage of each bit line in the bit lines. Pre-charging the voltage on the bit line coupled to the memory block including the selected memory cell includes: floating a common source line coupled to the memory block during at least a portion of a period in which the voltage of the bit line increases.

[0019] In one embodiment, precharging the voltage of a bit line coupled to a memory block including a selected memory cell may include increasing the voltage of a plurality of bit lines to a predetermined precharge voltage, and applying a turn-off voltage to a drain select line and a source select line coupled to the memory block.

[0020] In one embodiment, applying a read voltage to a word line coupled to a memory block, a selected word line coupled to a selected memory cell, and applying a read pass voltage to an unselected word line other than the selected word line may include: applying a read voltage to a selected word line coupled to a selected memory cell, applying a pass voltage to an unselected word line, and applying an on voltage to a drain select line and a source select line coupled to the memory block.

[0021] In one embodiment, applying a read voltage to a selected word line coupled to a selected memory cell and applying a read voltage to an unselected word line other than the selected word line may include applying a reference voltage to a common source line.

[0022] In one embodiment, based on the voltage of each bit line in the bit line, temporarily storing information indicating whether the selected memory cell is turned on may include: floating the common source line.

[0023] According to another embodiment of this disclosure, a semiconductor memory device includes a memory block, peripheral circuitry, and control logic. The memory block includes a plurality of memory cells. The peripheral circuitry performs a programming operation on a selected memory cell among the plurality of memory cells. The control logic controls the programming operation of the peripheral circuitry. The programming operation includes a plurality of programming cycles, and each programming cycle includes a programming phase and a verification phase. The verification phase includes a bit line precharge operation, an evaluation operation, and a sensing operation. The control logic is configured to control the peripheral circuitry to float a common source line coupled to the memory block during at least a portion of the bit line precharge operation, in which the voltages of the plurality of bit lines coupled to the memory block increase.

[0024] In one embodiment, during a bit line precharge operation, control logic can be configured to control peripheral circuitry to: increase the voltage of multiple bit lines to a predetermined precharge voltage, and apply a shutdown voltage to drain select lines and source select lines coupled to the memory block.

[0025] In one embodiment, during the evaluation operation, the control logic can be configured to control the peripheral circuitry to: apply a verification voltage to a selected word line coupled to a selected memory cell, apply a pass voltage to an unselected word line, apply an on voltage to a drain select line and a source select line coupled to a memory block, and apply a reference voltage to a common source line.

[0026] In one embodiment, during sensing operation, the control logic can be configured to: control peripheral circuitry to temporarily store information indicating whether a selected memory cell is turned on, and to float the common source line during at least a portion of the sensing operation.

[0027] According to another embodiment of this disclosure, an apparatus includes a storage region and at least one processor. The storage region is configured to store instructions. The at least one processor is configured to execute instructions to control a read operation including a bit line precharge operation, an evaluation operation, and a sensing operation. The at least one processor is configured to control the read operation such that a common source line coupled to a memory block is floated during at least a portion of the bit line precharge operation, in which the voltages of a plurality of bit lines coupled to the memory block are increased.

[0028] This technology can provide a semiconductor memory device and its operation method that can reduce power consumption during read or verification operations. Attached Figure Description

[0029] Figure 1 An embodiment of a semiconductor memory device is illustrated.

[0030] Figure 2 An embodiment of a memory cell array is illustrated.

[0031] Figure 3 An embodiment of a memory block is illustrated.

[0032] Figure 4 An embodiment of a memory block is illustrated.

[0033] Figure 5 An embodiment of a memory block is illustrated.

[0034] Figure 6 An embodiment of a page buffer is illustrated.

[0035] Figure 7 The illustration shows an example of the operations included in a read operation.

[0036] Figure 8 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0037] Figure 9 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0038] Figure 10 An embodiment of memory operation is illustrated.

[0039] Figure 11 An embodiment of memory operation is illustrated.

[0040] Figure 12 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0041] Figure 13 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0042] Figure 14 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0043] Figure 15 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0044] Figure 16 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0045] Figure 17 The illustration shows an example corresponding to multiple read operations.

[0046] Figure 18 The diagram illustrates a method for operating a semiconductor memory device.

[0047] Figure 19 This is a diagram illustrating one embodiment of the operation of a semiconductor memory device.

[0048] Figure 20 The illustration shows an example of the threshold voltage distribution of a multi-level cell.

[0049] Figure 21 An embodiment of a method for operating a semiconductor memory device is illustrated.

[0050] Figure 22 An embodiment of the memory system is illustrated.

[0051] Figure 23 The illustration shows an application example of a memory system.

[0052] Figure 24 An embodiment of the computing system is illustrated. Detailed Implementation

[0053] The specific structural or functional descriptions of embodiments based on the concepts disclosed in this specification or application are for illustrative purposes only. Embodiments based on the concepts of this disclosure may be implemented in various forms and are not limited to those described in this specification or application.

[0054] Figure 1 This is a block diagram illustrating a semiconductor memory device 100 according to one embodiment.

[0055] refer to Figure 1 The semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, control logic 140, and a voltage generator 150.

[0056] The memory cell array 110 includes multiple memory blocks BLK1 to BLKz connected to the address decoder 120 via word lines WL. The multiple memory blocks BLK1 to BLKz are connected to read and write circuitry 130 via bit lines BL1 to BLm. Each of the multiple memory blocks BLK1 to BLKz includes multiple memory cells. In one embodiment, the multiple memory cells are non-volatile memory cells and may include non-volatile memory cells with a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional memory cell array.

[0057] According to one embodiment, the memory cell array 110 can be configured as a three-dimensional memory cell array. Each memory cell in the plurality of memory cells included in the memory cell array can store at least one bit of data. In one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 can be a single-level cell (SLC) storing one bit of data. In one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 can be a multi-level cell (MLC) storing two bits of data. In one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 can be a three-level cell storing three bits of data. In one embodiment, each memory cell in the plurality of memory cells included in the memory cell array 110 can be a four-level cell storing four bits of data. According to one embodiment, the memory cell array 110 can include a plurality of memory cells, each of which stores five or more bits of data.

[0058] The address decoder 120, read and write circuitry 130, and voltage generator 150 can operate as peripheral circuitry driving the memory cell array 110. This peripheral circuitry can operate under the control of control logic 140. The address decoder 120 is connected to the memory cell array 110 via word line WL and can be configured to operate in response to the control logic 140. The address decoder 120 receives addresses through input / output buffers within the semiconductor memory device 100.

[0059] Address decoder 120 is configured to decode block addresses from received addresses. Address decoder 120 selects at least one memory block based on the decoded block address. During a read operation, when a read voltage is applied, address decoder 120 applies a read voltage Vread generated in voltage generator 150 to the selected word line of the selected memory block. At this time, address decoder 120 also applies a voltage Vpass to the remaining unselected word lines. During a program verification operation, address decoder 120 applies a verification voltage generated in voltage generator 150 to the selected word line of the selected memory block, and may also apply a voltage Vpass to the remaining unselected word lines.

[0060] Address decoder 120 is configured to decode the column address of the received address and transmit the decoded column address to read and write circuit 130.

[0061] Read and programming operations of the semiconductor memory device 100 are performed on a page-by-page basis. The address received when requesting a read or programming operation includes a block address, a row address, and a column address. The address decoder 120 selects a memory block and a word line based on the block and row addresses. The column address is decoded by the address decoder 120 and provided to the read and write circuitry 130.

[0062] Address decoder 120 may include block decoder, row decoder, column decoder, address buffer, etc.

[0063] The read and write circuit 130 includes multiple page buffers PB1 to PBm. The read and write circuit 130 can operate as a read circuit during read operations of the memory cell array 110 and as a write circuit during write operations of the memory cell array 110. The multiple page buffers PB1 to PBm are connected to the memory cell array 110 via bit lines BL1 to BLm. During read and program verification operations, in order to sense the threshold voltage of the memory cell, the page buffers PB1 to PBm can sense changes in the amount of current flowing through the sensing node according to the programming state of the corresponding memory cell. The page buffers PB1 to PBm can perform this operation while continuously providing sensing current to the bit lines connected to the memory cell, and can latch the sensed changes as sensed data. The read and write circuit 130 operates in response to a page buffer control signal output from control logic 140.

[0064] During a read operation, the read and write circuit 130 senses data in the memory cell, temporarily stores the read data, and outputs the data DATA to the input / output buffer of the semiconductor memory device 100. As an exemplary embodiment, in addition to a page buffer (or page register), the read and write circuit 130 may also include column select circuitry, etc.

[0065] Control logic 140 is connected to address decoder 120, read and write circuitry 130, and voltage generator 150. Control logic 140 can receive commands CMD and control signals CTRL via input / output buffers of semiconductor memory device 100. Control logic 140 is configured to control the overall operation of semiconductor memory device 100 in response to control signal CTRL. Furthermore, control logic 140 outputs control signals for adjusting the precharge potential levels of sensing nodes in multiple page buffers PB1 to PBm. Control logic 140 can control read and write circuitry 130 to perform read operations on memory cell array 110. The control logic controls voltage generator 150 to generate various voltages used during programming operations of memory cell array 110.

[0066] Furthermore, control logic 140 controls address decoder 120 to transmit the voltage generated by voltage generator 150 to the local lines of the memory block targeted by the operation via global lines. Simultaneously, control logic 140 controls read and write circuitry 130 to read data from the selected page of the memory block via bit lines BL1 to BLm during a read operation and store the data in page buffers PB1 to PBm. Furthermore, control logic 140 controls read and write circuitry 130 to program the data stored in page buffers PB1 to PBm into the selected page during a programmable operation.

[0067] In response to a control signal output from control logic 140, voltage generator 150 generates a read voltage Vread and a pass voltage Vpass during a read operation. To generate multiple voltages with various voltage levels, voltage generator 150 may include multiple pump capacitors that receive an internal supply voltage, and in response to control by control logic 140, voltage generator 150 can generate multiple voltages by selectively activating the pump capacitors.

[0068] The address decoder 120, read and write circuitry 130, and voltage generator 150 can be used as "peripheral circuitry" to perform read, write, and erase operations on the memory cell array 110. The peripheral circuitry performs these operations based on control logic 140.

[0069] Figure 2 This is a block diagram illustrating one embodiment of a memory cell array 110 comprising multiple memory blocks BLK1 to BLKz. Each memory block has a three-dimensional structure and includes multiple memory cells stacked on a substrate. These multiple memory cells are arranged along the +X, +Y, and +Z directions. (See reference...) Figure 3 and Figure 4 Describe an embodiment of each memory block.

[0070] Figure 3 This is a circuit diagram of the memory block BLKa, which can represent... Figure 2 The memory blocks BLK1 to BLKz.

[0071] refer to Figure 3 The memory block BLKa comprises multiple cell strings CS11 to CS1m and CS21 to CS2m. In one embodiment, each of the multiple cell strings CS11 to CS1m and CS21 to CS2m can be formed with a predetermined shape, such as a "U" shape or another shape. In the memory block BLKa, m cell strings are arranged in the row direction (e.g., the +X direction). Figure 3In this embodiment, two unit strings are arranged in the column direction (e.g., the +Y direction). In another embodiment, three or more unit strings may be arranged in the column direction.

[0072] Each of the multiple cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, a pipe transistor PT, and at least one drain selection transistor DST.

[0073] The select transistors SST and DST can have similar structures, and the memory cells MC1 to MCn can have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunnel insulating film, charge storage film, and barrier insulating film.

[0074] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCp. In one embodiment, the source select transistors of cell strings arranged in the same row are connected to a source select line extending in the row direction. Furthermore, the source select transistors of cell strings arranged in different rows are connected to different source select lines. Figure 3 In the first row, the source selection transistors CS11 to CS1m are connected to the first source selection line SSL1. The source selection transistors CS21 to CS2m in the second row are connected to the second source selection line SSL2.

[0075] In one embodiment, the source selection transistors of cell strings CS11 to CS1m and CS21 to CS2m can be connected together to a source selection line.

[0076] The first to nth memory cells MC1 to MCn of each cell string are connected between the source selection transistor SST and the drain selection transistor DST. The first to nth memory cells MC1 to MCn can be divided into the first to pth memory cells MC1 to MCp, and the (p+1)th to nth memory cells MCp+1 to MCn. The first to pth memory cells MC1 to MCp are arranged in the opposite direction to the +Z direction and are connected in series between the source selection transistor SST and the pipe transistor PT.

[0077] Memory cells (p+1) to nth memory cells MCp+1 to MCn are arranged sequentially in the +Z direction and connected in series between the channel transistor PT and the drain selection transistor DST. The first memory cells to pth memory cells MC1 to MCp, and the (p+1)th memory cells to nth memory cells MCp+1 to MCn are interconnected via the channel transistor PT. The gates of the first memory cells to nth memory cells MC1 to MCn in each cell string are respectively connected to the first word line to the nth word line WL1 to WLn.

[0078] The gate of the pipe transistor PT in each cell string is connected to the pipe line PL.

[0079] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MCp+1 to MCn. Cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11 to CS1m in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21 to CS2m in the second row are connected to the second drain select line DSL2.

[0080] The cell string arranged in the column direction is connected to the bit line extending in the column direction. Figure 3 In the diagram, the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0081] Memory cells connected to the same word line in a cell string arranged in a row direction constitute a page. For example, memory cells connected to the first word line WL1 (in cell strings CS11 to CS1m of the first row) can constitute one page. Memory cells connected to the first word line WL1 (in cell strings CS21 to CS2m of the second row) can constitute another page. A cell string arranged in a row direction can be selected by selecting one of the drain select lines DSL1 and DSL2. A page of the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0082] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines to the m-th bit lines BL1 to BLm. In the cell strings CS11 to CS1m or CS21 to CS2m, the cell strings with even-numbered positions arranged in the row direction can be connected to the even-numbered bit lines respectively, and the cell strings with odd-numbered positions arranged in the row direction can be connected to the odd-numbered bit lines respectively.

[0083] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. In one embodiment, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. Providing more dummy memory cells can improve the operational reliability of the memory block BLKa, but it increases the size of the memory block BLKa. Providing fewer dummy memory cells can reduce the size of the memory block BLKa, but it may decrease the operational reliability of the memory block BLKa.

[0084] To effectively control at least one dummy memory cell, each dummy memory cell can have a threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKa. When an erase operation is performed after a programming operation, the dummy memory cell can have a threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0085] Figure 4 This is a circuit diagram illustrating one embodiment of the memory block BLKb, which can represent... Figure 2 The memory blocks BLK1 to BLKz.

[0086] refer to Figure 4 The memory block BLKb includes multiple cell strings CS11' to CS1m' and CS21' to CS2m'. Each of the multiple cell strings CS11' to CS1m' and CS21' to CS2m' extends along the +Z direction and may include at least one source selection transistor SST, first memory cells to nth memory cells MC1 to MCn, and at least one drain selection transistor DST stacked on a substrate below the memory block BLK1'.

[0087] The source select transistor SST of each cell string is connected between the common source line CSL and memory cells MC1 to MCn. Source select transistors of cell strings arranged in the same row are connected to the same source select line. The source select transistors of cell strings CS11' to CS1m' arranged in the first row are connected to the first source select line SSL1. The source select transistors of cell strings CS21' to CS2m' arranged in the second row are connected to the second source select line SSL2. In one embodiment, the source select transistors of cell strings CS11' to CS1m' and CS21' to CS2m' may be connected to a common source select line.

[0088] The first memory cell to the nth memory cell MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first memory cell to the nth memory cell MC1 to MCn are respectively connected to the first word line to the nth word line WL1 to WLn.

[0089] The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn. The drain select transistors of cell strings arranged in the row direction are connected to drain select lines extending in the row direction. The drain select transistors of cell strings CS11' to CS1m' in the first row are connected to the first drain select line DSL1. The drain select transistors of cell strings CS21' to CS2m' in the second row are connected to the second drain select line DSL2.

[0090] As a result, in addition to excluding the pipe transistor PT from each cell string, Figure 4 The memory block BLKb can have the same as Figure 3 The equivalent circuit of the memory block BLKa is similar to the equivalent circuit.

[0091] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit line to the m-th bit line BL1 to BLm. In the cell strings CS11' to CS1m' or CS21' to CS2m', the cell strings with even-numbered numbers arranged in the row direction can be connected to the even-numbered bit lines respectively, and the cell strings with odd-numbered numbers arranged in the row direction can be connected to the odd-numbered bit lines respectively.

[0092] In one embodiment, at least one of the memory cells MC1 to MCn from the first memory cell to the nth memory cell can be used as a dummy memory cell. For example, at least one dummy memory cell can be provided to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCn. In one embodiment, at least one dummy memory cell is provided to reduce the electric field between the drain selection transistor DST and the memory cells MC1 to MCn. Providing more dummy memory cells can improve the reliability of operation on the memory block BLKb, but increases the size of the memory block BLKb. Providing fewer dummy memory cells can reduce the size of the memory block BLKb, but may decrease the reliability of operation on the memory block BLKb.

[0093] To effectively control at least one dummy memory cell, each dummy memory cell can have a threshold voltage. Programming operations can be performed on all or some of the dummy memory cells before or after an erase operation on the memory block BLKb. When an erase operation is performed after a programming operation, the dummy memory cell can have a threshold voltage by controlling the voltage applied to the dummy word line connected to the respective dummy memory cell.

[0094] Figure 5 This is a circuit diagram of one embodiment of the memory block BLKc, which can represent Figure 1 The memory blocks BLK1 to BLKz in the memory cell array 110.

[0095] refer to Figure 5 The memory block BLKc includes multiple cell strings CS1 to CSm connected to multiple bit lines BL1 to BLm respectively. Each cell string CS1 to CSm includes at least one source selection transistor SST, a first memory cell to an nth memory cell MC1 to MCn, and at least one drain selection transistor DST.

[0096] The select transistors SST and DST can have similar structures, and the memory cells MC1 to MCn can have similar structures. In one embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn may include a channel layer, a tunnel insulating film, a charge storage film, and a barrier insulating film. In one embodiment, a pillar for providing the channel layer may be provided in each cell string. In one embodiment, a pillar may be provided in each cell string for providing at least one of the channel layer, tunnel insulating film, charge storage film, and barrier insulating film.

[0097] The source select transistor (SST) of each cell string is connected between the common source line (CSL) and memory cells MC1 to MCn. The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor (SST) and the drain select transistor (DST). The drain select transistor (DST) of each cell string is connected between the corresponding bit line and memory cells MC1 to MCn.

[0098] Memory cells connected to the same word line can form a page. Cell strings CS1 to CSm can be selected by selecting the drain select line DSL. A page within the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0099] In one embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first bit lines to the m-th bit lines BL1 to BLm. In the cell strings CS1 to CSm, even-numbered cell strings can be connected to the even-numbered bit lines respectively, and odd-numbered cell strings can be connected to the odd-numbered bit lines respectively.

[0100] like Figures 2 to 4 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a three-dimensional memory cell array. For example... Figure 5 As shown, the memory cell array 110 of the semiconductor memory device 100 can be configured as a two-dimensional memory cell array.

[0101] Figure 6 It is a diagram. Figure 1 This diagram illustrates one embodiment of the configuration of each page buffer PBx in the read and write circuitry of the semiconductor memory device shown. The page buffer PBx can represent... Figure 1 The page buffers PB1 to PBm in the read and write circuit 130, and the bit line BLx is shown as being connected to the page buffer PBx.

[0102] The read and write circuitry 130 may include a plurality of page buffers PB1 to PBm. Each page buffer PB1 to PBm included in the read and write circuitry 130 may include a bit line transistor assembly 401 and a sensing transistor assembly 403. The bit line transistor assembly 401 may include fourth to sixth transistors TR4 to TR6, and the sensing transistor assembly 403 may include first to third transistors TR1 to TR3, and seventh to ninth transistors TR7 to TR9, as well as a latch assembly. Therefore, in this example, each page buffer may include first to ninth transistors TR1 to TR9 and a latch assembly. The latch assembly may be composed of transistors that store data sensed through the bit line BLx. The first to ninth transistors TR1 to TR9 may be turned on or off to adjust the voltage applied to the bit line BLx.

[0103] The first transistor TR1 can be a sensing node precharge transistor connected between the power supply VCORE and the sensing node SO. The first transistor TR1 can be turned on or off by the sensing node precharge signal PRECHSO_N. When the first transistor TR1 is turned on by the sensing node precharge signal PRECHSO_N, the power supply VCORE and the sensing node SO can be connected to each other. For example, a current path can be formed between the power supply VCORE and the sensing node SO via the sensing node precharge signal PRECHSO_N. In one embodiment, the first transistor TR1 can be implemented using a PMOS transistor, but in another embodiment, the first transistor TR1 can be implemented using an NMOS transistor.

[0104] The second transistor TR2 can be a data transfer transistor connected between the power supply VCORE and the third node N3. The second transistor TR2 can be turned on or off by the data transfer signal QS. When the second transistor TR2 is turned on by the data transfer signal QS, the power supply VCORE and the third node N3 can be connected to each other. For example, a current path can be formed between the power supply VCORE and the third node N3 via the data transfer signal QS. In one embodiment, the second transistor TR2 can be implemented using a PMOS transistor, but in another embodiment, the second transistor TR2 can be implemented using an NMOS transistor.

[0105] The third transistor TR3 can be a precharged transistor connected between the third node N3 and the sensing node SO. The third transistor TR3 can be turned on or off by the precharge signal PRE_N. When the third transistor TR3 is turned on by the precharge signal PRE_N, the third node N3 and the sensing node SO can be connected to each other. For example, a current path can be formed between the third node N3 and the sensing node SO via the precharge signal PRE_N. In one embodiment, the third transistor TR3 can be implemented using a PMOS transistor, but in another embodiment, the third transistor TR3 can be an NMOS transistor.

[0106] The fourth transistor TR4 can be a bit line precharge transistor connected between the power supply VCORE and the first node N1. The fourth transistor TR4 can be turned on or off by the bit line precharge signal BL_PRE. When the fourth transistor TR4 is turned on by the bit line precharge signal BL_PRE, the power supply VCORE and the first node N1 can be connected to each other. For example, a current path can be formed between the power supply VCORE and the first node N1 via the bit line precharge signal BL_PRE. In one embodiment, the fourth transistor TR4 can be implemented using a PMOS transistor, but in another embodiment, the fourth transistor TR4 can be an NMOS transistor.

[0107] The fifth transistor TR5 can be a bit line discharge transistor connected between the first node N1 and a reference potential (e.g., ground). The fifth transistor TR5 can be turned on or off by the bit line discharge signal BL_DIS. When the fifth transistor TR5 is turned on by the bit line discharge signal BL_DIS, the first node N1 and ground can be connected to each other. For example, a current path can be formed between the first node N1 and ground via the bit line discharge signal BL_DIS. In one embodiment, the fifth transistor TR5 can be implemented using an NMOS transistor, but in another embodiment, the fifth transistor TR5 can be a PMOS transistor.

[0108] The sixth transistor TR6 can be a bit line select transistor connected between the first node N1 and the bit line, which is connected to a page buffer in the page buffer. The sixth transistor TR6 can be turned on or off by the bit line select signal SEL_BL. When the sixth transistor TR6 is turned on by the bit line select signal SEL_BL, the bit line and the first node N1 can be connected to each other. For example, a current path can be formed between the bit line and the first node N1 via the bit line select signal SEL_BL. In one embodiment, the sixth transistor TR6 can be implemented using an NMOS transistor, but in another embodiment, the sixth transistor TR6 can be a PMOS transistor.

[0109] The seventh transistor TR7 can be a sensing transistor connected between the first node N1 and the second node N2. The seventh transistor TR7 can be turned on or off by the sensing signal PBSENSE. When the seventh transistor TR7 is turned on by the sensing signal PBSENSE, the first node N1 and the second node N2 can be connected. For example, a current path can be formed between the first node N1 and the second node N2 by the sensing signal PBSENSE. In one embodiment, the seventh transistor TR7 can be implemented using an NMOS transistor, but in another embodiment, the seventh transistor TR7 can be a PMOS transistor.

[0110] The eighth transistor TR8 can be a sensing transmission transistor connected between sensing node SO and the second node N2. The eighth transistor TR8 can be turned on or off by the sensing transmission signal SENSE. When the eighth transistor TR8 is turned on by the sensing transmission signal SENSE, sensing node SO and the second node N2 can be connected. For example, a current path can be formed between sensing node SO and the second node N2 by the sensing transmission signal SENSE. In one embodiment, the eighth transistor TR8 can be implemented using an NMOS transistor, but in another embodiment, the eighth transistor TR8 can be a PMOS transistor.

[0111] The ninth transistor TR9 can be a precharge transfer transistor connected between the second node N2 and the third node N3. The ninth transistor TR9 can be turned on or off by the precharge transfer signal CSOC. When the ninth transistor TR9 is turned on by the precharge transfer signal CSOC, the second node N2 and the third node N3 can be connected to each other. For example, a current path can be formed between the second node N2 and the third node N3 by the precharge transfer signal CSOC. In one embodiment, the ninth transistor TR9 can be implemented using a PMOS transistor, but in another embodiment, the ninth transistor TR9 can be an NMOS transistor.

[0112] In one embodiment, during sensing operation, the sensing node SO and the latch assembly can be connected. During sensing operation, data sensed via the bit line can be stored in the latch assembly. During sensing operation, control logic can control peripheral circuitry to turn on or off the data transfer transistor (second transistor TR2), the precharge transfer transistor (ninth transistor TR9), and the precharge transistor (third transistor TR3), thereby connecting the sensing node SO and the latch assembly. In another embodiment, during sensing operation, control logic can control peripheral circuitry to turn on or off the sensing transfer transistor (eighth transistor TR8), thereby connecting the sensing node SO and the latch assembly.

[0113] refer to Figure 6 An example structure of a page buffer PBx is shown. In one embodiment, the page buffer PBx may have other structures connected to bit lines to perform read operations.

[0114] Figure 7 This is a diagram illustrating one embodiment of an operation that can be performed in a read operation or can be included in a read operation.

[0115] refer to Figure 7 The read operation may include bit line precharge, evaluation, and sensing operations. The read operation may include sensing the result or information indicating whether the threshold voltage of one or more memory cells selected as read targets is greater than or less than the corresponding read voltage. This can be accomplished using a single read voltage, and the result can be stored in the latch component of the page buffer PBx. To read data from a single-level cell (SLC), Figure 7 The read operation shown can be performed once. To read data from a Multi-Level Cell (MLC), Figure 7 The read operation shown can be performed multiple times, for example, three times. Additionally, to read data from a three-level cell (TLC), Figure 7 The read operation shown can be performed multiple times, for example, seven times.

[0116] Bit line precharge operation may include increasing the voltage of the bit line connected to the memory cell selected as the read target to the precharge voltage.

[0117] The evaluation operation may include evaluating the threshold voltage of each memory cell in the selected memory cells. For example, among the selected memory cells, memory cells with a threshold voltage higher than the read voltage (e.g., bit lines connected to disconnected cells) may maintain a pre-charge voltage during the evaluation operation. For memory cells with a threshold voltage lower than the read voltage (e.g., bit lines connected to on cells), the voltage may decrease during the evaluation operation. Therefore, the voltage of the corresponding bit line can be distinguished based on the threshold voltage of each memory cell.

[0118] The sensing operation may include storing bit data (e.g., information) in a latch component that indicates whether each memory cell in the selected memory cells is an on or off cell. For example, the operation may be performed based on the voltage of the bit lines distinguished as described above.

[0119] In a read operation according to an exemplary embodiment, a reference (e.g., ground) voltage Vss can be applied to the common source line connected to the memory block during the bit line precharge period, the evaluation period, and the sensing period. This is because the common source line voltage is used to maintain the reference voltage so that the bit line voltage can be distinguished according to the threshold voltage of each memory cell during the evaluation operation. Therefore, in all (or predetermined) operations of the read operation, including the evaluation operation, the voltage of the common source line can be maintained at the reference voltage Vss.

[0120] When the voltage of the common source line is maintained at the reference voltage Vss, the average or peak current flowing through the common source line CSL may increase during certain periods of the read operation.

[0121] According to the method of operating a semiconductor memory device according to an embodiment, during at least a portion of a read operation, a reference (e.g., ground) voltage Vss applied to the common source line can be cut off. Therefore, during at least a portion of the read operation, the common source line CSL can be floated instead of maintaining its voltage at a specific voltage, such as the reference voltage Vss. This prevents problems such as an increase in the average or peak current flowing through the common source line CSL. (Reference) Figure 8 A method of operating a semiconductor memory device according to one embodiment is described.

[0122] Figure 8This is a timing diagram illustrating a method of operating a semiconductor memory device according to one embodiment. The timing diagram includes the voltages of the selected word line Sel_WL, the unselected word line Unsel_WL, the drain select line DSL, the source select line SSL, the bit line BL, and the common source line CSL during a read operation of the semiconductor memory device.

[0123] At time t1, the bit line precharge operation can begin, and the read voltage Vread can be applied to the selected word line Sel_WL, while the voltage Vpass can be applied to the unselected word line Unsel_WL. The voltage Vpass can be greater than the read voltage Vread, and it can be a voltage that enables all corresponding memory cells to be turned on, regardless of the threshold voltage of each memory cell in the selected memory block. Therefore, the memory cells connected to the unselected word line Unsel_WL can remain on from time t1.

[0124] As the read voltage Vread is applied to the selected word line Sel_WL, memory cells connected to the selected word line Sel_WL that have a threshold voltage lower than the read voltage Vread can be turned on. Conversely, memory cells connected to the selected word line Sel_WL that have a threshold voltage higher than the read voltage Vread can be turned off.

[0125] As the bit line precharge operation begins, the voltage of bit line BL can start increasing at time t1. The voltage of bit line BL can increase to the precharge voltage Vprch at time t4.

[0126] According to a method of operating a semiconductor memory device 100, in one embodiment, the common source line CSL can be floated during a portion of the bit line precharge operation. For example, the common source line CSL can be floated from time t2 to time t3, and a reference (e.g., ground) voltage Vss can be applied to the common source line CSL during periods other than the time period from time t2 to time t3.

[0127] exist Figure 8 In one embodiment, the common source line (CSL) is floated only during a portion of time periods t2 to t3 corresponding to the bit line precharge operation from time period t1 to t4. In one embodiment, the common source line (CSL) may be floated for different time periods; for example, the common source line (CSL) may be floated during any of the time periods t1 to t4 corresponding to the bit line precharge operation. For instance, the common source line (CSL) may be floated during the entire time period t1 to t4 corresponding to the bit line precharge operation.

[0128] At time t4, the bit line precharge operation can end and the evaluation operation can begin. At time t4, the supply voltage Vcc can be applied to the drain select line DSL and the source select line SSL to begin the evaluation operation. The supply voltage Vcc can be a voltage that enables the drain select transistor DST and the source select transistor SST to turn on. When the drain select transistor DST and the source select transistor SST are turned on, the cells in the selected memory block are connected in series to the common source line CSL and the corresponding bit line BL. Thereafter, the voltage of the bit line BL is changed or maintained according to the threshold voltage level of each memory cell in the memory cells connected to the selected word line Sel_WL.

[0129] exist Figure 8 In the timing diagram embodiment shown, starting from the bit line precharge operation, a read voltage Vread is applied to the selected word line Sel_WL, and a voltage Vpass is applied to the unselected word line Unsel_WL. In one embodiment, during the bit line precharge operation, a reference voltage Vss can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL, and during the evaluation operation, the read voltage Vread can be applied to the selected word line Sel_WL, and a voltage Vpass can be applied to the unselected word line Unsel_WL.

[0130] In the memory cells connected to the selected word line Sel_WL, the memory cell with a threshold voltage higher than the read voltage Vread is turned off. Therefore, because one memory cell in the corresponding cell string is turned off, the current path between the common source line CSL and the bit line BL can be blocked. Thus, the bit line connected to the turned-off cell (e.g., the disconnected cell) can maintain the precharge voltage Vprch.

[0131] In the memory cells connected to the selected word line Sel_WL, memory cells with a threshold voltage lower than the read voltage Vread are turned on. Therefore, since all memory cells in the corresponding cell string are turned on, a current path can be formed between the common source line CSL and the bit line BL. Consequently, the voltage on the bit line connected to the turned-on cell (e.g., the conducting cell) gradually decreases, for example, at a predetermined rate lower than the threshold rate.

[0132] At time t5, the evaluation operation can end and the sensing operation can begin. During the period from t5 to t6, the page buffer can sense the voltage of each bit line and store the sensing results as bit data in the latch component. Therefore, a read operation using the read voltage Vread can be completed.

[0133] like Figure 8 As shown, according to one embodiment of a method for operating a semiconductor memory device, the common source line CSL can be floated during at least a portion of the bit line precharge operation, from t2 to t3. Therefore, an increase in the average or peak current flowing through the common source line CSL can be reduced or prevented. As a result, power consumption for read operations of the semiconductor memory device 100 can be reduced.

[0134] Figure 9 This is a flowchart illustrating one embodiment of a method for operating a semiconductor memory device. Figure 10 It is a diagram. Figure 9 A flowchart of an exemplary embodiment of operation S110. Figure 11 It is a diagram. Figure 9 A flowchart of an exemplary embodiment of operation S130 is provided. Therefore, reference can be made to... Figures 9 to 11 An embodiment of a method for operating a semiconductor memory device is described.

[0135] refer to Figure 9 The method includes: pre-charging the voltage of the bit line BL connected to the selected memory cell (S110); applying a read voltage to the selected word line and applying a pass voltage to the unselected word line (S130); and storing information indicating whether the selected memory cell is turned on in a latch based on the voltage of each bit line (S150).

[0136] Operation S110 can correspond to Figure 7 The bit line precharge operation shown is a read operation. Furthermore, operation S110 can correspond to... Figure 8 The operations performed during the time periods t1 to t4 are shown in the figure. Figure 8 The time periods t1 to t4 shown can correspond to the bit line precharge operation. In the bit line precharge operation, the read voltage Vread is applied to the selected word line Sel_WL, and the voltage Vpass is applied to the unselected word line Unsel_WL.

[0137] Therefore, according to this method of operating a semiconductor memory device, the common source line CSL can be floated during at least a portion of the bit line precharge operation, from t2 to t3. For example, Figure 9 Operation S110 may include: during at least a portion of the time period in which the bit line voltage increases, floating the common source line CSL (S111), as... Figure 10 As shown in the diagram. Because the common source line CSL is floating during at least a portion of the bit line precharge operation, an increase in the average or peak current flowing through the common source line CSL can be reduced or prevented. As a result, power consumption for read operations of the semiconductor memory device 100 can be reduced.

[0138] Operation S130 can correspond to Figure 7 The evaluation operation for the read operation shown is illustrated. For example, it can be performed in... Figure 8 Operation S130 is performed during the time period t4 to t5 shown. For example, Figure 8 The time periods t4 to t5 shown can correspond to the evaluation operation.

[0139] During the evaluation operation, a read voltage Vread can be applied to the selected word line Sel_WL, and a voltage Vpass can be applied to the unselected word line Unsel_WL. Figure 8 The timing diagram shown illustrates one embodiment in which, starting from a bit line precharge operation, a read voltage Vread is applied to the selected word line Sel_WL, and a voltage Vpass is applied to the unselected word line Unsel_WL. In one embodiment, during the bit line precharge operation, a reference (e.g., ground) voltage Vss can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL. Furthermore, during the evaluation operation, the read voltage Vread can be applied to the selected word line Sel_WL, and a voltage Vpass can be applied to the unselected word line Unsel_WL. In one or more other embodiments, the reference voltage Vss may be different from the ground voltage.

[0140] During evaluation, the voltage level of the common source line CSL can be maintained at the reference voltage Vss to reduce the voltage of the bit lines connected to the conduction cells. For example, Figure 9 Operation S130 may include applying a reference voltage to the common source line (S131), such as Figure 11 As shown in the image.

[0141] Operation S150 can correspond to Figure 7 The reading operation shown is a sensing operation. For example, operation S150 can correspond to the sensing operation in... Figure 8 The operations performed during the time period t5 to t6 shown are illustrated. Figure 8 The time periods t5 to t6 shown can correspond to the evaluation operation. During the evaluation operation, the page buffer PBx can store the bit value corresponding to the current of each bit line in the latch component.

[0142] Figure 12 It is a schematic diagram corresponding to Figure 8 A diagram of one embodiment. (Refer to...) Figure 12 ,Apart from Figure 7In addition to the read operation shown and the operations included therein, the voltage of the common source line CSL is shown in each operation. Therefore, according to the method of operating a semiconductor memory device according to one embodiment, the common source line CSL is floated for at least a portion of the bit line precharge operation included in the read operation. Therefore, an increase in the average or peak current flowing through the common source line CSL can be reduced or prevented. As a result, the power consumption for the read operation of the semiconductor memory device 100 can be reduced.

[0143] Figure 13 This is a timing diagram illustrating one embodiment of a method for operating a semiconductor memory device. The timing diagram shows the voltages of the selected word line Sel_WL, the unselected word line Unsel_WL, the drain select line DSL, the source select line SSL, the bit line BL, and the common source line CSL during a read operation of the semiconductor memory device.

[0144] refer to Figure 13 At time t7, the bit line precharge operation can begin, and the read voltage Vread can be applied to the selected word line Sel_WL, while a voltage Vpass can be applied to the unselected word line Unsel_WL. The voltage Vpass can be greater than the read voltage Vread, enabling all corresponding memory cells to be switched on, regardless of the threshold voltage of the memory cells in the selected memory block. Therefore, all memory cells connected to the unselected word line Unsel_WL can remain switched on from time t7.

[0145] Because the read voltage Vread is applied to the selected word line Sel_WL, memory cells (connected to the selected word line Sel_WL) with a threshold voltage lower than the read voltage Vread can be turned on. Memory cells (connected to the selected word line Sel_WL) with a threshold voltage higher than the read voltage Vread can be turned off.

[0146] As the bit line precharge operation begins, the voltage of bit line BL can start increasing at time t7. The voltage of bit line BL can increase to the precharge voltage Vprch at time t8.

[0147] At time t8, the bit line precharge operation can end and the evaluation operation can begin. At time t8, the supply voltage Vcc can be applied to the drain select line DSL and the source select line SSL to begin the evaluation operation. The supply voltage Vcc is the voltage that enables the drain select transistor DST and the source select transistor SST to turn on. Because the drain select transistor DST and the source select transistor SST are turned on, the cell string included in the selected memory block is connected to the common source line CSL and the corresponding bit line BL. Thereafter, the voltage of the bit line BL is changed or maintained according to the threshold voltage level of each memory cell in the memory cell connected to the selected word line Sel_WL.

[0148] exist Figure 13 In the timing diagram shown, starting from the bit line precharge operation, a read voltage Vread is applied to the selected word line Sel_WL, and a voltage Vpass is applied to the unselected word line Unsel_WL. In one embodiment, during the bit line precharge operation, a reference voltage Vss can be applied to both the selected word line Sel_WL and the unselected word line Unsel_WL, and during the evaluation operation, the read voltage Vread can be applied to the selected word line Sel_WL, and a voltage Vpass can be applied to the unselected word line Unsel_WL.

[0149] In the memory cells connected to the selected word line Sel_WL, the memory cell with a threshold voltage higher than the read voltage Vread is turned off. Therefore, because one memory cell in the corresponding cell string is turned off, the current path between the common source line CSL and the bit line BL can be blocked. Thus, the bit line connected to the turned-off cell (e.g., the disconnected cell) can maintain the precharge voltage Vprch.

[0150] In the memory cells connected to the selected word line Sel_WL, memory cells with a threshold voltage lower than the read voltage Vread are turned on. Therefore, since all memory cells included in the corresponding cell string are turned on, a current path can be formed between the common source line CSL and the bit line BL. Thus, the voltage on the bit line connected to the turned-on cell (e.g., the conducting cell) can be gradually reduced, for example, at a predetermined rate.

[0151] At time t9, the evaluation operation can end and the sensing operation can begin. During the period from t9 to t10, the page buffer can sense the voltage of each bit line and store the sensing results as bit data in the latch component. Therefore, a read operation using the read voltage Vread can be completed.

[0152] Therefore, according to one embodiment, the common source line CSL can be floated for a portion of the bit line sensing operation. For example, the common source line CSL can be floated from time t9 to time t10, and the reference voltage Vss can be applied to the common source line CSL for periods other than the time period from time t9 to time t10.

[0153] exist Figure 13 In the illustrated embodiment, the common source line CSL floats for the entire period t9 to t10 corresponding to the sensing operation. In one embodiment, the common source line CSL may float only for a portion of the period t9 to t10 corresponding to the sensing operation.

[0154] like Figure 13 As shown, according to one embodiment, the common source line CSL can be floated during the time period t9 to t10 corresponding to the sensing operation. Therefore, an increase in the average or peak current flowing through the common source line CSL can be reduced or prevented. As a result, the power consumption for read operations of the semiconductor memory device 100 can be reduced.

[0155] Figure 14 It is a diagram. Figure 9 A flowchart illustrating an exemplary embodiment of operation S150. According to one embodiment, the common source line CSL can be floated during the time period t9 to t10 corresponding to the sensing operation. Therefore, Figure 9 The operation S150 shown may include: while storing information indicating whether each memory cell in the selected memory cell is turned on in a latch, floating the common source line (S151).

[0156] Figure 15 This is a schematic diagram corresponding to a read operation (e.g., with...). Figure 13 A diagram of one embodiment of the read operation related to the embodiment.

[0157] refer to Figure 15 ,Apart from Figure 7 In addition to the read operations shown and those included therein, the voltage of the common source line CSL is illustrated in each operation. In one embodiment, the common source line CSL is floated for at least a portion of the sensing operation included in the read operation. Therefore, an increase in the average or peak current flowing through the common source line CSL can be reduced or prevented. As a result, the power consumption of the read operations for the semiconductor memory device 100 can be reduced.

[0158] Figure 16 This is a schematic diagram illustrating one embodiment related to a read operation. Figure 12 In one embodiment, the common source line (CSL) is floated only for at least a portion of the bit line precharge operation during a read operation. Figure 15 In one embodiment, the common source line CSL is shown to float only for at least a portion of the sensing operation included in the read operation. However, in another embodiment, the common source line CSL may float for at least a portion of the bit line precharge operation included in the read operation and at least a portion of the sensing operation, as shown. Figure 16 As shown in the image.

[0159] Figure 17 This is a schematic diagram illustrating one embodiment corresponding to multiple read operations.

[0160] refer to Figure 17 This illustrates multiple read operations executed sequentially, such as a first read operation, a second read operation, a third read operation, etc. Multiple read operations can be performed while varying the read voltage for the same memory cell. For example, read operations using multiple read voltages can be repeatedly performed to read data stored in a three-level cell (TLC). However, in one embodiment, read operations can be performed on different memory cells. Figure 17 The diagram illustrates multiple read operations. For example, a first read operation can be performed on a memory cell connected to a first word line WL1, a second read operation can be performed on a memory cell connected to a second word line WL2, and a third read operation can be performed on a memory cell connected to a word line WL3.

[0161] Figure 17 An embodiment is shown, which includes a bit line precharge operation, an evaluation operation, and a sensing operation in a first read operation, and a bit line precharge operation, an evaluation operation, and a sensing operation in a second read operation.

[0162] The common source line (CSL) may be floated during at least a portion of the bit line precharge operation of the first read operation. The common source line (CSL) may be floated during the sensing operation of the first read operation and the bit line precharge operation of the second read operation. The common source line (CSL) may be floated during the sensing operation of the second read operation.

[0163] Therefore, according to one embodiment, for multiple consecutively executed read operations, the common source line can be floated during the sensing operation of the previous read operation and the bit line precharge operation of the current read operation. This allows for a more effective reduction or prevention of the increase in the average or peak current flowing through the common source line CSL. As a result, the power consumption of read operations for the semiconductor memory device 100 can be significantly reduced.

[0164] Figure 18 This is a flowchart illustrating a method of operating a semiconductor memory device according to one embodiment.

[0165] refer to Figure 18 The method includes: pre-charging a bit line voltage connected to a first memory cell to perform a first read operation (S210); applying a reference (e.g., ground) voltage to a common source line (S220); applying a first read voltage to a selected first word line and applying a pass voltage to an unselected word line (S230); and floating the common source line (S240).

[0166] The method further includes: storing information indicating whether the first memory cell is turned on in a first latch based on the voltage of each bit line (S250); precharging the bit line voltage connected to the second memory cell to perform a second read operation (S310); and applying a reference (e.g., ground) voltage to a common source line (S320).

[0167] The method further includes: applying a second read voltage to the selected second word line and applying a pass voltage to the unselected word line (S330); floating the common source line (S340); and storing information indicating whether the second memory cell is turned on in a second latch based on the voltage of each bit line (S350). Figure 18 Operations S210 to S250 can be included in the first read operation, and Figure 18 Operations S310 to S350 can be included in the second read operation.

[0168] In one embodiment, the first memory cell operating S210 can be the second memory cell operating S310. In this case, the first word line operating S230 can be the second word line operating S330. In this case, the first read voltage operating S230 can be a voltage different from the second read voltage operating S330.

[0169] In one embodiment, the first memory cell operating S210 may be a different memory cell than the second memory cell operating S310. In this case, the first word line operating S230 may be a different word line than the second word line operating S330. In this case, the first read voltage operating S230 may be the same as or different from the second read voltage operating S330.

[0170] Operation S210 can correspond to Figure 17 The bit line precharge operation of the first read operation shown is illustrated. Operations S220 and S230 can correspond to... Figure 17 The evaluation operation of the first read operation shown. Furthermore, operations S240 and S250 can correspond to... Figure 17 The sensing operation of the first read operation shown.

[0171] Operation S310 can correspond to Figure 17 The bit line precharge operation of the second read operation shown. Operations S320 and S330 can correspond to Figure 17 The evaluation operation of the second read operation shown. Furthermore, operations S340 and S350 can correspond to... Figure 17 The second read operation shown is a sensing operation.

[0172] refer to Figure 18 In operation S240 of the first read operation, the common source line CSL is floated, and in operation S320 of the second read operation, a reference (e.g., ground) voltage Vss is applied to the common source line CSL. This corresponds to the following configuration in which, Figure 17 During the sensing operation of the first read operation and the bit line precharge operation of the second read operation, the common source line CSL is floated. Therefore, according to one embodiment, for multiple consecutively executed read operations, the common source line can be floated during the sensing operation of the previous read operation and the bit line precharge operation of the current read operation. This allows for a more effective reduction or prevention of increases in the average or peak current flowing through the common source line CSL. As a result, the power consumption of the read operations for the semiconductor memory device 100 can be reduced to a greater extent.

[0173] pass Figures 7 to 18 An embodiment for a read operation applied to a semiconductor memory device has been described. However, other embodiments can be applied to the verification phase of a programming operation, for example, as described in the references... Figures 19 to 21 As described.

[0174] Figure 19 This is a diagram illustrating one embodiment of a programming loop included in a programming operation, and the programming and verification phases included in each programming loop.

[0175] refer to Figure 19 Programming operations can include multiple programming loops. A programming operation can begin by executing the first programming loop. st The PGM Loop begins. This continues until the programming operation is complete (even if the first programming loop has been executed). st PGM Loop) can execute the second programming loop 2 nd PGM Loop. This occurs when the programming operation is not complete (even if the second programming loop 2 has been executed). nd PGM Loop) can execute the third programming loop 3 rd PGM Loop.

[0176] In this method, the programming loop can be repeated until the programming operation is completed. If the programming operation fails to complete even after the programming loop has been repeated a predetermined maximum number of times, the programming operation can be considered a failure.

[0177] Each programming cycle may include a programming phase (PGM Phase) and a verification phase. In the programming phase, a programming pulse is applied to the word line, thus increasing the threshold voltage of the memory cell in the programming-enabled state. In the verification phase, it is determined whether the threshold voltage of each memory cell is greater than the verification voltage corresponding to the target programming state. To do this, a verification voltage is applied to the word line, and the threshold voltage of the selected memory cell is sensed to ensure it is greater than the verification voltage. This verification phase can be similar to a read operation.

[0178] Figure 20 This is a diagram illustrating an example of the threshold voltage distribution for a multilevel cell (MLC). This example of the threshold voltage distribution per memory cell per multilevel cell stores two bits of data. The multilevel cell has a threshold voltage corresponding to one of the erase state E, the first programming state P1, the second programming state P2, or the third programming state P3. Therefore, to read the data stored in the multilevel cell, a first read voltage Vread1, a second read voltage Vread2, and / or a third read voltage Vread3 can be used.

[0179] During programming operations, a first verification voltage Vvrf1 corresponding to the first programming state P1, a second verification voltage Vvrf2 corresponding to the second programming state P2, and a third verification voltage Vvrf3 corresponding to the third programming state P3 can be used.

[0180] Figure 21 This is a schematic diagram illustrating one embodiment performed during the verification phase. Figure 21 The example shown is just one programming loop (one of many programming loops included in the programming operation).

[0181] refer to Figure 21The programming cycle consists of a Programming Generation (PGM) Phase and a Verification Phase. During the PGM Phase, a programming voltage VPGM is applied to the selected word line Sel_WL. During the PGM Phase, a programming pass voltage can be applied to unselected word lines. In memory cells connected to the selected word line Sel_WL, the threshold voltage of the memory cell in the programming-enabled state can be increased during the PGM Phase. For example, a memory cell in the programming-enabled state may correspond to a memory cell connected to a bit line within the memory cell connected to the selected word line Sel_WL that is connected to the applied programming-enabled voltage.

[0182] During the programming phase (PGM Phase), the threshold voltage for memory cells in the selected word line Sel_WL that are in a programming-disabled state may not be increased. Memory cells in a programming-disabled state can be memory cells connected to bit lines within the selected word line Sel_WL that are connected to the applied programming-disabled voltage. In one embodiment, the programming-disabled voltage can be a voltage higher than the programming-enabled voltage.

[0183] In the Verify Phase following the PGM Phase, verification operations can be performed on memory cells to be programmed into each of the first to third programming states P1 to P3. Figure 21 In the illustrated embodiment, it is first determined whether the threshold voltage of each memory cell in the memory cell to be programmed to the third programming state P3 is greater than the third verification voltage Vvrf3. For this purpose, the third verification voltage Vvrf3 is applied to the selected word line.

[0184] Subsequently, it is determined whether the threshold voltage of each memory cell in the memory cells to be programmed to the second programming state P2 is greater than the second verification voltage Vvrf2. For this purpose, the second verification voltage Vvrf2 is applied to the selected word line. Subsequently, it is determined whether the threshold voltage of each memory cell in the memory cells to be programmed to the first programming state P1 is greater than the first verification voltage Vvrf1. For this purpose, the first verification voltage Vvrf1 is applied to the selected word line.

[0185] In one embodiment, reference Figure 21In the verification phase, the verification of memory cells to be programmed to the third programming state is performed first. Then, the verification of memory cells to be programmed to the second programming state is performed. Next, the verification of memory cells to be programmed to the first programming state is performed. However, variations are possible. For example, the verification of memory cells to be programmed to the first programming state can be performed first. Then, the verification of memory cells to be programmed to the second programming state can be performed. And then, the verification of memory cells to be programmed to the third programming state can be performed.

[0186] In one embodiment, reference Figure 21 The programming operations for multi-level cells can include performing verification of all memory cells to be programmed into the first to third programming states during the verification phase. However, variations are possible. For example, in the verification phase, verification operations can be performed only on one of the programming states P1 to P3. In another example, in the verification phase, verification operations can be performed on two selected programming states P1 to P3.

[0187] refer to Figure 21 The verification operation for a memory cell to be programmed into a third programming state may include a bit line precharge operation, an evaluation operation, and a sensing operation. The verification operation may include: sensing a result (or information) indicating whether the threshold voltage of the memory cell selected as the verification target is greater than or less than the verification voltage, and storing the result in a latch component in the page buffer PBx.

[0188] The bit line precharge operation may include increasing the voltage of the bit lines connected to the memory cells selected as verification targets to a precharge voltage. The evaluation operation may include evaluating the threshold voltage of each memory cell among the selected memory cells. For example, during the evaluation operation, the bit lines connected to memory cells among the selected memory cells that have a threshold voltage higher than the verification voltage (e.g., disconnected cells) may maintain the precharge voltage. During the evaluation operation, the voltage of the bit lines connected to memory cells among the selected memory cells that have a threshold voltage lower than the verification voltage (e.g., on cells) may decrease. Therefore, the voltage of the corresponding bit lines can be distinguished based on the threshold voltage of each memory cell. The sensing operation may include storing bit data (or information) indicating whether each memory cell among the selected memory cells is an on or off cell in a latch component based on the voltage of the bit lines distinguished as described above.

[0189] Figure 21The illustration shows the bit line precharge operation, evaluation operation, and sensing operation included in the verification operation corresponding to the third programming state P3, which corresponds to each of the programming states P3, P2, and P1. This embodiment also illustrates the bit line precharge operation, evaluation operation, and sensing operation included in the verification operation corresponding to the second programming state P2. The verification operation corresponding to the first programming state P1 may also include the bit line precharge operation, evaluation operation, and sensing operation.

[0190] During at least a portion of the bit line precharge operation corresponding to the verification operation in the third programming state P3, the common source line CSL can be floated. Furthermore, the common source line CSL can be floated during the sensing operation corresponding to the verification operation in the third programming state P3 and the bit line precharge operation corresponding to the verification operation in the second programming state P2. The common source line CSL can be floated during the sensing operation corresponding to the verification operation in the second programming state P2.

[0191] Therefore, according to one embodiment involving multiple consecutively executed verification operations, the common source line can be floated during the sensing operation of the previous verification operation and the bit line precharge operation of the current verification operation. This can thus reduce or prevent an increase in the average or peak current flowing through the common source line CSL. As a result, the power consumption of the verification operations for the semiconductor memory device 100 can be reduced.

[0192] Figure 22 The illustration includes Figure 1 A block diagram of an embodiment of a semiconductor memory device 100 and a memory system 1000.

[0193] refer to Figure 22 The memory system 1000 includes a semiconductor memory device 100 and a memory controller 1100. The semiconductor memory device 100 may be a reference... Figure 1 Or any of the other embodiments described herein, including the semiconductor memory device.

[0194] Memory controller 1100 is connected to a host computer and semiconductor memory device 100. Memory controller 1100 is configured to access semiconductor memory device 100 in response to requests from the host computer. For example, memory controller 1100 is configured to control read operations, write operations, erase operations, and background operations of semiconductor memory device 100. Memory controller 1100 is configured to provide an interface between semiconductor memory device 100 and the host computer. Memory controller 1100 is configured to execute instructions (e.g., driver firmware) to control semiconductor memory device 100.

[0195] The memory controller 1100 includes random access memory (RAM) 1110, a processing unit 1120, a host interface 1130, a memory interface 1140, and an error correction block 1150. RAM 1110 serves as at least one of the following: operating memory for the processing unit 1120, cache memory between the semiconductor memory device 100 and the host, and buffer memory between the semiconductor memory device 100 and the host. The processing unit 1120 controls the overall operation of the memory controller 1100. Additionally, the memory controller 1100 can temporarily store program data provided from the host during write operations.

[0196] The host interface 1130 operates based on a protocol for performing data exchange between the host and the memory controller 1100. As an exemplary embodiment, the memory controller 1100 is configured to communicate with the host via at least one of a variety of interface protocols. Examples include the Universal Serial Bus (USB) protocol, the Multimedia Card (MMC) protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI-Fast (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Electronic Integrated Drive (IDE) protocol, and proprietary protocols.

[0197] Memory interface 1140 is interfaced with semiconductor memory device 100. For example, memory interface 1240 includes a NAND interface or a NOR interface.

[0198] Error correction block 1150 is configured to use error correction codes (ECC) to detect and correct errors in data received from semiconductor memory device 100. As an exemplary embodiment, the error correction block may be provided as a component of memory controller 1100.

[0199] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device. As an exemplary embodiment, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. For example, the memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a memory card. Examples include PC cards (Personal Computer Memory Card International Association (PCMCIA)), compact flash memory cards (CF), smart media cards (SM or SMC), memory sticks, multimedia cards (MMC, RS-MMC, or MMCmicro), SD cards (SD, miniSD, microSD, or SDHC), and universal flash memory (UFS).

[0200] The memory controller 1100 and the semiconductor memory device 100 can be integrated into a single semiconductor device to form a semiconductor drive (solid-state drive (SSD)). A semiconductor drive (SSD) includes a storage device configured to store data in semiconductor memory. When the memory system 1000 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0201] In one example, the memory system 1000 is provided as one of a variety of components of an electronic device. Examples of electronic devices include computers, ultra-mobile PCs (UMPCs), workstations, netbooks, personal digital assistants (PDAs), portable computers, network tablets, cordless phones, mobile phones, smartphones, e-book readers, portable multimedia players (PMPs), portable game consoles, navigation devices, black boxes, digital cameras, 3D televisions, digital recorders, digital audio players, digital picture recorders, digital picture players, digital video recorders and digital video players, devices capable of transmitting and receiving information in a wireless environment, one of a variety of electronic devices constituting a home network, one of a variety of electronic devices constituting a computer network, one of a variety of electronic devices constituting a telematics network, RFID devices, or one of a variety of components constituting a computing system.

[0202] As an exemplary embodiment, the semiconductor memory device 100 or memory system 1000 can be mounted in various types of packages. For example, the semiconductor memory device 100 or memory system 1000 can be packaged and mounted in a stacked package (PoP), ball grid array (BGA), chip-scale package (CSP), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDIP), waffle die, wafer-scale die, chip-on-board (COB), ceramic dual in-line package (CERDIP), plastic metric square flat package (MQFP), thin square flat package (TQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline package (TSOP), system-in-package (SIP), multi-chip package (MCP), wafer-level fabrication package (WFP), or wafer-level fabrication stacked package (WSP).

[0203] Figure 23 It is a diagram. Figure 22 A block diagram illustrating an application example of a memory system.

[0204] refer to Figure 23 The memory system 2000 includes a semiconductor memory device 2100 and a memory controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips divided into multiple groups.

[0205] Multiple groups can communicate with the memory controller 2200 via channels CH1 to CHk, respectively. Each semiconductor memory chip is connected to a reference... Figure 1 The semiconductor memory device 100 described is similarly configured and operated.

[0206] Each group is configured to communicate with the memory controller 2200 via a common channel. The memory controller 2200 and the reference... Figure 22 The memory controller 1100 described is similarly configured and is configured to control multiple memory chips of the semiconductor memory device 2100 via multiple channels CH1 to CHk.

[0207] Figure 24 The illustration includes (for example, as shown in the reference) Figure 23 A block diagram of an embodiment of a computing system 3000 with a described memory system.

[0208] The computing system 3000 includes a central processing unit 3100, random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and a memory system 2000. The memory system 2000 is electrically connected to the central processing unit 3100, RAM 3200, user interface 3300, and power supply 3400 via the system bus 3500. Data provided through the user interface 3300 or processed by the central processing unit 3100 is stored in the memory system 2000.

[0209] Semiconductor memory device 2100 is connected to system bus 3500 via memory controller 2200. However, semiconductor memory device 2100 can be configured to be directly connected to system bus 3500. In this case, the functions of memory controller 2200 are performed by central processing unit 3100 and RAM 3200.

[0210] Provided reference Figure 23 The memory system 2000 is described. However, the memory system 2000 can be described using references. Figure 22 The memory system 1000 described herein is used instead. As an exemplary embodiment, the computing system 3000 may be configured to include a reference... Figure 22 and Figure 23 The memory systems described are 1000 and 2000.

[0211] According to one embodiment, an apparatus includes a storage region configured to store instructions and at least one processor. The storage region may be coupled to or included in any embodiment of the control logic, processor, or controller described herein, or may be included in any memory described herein. The at least one processor may correspond wholly or partially to the control logic, processor, and / or controller described herein.

[0212] In operation, at least one processor executes instructions to perform the operations of the embodiments described herein. For example, at least one processor may execute instructions to control a read operation including a bit line precharge operation, an evaluation operation, and a sensing operation. At least one processor may control the read operation to float a common source line connected to the memory block for at least a portion of a time period. The portion of the time period may be included during the bit line precharge operation, in which the voltages of a plurality of bit lines connected to the memory block are increased.

[0213] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein, or it can be a computer, processor, controller, or other signal processing device other than those elements described herein. Because the algorithms underlying the methods (or the operations of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions used to implement the operations of the method embodiments can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0214] When implemented at least partially in software, controllers, processors, devices, managers, components, modules, units, multiplexers, generators, blocks, logic, interfaces, decoders, drivers, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions to be executed by, for example, a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be the computer, processor, microprocessor, controller, or other signal processing device described herein, or it may be a computer, processor, microprocessor, controller, or other signal processing device other than those described herein. Because the algorithms underlying the methods (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can convert the computer, processor, controller, or other signal processing device into a dedicated processor for performing the methods described herein.

[0215] While this disclosure has been shown and described with reference to certain exemplary embodiments, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of this disclosure as defined by the appended claims and their equivalents. Therefore, the scope of this disclosure should not be limited to the exemplary embodiments described above, but should be determined by the appended claims and their equivalents.

[0216] In the above embodiments, all steps may be performed selectively, or some steps may be omitted. In each embodiment, the steps need not be performed in the described order and may be rearranged. The embodiments disclosed in this specification and accompanying drawings are merely examples to facilitate understanding of this disclosure, and this disclosure is not limited thereto. That is, it will be apparent to those skilled in the art that various modifications can be made based on the technical scope of this document.

[0217] Furthermore, exemplary embodiments of this disclosure have been described in the accompanying drawings and specification. While specific terminology is used herein, it is for the purpose of explaining embodiments of this disclosure only. Therefore, this disclosure is not limited to the embodiments described above, and many variations are possible within the spirit and scope of this disclosure. It will be apparent to those skilled in the art that various modifications can be made beyond the embodiments disclosed herein, building upon the technical scope of this disclosure. Embodiments may be combined to form additional embodiments.

Claims

1. A semiconductor memory device, comprising: a memory block comprising a plurality of memory cells; and control logic configured to control a peripheral circuit to perform a read operation on a selected memory cell of the plurality of memory cells, wherein the read operation comprises a bit line pre-charge operation, an evaluation operation, and a sensing operation, the bit line pre-charge operation increasing a voltage of a plurality of bit lines to a predetermined pre-charge voltage, and wherein the control logic is configured to: control the peripheral circuit to float a common source line coupled to the memory block during at least a portion of a period in which the voltage of the plurality of bit lines is increased.

2. The semiconductor memory device of claim 1, wherein, In the bit line pre-charge operation, the control logic is configured to control the peripheral circuit to: apply an off voltage to drain select lines and source select lines coupled to the memory block.

3. The semiconductor memory device of claim 1, wherein, In the evaluation operation, the control logic is configured to control the peripheral circuit to: apply a read voltage to a selected word line coupled to the selected memory cell, apply a pass voltage to unselected word lines, and apply an on voltage to drain select lines and source select lines coupled to the memory block.

4. The semiconductor memory device of claim 3, wherein the control logic is configured to control the peripheral circuit to apply a reference voltage to the common source line in the evaluation operation.

5. The semiconductor memory device of claim 3, wherein, In the sensing operation, the control logic is configured to control the peripheral circuit to temporarily store information indicative of whether the selected memory cell is on.

6. The semiconductor memory device of claim 5, wherein the control logic is configured to control the peripheral circuit to float the common source line during at least a portion of the sensing operation.

7. A semiconductor memory device, comprising: a memory block comprising a plurality of memory cells; and control logic configured to control a peripheral circuit to perform a plurality of read operations on selected memory cells of the plurality of memory cells, wherein each read operation of the plurality of read operations comprises a bit line pre-charge operation, an evaluation operation, and a sensing operation, the bit line pre-charge operation increasing a voltage of a plurality of bit lines to a predetermined pre-charge voltage, wherein the control logic is configured to control the peripheral circuit to float a common source line coupled to the memory block during at least a portion of a period in which the voltage of the plurality of bit lines is increased, and wherein the period comprises the sensing operation of a first read operation and a second read operation after the first read operation.

8. The semiconductor memory device of claim 7, wherein, In the sensing operation of the first read operation, the control logic is configured to control the peripheral circuit to temporarily store information indicative of whether a memory cell selected as a target of the first read operation is on.

9. The semiconductor memory device of claim 7, wherein, In the bit line pre-charge operation of the second read operation, the control logic is configured to control the peripheral circuit to: apply an off voltage to drain select lines and source select lines coupled to the memory block.

10. The semiconductor memory device of claim 7, wherein, In the evaluation operation of the first read operation, the control logic is configured to control the peripheral circuitry to: apply a read voltage to a first selected word line coupled to a first memory cell selected as a target of the first read operation, apply a pass voltage to unselected word lines other than the first selected word line, apply an on voltage to drain select lines and source select lines coupled to the memory block, and apply a reference voltage to the common source line.

11. The semiconductor memory device of claim 10, wherein, In the evaluation operation of the second read operation, the control logic is configured to control the peripheral circuitry to: apply the read voltage to a second selected word line coupled to a second memory cell selected as a target of the second read operation, apply the pass voltage to unselected word lines other than the second selected word line, apply the on voltage to the drain select lines and the source select lines coupled to the memory block, and apply the reference voltage to the common source line.

12. A method of operating a semiconductor memory device, the method comprising: performing a read operation on a selected memory cell of a plurality of memory cells, the read operation including: pre-charging voltages of bit lines coupled to a memory block including the selected memory cell; applying a read voltage to a selected word line of word lines coupled to the memory block, the selected word line coupled to the selected memory cell, and applying a read pass voltage to unselected word lines of the word lines other than the selected word line; and temporarily storing information indicating whether the selected memory cell is turned on based on the voltage of each of the bit lines coupled to the memory block including the selected memory cell, wherein pre-charging the voltages of the bit lines coupled to the memory block including the selected memory cell includes floating a common source line coupled to the memory block during at least a portion of a period in which the voltages of the bit lines increase.

13. The method of claim 12, wherein pre-charging the voltages of the bit lines coupled to the memory block including the selected memory cell includes: increasing the voltages of the bit lines to a predetermined pre-charge voltage, and applying an off voltage to drain select lines and source select lines coupled to the memory block.

14. The method of claim 12, wherein applying the read voltage to the selected word line of the word lines coupled to the memory block, the selected word line coupled to the selected memory cell, and applying the read pass voltage to the unselected word lines of the word lines other than the selected word line includes: applying the read voltage to the selected word line coupled to the selected memory cell, applying a pass voltage to the unselected word lines, and applying an on voltage to drain select lines and source select lines coupled to the memory block.

15. The method of claim 14, wherein applying the read voltage to the selected word line of the word lines coupled with the memory block coupled with the selected memory cell and applying the pass voltage to the unselected word lines of the word lines other than the selected word line comprises: applying a reference voltage to the common source line.

16. The method of claim 12, wherein temporarily storing information indicative of whether the selected memory cell is turned on based on a voltage of each of the bit lines comprises: floating the common source line.

17. A semiconductor memory device, comprising: a memory block comprising a plurality of memory cells; peripheral circuitry configured to perform a program operation on a selected memory cell of the plurality of memory cells; and control logic configured to control the program operation of the peripheral circuitry, wherein the program operation comprises a plurality of program loops, each program loop of the plurality of program loops comprising a program phase and a verify phase, the verify phase comprises a bit line pre-charge operation, an evaluate operation, and a sense operation, and the control logic is configured to control the peripheral circuitry to float a common source line coupled to the memory block during at least a portion of a time period of the bit line pre-charge operation in which a voltage of a plurality of bit lines coupled to the memory block is increased.

18. The semiconductor memory device of claim 17, wherein, in the bit line pre-charge operation, the control logic is configured to control the peripheral circuitry to: increase the voltage of the plurality of bit lines to a predetermined pre-charge voltage, and apply an off voltage to drain select lines and source select lines coupled to the memory block.

19. The semiconductor memory device of claim 17, wherein, in the evaluate operation, the control logic is configured to control the peripheral circuitry to: apply a verify voltage to a selected word line coupled to the selected memory cell, apply a pass voltage to unselected word lines, apply an on voltage to drain select lines and source select lines coupled to the memory block, and apply a reference voltage to the common source line.

20. The semiconductor memory device of claim 19, wherein, in the sense operation, the control logic is configured to control the peripheral circuitry to temporarily store information indicative of whether the selected memory cell is on and to float the common source line during at least a portion of a time period of the sense operation.

21. An electronic device, comprising: a storage area configured to store instructions; and at least one processor configured to execute the instructions to control a read operation comprising a bit line pre-charge operation, an evaluate operation, and a sense operation, the bit line pre-charge operation increasing a voltage of a plurality of bit lines to a predetermined pre-charge voltage, wherein the at least one processor is configured to control the read operation to: float a common source line coupled to a memory block during at least a portion of a time period of the bit line pre-charge operation in which the voltage of the plurality of bit lines is increased. in the bit line pre-charge operation, the control logic is configured to control the peripheral circuitry to: increase the voltage of the plurality of bit lines to a predetermined pre-charge voltage, and apply an off voltage to drain select lines and source select lines coupled to the memory block. in the evaluate operation, the control logic is configured to control the peripheral circuitry to: apply a verify voltage to a selected word line coupled to the selected memory cell, apply a pass voltage to unselected word lines, apply an on voltage to drain select lines and source select lines coupled to the memory block, and apply a reference voltage to the common source line. in the sense operation, the control logic is configured to control the peripheral circuitry to temporarily store information indicative of whether the selected memory cell is on and to float the common source line during at least a portion of a time period of the sense operation.

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