Electronic packaging and method of manufacturing the same

Abstract

The present invention relates to an electronic package and a method for manufacturing the same, comprising first forming an inclined surface on at least one side surface of at least one of a plurality of electronic components, then placing the plurality of electronic components on a supporting structure so that two adjacent electronic components form a space with their inclined surfaces, and then forming a packaging layer on the supporting structure and filling the space to cover the two adjacent electronic components, thereby dispersing the stress on the electronic components through the design of the space to avoid the problem of cracking due to stress concentration.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a flip chip package type electronic package and a manufacturing method thereof. Background Art

[0002] With the booming development of the electronics industry, electronic products are gradually moving towards multi-function and high performance. There are many technologies currently used in the field of chip packaging, such as chip scale package (CSP), direct chip attached package (DCA) or multi-chip module package (MCM) and other flip chip packaging modules, or three-dimensional chip stacking integration into a three-dimensional integrated circuit (3D IC) chip stacking module.

[0003] Figure 1 The schematic cross-sectional view of a conventional 3D IC semiconductor package 1 is shown. First, a through silicon interposer (TSI) 10 having a transfer side 10a and a die side 10b opposite to each other is provided, and the silicon interposer 10 has a plurality of conductive through silicon vias (TSVs) 100 connecting the die side 10b and the transfer side 10a, and a circuit structure 101 is formed on the die side 10b for receiving a plurality of semiconductor elements 11 having a plurality of solder bumps 12, and then the solder bumps 12 are coated with a primer 13, and a packaging layer 14 is formed to cover the semiconductor element 11, and the packaging layer 14 is polished to expose the packaging layer 14 on the upper surface of the semiconductor element 11. Next, the silicon interposer 10 is disposed on a packaging substrate 16 through a plurality of conductive elements 15 at its transfer side 10a, and the packaging substrate 16 is electrically connected to the conductive through silicon vias 100, and the conductive elements 15 are then covered with an underfill 17. Next, a packaging colloid 18 is formed on the packaging substrate 16, so that the packaging colloid 18 covers the packaging layer 14 and the silicon interposer 10. Finally, a plurality of solder balls 160 are formed on the lower side of the packaging substrate 16 for being placed on a circuit board 19.

[0004] However, in the conventional semiconductor package 1, during packaging, the base glue 13 or the packaging layer 14 may be formed at the corners of the semiconductor element 11 or the edges of the non-active surface, causing the internal stress of the semiconductor element 11 to increase and stress concentration, resulting in cracks, and making the reliability of the semiconductor package 1 poor.

[0005] Therefore, how to overcome the above-mentioned problems of the prior art has become a topic that needs to be solved urgently. Summary of the invention

[0006] In view of the above-mentioned defects of the prior art, the present invention provides an electronic package and a method for manufacturing the same, which can avoid the problem of cracking due to stress concentration.

[0007] The electronic package of the present invention comprises: a supporting structure; a plurality of electronic components which are arranged on the supporting structure at intervals, wherein the electronic components have opposite active surfaces and inactive surfaces and side surfaces adjacent to the active surfaces and the inactive surfaces, the width of the active surface of at least one of the plurality of electronic components is greater than the width of the inactive surface, so that at least one side surface of at least one of the plurality of electronic components forms an inclined surface, and a space is formed between two adjacent electronic components, so that at least one side of the space has the inclined surface; and a packaging layer which is formed on the supporting structure to cover the plurality of electronic components.

[0008] The present invention also provides a method for manufacturing an electronic package, comprising: providing a plurality of electronic components, wherein the electronic components have opposite active surfaces and inactive surfaces and side surfaces adjacent to the active surfaces and the inactive surfaces, and the width of the active surface of at least one of the plurality of electronic components is greater than the width of the inactive surface, so that at least one side surface of at least one of the plurality of electronic components forms an inclined surface; arranging the plurality of electronic components at intervals on a supporting structure, so that a space is formed between two adjacent electronic components, so that at least one side of the space has the inclined surface; and forming a packaging layer on the supporting structure to cover the plurality of electronic components.

[0009] In the aforementioned electronic package and the method for manufacturing the same, the structures of the plurality of electronic components are different from each other.

[0010] In the aforementioned electronic package and its manufacturing method, the active surface of the electronic component has a plurality of electrode pads electrically connected to the supporting structure.

[0011] In the aforementioned electronic package and its manufacturing method, a chamfer is formed at the junction between the active surface of the electronic component and the side surface.

[0012] In the aforementioned electronic package and its manufacturing method, the width of the space gradually decreases toward the supporting structure.

[0013] In the aforementioned electronic package and its manufacturing method, the electronic component is electrically connected to the supporting structure via a plurality of conductive bumps. Further, before forming the packaging layer, a coating layer is formed between the electronic component and the supporting structure, so that the coating layer covers the plurality of conductive bumps, and when forming the packaging layer, the packaging layer also covers the coating layer.

[0014] In the aforementioned electronic package and its manufacturing method, the inactive surface of the electronic component is exposed on the surface of the packaging layer.

[0015] In the aforementioned electronic package and its manufacturing method, a plurality of spaces are formed between the plurality of electronic components.

[0016] The aforementioned electronic package and its manufacturing method further include forming a plurality of conductive elements on the other side of the supporting structure opposite to the electronic element.

[0017] As can be seen from the above, in the electronic package and its manufacturing method of the present invention, at least one side of the electronic component is designed to be inclined so that two adjacent electronic components form a space with their inclined surfaces, so that the stress generated by the packaging layer inside the electronic component can be reduced. Therefore, compared with the prior art, the present invention can disperse the stress on the electronic component to avoid the problem of the electronic component being broken due to stress concentration, thereby improving the reliability of the electronic package. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a cross-sectional schematic diagram of a conventional semiconductor package.

[0019] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing an electronic package of the present invention.

[0020] Figure 2A 'for Figure 2A A cross-sectional schematic diagram of another manufacturing method.

[0021] Figure 2A "for Figure 2A A cross-sectional schematic diagram of another embodiment of the present invention.

[0022] Figure 2C 'and Figure 2C "for Figure 2C Schematic cross-sectional view of other embodiments.

[0023] Figure 2D for Figure 2C A cross-sectional schematic diagram of the subsequent process.

[0024] Figure 2D 'and Figure 2D "for Figure 2D Schematic cross-sectional view of other embodiments.

[0025] Figure 3A-1 to Figure 3A-5 for Figure 2A Partial bottom schematic diagrams of various different embodiments.

[0026] Figure 4 for Figure 2D A cross-sectional schematic diagram of another embodiment of the present invention.

[0027] Description of Reference Numerals

[0028] 1: Semiconductor packaging

[0029] 10: Silicon interposer

[0030] 10a: Transfer side

[0031] 10b: Chip side

[0032] 100: Conductive silicon via

[0033] 101: Line structure

[0034] 11: Semiconductor components

[0035] 21c: Side

[0036] 12: Solder Bump

[0037] 13: Primer

[0038] 14,24: Encapsulation layer

[0039] 15,25: Conductive elements

[0040] 16:Packaging substrate

[0041] 160,27: Solder ball

[0042] 17: Primer

[0043] 18: Encapsulation colloid

[0044] 19: Circuit Board

[0045] 2,2',2”,3,3',4: Electronic packaging

[0046] 2a: Full-page substrate structure

[0047] 20: Bearing structure

[0048] 200: Circuit layer

[0049] 21,21',21",31: Electronic components

[0050] 21a: Action surface

[0051] 21b: Non-active surface

[0052] 210: Electrode pad

[0053] 22: Conductive bump

[0054] 23: Coating layer

[0055] 24b: Upper surface

[0056] 26: Electronic devices

[0057] A:Flat surface

[0058] B: Chamfer

[0059] D1,D2,R: Width

[0060] L: Cutting path

[0061] P: Incline

[0062] S,S',S”,S1: space

[0063] V: Cone-shaped notch

[0064] X: horizontal direction. DETAILED DESCRIPTION

[0065] The following describes the implementation of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0066] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions under which the present invention can be implemented, so they have no substantial technical significance. Any structural modification, change in proportional relationship, or adjustment of size, without affecting the effects and purposes that can be achieved by the present invention, should still fall within the scope of the technical contents disclosed by the present invention. At the same time, the terms such as "above" and the like cited in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. The change or adjustment of the relative relationship, without substantially changing the technical contents, should also be regarded as the scope of the implementation of the present invention.

[0067] FIG. 2A to FIG. 2C It is a cross-sectional schematic diagram of a method for manufacturing an electronic package 2 of the present invention.

[0068] like Figure 2A As shown, a full-page substrate structure 2a is provided, which includes a plurality of electronic components 21 arranged in an array, and at least one side surface 21c of each of the electronic components 21 is a slope P.

[0069] The electronic component 21 may be an active component, a passive component, a packaging structure or a combination thereof, and the active component may be a semiconductor chip, and the passive component may be a resistor, a capacitor and an inductor. In the present embodiment, the electronic component 21 is a semiconductor chip, and has an active surface 21a and an inactive surface 21b opposite to each other, so that the side surface 21c (or the inclined surface P) is adjacent to the active surface 21a and the inactive surface 21b, and the active surface 21a has a plurality of electrode pads 210. For example, the width D1 of the active surface 21a is greater than the width D2 of the inactive surface 21b, so that the side surface 21c forms the inclined surface P.

[0070] In addition, the side surface 21c of the electronic component 21 can be formed into the inclined surface P by the cutting tool of the singulation process, such as Figure 2A The conical notch V shown. Alternatively, Figure 2A As shown in FIG. 1 , the side surface 21c of the electronic component 21 can be shaped by a tool (such as grinding or cutting) to form the inclined surface P after the singulation process.

[0071] In addition, if Figure 2A ” As shown, the adjacent corners of the active surface 21a of the electronic component 21′ and the side surface 21c can be formed with a chamfer B as required.

[0072] In addition, the inclined surface P can be formed on at least one side surface 21c of the electronic component 21 as required, such as Figure 3A-1 to Figure 3A-5 The active surface 21a and the inactive surface 21b of the electronic component 21 are quadrilaterals such as squares. It should be understood that there are many types of shapes of the electronic components 21, 21', and there is no particular limitation.

[0073] like Figure 2B As shown, continued Figure 2A The process is as follows Figure 2A The cutting path L shown is used to perform a singulation process on the entire panel substrate structure 2a to separate each of the electronic components 21, and then at least two electronic components 21 are arranged on a supporting structure 20 in a panel form or a wafer form along a horizontal direction X at intervals, and two adjacent electronic components 21 are arranged with their inclined surfaces P facing each other (such as the inclined surface P is in a landslide state), so that a space S is formed between the two adjacent electronic components 21.

[0074] The supporting structure 20 may be a packaging substrate (substrate) having a core layer and a circuit structure or a circuit structure without a core layer (coreless), and it is composed of a plurality of circuit layers 200 formed on a dielectric material, such as a circuit redistribution layer (RDL for short). In the present embodiment, the supporting structure 20 is a circuit structure without a core layer (coreless). However, in other embodiments, the supporting structure 20 may also be a semiconductor substrate having a plurality of conductive through-silicon vias (TSV for short) to serve as a Through Silicon interposer (TSI for short). It should be understood that the supporting structure 20 may also be other supporting units that can be used to carry electronic components such as chips, such as a lead frame, but is not limited to the above.

[0075] In addition, the width R of the space S is inconsistent from the top side (the side away from the supporting structure 20) to the bottom side (the side close to the supporting structure 20). For example, the width R of the space S can gradually decrease from the top side to the bottom side (i.e., toward the supporting structure 20), that is, the space S is conical, so the stress on the electronic component 21 is reduced by changing the width R.

[0076] In addition, the electronic component 21 forms conductive bumps 22 on each of the electrode pads 210, so that the electronic component 21 is electrically connected to the circuit layer 200 of the supporting structure 20 through the conductive bumps 22 in a flip chip manner, and a coating layer 23 is formed between the active surface 21a and the supporting structure 20 to cover the conductive bumps 22. For example, the conductive bumps 22 are metal pillars (such as copper pillars), solder materials or a combination thereof, and the coating layer 23 is a primer.

[0077] In addition, in this embodiment, although the electronic components 21 are of the same type (ie, active components), their internal structures may be the same or different.

[0078] like Figure 2C As shown, a packaging layer 24 is formed on the supporting structure 20 to cover the covering layer 23 and the electronic components 21. Then, a plurality of conductive elements 25 such as solder balls are formed on the lower side (or the ball implantation side) of the supporting structure 20. After that, a singulation process is performed to obtain the electronic package 2.

[0079] The packaging layer 24 can be an insulating material, such as polyimide (PI), dry film, epoxy, molding compound or other suitable materials. In this embodiment, the packaging layer 24 is formed on the supporting structure 20 by lamination or molding, so that the packaging layer 24 fills the gap S.

[0080] In addition, the Young's modulus of the packaging layer 24 is greater than that of the cladding layer 23. In this embodiment, the Young's modulus of the packaging layer 24 is greater than 20 GPa.

[0081] In addition, the inactive surface 21b of the electronic component 21 and the upper surface 24b of the packaging layer 24 may be made coplanar through a flattening process or a thinning process. Figure 2C', so that the inactive surface 21b of the electronic component 21 is exposed to the packaging layer 24. For example, when the packaging layer 24 is formed on the supporting structure 20, the packaging layer 24 covers the inactive surface 21b of the electronic component 21, and then part of the material of the packaging layer 24 is removed by grinding or cutting (part of the material of the inactive surface 21b of the electronic component 21 can also be removed at the same time as required), so that the inactive surface 21b of the electronic component 21 is flush with the upper surface 24b of the packaging layer 24.

[0082] In addition, if the continuation Figure 2A ” The process shown in FIG. 2 (the electronic component 21 ′ is formed with a chamfer B) can obtain the following Figure 2C 'The electronic package 2 shown'. Or, as Figure 2C In the electronic package 2 shown in FIG. 1 , the covering layer 23 can also fill the space S.

[0083] like Figure 2D As shown, in the subsequent process, Figure 2C The electronic package 2 shown (or Figure 2C The electronic package 2 shown in the figure is placed on a circuit board (PCB) or other electronic device 26 with circuits via the conductive elements 25, and a plurality of solder balls 27 may be implanted under the circuit board (PCB) or other electronic device 26 with circuits.

[0084] It should be understood that the electronic package 3, 3' may also be configured with electronic components 21, 21', 21", 31 of different embodiments, such as Figure 2D 'or Figure 2D ” to form various types of spaces S', S". For example, one side of the space S' is a slope P, and the other side is a slope P and a chamfer B; or one side of the space S" is a slope P, and the other side is a straight surface A; even more, Figure 4 The electronic package 4 shown is provided with a plurality of electronic components 21 , 21 ′, 21 ″, 31 , and a plurality of spaces S′, S″, S1 are defined between the plurality of electronic components 21 , 21 ′, 21 ″, 31 .

[0085] On the other hand, the electronic components 21 may also be electronic components of different types. For example, one electronic component 21 (active component) is an application-specific integrated circuit (ASIC) type semiconductor chip, and another electronic component 21 is a packaging structure, which includes a packaging module including a packaging material, a control chip and at least one high bandwidth memory (HBM) type chip, and the control chip is electrically connected to the conductive bumps 22.

[0086] Therefore, the manufacturing method of the present invention mainly forms the inclined surface P on at least one side surface 21c of the electronic component 21, 21', 21" before the inclined surface P is formed, so that the space S, S', S", S1 formed by the inclined surface P of at least one of the two adjacent electronic components 21, 21', 21" can be used as a stress buffer, so that the stress generated by the packaging layer 24 inside the electronic component 21, 21', 21", 31 can be reduced, that is, the stress increase inside the electronic component 21, 21', 21", 31 can be avoided. Therefore, compared with the prior art, the manufacturing method of the present invention can disperse the stress on the electronic component 21, 21', 21", 31, avoid the problem of the electronic component 21, 21', 21", 31 being broken due to stress concentration, and improve the reliability of the electronic package 2, 2', 2", 3, 3', 4.

[0087] In addition, by filling the space S with the packaging layer 24, the coating layer 23 and / or other appropriate materials, the strength of the space S, S', S", S1 can be enhanced so that stress concentration will not occur inside the electronic component 21, 21', 21", 31, causing the electronic package 2, 2', 2", 3, 3', 4 to rupture.

[0088] The present invention further provides an electronic package 2 , 2 ′, 2 ″, 3 , 3 ′, 4 , comprising: a supporting structure 20 , a plurality of electronic components 21 , 21 ′, 21 ″, 31 , and a packaging layer 24 .

[0089] The multiple electronic components 21, 21', 21", 31 are arranged on the supporting structure 20 at intervals, wherein the electronic components 21, 21', 21" have opposite active surfaces 21a and inactive surfaces 21b and side surfaces 21c adjacent to the active surfaces 21a and the inactive surfaces 21b, and the width D1 of the active surface 21a of at least one of the multiple electronic components 21, 21', 21", 31 is greater than the width D2 of the inactive surface 21b, so that at least one side surface 21c of at least one of the multiple electronic components 21, 21', 21", 31 forms an inclined surface P, and a space S, S', S", S1 is formed between two adjacent electronic components 21, 21', 21", 31, so that at least one side of the space S, S', S", S1 has the inclined surface P.

[0090] The packaging layer 24 is formed on the supporting structure 20 to cover the plurality of electronic components 21 , 21 ′, 21 ″, 31 .

[0091] In one embodiment, the structures of the plurality of electronic components 21 , 21 ′, 21 ″, 31 are different from each other.

[0092] In one embodiment, the active surface 21 a of the electronic element 21 , 21 ′, 21 ″, 31 has a plurality of electrode pads 210 electrically connected to the supporting structure 20 .

[0093] In one embodiment, a chamfer B is formed at a junction between the active surface 21 a of the electronic component 21 ′ and the side surface 21 c .

[0094] In one embodiment, the width R of the space S, S′, S″, S1 gradually decreases toward the supporting structure 20 .

[0095] In one embodiment, the electronic components 21, 21', 21", 31 are electrically connected to the supporting structure 20 via a plurality of conductive bumps 22. Furthermore, a coating layer 23 is formed between the electronic components 21, 21', 21", 31 and the supporting structure 20, so that the coating layer 23 covers the plurality of conductive bumps 22, and the packaging layer 24 also covers the coating layer 23.

[0096] In one embodiment, the inactive surface 21 b of the electronic component 21 ′ is exposed on the upper surface 24 b of the packaging layer 24 .

[0097] In one embodiment, the electronic package 2 , 2 ′, 2 ″, 3 , 3 ′, 4 further includes a plurality of conductive elements 25 formed on a side of the supporting structure 20 opposite to the electronic element 21 .

[0098] In summary, the electronic package and its manufacturing method of the present invention form a conical space through the inclined surface of the electronic component, so that the stress generated by the packaging layer inside the electronic component can be reduced, the stress on the electronic component can be dispersed, and the problem of the electronic component being broken due to stress concentration can be avoided, thereby improving the reliability of the electronic package.

[0099] The above embodiments are only used to illustrate the principles and effects of the present invention, and are not used to limit the present invention. Any person skilled in the art may modify the above embodiments without violating the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as listed in the claims.

Claims

1. An electronic package, It is characterized in that include: load-bearing structure; A first electronic component and a second electronic component are disposed on the supporting structure at intervals, wherein the first electronic component and the second electronic component both have an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, the width of the active surface of the first electronic component is greater than the width of the inactive surface, so that at least one side surface of the first electronic component forms an inclined surface, and a space is formed between the inclined surface of the first electronic component and the side surface of the second electronic component, so that at least one side of the space has the inclined surface; and a packaging layer formed on the supporting structure to cover the first electronic component and the second electronic component, The single electronic package at least includes the packaging layer, the first electronic component, the second electronic component, and the space between the inclined surface of the first electronic component and the side surface of the second electronic component, and only the packaging layer is formed on the inclined surface of the first electronic component.

2. The electronic package according to claim 1, It is characterized in that The first electronic component and the second electronic component are different in structure from each other.

3. The electronic package as claimed in claim 1, It is characterized in that The active surface of the first electronic element or the second electronic element has a plurality of electrode pads electrically connected to the supporting structure.

4. The electronic package according to claim 1, It is characterized in that A chamfer is formed at a junction between the active surface of the first electronic component and the side surface.

5. The electronic package as claimed in claim 1, It is characterized in that The width of the space gradually decreases toward the supporting structure.

6. The electronic package according to claim 1, It is characterized in that The first electronic component or the second electronic component is electrically connected to the supporting structure via a plurality of conductive bumps.

7. The electronic package as claimed in claim 6, It is characterized in that A coating layer is formed between the first electronic element and the supporting structure, so that the coating layer covers the plurality of conductive bumps, and the packaging layer also covers the coating layer.

8. The electronic package as claimed in claim 1, It is characterized in that The packaging layer is exposed outside the inactive surface of the first electronic component.

9. The electronic package as claimed in claim 1, It is characterized in that The electronic package also includes a third electronic component arranged on the supporting structure, and a plurality of spaces are formed between the first electronic component, the second electronic component and the third electronic component.

10. The electronic package according to claim 1, It is characterized in that The electronic package also includes a plurality of conductive elements formed on the other side of the supporting structure opposite to the first electronic element or the second electronic element.

11. A method for manufacturing an electronic package, It is characterized in that include: A first electronic component and a second electronic component are provided, wherein the first electronic component and the second electronic component both have an active surface and an inactive surface opposite to each other and side surfaces adjacent to the active surface and the inactive surface, and the width of the active surface of the first electronic component is greater than the width of the inactive surface, so that at least one side surface of the first electronic component forms an inclined surface; The first electronic component and the second electronic component are spaced apart on a supporting structure so that a space is formed between the inclined surface of the first electronic component and the side surface of the second electronic component, and at least one side of the space has the inclined surface; and forming a packaging layer on the supporting structure to cover the first electronic component and the second electronic component, The single electronic package at least includes the packaging layer, the first electronic component, the second electronic component, and the space between the inclined surface of the first electronic component and the side surface of the second electronic component, and only the packaging layer is formed on the inclined surface of the first electronic component.

12. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The first electronic component and the second electronic component are different in structure from each other.

13. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The active surface of the first electronic element or the second electronic element has a plurality of electrode pads electrically connected to the supporting structure.

14. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that A chamfer is formed at a junction between the active surface of the first electronic component and the side surface.

15. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The width of the space gradually decreases toward the supporting structure.

16. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The first electronic component or the second electronic component is electrically connected to the supporting structure via a plurality of conductive bumps.

17. The method for manufacturing an electronic package as claimed in claim 16, It is characterized in that The manufacturing method also includes forming a coating layer between the first electronic element and the supporting structure before forming the packaging layer, so that the coating layer covers the plurality of conductive bumps, and when forming the packaging layer, the packaging layer also covers the coating layer.

18. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The packaging layer is exposed outside the inactive surface of the first electronic component.

19. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The manufacturing method further includes arranging a third electronic component on the supporting structure so that a plurality of the spaces are formed between the first electronic component, the second electronic component and the third electronic component.

20. The method for manufacturing an electronic package as claimed in claim 11, It is characterized in that The manufacturing method further includes forming a plurality of conductive elements on the other side of the supporting structure opposite to the first electronic element or the second electronic element.

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