D-type flip-flop

Abstract

The present invention relates to a D-type flip-flop, in particular to a true single-phase clock (TSPC) D-type flip-flop, comprising four stages connected in series between an input terminal and an output terminal. The present invention selectively adds two connecting elements in each stage. Furthermore, one of the two connecting elements is a resistive element, and the other of the two connecting elements is a short-circuit element. When the connection node between the stages is floating, the resistive element can slow down the change of the node voltage and prevent the D-type flip-flop from operating incorrectly.

Description

Technical Field

[0001] The present invention is a D-type flip-flop, and in particular relates to a true single-phase clock D flip-flop. Background Art

[0002] Generally speaking, the D-type flip-flops in logic circuits are master-slave type D-type flip-flops. Master-slave type D-type flip-flops have better anti-interference capabilities, but they have the disadvantages of being larger in size, slower in operation speed, and higher in energy consumption.

[0003] In integrated circuits, dynamic circuits use clock signals to operate. True single-phase clock D flip-flop (TSPC D flip-flop) is a type of dynamic circuit. Due to the advantages of high speed, space saving and low energy consumption, dynamic circuits have been designed in logic circuits or application-specific integrated circuits (ASICs). Summary of the invention

[0004] The present invention provides a D-type flip-flop, comprising: a first connection element having a first end and a second end, wherein the first end of the first connection element receives a first supply voltage; a first first-type transistor having a gate end, a first drain / source end and a second drain / source end, wherein the gate end of the first first-type transistor receives an input signal, the first drain / source end of the first first-type transistor is connected to the second end of the first connection element, and the second drain / source end of the first first-type transistor is connected to a first node; a first second-type transistor having a gate end, a first drain / source end and a second drain / source end, wherein the first The gate terminal of the second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor has a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, and the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor; a second connecting element has a first terminal and a second terminal, the first terminal of the second connecting element is connected to the second drain / source terminal of the second second-type transistor, and the second terminal of the second connecting element is connected to the a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the second first-type transistor receiving the clock signal, the first drain / source terminal of the second first-type transistor receiving the first supply voltage; a third first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is coupled to the second drain / source terminal of the second first-type transistor, the second drain / source terminal of the third first-type transistor is connected to the first node, the second drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to the first node. an input terminal connected to a second node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is coupled to the second node, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor is connected to the second node, and the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage;a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; and a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; wherein one of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element. ;

[0005] The present invention provides a D-type flip-flop, comprising: a first first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the second first-type transistor receives the clock signal, the first drain / source terminal of the second first-type transistor receives the first supply voltage a first connection element having a first end and a second end, the first end of the first connection element being connected to the second drain / source end of the second first-type transistor; a third first-type transistor having a gate end, a first drain / source end and a second drain / source end, wherein the gate end of the third first-type transistor is connected to the first node, the first drain / source end of the third first-type transistor is connected to the second end of the first connection element, and the second drain / source end of the third first-type transistor is connected to a second node; a second connection element having a first end and a second end, the first end of the second connection element being connected to the second a node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is connected to the second terminal of the second connecting element, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor is connected to the second node, and the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage;a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; and a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; wherein one of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element. ;

[0006] The present invention provides a D-type flip-flop, comprising: a first first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, the first drain / source terminal of the first second-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; / source terminal is connected to the first node; a second second-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the second first-type transistor receives the clock signal, the second a first-type transistor, the first drain / source terminal of which receives the first supply voltage; a third first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a third second-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a first connection element having a first terminal and a second terminal, the first terminal of the first connection element receiving the first supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor being connected to the second node, the first drain / source terminal of the fourth first-type transistor being connected to the second terminal of the first connection element;a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, and the first drain / source terminal of the fourth second-type transistor is connected to the third node; and a second connecting element having a first terminal and a second terminal, wherein the first terminal of the second connecting element is connected to the second drain / source terminal of the fourth second-type transistor, and the second terminal of the second connecting element receives the second supply voltage; wherein one of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element. ;

[0007] The present invention provides a D-type flip-flop, comprising: a first first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, the first The first drain / source terminal of the second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the second The gate terminal of a first-type transistor receives the clock signal, and the first drain / source terminal of the second first-type transistor receives the first supply voltage; a third first-type transistor has a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a third second-type transistor has a a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is connected to the second node, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor, having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor is connected to the second node, and the first drain / source terminal of the fourth first-type transistor receives the first supply voltage;a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor receives the second supply voltage; and a first capacitor having a first terminal and a second terminal gate terminal, wherein the first terminal of the first capacitor is connected to the first node, and the second terminal of the first capacitor receives the first supply voltage or the second supply voltage. ; BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to better understand the above and other aspects of the present invention, the following preferred embodiments are specifically described in detail with reference to the accompanying drawings as follows:

[0009] Figure 1A and Figure 1B It is a TSPC D-type flip-flop;

[0010] Figure 2A and Figure 2B This is a schematic diagram of related signals of a negatively triggered TSPC D-type flip-flop;

[0011] FIG. 3A to FIG. 3C This is the first embodiment of the TSPC D-type flip-flop of the present invention;

[0012] FIG. 4A to FIG. 4D Various examples of resistive elements;

[0013] FIG. 5A to FIG. 5C This is the second embodiment of the TSPC D-type flip-flop of the present invention;

[0014] FIG. 6A to FIG. 6D Various examples of resistive elements;

[0015] FIG. 7A to FIG. 7C The third embodiment of the TSPC D-type flip-flop of the present invention;

[0016] FIG. 8A to FIG. 8F Various examples of resistive elements;

[0017] Fig.9A and Fig. 9BThe fourth embodiment of the TSPC D-type flip-flop of the present invention; and

[0018] FIG. 10A to FIG. 10E are various examples of capacitor elements.

[0019] The reference numerals are described as follows:

[0020] 112, 122: Inverter

[0021] 110, 120, 310, 510, 710, 910: D-type flip-flop

[0022] 312, 314, 512, 514, 712, 714: Connecting elements

[0023] 912, 914: Capacitor elements DETAILED DESCRIPTION

[0024] Please refer to Figure 1A and Figure 1B , which is a TSPC D-type flip-flop. Figure 1A It is a negative trigger TSPC D-type flip-flop. Figure 1B It is a positive trigger TSPC D-type flip-flop.

[0025] like Figure 1A As shown, the negative trigger TSPC D-type flip-flop 110 includes: p-type transistors Mp1 to Mp6 and n-type transistors Mn1 to Mn5. The p-type transistors and the n-type transistors are transistors of different types. For example, the p-type transistors are first-type transistors, and the n-type transistors are second-type transistors.

[0026] Four stages are connected in series between the input and output ends of the negative-triggered TSPC D-type flip-flop 110. The first stage includes a p-type transistor Mp1 and n-type transistors Mn1 and Mn2. The second stage includes p-type transistors Mp2 and Mp3 and n-type transistor Mn3. The third stage includes p-type transistors Mp4 and Mp5 and n-type transistor Mn4. The fourth stage includes a p-type transistor Mp6 and n-type transistor Mn5.

[0027] In the first stage, the gate terminal of the p-type transistor Mp1 receives the input signal D, the first drain / source terminal of the p-type transistor Mp1 receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mp1 is connected to the node a2. The gate terminal of the n-type transistor Mn1 receives the clock signal CK, and the first drain / source terminal of the n-type transistor Mn1 is connected to the node a2. The gate terminal of the n-type transistor Mn2 receives the input signal D, the first drain / source terminal of the n-type transistor Mn2 is connected to the second drain / source terminal of the n-type transistor Mn1, and the second drain / source terminal of the n-type transistor Mn2 receives the supply voltage GND. The supply voltage Vdd is greater than the supply voltage GND, for example, the supply voltage Vdd is 3.3V, and the supply voltage GND is 0V.

[0028] In the second stage, the gate terminal of the p-type transistor Mp2 receives the clock signal CK, and the first drain / source terminal of the p-type transistor Mp2 receives the supply voltage Vdd. The gate terminal of the p-type transistor Mp3 is connected to the node a2, the first drain / source terminal of the p-type transistor Mp3 is connected to the second drain / source terminal of the p-type transistor Mp2, and the second drain / source terminal of the p-type transistor Mp3 is connected to the node b2. The gate terminal of the n-type transistor Mn3 receives the clock signal CK, the first drain / source terminal of the n-type transistor Mn3 is connected to the node b2, and the second drain / source terminal of the n-type transistor Mn3 receives the supply voltage GND.

[0029] In the third stage, the gate terminal of the p-type transistor Mp4 is connected to the node b2, and the first drain / source terminal of the p-type transistor Mp4 receives the supply voltage Vdd. The gate terminal of the p-type transistor Mp5 receives the clock signal CK, the first drain / source terminal of the p-type transistor Mp5 is connected to the second drain / source terminal of the p-type transistor Mp4, and the second drain / source terminal of the p-type transistor Mp5 is connected to the node c2. The gate terminal of the n-type transistor Mn4 is connected to the node b2, the first drain / source terminal of the n-type transistor Mn4 is connected to the node c2, and the second drain / source terminal of the n-type transistor Mn4 receives the supply voltage GND.

[0030] In the fourth stage, the p-type transistor Mp6 and the n-type transistor Mn5 form an inverter 112. The input terminal of the inverter 112 is connected to the node c2, and the output terminal of the inverter 112 generates an output signal Q. The gate terminal of the p-type transistor Mp6 is connected to the node c2, the first drain / source terminal of the p-type transistor Mp6 receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mp6 generates the output signal Q. The gate terminal of the n-type transistor Mn5 is connected to the node c2, the first drain / source terminal of the n-type transistor Mn5 is connected to the second drain / source terminal of the p-type transistor Mp6, and the second drain / source terminal of the n-type transistor Mn5 receives the supply voltage GND.

[0031] like Figure 1B As shown, the positive-triggered TSPC D-type flip-flop 120 includes: n-type transistors Mn1-Mn6 and p-type transistors Mp1-Mp5. The p-type transistors and the n-type transistors are transistors of different types. For example, the n-type transistors are first-type transistors, and the p-type transistors are second-type transistors.

[0032] Four stages are connected in series between the input and output ends of the positive-triggered TSPC D-type flip-flop 120. The first stage includes p-type transistors Mp1 and Mp2 and n-type transistor Mn1. The second stage includes p-type transistor Mp3 and n-type transistors Mn2 and Mn3. The third stage includes p-type transistor Mp4 and n-type transistors Mn4 and Mn5. The fourth stage includes p-type transistor Mp5 and n-type transistor Mn6.

[0033] In the first stage, the gate terminal of the n-type transistor Mn1 receives the input signal D, the first drain / source terminal of the n-type transistor Mn1 receives the supply voltage GND, and the second drain / source terminal of the n-type transistor Mn1 is connected to the node d2. The gate terminal of the p-type transistor Mp1 receives the clock signal CK, and the first drain / source terminal of the p-type transistor Mp1 is connected to the node d2. The gate terminal of the p-type transistor Mp2 receives the input signal D, the first drain / source terminal of the p-type transistor Mp2 is connected to the second drain / source terminal of the p-type transistor Mp1, and the second drain / source terminal of the p-type transistor Mp2 receives the supply voltage Vdd. The supply voltage Vdd is greater than the supply voltage GND, for example, the supply voltage Vdd is 3.3V, and the supply voltage GND is 0V.

[0034] In the second stage, the gate terminal of the n-type transistor Mn2 receives the clock signal CK, and the first drain / source terminal of the n-type transistor Mn2 receives the supply voltage GND. The gate terminal of the n-type transistor Mn3 is connected to the node d2, the first drain / source terminal of the n-type transistor Mn3 is connected to the second drain / source terminal of the n-type transistor Mn2, and the second drain / source terminal of the n-type transistor Mn3 is connected to the node e2. The gate terminal of the p-type transistor Mp3 receives the clock signal CK, the first drain / source terminal of the p-type transistor Mp3 is connected to the node e2, and the second drain / source terminal of the p-type transistor Mp3 receives the supply voltage Vdd.

[0035] In the third stage, the gate terminal of the n-type transistor Mn4 is connected to the node e2, and the first drain / source terminal of the n-type transistor Mn4 receives the supply voltage GND. The gate terminal of the n-type transistor Mn5 receives the clock signal CK, the first drain / source terminal of the n-type transistor Mn5 is connected to the second drain / source terminal of the n-type transistor Mn4, and the second drain / source terminal of the n-type transistor Mn5 is connected to the node f2. The gate terminal of the p-type transistor Mp4 is connected to the node e2, the first drain / source terminal of the p-type transistor Mp4 is connected to the node f2, and the second drain / source terminal of the p-type transistor Mp4 receives the supply voltage Vdd.

[0036] In the fourth stage, the p-type transistor Mp5 and the n-type transistor Mn6 form an inverter 122. The input terminal of the inverter 122 is connected to the node f2, and the output terminal of the inverter 122 generates an output signal Q. The gate terminal of the n-type transistor Mn6 is connected to the node f2, the first drain / source terminal of the n-type transistor Mn6 receives the supply voltage GND, and the second drain / source terminal of the n-type transistor Mn6 generates the output signal Q. The gate terminal of the p-type transistor Mp5 is connected to the node f2, the first drain / source terminal of the p-type transistor Mp5 is connected to the second drain / source terminal of the n-type transistor Mn6, and the second drain / source terminal of the p-type transistor Mp5 receives the supply voltage Vdd.

[0037] Since the positive-triggered TSPC D-type flip-flop 120 and the negative-triggered TSPC D-type flip-flop 110 operate similarly, the following only takes the negative-triggered TSPC D-type flip-flop 110 as an example to describe the phenomenon when nodes a2, b2, and c2 are floating. Figure 2A and Figure 2B , which is a schematic diagram of related signals of a negative-triggered TSPC D-type flip-flop.

[0038] Between time point ta and time point tb, the clock signal CK is at a low level (e.g., supply voltage GND) and the input signal D is at a high level (e.g., supply voltage Vdd), the p-type transistor Mp1 and the n-type transistor Mn1 are turned off, so that the node a2 is floating. In theory, when the node a2 is floating, the node a2 needs to be maintained at a low level. However, since the p-type transistor Mp1 has a larger leakage current, the leakage current charges the node a2, causing the voltage of the node a2 to gradually rise. When the node a2 is floating, if the voltage of the node a2 rises too high and thus turns off the p-type transistor Mp2, it will cause the D-type flip-flop 110 to function incorrectly.

[0039] Between time point td and time point te, the voltage of node a2 is at a high level and the clock signal CK is at a low level, the p-type transistor Mp3 and the n-type transistor Mn3 are turned off, and the node b2 is floating. Theoretically, when the node b2 is floating, the node b2 needs to be maintained at a low level. However, since the p-type transistors Mp2 and Mp3 have a large leakage current, and the leakage current charges the node b2, the voltage of the node b2 gradually rises. When the node b2 is floating, if the voltage of the node b2 rises too high and then turns off the p-type transistor Mp4 and turns on the n-type transistor Mn4, it will cause the D-type flip-flop 110 to fail.

[0040] Similarly, between time point tb and time point tc, node b2 is at a low level and clock signal CK is at a high level, n-type transistor Mn4 and p-type transistor Mp5 are turned off, making node c2 floating. In theory, when node c2 is floating, node c2 needs to be maintained at a low level. However, since p-type transistors Mp4 and Mp5 have a large leakage current, the leakage current charges node c2, causing the voltage of node c2 to gradually rise. If the voltage of node c2 rises too high and then turns off p-type transistor Mp6 and turns on n-type transistor Mn5, it will cause the D-type flip-flop 110 to function incorrectly.

[0041] Please refer to Figure 2B, which is a detailed signal diagram of the node a2 when it is floating. At time point ta, the clock signal CK changes from a high level to a low level, the p-type transistor Mp2 turns on and the n-type transistor Mn3 turns off, so that the node b2 changes from a low level to a high level. Therefore, as shown from time point ta to time point tf, due to the Miller effect, the voltage of the node b2 rises, causing the voltage of the node a2 to be quickly boosted from a low level. Afterwards, as shown from time point tf to time point tb, since the node a2 is floating, the leakage current of the p-type transistor Mp1 charges the node a2, causing the voltage of the node a2 to gradually rise.

[0042] In addition, the node b2 and the node c2 are not affected by the Miller effect, and the voltages of the node b2 and the node c2 are only affected by the leakage current.

[0043] Generally speaking, a transistor with a larger size has a stronger driving strength and generates a larger leakage current.

[0044] According to the above description, in the TSPC D-type flip-flops 110 and 120, if the p-type transistor is designed to have a stronger driving capability, the p-type transistor will also generate a larger leakage current. Therefore, when the node in the TSPC D-type flip-flops 110 and 120 is floating, the voltage of the node will gradually be charged to the power supply voltage Vdd. Similarly, if the n-type transistor is designed to have a stronger driving capability, the n-type transistor will also generate a larger leakage current. Therefore, when the node in the TSPC D-type flip-flops 110 and 120 is floating, the voltage of the node will gradually be discharged to the power supply voltage GND.

[0045] Since the TSPC D-type flip-flops 110 and 120 are inevitably affected by the leakage current of the transistors, in order to prevent the D-type flip-flops 110 and 120 from functioning incorrectly (function fail), the present invention designs the TSPC D-type flip-flops for the purpose of reducing the leakage current of the transistors. Furthermore, the present invention is described below by taking a negative-triggered TSPC D-type flip-flop as an example. Of course, the technical content disclosed in the present invention can also be applied to a positive-triggered TSPC D-type flip-flop, which will not be repeated here.

[0046] Please refer to FIG. 3A to FIG. 3C , which illustrates the first embodiment of the TSPC D-type flip-flop of the present invention. Figure 1AThe negative trigger TSPC D-type flip-flop 110 is different in that two connecting devices 312 and 314 are added to the first stage of the D-type flip-flop 310. The following only introduces the connection relationship between the two connecting devices 312 and 314, and the rest is not repeated.

[0047] like Figure 3A As shown, the connection element 312 of the D-type flip-flop 310 has a first end and a second end. The first end of the connection element 312 receives the supply voltage Vdd, and the second end of the connection element 312 is connected to the first drain / source terminal of the p-type transistor Mp1. Furthermore, the connection element 314 has a first end and a second end. The first end of the connection element 314 is connected to the second drain / source terminal of the n-type transistor Mn2, and the second end of the connection element 314 receives the supply voltage GND. According to the first embodiment of the present invention, one of the two connection elements 312, 314 is a resistive element, and the other of the two connection elements 312, 314 is a short circuit element.

[0048] According to the first embodiment of the present invention, in the D-type flip-flop 310 , two connecting elements 312 and 314 are designed according to the driving strengths of the p-type transistor and the n-type transistor.

[0049] like Figure 3B As shown, in the D-type flip-flop 310, when the driving strength of the p-type transistor Mp1 is designed to be stronger than the driving strength of the n-type transistors Mn1 and Mn2, the connecting element 312 is a resistive element and the connecting element 314 is a short-circuit element. When the node a2 is floating, since the charging path between the supply voltage Vdd and the node a2 includes a resistive element, the leakage current of the p-type transistor Mp1 can be reduced to reduce the voltage rise speed of the node a2, so that the D-type flip-flop 310 can operate correctly.

[0050] like Figure 3C As shown, in the D-type flip-flop 310 , if the driving strength of the p-type transistor Mp1 is designed to be weaker than the driving strength of the n-type transistors Mn1 and Mn2 , the connecting element 312 is a short-circuit element and the connecting element 314 is a resistive element.

[0051] Basically, in the first embodiment, the short-circuit element can be implemented by a metal wire, and the resistive element can be implemented by a polysilicon resistor or other electronic components, as described below.

[0052] Please refer to FIG. 4A to FIG. 4D , which shows various examples of resistive elements. Figure 4A As shown, in the first stage, the connection element 312 of the charging path between the supply voltage Vdd and the node a2 is implemented by a p-type transistor Mpx. The gate terminal of the p-type transistor Mpx receives the input signal D, the first drain / source terminal of the p-type transistor Mpx receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mpx is connected to the first drain / source terminal of the p-type transistor Mp1.

[0053] like Figure 4B As shown, in the first stage, the connection element 312 of the charging path between the supply voltage Vdd and the node a2 is implemented by p-type transistors Mpx1, Mpx2 and n-type transistor Mnx1. A bias circuit is formed by the p-type transistor Mpx1 and the n-type transistor Mnx1 to provide a bias voltage Vb to the gate terminal of the p-type transistor Mpx2. Among them, the first drain / source terminal of the p-type transistor Mpx1 receives the supply voltage Vdd, the gate terminal and the second drain / source terminal of the p-type transistor Mpx1 are connected to each other, the gate terminal of the n-type transistor Mnx1 is connected to the gate terminal of the p-type transistor Mpx1, the first drain / source terminal of the n-type transistor Mnx1 generates a bias voltage Vb, the second drain / source terminal of the n-type transistor Mnx1 receives the supply voltage GND, the gate terminal of the p-type transistor Mpx2 receives the bias voltage Vb, the first drain / source terminal of the p-type transistor Mpx2 receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mpx2 is connected to the first drain / source terminal of the p-type transistor Mp1.

[0054] like Figure 4C As shown, in the first stage, the connection element 314 of the discharge path between the node a2 and the supply voltage GND is implemented by an n-type transistor Mny. The gate terminal of the n-type transistor Mny receives the input signal D, the first drain / source terminal of the n-type transistor Mny is connected to the second drain / source terminal of the n-type transistor Mn2, and the second drain / source terminal of the n-type transistor Mny receives the supply voltage GND.

[0055] like Figure 4DAs shown, in the first stage, the connection element 314 of the discharge path between the node a2 and the supply voltage GND is realized by the n-type transistors Mny1, Mny2 and the p-type transistor Mpy1. A bias circuit is formed by the p-type transistor Mpy1 and the n-type transistor Mny1 to provide a bias voltage Vb to the gate terminal of the n-type transistor Mny2. Among them, the first drain / source terminal of the p-type transistor Mpy1 receives the supply voltage Vdd, the second drain / source terminal of the p-type transistor Mpy1 generates the bias voltage Vb, the gate terminal of the n-type transistor Mny1 is connected to the gate terminal of the p-type transistor Mpy1, the gate terminal of the n-type transistor Mny1 and the first drain / source terminal are connected to each other, the second drain / source terminal of the n-type transistor Mny1 receives the supply voltage GND, the gate terminal of the n-type transistor Mny2 receives the bias voltage Vb, the first drain / source terminal of the n-type transistor Mny2 is connected to the second drain / source terminal of the n-type transistor Mn2, and the second drain / source terminal of the n-type transistor Mny2 receives the supply voltage GND.

[0056] Please refer to FIG. 5A to FIG. 5C , which shows the second embodiment of the TSPC D-type flip-flop of the present invention. Figure 1A The negative trigger TSPC D-type flip-flop 110 is different in that two connecting elements 512 and 514 are added to the second stage of the D-type flip-flop 510. The following only introduces the connection relationship between the two connecting elements 512 and 514, and the rest is not repeated.

[0057] The connecting element 512 of the D-type flip-flop 510 has a first end and a second end. The first end of the connecting element 512 is connected to the second drain / source end of the p-type transistor Mp2, and the second end of the connecting element 512 is connected to the first drain / source end of the p-type transistor Mp3. Furthermore, the connecting element 514 has a first end and a second end. The first end of the connecting element 514 is connected to the node b2, and the second end of the connecting element 514 is connected to the first drain / source end of the n-type transistor Mn3. According to the second embodiment of the present invention, one of the two connecting elements 512, 514 is a resistive element, and the other of the two connecting elements 512, 514 is a short-circuit element.

[0058] According to the second embodiment of the present invention, in the D-type flip-flop 510 , two connecting elements 512 and 514 are designed according to the driving strengths of the p-type transistor and the n-type transistor.

[0059] like Figure 5BAs shown, in the D-type flip-flop 510, when the driving strength of the p-type transistors Mp2 and Mp3 is designed to be stronger than the driving strength of the n-type transistor Mn3, the connecting element 512 is a resistive element and the connecting element 514 is a short-circuit element. When the node b2 is floating, since the charging path between the supply voltage Vdd and the node b2 includes a resistive element, the leakage current of the p-type transistors Mp2 and Mp3 can be reduced to reduce the voltage rise speed of the node b2, so that the D-type flip-flop 510 can operate correctly.

[0060] like Figure 5C As shown, in the D-type flip-flop 510 , if the driving strengths of the p-type transistors Mp2 and Mp3 are designed to be weaker than the driving strength of the n-type transistor Mn3 , the connecting element 512 is a short-circuit element and the connecting element 514 is a resistive element.

[0061] Similarly, in the second embodiment, the short-circuit element can be implemented by a metal wire, and the resistive element can be implemented by a polysilicon resistor or other electronic components, as described below.

[0062] Please refer to FIG. 6A to FIG. 6D , which shows various examples of resistive elements. Fig. 6A As shown, in the second stage, the connection element 512 of the charging path between the supply voltage Vdd and the node b2 is implemented by a p-type transistor Mpx. The gate terminal of the p-type transistor Mpx is connected to the node a2, the first drain / source terminal of the p-type transistor Mpx is connected to the second drain / source terminal of the p-type transistor Mp2, and the second drain / source terminal of the p-type transistor Mpx is connected to the first drain / source terminal of the p-type transistor Mp3.

[0063] like Figure 6BAs shown, in the second stage, the connection element 512 of the charging path between the supply voltage Vdd and the node b2 is implemented by p-type transistors Mpx1, Mpx2 and n-type transistor Mnx1. A bias circuit is formed by the p-type transistor Mpx1 and the n-type transistor Mnx1 to provide a bias voltage Vb to the gate terminal of the p-type transistor Mpx2. Among them, the first drain / source terminal of the p-type transistor Mpx1 receives the supply voltage Vdd, the gate terminal and the second drain / source terminal of the p-type transistor Mpx1 are connected to each other, the gate terminal of the n-type transistor Mnx1 is connected to the gate terminal of the p-type transistor Mpx1, the first drain / source terminal of the n-type transistor Mnx1 generates a bias voltage Vb, the second drain / source terminal of the n-type transistor Mnx1 receives the supply voltage GND, the gate terminal of the p-type transistor Mpx2 receives the bias voltage Vb, the first drain / source terminal of the p-type transistor Mpx2 is connected to the second drain / source terminal of the p-type transistor Mp2, and the second drain / source terminal of the p-type transistor Mpx2 is connected to the first drain / source terminal of the p-type transistor Mp3.

[0064] like Figure 6C As shown, in the second stage, the connection element 514 of the discharge path between the node b2 and the supply voltage GND is implemented by an n-type transistor Mny. The gate terminal of the n-type transistor Mny is connected to the node a2, the first drain / source terminal of the n-type transistor Mny is connected to the node b2, and the second drain / source terminal of the n-type transistor Mny is connected to the first drain / source terminal of the n-type transistor Mn3.

[0065] like Fig.6D As shown, in the second stage, the connection element 514 of the discharge path between the node b2 and the supply voltage GND is realized by n-type transistors Mny1, Mny2 and p-type transistor Mpy1. A bias circuit is formed by using the p-type transistor Mpy1 and the n-type transistor Mny1 to provide a bias voltage Vb to the gate terminal of the n-type transistor Mny2. Among them, the first drain / source terminal of the p-type transistor Mpy1 receives the supply voltage Vdd, the second drain / source terminal of the p-type transistor Mpy1 generates the bias voltage Vb, the gate terminal of the n-type transistor Mny1 is connected to the gate terminal of the p-type transistor Mpy1, the gate terminal of the n-type transistor Mny1 and the first drain / source terminal are connected to each other, the second drain / source terminal of the n-type transistor Mny1 receives the supply voltage GND, the gate terminal of the n-type transistor Mny2 receives the bias voltage Vb, the first drain / source terminal of the n-type transistor Mny2 is connected to the node b2, and the second drain / source terminal of the n-type transistor Mny2 is connected to the first drain / source terminal of the n-type transistor Mn3.

[0066] Please refer to FIG. 7A to FIG. 7C, which illustrates the third embodiment of the TSPC D-type flip-flop of the present invention. Figure 1A The negative trigger TSPC D-type flip-flop 110 has the difference that two connecting elements 712 and 714 are added to the third stage of the D-type flip-flop 710. The following only introduces the connection relationship between the two connecting elements 712 and 714, and the rest is not repeated.

[0067] The connecting element 712 of the D-type flip-flop 710 has a first end and a second end. The first end of the connecting element 712 receives the supply voltage Vdd, and the second end of the connecting element 712 is connected to the first drain / source end of the p-type transistor Mp4. Furthermore, the connecting element 714 has a first end and a second end. The first end of the connecting element 714 is connected to the second drain / source end of the n-type transistor Mn4, and the second end of the connecting element 714 is connected to the supply voltage GND. According to the third embodiment of the present invention, one of the two connecting elements 712, 714 is a resistive element, and the other of the two connecting elements 712, 714 is a short-circuit element.

[0068] According to the third embodiment of the present invention, in the D-type flip-flop 710 , two connecting elements 712 and 714 are designed according to the driving strengths of the p-type transistor and the n-type transistor.

[0069] like Figure 7B As shown, in the D-type flip-flop 710, when the driving strength of the p-type transistors Mp4 and Mp5 is designed to be stronger than the driving strength of the n-type transistor Mn4, the connecting element 712 is a resistive element and the connecting element 714 is a short-circuit element. When the node c2 is floating, since the charging path between the supply voltage Vdd and the node c2 includes a resistive element, the leakage current of the p-type transistors Mp4 and Mp5 can be reduced to reduce the voltage rise speed of the node c2, so that the D-type flip-flop 710 can operate correctly.

[0070] like Figure 7C As shown, in the D-type flip-flop 710, if the driving strengths of the p-type transistors Mp4 and Mp5 are designed to be weaker than the driving strength of the n-type transistor Mn4, the connecting element 712 is a short-circuit element and the connecting element 714 is a resistive element.

[0071] Similarly, in the third embodiment, the short-circuit element can be implemented by a metal wire, and the resistive element can be implemented by a polysilicon resistor or other electronic components, as described below.

[0072] Please refer to FIG. 8A to FIG. 8F , which shows various examples of resistive elements. Fig. 8A As shown, in the third stage, the connection element 712 of the charging path between the supply voltage Vdd and the node c2 is implemented by a p-type transistor Mpx. The gate terminal of the p-type transistor Mpx is connected to the node b2, the first drain / source terminal of the p-type transistor Mpx receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mpx is connected to the first drain / source terminal of the p-type transistor Mp4.

[0073] Furthermore, Fig. 8A The resistive element in the first stage, i.e., the p-type transistor Mpx, can be replaced by the p-type transistor Mp2 in the second stage. Figure 8B As shown, the connection element 712 of the charging path between the supply voltage Vdd and the node c2 is implemented by a p-type transistor Mp2. The gate terminal of the p-type transistor Mp2 receives the clock signal CK, the first drain / source terminal of the p-type transistor Mp2 receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mp2 is connected to the first drain / source terminal of the p-type transistor Mp4.

[0074] like Figure 8C As shown, in the third stage, the connection element 712 of the charging path between the supply voltage Vdd and the node c2 is implemented by p-type transistors Mpx1, Mpx2 and n-type transistor Mnx1. The p-type transistor Mpx1 and the n-type transistor Mnx1 form a bias circuit to provide a bias voltage Vb to the gate terminal of the p-type transistor Mpx2. Among them, the first drain / source terminal of the p-type transistor Mpx1 receives the supply voltage Vdd, the gate terminal and the second drain / source terminal of the p-type transistor Mpx1 are connected to each other, the gate terminal of the n-type transistor Mnx1 is connected to the gate terminal of the p-type transistor Mpx1, the first drain / source terminal of the n-type transistor Mnx1 generates a bias voltage Vb, the second drain / source terminal of the n-type transistor Mnx1 receives the supply voltage GND, the gate terminal of the p-type transistor Mpx2 receives the bias voltage Vb, the first drain / source terminal of the p-type transistor Mpx2 receives the supply voltage Vdd, and the second drain / source terminal of the p-type transistor Mpx2 is connected to the first drain / source terminal of the p-type transistor Mp4.

[0075] like Fig.8D As shown, in the third stage, the connection element 714 of the discharge path between the node c2 and the supply voltage GND is implemented by an n-type transistor Mny. The gate terminal of the n-type transistor Mny is connected to the node b2, the first drain / source terminal of the n-type transistor Mny is connected to the second drain / source terminal of the n-type transistor Mn4, and the second drain / source terminal of the n-type transistor Mny receives the supply voltage GND.

[0076] Furthermore, Fig.8DThe resistive element in the first stage, that is, the n-type transistor Mny, can be replaced by the n-type transistor Mn3 in the second stage. Fig. 8E As shown, the connection element 714 of the discharge path between the node c2 and the supply voltage GND is implemented by an n-type transistor Mn3. The gate terminal of the n-type transistor Mn3 receives the clock signal CK, the first drain / source terminal of the n-type transistor Mn3 is connected to the second drain / source terminal of the n-type transistor Mn4, and the second drain / source terminal of the n-type transistor Mn3 receives the supply voltage GND.

[0077] like Fig.8F As shown, in the third stage, the connection element 714 of the discharge path between the node c2 and the supply voltage GND is realized by the n-type transistors Mny1, Mny2 and the p-type transistor Mpy1. A bias circuit is formed by the p-type transistor Mpy1 and the n-type transistor Mny1 to provide a bias voltage Vb to the gate terminal of the n-type transistor Mny2. Among them, the first drain / source terminal of the p-type transistor Mpy1 receives the supply voltage Vdd, the second drain / source terminal of the p-type transistor Mpy1 generates the bias voltage Vb, the gate terminal of the n-type transistor Mny1 is connected to the gate terminal of the p-type transistor Mpy1, the gate terminal of the n-type transistor Mny1 and the first drain / source terminal are connected to each other, the second drain / source terminal of the n-type transistor Mny1 receives the supply voltage GND, the gate terminal of the n-type transistor Mny2 receives the bias voltage Vb, the first drain / source terminal of the n-type transistor Mny2 is connected to the second drain / source terminal of the n-type transistor Mn4, and the second drain / source terminal of the n-type transistor Mny2 receives the supply voltage GND.

[0078] Furthermore, the present invention can also be combined into other D-type flip-flops according to the above three embodiments. For example, two connecting elements are added in the first stage, and two connecting elements are added in the second stage to form a D-type flip-flop. Alternatively, two connecting elements are added in the first stage, and two connecting elements are added in the third stage to form a D-type flip-flop. Alternatively, two connecting elements are added in the second stage, and two connecting elements are added in the third stage to form a D-type flip-flop. Alternatively, two connecting elements are added in all three stages to form a D-type flip-flop.

[0079] Furthermore, in order to reduce the influence of Miller effect, the present invention further connects at least one capacitance device to node a2. Fig.9A and Fig. 9B , which illustrates the fourth embodiment of the TSPC D-type flip-flop of the present invention. Figure 1AThe difference between the negative trigger TSPC D-type flip-flop 110 and the negative trigger TSPC D-type flip-flop 110 is that the node a2 of the D-type flip-flop 910 is connected to a capacitor element to reduce the hold time of the input signal D and increase the operating speed of the D-type flip-flop. The following only introduces the connection relationship of the capacitor element, and the rest is not repeated.

[0080] like Fig.9A As shown, the capacitor 912 of the D-type flip-flop 910 has a first end and a second end. The first end of the capacitor 912 is connected to the node a2, and the second end of the capacitor 912 receives the supply voltage GND.

[0081] like Fig. 9B As shown, the capacitor 914 of the D-type flip-flop 920 has a first terminal and a second terminal. The first terminal of the capacitor 914 is connected to the node a2, and the second terminal of the capacitor 914 receives the supply voltage Vdd.

[0082] Of course, the present invention can also form other D-type flip-flops based on the above-mentioned D-type flip-flops 910 and 920. For example, the node a2 of the D-type flip-flop is connected to two capacitors, one of which is connected between the node a2 and the supply voltage Vdd, and the other is connected between the node a2 and the supply voltage GND.

[0083] Basically, in the fourth embodiment, the capacitor element can be implemented by using a Metal-Insulator-Metal capacitor (MIM capacitor for short). In addition, the capacitor element can also be implemented by using other electronic components, which will be described below.

[0084] Please refer to FIG. 10A to FIG. 10E , which shows various examples of capacitor elements. Fig. 10A As shown, the capacitor 912 is implemented by an n-type transistor Mnx. The gate terminal of the n-type transistor Mnx is connected to the node a2, and the first drain / source terminal and the second drain / source terminal of the n-type transistor Mnx receive the supply voltage GND.

[0085] like Fig. 10B As shown, the capacitor 914 is implemented by a p-type transistor Mpx. The gate terminal of the p-type transistor Mpx is connected to the node a2, and the first drain / source terminal and the second drain / source terminal of the p-type transistor Mpx receive the supply voltage Vdd.

[0086] like Fig. 10CAs shown, the two capacitor elements 912 and 914 are respectively implemented by an n-type transistor Mnx and a p-type transistor Mpx. The gate terminal of the n-type transistor Mnx is connected to the node a2, the first drain / source terminal and the second drain / source terminal of the n-type transistor Mnx receive the supply voltage GND, the gate terminal of the p-type transistor Mpx is connected to the node a2, and the first drain / source terminal and the second drain / source terminal of the p-type transistor Mpx receive the supply voltage Vdd.

[0087] like Fig. 10D As shown, the two capacitor elements 912 and 914 are respectively implemented by an n-type transistor Mnx and a p-type transistor Mpx. The first drain / source terminal of the p-type transistor Mpx receives the supply voltage Vdd, the second drain / source terminal of the p-type transistor Mpx is connected to the node a2, the gate terminal of the n-type transistor Mnx is connected to the node a2, the first drain / source terminal of the n-type transistor Mnx is connected to the gate terminal of the p-type transistor Mpx, and the second drain / source terminal of the n-type transistor Mnx receives the supply voltage GND.

[0088] like Fig.10E As shown, the two capacitor elements 912 and 914 are respectively implemented by an n-type transistor Mnx and a p-type transistor Mpx. The first drain / source terminal of the p-type transistor Mpx receives the supply voltage Vdd, the gate terminal of the p-type transistor Mpx is connected to the node a2, the gate terminal of the n-type transistor Mnx is connected to the second drain / source terminal of the p-type transistor Mpx, the first drain / source terminal of the n-type transistor Mnx is connected to the node a2, and the second drain / source terminal of the n-type transistor Mnx receives the supply voltage GND.

[0089] Of course, according to the fourth embodiment of the present invention, technicians in this field can also match the capacitor element with the above-mentioned first embodiment to the third embodiment to form various other D-type flip-flops. For example, two connecting elements are added in the first stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the second stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the third stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the first stage, two connecting elements are added in the second stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the first stage, two connecting elements are added in the third stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the second stage, two connecting elements are added in the third stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in the second stage, two connecting elements are added in the third stage, and the capacitor element is connected at node a2 to form a D-type flip-flop. Alternatively, two connecting elements are added in each of the three stages, and a capacitor element is connected to the node a2 to form a D-type flip-flop.

[0090] Furthermore, in the above four embodiments, the D-type flip-flop includes four stages connected in series between the input terminal and the output terminal. Since the fourth stage is an inverter, technicians in this field can omit the inverter of the fourth stage according to actual needs, so that the D-type flip-flop receives the input signal D and generates an inverted output signal according to the clock signal.

[0091] In summary, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the following claims.

Claims

1. A D-type flip-flop, comprising: A first connecting element having a first end and a second end, wherein the first end of the first connecting element receives a first supply voltage; a first first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor is connected to the second terminal of the first connecting element, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, and the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor; a second connecting element having a first end and a second end, wherein the first end of the second connecting element is connected to the second drain / source end of the second second-type transistor, and the second end of the second connecting element receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second first-type transistor receives the clock signal, and the first drain / source terminal of the second first-type transistor receives the first supply voltage; a third first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is coupled to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is coupled to the second node, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor being connected to the second node, the first drain / source terminal of the fourth first-type transistor being coupled to the first supply voltage; a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; as well as a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; One of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element.

2. The D-type flip-flop as claimed in claim 1, further comprising an inverter, an input terminal of the inverter being connected to the third node, and an output terminal of the inverter generating an output signal.

3. The D-type flip-flop as claimed in claim 1, wherein: The first connecting element is a resistive element, and the first connecting element includes a sixth first-type transistor, a gate terminal of the sixth first-type transistor receives the input signal or a bias voltage, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, and a second drain / source terminal of the sixth first-type transistor is connected to the first drain / source terminal of the first first-type transistor.

4. The D-type flip-flop as claimed in claim 3, wherein: The first connecting element also includes a seventh first-type transistor and a fifth second-type transistor, a first drain / source terminal of the seventh first-type transistor receives the first supply voltage, a gate terminal of the seventh first-type transistor is connected to a second drain / source terminal of the seventh first-type transistor, a gate terminal of the fifth second-type transistor is connected to the gate terminal of the seventh first-type transistor, a first drain / source terminal of the fifth second-type transistor generates the bias voltage, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

5. The D-type flip-flop as claimed in claim 1, wherein: The second connecting element is a resistive element, and the second connecting element includes a fifth second-type transistor, a gate terminal of the fifth second-type transistor receives the input signal or a bias voltage, a first drain / source terminal of the fifth second-type transistor is connected to the second drain / source terminal of the second second-type transistor, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

6. The D-type flip-flop as claimed in claim 5, wherein: The second connecting element also includes a sixth first-type transistor and a sixth second-type transistor, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, a second drain / source terminal of the sixth first-type transistor generates the bias voltage, a gate terminal of the sixth second-type transistor is connected to a gate terminal of the sixth first-type transistor, the gate terminal of the sixth second-type transistor is connected to a first drain / source terminal of the sixth second-type transistor, and a second drain / source terminal of the sixth second-type transistor receives the second supply voltage.

7. The D-type flip-flop as described in claim 1 further includes a third connecting element and a fourth connecting element; wherein the third connecting element is connected between the second drain / source terminal of the second first-type transistor and the first drain / source terminal of the third first-type transistor, so that the first drain / source terminal of the third first-type transistor is coupled to the second drain / source terminal of the second first-type transistor; wherein the fourth connecting element is connected between the first drain / source terminal of the third second-type transistor and the second node, so that the first drain / source terminal of the third second-type transistor is coupled to the second node; wherein one of the third connecting element and the fourth connecting element is the resistive element, and the other of the third connecting element and the fourth connecting element is the short-circuit element.

8. The D-type flip-flop as claimed in claim 7, wherein: The third connecting element is a resistive element, and the third connecting element includes a sixth first-type transistor, a gate terminal of the sixth first-type transistor is connected to the first node or receives a bias voltage, a first drain / source terminal of the sixth first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and a second drain / source terminal of the sixth first-type transistor is connected to the first drain / source terminal of the third first-type transistor.

9. The D-type flip-flop as claimed in claim 8, wherein: The third connecting element also includes a seventh first-type transistor and a fifth second-type transistor, a first drain / source terminal of the seventh first-type transistor receives the first supply voltage, a gate terminal of the seventh first-type transistor is connected to a second drain / source terminal of the seventh first-type transistor, a gate terminal of the fifth second-type transistor is connected to the gate terminal of the seventh first-type transistor, a first drain / source terminal of the fifth second-type transistor generates the bias voltage, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

10. The D-type flip-flop as claimed in claim 7, wherein: The fourth connecting element is a resistive element, and the fourth connecting element includes a fifth second-type transistor, a gate terminal of the fifth second-type transistor is connected to the first node or receives a bias voltage, a first drain / source terminal of the fifth second-type transistor is connected to the second node, and a second drain / source terminal of the fifth second-type transistor is connected to the first drain / source terminal of the third second-type transistor.

11. The D-type flip-flop according to claim 10, wherein: The fourth connecting element also includes a sixth first-type transistor and a sixth second-type transistor, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, a second drain / source terminal of the sixth first-type transistor generates the bias voltage, a gate terminal of the sixth second-type transistor is connected to a gate terminal of the sixth first-type transistor, the gate terminal of the sixth second-type transistor is connected to a first drain / source terminal of the sixth second-type transistor, and a second drain / source terminal of the sixth second-type transistor receives the second supply voltage.

12. The D-type flip-flop as described in claim 7 further includes a fifth connecting element and a sixth connecting element; wherein the fifth connecting element is connected between the first supply voltage and the first drain / source terminal of the fourth first-type transistor, so that the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage; wherein the sixth connecting element is connected between the second drain / source terminal of the fourth second-type transistor and the second supply voltage, so that the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; wherein one of the fifth connecting element and the sixth connecting element is the resistive element, and the other of the fifth connecting element and the sixth connecting element is the short-circuit element.

13. The D-type flip-flop according to claim 12, wherein: The first drain / source terminal of the fourth first-type transistor is connected to the second drain / source terminal of the second first-type transistor, so that the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage.

14. The D-type flip-flop as claimed in claim 12, wherein: The second drain / source terminal of the fourth second-type transistor is connected to the first drain / source terminal of the third second-type transistor, so that the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage.

15. The D-type flip-flop as claimed in claim 12, wherein: The fifth connecting element is a resistive element, and the fifth connecting element includes a sixth first-type transistor, a gate terminal of the sixth first-type transistor is connected to the second node or receives a bias voltage, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, and a second drain / source terminal of the sixth first-type transistor is connected to the first drain / source terminal of the fourth first-type transistor.

16. The D-type flip-flop as claimed in claim 15, wherein: The fifth connecting element also includes a seventh first-type transistor and a fifth second-type transistor, a first drain / source terminal of the seventh first-type transistor receives the first supply voltage, a gate terminal of the seventh first-type transistor is connected to a second drain / source terminal of the seventh first-type transistor, a gate terminal of the fifth second-type transistor is connected to the gate terminal of the seventh first-type transistor, a first drain / source terminal of the fifth second-type transistor generates the bias voltage, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

17. The D-type flip-flop as claimed in claim 12, wherein: The sixth connecting element is a resistive element, and the sixth connecting element includes a fifth second-type transistor, a gate terminal of the fifth second-type transistor is connected to the second node or receives a bias voltage, a first drain / source terminal of the fifth second-type transistor is connected to the second drain / source terminal of the fourth second-type transistor, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

18. The D-type flip-flop as claimed in claim 17, wherein: The sixth connecting element also includes a sixth first-type transistor and a sixth second-type transistor, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, a second drain / source terminal of the sixth first-type transistor generates the bias voltage, a gate terminal of the sixth second-type transistor is connected to a gate terminal of the sixth first-type transistor, the gate terminal of the sixth second-type transistor is connected to a first drain / source terminal of the sixth second-type transistor, and a second drain / source terminal of the sixth second-type transistor receives the second supply voltage.

19. The D-type flip-flop as described in claim 1 further includes a third connecting element and a fourth connecting element; wherein the third connecting element is connected between the first supply voltage and the first drain / source terminal of the fourth first-type transistor, so that the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage; wherein the fourth connecting element is connected between the second drain / source terminal of the fourth second-type transistor and the second supply voltage, so that the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; wherein one of the third connecting element and the fourth connecting element is the resistive element, and the other of the third connecting element and the fourth connecting element is the short-circuit element.

20. The D-type flip-flop as claimed in claim 1, wherein: The first-type transistor is a p-type transistor, the second-type transistor is an n-type transistor, and the first supply voltage is greater than the second supply voltage.

21. The D-type flip-flop as claimed in claim 1, wherein: The first-type transistor is an n-type transistor, the second-type transistor is a p-type transistor, and the second supply voltage is greater than the first supply voltage.

22. The D-type flip-flop as claimed in claim 1, further comprising a capacitor connected to the first node.

23. A D-type flip-flop, comprising: a first first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second first-type transistor receives the clock signal, and the first drain / source terminal of the second first-type transistor receives the first supply voltage; a first connecting element having a first end and a second end, wherein the first end of the first connecting element is connected to the second drain / source end of the second first-type transistor; a third first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second terminal of the first connecting element, and the second drain / source terminal of the third first-type transistor is connected to a second node; a second connecting element having a first end and a second end, wherein the first end of the second connecting element is connected to the second node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is connected to the second terminal of the second connecting element, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor being connected to the second node, the first drain / source terminal of the fourth first-type transistor being coupled to the first supply voltage; a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; as well as a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; One of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element. 24 . The D-type flip-flop as claimed in claim 23 , further comprising an inverter, an input terminal of the inverter being connected to the third node, and an output terminal of the inverter generating an output signal.

25. The D-type flip-flop as described in claim 23 further includes a third connecting element and a fourth connecting element; wherein the third connecting element is connected between the first supply voltage and the first drain / source terminal of the fourth first-type transistor, so that the first drain / source terminal of the fourth first-type transistor is coupled to the first supply voltage; wherein the fourth connecting element is connected between the second drain / source terminal of the fourth second-type transistor and the second supply voltage, so that the second drain / source terminal of the fourth second-type transistor is coupled to the second supply voltage; wherein one of the third connecting element and the fourth connecting element is the resistive element, and the other of the third connecting element and the fourth connecting element is the short-circuit element.

26. The D-type flip-flop as claimed in claim 23, wherein: The first-type transistor is a p-type transistor, the second-type transistor is an n-type transistor, and the first supply voltage is greater than the second supply voltage.

27. The D-type flip-flop as claimed in claim 23, wherein: The first-type transistor is an n-type transistor, the second-type transistor is a p-type transistor, and the second supply voltage is greater than the first supply voltage.

28. The D-type flip-flop as claimed in claim 23, further comprising a capacitor connected to the first node.

29. A D-type flip-flop, comprising: a first first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second first-type transistor receives the clock signal, and the first drain / source terminal of the second first-type transistor receives the first supply voltage; a third first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is connected to the second node, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a first connecting element having a first end and a second end, wherein the first end of the first connecting element receives the first supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor being connected to the second node, the first drain / source terminal of the fourth first-type transistor being connected to the second terminal of the first connecting element; a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, and the first drain / source terminal of the fourth second-type transistor is connected to the third node; as well as a second connecting element having a first end and a second end, wherein the first end of the second connecting element is connected to the second drain / source end of the fourth second-type transistor, and the second end of the second connecting element receives the second supply voltage; One of the first connecting element and the second connecting element is a resistive element, and the other of the first connecting element and the second connecting element is a short-circuit element. 30 . The D-type flip-flop as claimed in claim 29 , further comprising an inverter, an input terminal of the inverter being connected to the third node, and an output terminal of the inverter generating an output signal.

31. The D-type flip-flop as claimed in claim 29, wherein: The first-type transistor is a p-type transistor, the second-type transistor is an n-type transistor, and the first supply voltage is greater than the second supply voltage.

32. The D-type flip-flop as claimed in claim 29, wherein: The first-type transistor is an n-type transistor, the second-type transistor is a p-type transistor, and the second supply voltage is greater than the first supply voltage.

33. The D-type flip-flop as claimed in claim 29, further comprising a capacitor connected to the first node.

34. A D-type flip-flop, comprising: a first first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first first-type transistor receives an input signal, the first drain / source terminal of the first first-type transistor receives a first supply voltage, and the second drain / source terminal of the first first-type transistor is connected to a first node; a first second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the first second-type transistor receives a clock signal, and the first drain / source terminal of the first second-type transistor is connected to the first node; a second second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second second-type transistor receives the input signal, the first drain / source terminal of the second second-type transistor is connected to the second drain / source terminal of the first second-type transistor, and the second drain / source terminal of the second second-type transistor receives a second supply voltage; a second first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the second first-type transistor receives the clock signal, and the first drain / source terminal of the second first-type transistor receives the first supply voltage; a third first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third first-type transistor is connected to the first node, the first drain / source terminal of the third first-type transistor is connected to the second drain / source terminal of the second first-type transistor, and the second drain / source terminal of the third first-type transistor is connected to a second node; a third second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the third second-type transistor receives the clock signal, the first drain / source terminal of the third second-type transistor is connected to the second node, and the second drain / source terminal of the third second-type transistor receives the second supply voltage; a fourth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, the gate terminal of the fourth first-type transistor being connected to the second node, the first drain / source terminal of the fourth first-type transistor receiving the first supply voltage; a fifth first-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fifth first-type transistor receives the clock signal, the first drain / source terminal of the fifth first-type transistor is connected to the second drain / source terminal of the fourth first-type transistor, and the second drain / source terminal of the fifth first-type transistor is connected to a third node; a fourth second-type transistor having a gate terminal, a first drain / source terminal and a second drain / source terminal, wherein the gate terminal of the fourth second-type transistor is connected to the second node, the first drain / source terminal of the fourth second-type transistor is connected to the third node, and the second drain / source terminal of the fourth second-type transistor receives the second supply voltage; a first capacitor having a first end and a second end, wherein the first end of the first capacitor is connected to the first node, and the second end of the first capacitor receives the first supply voltage; as well as A second capacitor element has a first end and a second end, wherein the first end of the second capacitor element is connected to the first node, and the second end of the second capacitor element receives the second supply voltage. 35 . The D-type flip-flop as claimed in claim 34 , further comprising an inverter, an input terminal of the inverter being connected to the third node, and an output terminal of the inverter generating an output signal.

36. The D-type flip-flop as claimed in claim 34, wherein: The first-type transistor is a p-type transistor, the second-type transistor is an n-type transistor, and the first supply voltage is greater than the second supply voltage.

37. The D-type flip-flop as claimed in claim 34, wherein: The first-type transistor is an n-type transistor, the second-type transistor is a p-type transistor, and the second supply voltage is greater than the first supply voltage.

38. The D-type flip-flop as claimed in claim 34, wherein: The second capacitor element includes a fifth second-type transistor, a gate terminal of the fifth second-type transistor is connected to the first node, a first drain / source terminal of the fifth second-type transistor and a second drain / source terminal of the fifth second-type transistor receive the second supply voltage.

39. The D-type flip-flop as claimed in claim 34, wherein: The first capacitor element includes a sixth first-type transistor, a gate terminal of the sixth first-type transistor is connected to the first node, a first drain / source terminal of the sixth first-type transistor and a second drain / source terminal of the sixth first-type transistor receive the first supply voltage.

40. The D-type flip-flop as claimed in claim 34, wherein: The second capacitor element includes a fifth second-type transistor, the first capacitor element includes a sixth first-type transistor, a gate terminal of the fifth second-type transistor is connected to the first node, a first drain / source terminal of the fifth second-type transistor and a second drain / source terminal of the fifth second-type transistor receive the second supply voltage, a gate terminal of the sixth first-type transistor is connected to the first node, a first drain / source terminal of the sixth first-type transistor and a second drain / source terminal of the sixth first-type transistor receive the first supply voltage.

41. The D-type flip-flop as claimed in claim 34, wherein: The second capacitor element includes a fifth second-type transistor, the first capacitor element includes a sixth first-type transistor, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, a second drain / source terminal of the sixth first-type transistor is connected to the first node, a gate terminal of the fifth second-type transistor is connected to the first node, a first drain / source terminal of the fifth second-type transistor is connected to a gate terminal of the sixth first-type transistor, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

42. The D-type flip-flop as claimed in claim 34, wherein: The second capacitor element includes a fifth second-type transistor, the first capacitor element includes a sixth first-type transistor, a first drain / source terminal of the sixth first-type transistor receives the first supply voltage, a gate terminal of the sixth first-type transistor is connected to the first node, a gate terminal of the fifth second-type transistor is connected to a second drain / source terminal of the sixth first-type transistor, a first drain / source terminal of the fifth second-type transistor is connected to the first node, and a second drain / source terminal of the fifth second-type transistor receives the second supply voltage.

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