Method and apparatus for reducing drawing command information

Abstract

The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure may determine a state for each of a plurality of graphics state groups. Furthermore, aspects of the present disclosure may determine whether at least one of the plurality of graphics state groups includes a changed state. Additionally, aspects of the present disclosure may transmit state information for at least one graphics state group when the at least one graphics state group includes a changed state. In some aspects, the state information includes information about the state of the at least one graphics state group. Aspects of the present disclosure may also configure a drawing state for the plurality of graphics state groups, wherein the drawing state includes state information for each of the graphics state groups.

Description

[0001] Claim priority

[0002] This application claims priority to and the benefit of U.S. Non-Provisional Application No. 16 / 694,956, filed on November 25, 2019, which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically utilize a graphics processing unit (GPU) to accelerate the rendering of graphics data for display. Such computing devices may include, for example, computer workstations, mobile phones such as so-called smart phones, embedded systems, personal computers, tablet computers, and video game consoles. The GPU performs a graphics processing pipeline, which includes one or more processing stages that operate together to execute graphics processing commands and output frames. A central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may need to utilize a GPU during execution. Devices providing content for visual presentation on a display typically include a GPU.

[0005] Typically, a device's GPU is configured to perform processes in a graphics processing pipeline. However, with the advent of wireless communications and smaller handheld devices, there is a growing demand for improved graphics processing. Summary of the Invention

[0006] The following provides a simplified overview of one or more aspects in order to provide a basic understanding of such aspects. This overview is not an exhaustive overview of all contemplated aspects and is neither intended to identify key elements of all aspects nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that will be presented later.

[0007] In one aspect of the present disclosure, a method, computer-readable medium, and apparatus are provided. The apparatus may be a central processing unit (CPU), a graphics processing unit (GPU), or any other apparatus capable of performing graphics processing. The apparatus may determine a state of each graphics state group in a plurality of graphics state groups. The apparatus may also determine whether at least one of the plurality of graphics state groups includes a changed state. Additionally, when at least one graphics state group includes a changed state, the apparatus may transmit state information for the at least one graphics state group. In some aspects, the state information includes information about the state of the at least one graphics state group. The apparatus may also identify at least one of the plurality of graphics state groups that includes a changed state. Additionally, the apparatus may change the state of at least one of the plurality of graphics state groups so that the at least one graphics state group includes the changed state. The apparatus may also determine state information for at least one of the plurality of graphics state groups. The apparatus may also transmit the state information for at least one of the plurality of graphics state groups to the GPU. Additionally, the apparatus may determine whether one or more of the plurality of graphics state groups include an unchanged state. When one or more graphics state groups include an unchanged state, the device may also copy a state or a state pointer for each of the one or more graphics state groups in the plurality of graphics state groups. The device may also configure drawing states for the plurality of graphics state groups. Furthermore, the device may render at least some of the display content based on state information for at least one of the plurality of graphics state groups. The device may also determine each of the plurality of graphics state groups based on the display content.

[0008] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0010] Figure 2 An example GPU in accordance with one or more techniques of this disclosure is shown.

[0011] Figure 3 Example images or surfaces are shown in accordance with one or more techniques of this disclosure.

[0012] Figure 4 An example diagram including state information is shown in accordance with one or more techniques of this disclosure.

[0013] Figure 5 An example diagram including state information is shown in accordance with one or more techniques of this disclosure.

[0014] Figure 6 An example diagram including state information is shown in accordance with one or more techniques of this disclosure.

[0015] Figure 7 An example flow diagram illustrating an example method in accordance with one or more techniques of this disclosure is shown. DETAILED DESCRIPTION

[0016] Some CPUs build or write a complete set of state information for each graphics state group, regardless of whether the state or context state of the particular graphics state group has changed. Building a complete set of state information for each draw call can result in a significant amount of CPU overhead. The CPU can also notify the GPU to process the state of each individual graphics state group, which can place excessive workload on the CPU and / or GPU. Furthermore, if the GPU is instructed to render each graphics state group regardless of whether the graphics state group changes state, the GPU may perform unnecessary work. Various aspects of the present disclosure can reduce CPU workload overhead when transferring graphics state information for each workload between draw calls. For example, various aspects of the present disclosure can transfer the incremental or changed state of the graphics state group for each draw call and eliminate transferring the non-incremental or non-changed state of the graphics state group. By reducing the number of unnecessary instructions from the CPU and unnecessary state processing at the GPU, various aspects of the present disclosure can reduce a significant amount of workload at the CPU and / or GPU.

[0017] The following describes various aspects of the system, device, computer program product and method more fully with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. More precisely, these aspects are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings herein, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether that aspect is implemented independently of or in combination with other aspects of the present disclosure. For example, a device can be implemented or a method can be implemented using any number of aspects set forth herein. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functions, or structures and functions other than or different from the various aspects of the present disclosure set forth herein. Any aspect disclosed herein can be implemented by one or more elements of the claims.

[0018] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to a particular benefit, use, or objective. Rather, various aspects of the present disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the accompanying drawings and the following description. The detailed description and drawings are merely illustrative of the present disclosure and are not intended to be limiting, and the scope of the present disclosure is defined by the appended claims and their equivalents.

[0019] Several aspects will now be presented with reference to various apparatus and methods. These apparatus and methods will be described in the following detailed description and illustrated in the accompanying drawings by means of various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements may be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0020] For example, an element, or any part of an element, or any combination of elements can be implemented as a "processing system", which includes one or more processors (which may also be referred to as processing units). Examples of processors include: microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set operations (RISC) processors, systems on chip (SoCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic, discrete hardware circuits, and other appropriate hardware configured to perform the various functions described throughout this disclosure. One or more processors in a processing system can execute software. Whether referred to as software, firmware, middleware, microcode, hardware description language or other names, software should be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc. The term application can refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such an example, the application may be stored on a memory, such as an on-chip memory of a processor, a system memory, or any other memory. The hardware described herein (e.g., a processor) may be configured to execute an application. For example, an application may be described as including a code that causes the hardware to execute one or more technologies described herein when executed by the hardware. As an example, the hardware may access code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in this disclosure. In such an example, a component may be hardware, software, or a combination thereof. A component may be a separate component or a subcomponent of a single component.

[0021] Accordingly, in one or more examples described herein, the functions described can be implemented with hardware, software, or any combination thereof. If implemented with software, the functions can be stored on a computer-readable medium or encoded as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media. Storage media can be any available medium that can be accessed by a computer. By way of example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, a combination of the above-mentioned types of computer-readable media, or any other medium that can be used to store computer-executable code in the form of instructions or data structures that can be accessed by a computer.

[0022] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices, or a single device with multiple pipelines, that improves rendering of graphics content and / or reduces the load on a processing unit (i.e., any processing unit (e.g., a GPU) configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0023] As used herein, instances of the term "content" may refer to "graphics content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphics content" may refer to content generated by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" may refer to content generated by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" may refer to content generated by a graphics processing unit.

[0024] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed into display content. For example, a graphics processing unit may output graphics content such as a frame to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (e.g., one or more frames) from the buffer and perform one or more display processing techniques on it to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to synthesize, blend, or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling (e.g., upsampling or downsampling) on ​​a frame. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form a frame, i.e., a frame includes two or more layers, and the frame including two or more layers may then be blended.

[0025] Figure 1is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of this disclosure. Content generation system 100 includes a device 104. Device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a system-on-chip (SoC). Device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some aspects, device 104 may include multiple optional components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to displays 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation. In other examples, the first and second displays may receive the same frame for presentation thereon. In yet another example, the results of the graphics processing may not be displayed on the device, e.g., the first and second displays may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be transmitted to another device. In some aspects, this may be referred to as split rendering.

[0026] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (e.g., display processor 127) for performing one or more display processing techniques on one or more frames generated by processing unit 120 before presentation by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0027] Memory external to processing unit 120 and content encoder / decoder 122 (e.g., system memory 124) can be accessible to processing unit 120 and content encoder / decoder 122. For example, processing unit 120 and content encoder / decoder 122 can be configured to read from and / or write to external memory, such as system memory 124. Processing unit 120 and content encoder / decoder 122 can be communicatively coupled to system memory 124 via a bus. In some examples, processing unit 120 and content encoder / decoder 122 can be communicatively coupled to each other via a bus or a different connection.

[0028] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as system memory 124 and / or communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0029] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0030] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagated signal. However, the term "non-transitory" should not be interpreted to mean that internal memory 121 or system memory 124 is non-removable or that its contents are static. As an example, system memory 124 may be removable from device 104 and moved to another device. As another example, system memory 124 may not be removable from device 104.

[0031] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in an appropriate non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute the instructions in hardware to perform the technology of the present disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., may be considered to be one or more processors.

[0032] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the mainboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 can store instructions for the software in an appropriate non-transitory computer-readable storage medium (e.g., internal memory 123) and can use one or more processors to execute the instructions in hardware to perform the technology of the present disclosure. Any of the foregoing, including hardware, software, a combination of hardware and software, etc., can be considered to be one or more processors.

[0033] In some aspects, the content generation system 100 may include an optional communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any of the receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or position information. The transmitter 130 may be configured to perform any of the transmitting functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device that may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such an example, the transceiver 132 may be configured to perform any of the receiving functions and / or transmitting functions described herein with respect to the device 104.

[0034] Refer again Figure 1 In some aspects, graphics processing pipeline 107 may include a determination component 198 configured to determine a state for each of a plurality of graphics state groups. Determination component 198 may also be configured to determine whether at least one of the plurality of graphics state groups includes a changed state. Determination component 198 may also be configured to transmit state information for the at least one graphics state group when the at least one graphics state group includes a changed state. In some aspects, the state information includes information about the state of the at least one graphics state group. Determination component 198 may also be configured to identify at least one of the plurality of graphics state groups that includes a changed state. Determination component 198 may also be configured to change the state of at least one of the plurality of graphics state groups such that the at least one graphics state group includes the changed state. Determination component 198 may also be configured to determine state information for at least one of the plurality of graphics state groups. Determination component 198 may also be configured to transmit the state information for at least one of the plurality of graphics state groups to the GPU. Determining component 198 may also be configured to determine whether one or more of the plurality of graphics state groups includes an unchanged state. Determining component 198 may also be configured to, when the one or more graphics state groups include an unchanged state, copy a state or state pointer for each of the one or more graphics state groups in the plurality of graphics state groups. Determining component 198 may also be configured to configure drawing states for the plurality of graphics state groups. Determining component 198 may also be configured to render at least some of the display content based on state information for at least one of the plurality of graphics state groups. Determining component 198 may also be configured to determine each of the plurality of graphics state groups based on the display content.

[0035] As described herein, a device such as device 104 may refer to any device, apparatus, or system configured to perform one or more of the techniques described herein. For example, a device may be a server, a base station, a user device, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation, or a mainframe computer), an end product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device, or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device, or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an onboard computer, any mobile device, any device configured to generate graphical content, or any device configured to perform one or more of the techniques described herein. The processes herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0036] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a collection of global state information (e.g., information about global registers, shader programs, or constant data) that can regulate how the graphics context is processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, there can be a bit indicating which workload belongs to the context register. In addition, there can be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Therefore, the context register can define multiple states of the GPU.

[0037] Context states can be used to determine how individual processing units (e.g., vertex fetchers (VFDs), vertex shaders (VSs), shader processors, or geometry processors) operate and / or in which mode a processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads in the pipeline, such as vertex or pixel workloads, based on context register definitions of modes or states. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Because these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changing mode or state.

[0038] Figure 2 An example GPU 200 is shown in accordance with one or more techniques of this disclosure. Figure 2 As shown, the GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, an L2 cache (UCHE) 238, a virtual partition cache (VSC) 239, and a system memory 240. Although Figure 2 The GPU 200 is shown to include processing units 220-238, but the GPU 200 may include multiple additional processing units. In addition, the processing units 220-238 are only examples, and according to the present disclosure, the GPU may use any combination or order of processing units. The GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0039] like Figure 2 As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to parse a command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then send context register packet 260 or draw call data packet 212 to processing units or blocks in the GPU via separate paths. Furthermore, command buffer 250 can change the different states of context registers and draw calls. For example, a command buffer can be constructed in the following manner: context registers for context N, draw calls for context N, context registers for context N+1, and draw calls for context N+1.

[0040] The GPU can render an image in a variety of different ways. In some cases, the GPU can use rendering or tile rendering to render an image. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning pass, the image can be divided into different bins or tiles. In addition, in the binning pass, different primitives can be shaded in certain bins, for example, using draw calls. In some aspects, during the binning pass, a visibility stream can be constructed in which visible primitives or draw calls can be identified.

[0041] In some aspects, the GPU may apply the drawing or rendering process to different bins or tiles. For example, the GPU may render to one bin and then perform all drawing on the primitives or pixels in the bin. Alternatively, the GPU may render to another bin and perform drawing on the primitives or pixels in that bin. Thus, in some aspects, there may be a small number of bins, such as four bins, that cover all drawing on a surface. Furthermore, the GPU may loop through all drawing in one bin, but perform drawing on visible draw calls (i.e., draw calls that include visible geometry). In some aspects, a visibility stream may be generated, for example, in a binning pass, to determine visibility information for each primitive in an image or scene. For example, the visibility stream may identify whether a primitive is visible. In some aspects, this information may be used to remove primitives that are not visible, for example, in a rendering pass. Furthermore, at least some primitives identified as visible may be rendered in a rendering pass.

[0042] In some aspects of tiled rendering, there can be multiple processing stages or passes. For example, rendering can be performed in two passes, such as a visibility or bin visibility pass and a rendering or bin rendering pass. During the visibility pass, the GPU can input the rendering workload, record the location of the primitives or triangles, and then determine which primitives or triangles fall into which bin or region. In some aspects of the visibility pass, the GPU can also identify or mark the visibility of each primitive or triangle in the visibility stream. During the rendering pass, the GPU can input the visibility stream and process one bin or region at a time. In some aspects, the visibility stream can be analyzed to determine which primitives or vertices of primitives are visible or invisible. Therefore, visible primitives or vertices of primitives can be processed. By doing so, the GPU can reduce the workload of unnecessary processing or rendering of invisible primitives or triangles.

[0043] In some aspects, certain types of primitive geometry may be processed during the visibility pass, such as position-only geometry. Additionally, primitives may be sorted into different bins or regions depending on their position or positioning. In some cases, sorting primitives or triangles into different bins may be performed by determining visibility information for those primitives or triangles. For example, the GPU may determine visibility information for each primitive in each bin or region or write it to, for example, system memory. This visibility information may be used to determine or generate a visibility stream. In the rendering pass, primitives in each bin may be rendered separately. In these cases, a visibility stream may be retrieved from memory to discard primitives that are not visible to that bin.

[0044] Some aspects of the GPU or GPU architecture can provide a variety of different options for rendering, such as software rendering and hardware rendering. In software rendering, the driver or CPU can copy the entire frame geometry by processing each view at a time. In addition, some different states can be changed depending on the view. Therefore, in software rendering, the software can copy the entire workload by changing some states that can be used to render each viewpoint in the image. In some aspects, the amount of overhead may increase because the GPU may submit the same workload multiple times for each viewpoint in the image. In hardware rendering, the hardware or GPU may be responsible for copying or processing the geometry of each viewpoint in the image. Therefore, the hardware can manage the copying or processing of primitives or triangles for each viewpoint in the image.

[0045] Figure 3 An image or surface 300 is shown, which includes a plurality of primitives divided into a plurality of bins. Figure 3 As shown, image or surface 300 includes region 302, which includes primitives 321, 322, 323, and 324. Primitives 321, 322, 323, and 324 are divided into or placed in different bins, such as bins 310, 311, 312, 313, 314, and 315. Figure 3 An example of tiled rendering using multiple viewpoints is shown for primitives 321-324. For example, primitives 321-324 are in a first viewpoint 350 and a second viewpoint 351. Thus, GPU processing or rendering of an image or surface 300 including region 302 may utilize multiple viewpoints or multi-view rendering.

[0046] As noted herein, a GPU, or graphics processor unit, can use a tiled rendering architecture to reduce power consumption or conserve memory bandwidth. As further described above, this rendering method can divide a scene into a plurality of bins, and include a visibility pass that identifies triangles visible in each bin. Thus, in tiled rendering, the full screen can be divided into a plurality of bins or tiles. The scene can then be rendered multiple times, for example, once for each bin.

[0047] As noted above, the GPU can loop through each draw call in a bin and execute visible draw calls. In some aspects, draw calls that fall into a given bin are considered live draw calls, while draw calls that fall outside of the bin are considered dead draw calls. Efficiently skipping dead draw calls can reduce the hardware overhead incurred by rendering the scene multiple times.

[0048] For each function of the GPU, there can be an assigned group, namely a workload group or graphics state group. A workload or graphics state group can also include a corresponding state or context state. Therefore, each workload or graphics state group corresponding to a specific state or context state can perform a function of the GPU. For example, the depth state can be one workload or graphics state group, the blend state can be another workload or graphics state group, and the fragment shader state can be another workload or graphics state group.

[0049] For each bin or tile, the GPU can execute all workloads or graphics state groups and retrieve every active draw call for that particular bin. Furthermore, the GPU can retrieve a command stream for each bin render. Furthermore, as noted above, during the visibility pass, the GPU can process the command stream. The GPU can also determine which draw calls are visible in a particular bin during the visibility pass.

[0050] During the visibility pass, the GPU can also build a set of state information or context state information for each graphics state group in each draw call. In some aspects, the GPU can also build a complete set of state information for each draw call when the CPU or software provides incremental or changed state or context state. Thus, the CPU can transmit these incremental states or context states for the workload or graphics state group during the visibility pass. In some aspects, a command stream can be sent before each draw call is executed, for example, in the visibility pass. Thus, a command stream can be sent in the visibility pass before the GPU renders or draws.

[0051] In some cases, the CPU or software can build or write a complete state or context state for each graphics state group between draw calls. By doing so, the CPU can help the GPU or hardware jump to the next draw call instead of fetching a command stream for a dead draw call. Thus, in some aspects, the CPU can build or write a complete set of state information for each graphics state group, regardless of whether the state or context state of a particular graphics state group has changed. For example, if draw calls 1-3 are dead draw calls, then in order to jump from draw call 0 to draw call 4, the CPU or software can build a complete set of state information for each graphics state group between draw calls.

[0052] To build a complete set of state information for each graphics state group, the CPU can utilize the graphics state of each graphics state group, such as context registers, constants, shaders, and resource descriptors. In fact, in some aspects, each draw call can contain a complete set of context state information, which can add considerable driver overhead.

[0053] As described above, a workload or graphics state group may include constants, vertex shaders, fragment shaders, geometry shaders, context registers, getters, resource descriptors, blend states, data states, depth states, and the like. The number of workload or graphics state groups may be any appropriate number, such as 8, 16, 32, or 64. Furthermore, each workload or graphics state group may correspond to a specific state or context state, such as that executed at the GPU. In some aspects, the CPU may instruct the GPU how to divide its workload into different workloads or graphics state groups. The GPU may then process these different workloads or graphics state groups. In some aspects, the GPU may not have knowledge of which group corresponds to a specific state or context state.

[0054] In some aspects, the CPU or driver may include an amount of workload overhead, for example, 1% to 20%, to build a complete set of state information for each draw call. This complete state building is necessary to enable the CPU to efficiently skip dead draw calls during a bin rendering pass and move on to the next live draw call for that bin. This overhead depends on the workload type and whether the CPU builds the previous state information for each graphics state group with unchanged state. In some cases, software can construct a command stream with new state information (i.e., delta state information) for the changed group. Thus, delta state may be a state that has changed from a previous draw call. Similarly, non-delta state may be a state that has not changed from a previous draw call. By sending delta state instead of non-delta state, the CPU can reduce workload overhead. Furthermore, the CPU can construct a command stream with delta state to avoid driver overhead.

[0055] Figure 4 An example graph 400 including status information is shown. Figure 4 Displays graphics state groups 0-7, which contain the corresponding states for a particular draw call. Additionally, Figure 4 The CPU is shown building or writing complete state information for each state in each draw call. Thus, even if the context state of the graphics state group does not change from one draw call to the next, the CPU can continue building that particular state.

[0056] Figure 4Also shown are graphics state groups corresponding to specific context states for each draw call. For example, for draw call 0 executed at step 419, the CPU may set the draw state at 410, including state information 411-418 for groups 0-7. For draw call 1 executed at step 429, the CPU may set the draw state at 420, including state information 421-428 for groups 0-7. For draw call 2 executed at step 439, the CPU may set the draw state at 430, including state information 431-438 for groups 0-7. For draw call 3 executed at step 449, the CPU may set the draw state at 440, including state information 441-448 for groups 0-7. For draw call 4 executed at step 459, the CPU may set the draw state at 450, including state information 451-458 for groups 0-7. For draw call 5 executed at step 469, the CPU may set the draw state at 460, including state information 461-468 for groups 0-7. For draw call 6 executed at step 479 , the CPU may set the draw state at 470 , including state information 471 - 478 for corresponding groups 0 - 7 .

[0057] like Figure 4 As shown, for different draw calls, graphics state groups 0-7 can include three different context states, for example, state 0, 1, or 2. The context state of some graphics state groups can change between subsequent draw calls, for example, moving from state 0 to state 1. For example, from draw call 0 to draw call 1, the context state of group 5 changes from 0 to 1. Figure 4 As further shown in , this pattern can continue for the graphics state group until a specific draw call (eg, draw N) is made for a different state (eg, state X, Y, or Z). Figure 4 Also shown are eight different graphics state groups, but there may be any different number of suitable graphics state groups, such as 8, 16, 32, or 64. As described above, the workload or state of the GPU is divided into these workloads or graphics state groups.

[0058] As pointed out above, Figure 4 This shows that the state of each graphics state group can be built even if they do not change. Building a complete set of state information for each draw call can cause significant overhead from the CPU, which can also result in a large number of CPU workload cycles. This may also affect the CPU power consumption when the GPU workload is running. Figure 4As shown, from draw call 0 to draw call 1, group 5 can go from state 0 to state 1, but the CPU may still build or write each state for draw call 1. Additionally, from draw call 1 to draw call 2, groups 2 and 6 can go from state 0 to state 1, but the CPU may still build or write each state for draw call 2. Therefore, the CPU can write the complete state of all groups, regardless of whether the state of each group changes.

[0059] In some aspects, when the CPU writes the complete state for all groups, the CPU can notify the GPU to process each of these states for each group. As a result, the GPU can process more workload cycles because the complete state exists for each draw call. Furthermore, the CPU can send the complete state information to the GPU for each draw call, regardless of the GPU rendering mode.

[0060] In some aspects, the GPU can have different rendering modes, such as direct or software binning mode and / or hardware binning mode. As mentioned herein, in software binning mode, the GPU can render each tile and process all draw calls in each bin. Additionally, in software binning mode, information about live or dead draw calls may not be transmitted. For example, in software binning mode, an entire surface can be rendered at once, rather than by dividing the surface into small tiles or bins. As mentioned herein, software binning mode may not include visibility passes. In some aspects, software binning mode can be useful when there are a small number of draw calls.

[0061] In hardware binning mode, there is a visibility pass in which the GPU processes each draw call and / or generates visibility information. As mentioned herein, the visibility information may describe which draw calls are visible in each bin or tile. Furthermore, in hardware binning mode, the surface is divided into tiles, and each tile is rendered separately by processing all draw calls for each tile. As described above, this visibility information includes information about live or dead draw calls. In some aspects, during or after the visibility pass, live or dead draw call information for each bin may be transmitted to the GPU, and the GPU may render each bin based on the live or dead draw call information. Thus, before rendering each bin, the GPU may copy a complete set of state information for each draw call.

[0062] As noted above, in some aspects, the CPU may notify the GPU to process the state of each individual graphics state group, which may utilize a significant amount of workload on the CPU. Furthermore, if the GPU is instructed to process each graphics state group regardless of whether the graphics state group changes state, the GPU may perform unnecessary work. By eliminating unnecessary instructions from the CPU and unnecessary state processing at the GPU, significant workload can be saved on both the CPU and the GPU.

[0063] Various aspects of the present disclosure can eliminate CPU workload overhead by transferring complete graphics state information for each workload between draw calls, for example, proportional to the CPU power utilized. For example, various aspects of the present disclosure can transfer the incremental or changed state of the graphics state group for each draw call and eliminate transferring the non-incremental or non-changed state of the graphics state group. This can occur in both software binning mode and hardware binning mode.

[0064] In some aspects, in hardware binning mode, the GPU's command processor (CP) can copy non-incremental state from a previous draw call to the next draw call. The CP can also obtain the command stream for the visibility pass. Therefore, during the visibility pass, the CP's command stream can copy non-incremental state. In some cases, the CP's overhead of copying non-incremental state can be hidden. For example, when the GPU processes the visibility pass before the rendering pass for each bin or in parallel with the previous rendering pass, the CP's overhead can be hidden or moved. In fact, the GPU pipeline can process the visibility pass in parallel with the rendering pass of the previous frame, and by doing so, the entire visibility pass processing can be hidden.

[0065] As noted herein, aspects of the present disclosure may enable the CPU or software to identify incremental or changed state for each graphics state group from a previous draw call, rather than providing a complete set of state information for each group for each draw call. Thus, the CPU or software may send the changed state to the GPU. By doing so, this may save CPU workload cycles and / or reduce CPU driver overhead. For example, rather than building a complete set of state information for each graphics state group for each draw call, the CPU may construct or write a non-incremental or non-changing state, which reduces the amount of workload performed.

[0066] As noted herein, in some aspects, for example, in direct rendering mode or software binning mode, the CP of the GPU may directly process the incremental state of the graphics state group, rather than building a complete set of state information for each draw call. This may reduce the amount of workload, such that the reduced workload may be processed faster than a full state workload (e.g., processing a complete set of state information including non-incremental state for each draw call). Since a complete set of state information will not be built, the GPU may perform other processing while processing the incremental state. As noted above, in a hardware binning visibility pass, the CP may not process a complete set of state information for each draw call. The CP may also build a set draw state mask that can be used in a binning rendering pass. Furthermore, since the CP may not process the complete state, visibility pass processing at the GPU may be faster than if a complete set of state information were built.

[0067] In some aspects, in different rendering modes, for example, in direct mode, software binning mode, or hardware binning mode, the CPU can send incremental state information to the GPU. In direct mode or software binning mode, since there is no visibility path, the GPU may not build a complete set of state information or copy non-changing state. When the GPU is rendering a frame, the GPU can directly process the changing state. In some aspects, in direct mode or software binning mode, the GPU can process the rendering pass faster because it does not build a complete set of state information or copy non-changing state. For example, during the rendering pass, the GPU can process the incremental state of the graphics state group, so the GPU can perform fewer workload cycles for each draw call.

[0068] In hardware binning mode, the GPU can build a complete set of state information for each graphics state group in each draw call, for example, during a visibility pass. As noted above, hardware binning mode can include a visibility pass, and a copy of non-incremental state information can also be performed during the visibility pass. The GPU will perform fewer workload cycles because it copies non-changing states instead of processing all states, including non-changing states. Additionally, by copying each non-changing state, various aspects of the present disclosure can more efficiently build a complete set of state information for each graphics state group in each draw call, allowing each tile rendering pass to be processed faster.

[0069] As noted above, aspects of the present disclosure may include the CPU constructing or writing incremental state change information for each graphics state group. In some aspects, for example, during hardware binning mode, the GPU may generate or copy the remaining state information for the non-changing graphics state groups during a visibility pass. As mentioned herein, the visibility pass may occur before the rendering pass for each bin.

[0070] Figure 5 An example graph 500 including state information is shown, in accordance with one or more techniques of this disclosure. Figure 5 Displays workload or graphics state groups 0-7, which include the corresponding context state for each draw call. In addition, Figure 5 The CPU builds or writes context state information for each incremental or changing state in each draw call. Therefore, if the context state of the graphics state group does not change from one draw call to the next, the CPU will not build or write that context state. Non-incremental state that is not built or written is not written in Figure 5 Marked as "Not used".

[0071] Figure 5 Also shown are which graphics state groups for each draw call correspond to the incremental or changing state. For example, for draw call 0 executed at step 519, the CPU may set the draw state at 510, including the incremental state information 511-518 for groups 0-7. For draw call 1 executed at step 529, the CPU may set the draw state at 520, including the incremental state information 521 for group 5. For draw call 2 executed at step 539, the CPU may set the draw state at 530, including the incremental state information 531 and 532 for groups 2 and 6. For draw call 3 executed at step 549, the CPU may set the draw state at 540, including the incremental state information 541 for group 4. For draw call 4 executed at step 559, the CPU may set the draw state at 550, including the incremental state information 551 and 552 for groups 1 and 6. For draw call 5 executed at step 569, the CPU may set the draw state at 560, including the incremental state information 561 for group 3. For draw call 6 executed at step 579, the CPU may set the draw state at 570, including incremental state information 571, 572, and 573 for corresponding groups 0, 1, and 2. As indicated above, state information marked as "unused" may correspond to a non-incremental or unchanged state of the graphics state group.

[0072] like Figure 5As shown, for different draw calls, graphics state groups 0-7 may include three different context states, for example, states 0, 1, or 2. The context state of some graphics state groups may change between subsequent draw calls, for example, moving from state 0 to state 1. For example, from draw call 0 to draw call 1, the context state of group 5 changes from 0 to 1, for example, as shown in step 521. As described above, Figure 5 Also shown are eight different graphics state groups, but there may be any different number of suitable graphics state groups, such as 8, 16, 32, or 64.

[0073] Figure 5 A delta flow is shown that includes delta state information that is sent from the CPU to the GPU before the GPU executes the visibility pass. Figure 5 The set drawing state in steps (e.g., “SET_DRAW_STATE” at steps 510, 520, 530, 540, 550, 560, and 570) instructs the GPU to set the drawing state for each group. Since no group with a non-incremental state is identified, the set drawing state may instruct the GPU to set the drawing state for a group including an incremental state or a changing state. Figure 5 As shown, the CPU or software reserves space for non-incremental state without constructing or writing any information. In hardware binning mode, the CPU can send this information to the GPU before the visibility pass.

[0074] As noted herein, in some aspects of the present disclosure, the CPU may send information about the incremental or changed state of a workload or graphics state group to the GPU. The CPU may send information for graphics state groups that actually changed state, but not for graphics state groups that did not change state. Figure 5 As shown, for a new draw call, there is no information for groups that have not changed state, that is, "unused" information. In some cases, "unused" may be memory that is not used by the CPU. For example, the CPU may not use the system memory, so that the GPU can copy non-incremental state based on the GPU rendering mode. By skipping the non-changed state in each draw call, the CPU can save processing time for each draw call. After the CPU sends the changed state information for the group, the GPU can generate visibility information for each draw and can also build a complete state information set for each draw call. In hardware binning mode, the GPU can copy state information for non-incremental state in the visibility pass.

[0075] The GPU can determine which workloads or context state groups have not changed state based on state information from the GPU. The GPU or command processor (CP) can, for example, in hardware binning mode, replicate groups that have not changed state during the visibility pass. Additionally, the GPU can hide or move these cycles in a parallel pipeline during the visibility pass. In some aspects of the present disclosure, the CPU or software can construct a command stream with incremental state, such as Figure 5 As shown in the example above, instead of building a complete set of state information for each draw call, the CPU can reduce its processing workload, as well as reducing the processing workload at the GPU.

[0076] Figure 6 An example graph 600 including state information is shown, in accordance with one or more techniques of this disclosure. Figure 6 Workload or graphics state groups 0-7 are shown, which include the corresponding context state for each draw call. Figure 6 It is also shown that the CPU builds or writes context state information for each incremental or changing state in each draw call, e.g. Figure 6 If the context state of a graphics state group does not change from one draw call to the next, the CPU will not build or write that context state. The GPU or CP can then copy the non-incremental or unchanged state from the previous draw call, such as during a visibility pass. Figure 6 shown in dark grey.

[0077] Figure 6 6. It is shown which graphics state groups for each draw call include incremental or changing state, and which graphics state groups include non-incremental state and are copied by the GPU. For example, for draw call 0 executed at step 619, the CPU may set the draw state at 610, including incremental state information 611-618 for corresponding groups 0-7. For draw call 1 executed at step 629, the CPU may set the draw state at 620, including incremental state information 621 for corresponding group 5. The GPU may copy the corresponding non-incremental state information 622-628 for groups 0-4 and 6-7. For draw call 2 executed at step 639, the CPU may set the draw state at 630, including incremental state information 631 and 632 for corresponding groups 2 and 6. The GPU may copy the corresponding non-incremental state information 633-638 for groups 0-1, 3-5, and 7. Although Figure 4-6 Eight groups are shown, but the number of groups is not limited to 8. For example, there may be any suitable number of groups. Figure 4-6 Simplified to show eight groups.

[0078] For draw call 3 executed at step 649, the CPU may set the draw state at 640, including the corresponding incremental state information 641 for group 4. The GPU may copy the corresponding non-incremental state information 642-648 for groups 0-3 and 5-7. For draw call 4 executed at step 659, the CPU may set the draw state at 650, including the corresponding incremental state information 651 and 652 for groups 1 and 6. The GPU may copy the corresponding non-incremental state information 653-658 for groups 0, 2-5, and 7. For draw call 5 executed at step 669, the CPU may set the draw state at 660, including the corresponding incremental state information 661 for group 3. The GPU may copy the corresponding non-incremental state information 662-668 for groups 0-2 and 4-7. For draw call 6 executed at step 679, the CPU may set the draw state at 670, including the corresponding incremental state information 671, 672, and 673 for groups 0, 1, and 2. The GPU may copy the non-incremental state information 674 - 678 of corresponding groups 3 - 7 .

[0079] like Figure 6 As shown, for different draw calls, graphics state groups 0-7 may include three different context states, e.g., states 0, 1, or 2. For example, the context state of some graphics state groups may change between subsequent draw calls, e.g., moving from state 0 to state 1. For example, from draw call 0 to draw call 1, the context state of group 5 changes from 0 to 1, e.g., as shown in step 621. As described above, Figure 6 Also shown are eight different graphics state groups, but there may be any different number of suitable graphics state groups, such as 8, 16, 32, or 64.

[0080] Figure 6 The command stream executed by the GPU during a visibility pass (e.g., in hardware binning mode) is shown. The command stream includes incremental state information established and sent by the CPU and non-incremental state information copied by the GPU. As described above, the CPU can reserve non-incremental state for each group in the command stream, and the GPU can then copy each non-incremental state. So the CPU or software can execute Figure 6 The light grey steps in the image are represented by the image, and the dark grey steps can be replicated by the GPU or hardware.

[0081] Figure 6 The diagram 600 in FIG. 1 shows a visible representation of the command flow, for example, after the GPU has completed processing the visibility pass. Figure 6As shown, the GPU will perform Draw 0 at step 619 in the visibility pass. The GPU then obtains state information for group 5 at step 621 and performs Draw 1 at step 629 of the visibility pass. As the GPU performs the visibility pass, it may copy or populate the unchanged state of groups 0-4 and 6-7 at steps 622-628. Thus, after the CPU sends the incremental or changed state information for the changed groups, and during the visibility pass, the GPU may generate visibility information for each draw call and also copy the non-incremental state information to prepare a complete state for each draw call. For example, the CPU may send incremental or changed state information for Draw 1, e.g., when group 5 changes from state 0 to state 1, and then the GPU generates visibility information for group 5 and copies or populates the state information for the unchanged groups 0-4 and 6-7.

[0082] As noted herein, the GPU's CP can, for example, copy the non-incremental state of the corresponding workload from a previous draw call to the next draw call during a visibility pass. Thus, in hardware binning mode, the GPU builds a complete set of state information during the visibility pass. One advantage of this is that the work being performed by the GPU (e.g., copying non-incremental state information from a previous draw call) can be hidden or moved away from normal GPU processing. This hidden or moved work can be executed in parallel work pipelines.

[0083] Figure 5 and 6 An example of the above process for transmitting status information during incremental flow or command flow is shown. Figure 5 and 6 As shown, various aspects of the present disclosure (e.g., the CPU and GPU herein) may perform a number of different steps or processes to transmit state information in a delta stream or command stream. For example, the CPU herein may determine a number of graphics state groups (e.g., Figure 5 and 6 Each graphics state group in groups 0-7 in the present invention. The CPU of this article can also be used, for example, in Figure 5 The drawing state of the plurality of graphics state groups is configured or set at steps 510, 520, 530, 540, 550, 560, and 570 in FIG. In some aspects, the drawing state may include state information for each of the plurality of graphics state groups, for example, Figure 5 The CPU of this article can also determine the status of each graphics state group in multiple graphics state groups, for example, Figure 5 The status in 511-518.

[0084] The CPU herein may also change the state of at least one of the plurality of graphics state groups so that the at least one graphics state group includes the changed state, e.g., Figure 5 At 521 in , group 5 changes from state 0 to state 1. The CPU herein may also determine whether at least one of the plurality of graphics state groups includes a changed state, for example, the CPU may determine whether at least one of the plurality of graphics state groups includes a changed state. Figure 5 At 521 in group 5, state 0 changes to state 1. The CPU herein may also identify at least one graphics state group among a plurality of graphics state groups including a changed state, for example, the CPU may identify Figure 5 At 521 in group 5 changes from state 0 to state 1.

[0085] The CPU herein may also determine state information for at least one of the plurality of graphics state groups. For example, the CPU may determine Figure 6 The CPU herein may also transmit state information for at least one of the plurality of graphics state groups when at least one graphics state group includes a changed state, for example, the CPU may transmit Figure 6 State information for group 5 at 621. In some aspects, the state information may include information about the state of at least one graphics state group, for example, Figure 6 The CPU in this article may also send state information for at least one of the multiple graphics state groups to the GPU. For example, the CPU may send Figure 6 State information for group 5 at 621. In some aspects, state information for at least one graphics state group may be sent by the CPU, e.g., Figure 6 As shown in 621.

[0086] The CPU and GPU herein may also determine whether one or more of the plurality of graphics state groups includes an unchanged state. For example, the CPU or GPU may determine whether groups 0-4 and 6-7 include Figure 6 The CPU and GPU herein may also copy the state or state pointer for each of one or more graphics state groups in the plurality of graphics state groups when one or more graphics state groups include an unchanged state, e.g., the CPU or GPU may copy the state or state pointer for each of the one or more graphics state groups in the plurality of graphics state groups. Figure 6In some aspects, the state of each of the one or more graphics state groups that includes an unchanged state may be copied by the CP of the GPU during a visibility pass. In some aspects, the one or more graphics state groups that include an unchanged state may be determined based on the state information, e.g., the one or more graphics state groups that include an unchanged state may be determined based on the state information. Figure 6 Groups 0-4 and 6-7 at 622-628.

[0087] The CPU and GPU herein may also render at least some of the display content based on state information for at least one of the plurality of graphics state groups. For example, the GPU may render at least some of the display content based on the state information for at least one of the plurality of graphics state groups. Figure 6 At least some of the display content is rendered using state information for group 5 at 621 of the graphics state group. In some aspects, the changed state of the at least one graphics state group may be determined based on a previous draw call and a current draw call, e.g., the changed state of group 5 at 621 may be determined based on draw call 0 at 619 and draw call 1 at 629. In some cases, the state information may include a list of states for each of the at least one graphics state group, e.g., Figure 6 Lists of state information are shown at 611-618. In some aspects, the determination as to whether at least one of the plurality of graphics state groups includes a changed state may be performed by a CPU.

[0088] The above aspects of the present disclosure can include multiple advantages. For example, aspects of the present disclosure can reduce CPU overhead when processing the command stream for each bin, while reducing GPU overhead. In fact, instead of the CPU building complete state information for each draw call, the CPU can build information for incremental or non-changing state. In addition, in direct rendering mode or software binning mode, the GPU can directly process incremental state instead of building complete state information for each draw call, which can increase processing speed. Moreover, in the visibility pass in hardware binning mode, the CP of the GPU may not process a complete set of state information for each draw call because the state information for non-incremental state can be copied. By doing so, the GPU can build a set draw state mask that can be used in the rendering pass.

[0089] Figure 7 An example flow chart 700 of an example method according to one or more techniques of the present disclosure is shown. The method may be performed by a device such as a CPU, a GPU, or a device for graphics processing. At 702, the device may determine each of a plurality of graphics state groups based on display content, such as in combination with Figure 3 、4 , 5 and 6. At 704, the device can configure drawing states for multiple graphics state groups, such as in combination with Figure 3 、 4 , 5 and 6. In some aspects, the drawing state may include state information for each of the plurality of graphics state groups, such as in conjunction with Figure 3 、 4 , 5 and 6. At 706, the apparatus may determine the state of each of the plurality of graphics state groups, such as in combination with Figure 3 、 4 , 5 and 6 as described by the examples.

[0090] At 708, the apparatus may change a state of at least one of the plurality of graphics state groups such that the at least one graphics state group includes a changed state, such as in conjunction with Figure 3 、 4 , 5 and 6. At 710, the apparatus may determine whether at least one of the plurality of graphics state groups includes a changed state, such as in conjunction with Figure 3 、 4 , 5 and 6. At 712, the apparatus may identify at least one graphics state group of a plurality of graphics state groups including a changed state, such as in conjunction with Figure 3 、 4 , 5 and 6 as described by the examples.

[0091] At 714, the apparatus may determine state information for at least one of the plurality of graphics state groups, such as in conjunction with Figure 3 、 4 , 5 and 6. At 716, when at least one graphics state group includes a changed state, the apparatus may transmit state information for at least one graphics state group in the plurality of graphics state groups, such as in conjunction with Figure 3 、 4 In some aspects, the state information may include information about the state of at least one graphics state group, such as in conjunction with Figure 3 、 4 , 5 and 6. At 718, the apparatus may send state information for at least one of the plurality of graphics state groups to the GPU, as described in conjunction with Figure 3 、 4 In some aspects, state information for at least one graphics state group may be sent by the CPU, such as in conjunction with Figure 3 、 4 , 5 and 6 as described by the examples.

[0092] At 720, the apparatus may determine whether one or more of the plurality of graphics state groups includes an unchanged state, such as in conjunction with Figure 3 、 4 , 5, and 6. At 722, when one or more graphics state groups include an unchanged state, the device may copy the state or state pointer for each of the one or more graphics state groups of the plurality of graphics state groups, as described in conjunction with Figure 3 、 4 , 5, and 6. In some aspects, the state of each of the one or more graphics state groups that includes unchanged state can be copied by the CP of the GPU during the visibility pass, such as in conjunction with Figure 3 、 4 In some aspects, one or more graphics state groups in a plurality of graphics state groups including unchanged states may be determined based on the state information, such as in conjunction with Figure 3 、 4 , 5 and 6 as described by the examples.

[0093] At 724, the apparatus may render at least some of the display content based on state information for at least one of the plurality of graphics state groups, such as in conjunction with Figure 3 、 4 In some aspects, the changed state of at least one graphics state group may be determined based on a previous draw call and a current draw call, such as in combination with Figure 3 、 4 , 5 and 6. In some cases, the state information may include a list of states of each of the at least one graphics state group, such as in conjunction with Figure 3 、 4 , 5 and 6. In some aspects, the determination of whether at least one of the plurality of graphics state groups includes a changed state may be performed by a CPU, such as in conjunction with Figure 3 、 4 , 5 and 6 as described by the examples.

[0094] In one configuration, a method or apparatus for graphics processing is provided. The apparatus may be a CPU, a GPU, or some other processor capable of performing graphics processing. In one aspect, the apparatus may be processing unit 120 within device 104, or may be some other hardware within device 104 or another device. The apparatus may include means for determining a state of each of a plurality of graphics state groups. The apparatus may also include means for determining whether at least one of the plurality of graphics state groups includes a changed state. The apparatus may also include means for transmitting state information for at least one of the plurality of graphics state groups when the at least one graphics state group includes a changed state. The apparatus may also include means for identifying at least one of the plurality of graphics state groups that includes a changed state. The apparatus may also include means for changing the state of at least one of the plurality of graphics state groups such that the at least one graphics state group includes the changed state. The apparatus may also include means for determining state information for at least one of the plurality of graphics state groups. The apparatus may also include means for sending the state information for at least one of the plurality of graphics state groups to a GPU. The apparatus may further include means for determining whether one or more graphics state groups in the plurality of graphics state groups include an unchanged state. The apparatus may further include means for replicating a state for each of the one or more graphics state groups in the plurality of graphics state groups when the one or more graphics state groups include an unchanged state. The apparatus may further include means for configuring drawing states for the plurality of graphics state groups. The apparatus may further include means for rendering at least some of the display content based on state information for at least one of the plurality of graphics state groups. The apparatus may further include means for determining each of the plurality of graphics state groups based on the display content.

[0095] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a CPU, or some other processor that can perform graphics processing to implement the state information technology described herein. This can also be achieved at a low cost compared to other graphics processing techniques. In addition, the graphics processing techniques herein can improve or accelerate data processing or execution. In addition, the graphics processing techniques herein can improve resource or data utilization and / or resource efficiency. In addition, various aspects of the present disclosure can utilize a state information process that can reduce the time spent and money consumed during incremental flow or command flow.

[0096] In accordance with the present disclosure, the term "or" may be interpreted as "and / or" unless the context dictates otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used with respect to some features disclosed herein but not others, features for which such language is not used may be interpreted as implying such meaning unless the context dictates otherwise.

[0097] In one or more examples, the functionality described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" has been used throughout this disclosure, such a processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique described herein, or other module is implemented in software, any functionality, processing unit, technique described herein, or other module may be stored on or transmitted through a computer-readable medium as one or more instructions or code. Computer-readable media may include computer data storage media or communication media, including any media that facilitates the transfer of a computer program from one place to another. In this manner, a computer-readable medium may generally correspond to: (1) a non-transitory, tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to obtain instructions, code, and / or data structures for implementing the techniques described in this disclosure. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. As used herein, disk and optical disc include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, wherein disks usually reproduce data magnetically, while optical discs use lasers to reproduce data optically. Combinations of the above should also be included within the scope of computer-readable media. Any computer program product may include computer-readable media.

[0098] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field-programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor," as used herein, may refer to any of the foregoing structures or any other structure suitable for implementing the techniques described herein. Furthermore, the techniques may be implemented entirely in one or more circuits or logic elements.

[0099] The techniques of the present disclosure can be implemented in a wide variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in this disclosure to emphasize the functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Specifically, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware.

[0100] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. A method for graphics processing, comprising: determining a state of each graphics state group in a plurality of graphics state groups; determining whether at least one graphics state group of the plurality of graphics state groups includes a changed state; as well as transmitting state information for the at least one graphics state group of the plurality of graphics state groups when the at least one graphics state group includes a changed state, wherein the state information includes information about the state of the at least one graphics state group, The method further comprises: determining whether one or more of the plurality of graphics state groups includes an unchanged state; and When the one or more graphics state groups include unchanged state, copying the state of each of the one or more graphics state groups in the plurality of graphics state groups from a previous draw call to a current draw call, wherein the state of each of the one or more graphics state groups including the unchanged state is copied by a command processor of a graphics processing unit (GPU) during a visibility pass.

2. The method according to claim 1, further comprising: The at least one graphics state group of the plurality of graphics state groups that includes the changed state is identified.

3. The method according to claim 1, further comprising: The state of the at least one graphics state group in the plurality of graphics state groups is changed such that the at least one graphics state group includes the changed state.

4. The method according to claim 1, further comprising: The state information for the at least one graphics state group of the plurality of graphics state groups is determined.

5. The method according to claim 1, wherein Transmitting the state information for the at least one graphics state group of the plurality of graphics state groups further comprises: The state information for the at least one graphics state group of the plurality of graphics state groups is sent to a graphics processing unit (GPU).

6. The method according to claim 5, wherein: The state information for the at least one graphics state group is sent by a central processing unit (CPU).

7. The method according to claim 1, wherein The one or more graphics state groups of the plurality of graphics state groups that include unchanged states are determined based on the state information.

8. The method according to claim 1, further comprising: A drawing state is configured for the plurality of graphics state groups, wherein the drawing state includes state information for each of the plurality of graphics state groups.

9. The method according to claim 1, further comprising: At least some of the display content is rendered based on the state information for the at least one graphics state group of the plurality of graphics state groups.

10. The method according to claim 9, further comprising: Each graphics state group of the plurality of graphics state groups is determined based on the display content.

11. The method according to claim 1, wherein The changed state of the at least one graphics state group is determined based on a previous draw call and a current draw call.

12. The method according to claim 1, wherein The state information includes a listing of the states for each of the at least one graphics state group.

13. The method according to claim 1, wherein The determination as to whether the at least one of the plurality of graphics state groups includes a changed state is performed by a central processing unit (CPU).

14. A device for graphics processing, comprising: Memory; as well as At least one processor coupled to the memory and configured to: determining a state of each graphics state group in a plurality of graphics state groups; determining whether at least one graphics state group of the plurality of graphics state groups includes a changed state; as well as transmitting state information for the at least one graphics state group of the plurality of graphics state groups when the at least one graphics state group includes a changed state, wherein the state information includes information about the state of the at least one graphics state group, The at least one processor is further configured to: determining whether one or more of the plurality of graphics state groups includes an unchanged state; and When the one or more graphics state groups include unchanged state, copying the state of each of the one or more graphics state groups in the plurality of graphics state groups from a previous draw call to a current draw call, wherein the state of each of the one or more graphics state groups including the unchanged state is copied by a command processor of a graphics processing unit (GPU) during a visibility pass.

15. The device according to claim 14, wherein The at least one processor is further configured to: The at least one graphics state group of the plurality of graphics state groups that includes the changed state is identified.

16. The device according to claim 14, wherein The at least one processor is further configured to: The state of the at least one graphics state group in the plurality of graphics state groups is changed such that the at least one graphics state group includes the changed state.

17. The device according to claim 14, wherein The at least one processor is further configured to: The state information for the at least one graphics state group of the plurality of graphics state groups is determined.

18. The device according to claim 14, wherein To transmit the state information for the at least one graphics state group among the plurality of graphics state groups, the at least one processor is further configured to: The state information for the at least one graphics state group of the plurality of graphics state groups is sent to a graphics processing unit (GPU).

19. The device according to claim 18, wherein The state information for the at least one graphics state group is sent by a central processing unit (CPU).

20. The apparatus according to claim 14, wherein The one or more graphics state groups of the plurality of graphics state groups that include unchanged states are determined based on the state information.

21. The apparatus according to claim 14, wherein The at least one processor is further configured to: A drawing state is configured for the plurality of graphics state groups, wherein the drawing state includes state information for each of the plurality of graphics state groups.

22. The apparatus according to claim 14, wherein The at least one processor is further configured to: At least some of the display content is rendered based on the state information for the at least one graphics state group of the plurality of graphics state groups.

23. The device according to claim 22, wherein The at least one processor is further configured to: Each graphics state group of the plurality of graphics state groups is determined based on the display content.

24. The apparatus according to claim 14, wherein The changed state of the at least one graphics state group is determined based on a previous draw call and a current draw call.

25. The apparatus according to claim 14, wherein The state information includes a listing of the states for each of the at least one graphics state group.

26. The apparatus according to claim 14, wherein The determination as to whether the at least one of the plurality of graphics state groups includes a changed state is performed by a central processing unit (CPU).

27. A device for graphics processing, comprising: means for determining a state of each graphics state group of a plurality of graphics state groups; means for determining whether at least one graphics state group of the plurality of graphics state groups includes a changed state; as well as means for transmitting state information for the at least one graphics state group of the plurality of graphics state groups when the at least one graphics state group includes a changed state, wherein the state information includes information regarding the state of the at least one graphics state group, The device further comprises: means for determining whether one or more of the plurality of graphics state groups includes an unchanged state; and means for copying the state of each of the one or more graphics state groups in the plurality of graphics state groups from a previous draw call to a current draw call when the one or more graphics state groups include unchanged state, wherein the state of each of the one or more graphics state groups including the unchanged state is copied by a command processor of a graphics processing unit (GPU) during a visibility pass.

28. The apparatus according to claim 27, further comprising: Means for identifying the at least one graphics state group of the plurality of graphics state groups that includes the changed state.

29. The apparatus of claim 27, further comprising: Unit for changing the state of the at least one graphics state group of the plurality of graphics state groups such that the at least one graphics state group includes the changed state.

30. The apparatus of claim 27, further comprising: Means for determining the state information for the at least one graphics state group of the plurality of graphics state groups.

31. The apparatus according to claim 27, wherein The means for transmitting the state information for the at least one graphics state group of the plurality of graphics state groups when the at least one graphics state group includes a changed state is configured to: The state information for the at least one graphics state group of the plurality of graphics state groups is sent to a graphics processing unit (GPU).

32. The apparatus according to claim 31, wherein The state information for the at least one graphics state group is sent by a central processing unit (CPU).

33. The apparatus according to claim 27, wherein The one or more graphics state groups of the plurality of graphics state groups that include unchanged states are determined based on the state information.

34. The apparatus of claim 27, further comprising: Means for configuring a drawing state for the plurality of graphics state groups, wherein the drawing state includes state information for each graphics state group in the plurality of graphics state groups.

35. The apparatus of claim 27, further comprising: Means for rendering at least some of display content based on the state information for the at least one graphics state group of the plurality of graphics state groups.

36. The apparatus of claim 35, further comprising: Means for determining each graphics state group of the plurality of graphics state groups based on the display content.

37. The apparatus of claim 27, wherein: The changed state of the at least one graphics state group is determined based on a previous draw call and a current draw call.

38. The apparatus of claim 27, wherein: The state information includes a listing of the states for each of the at least one graphics state group.

39. The apparatus of claim 27, wherein: The determination as to whether the at least one of the plurality of graphics state groups includes a changed state is performed by a central processing unit (CPU).

40. A computer-readable medium storing computer-executable code for graphics processing, comprising code for performing the following operations: determining a state of each graphics state group in a plurality of graphics state groups; determining whether at least one graphics state group of the plurality of graphics state groups includes a changed state; as well as transmitting state information for the at least one graphics state group of the plurality of graphics state groups when the at least one graphics state group includes a changed state, wherein the state information includes information about the state of the at least one graphics state group, Also included is code for: determining whether one or more of the plurality of graphics state groups includes an unchanged state; and When the one or more graphics state groups include unchanged state, copying the state of each of the one or more graphics state groups in the plurality of graphics state groups from a previous draw call to a current draw call, wherein the state of each of the one or more graphics state groups including the unchanged state is copied by a command processor of a graphics processing unit (GPU) during a visibility pass.

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