Monitoring circuit, integrated circuit and monitoring protection method thereof

Abstract

The application provides a monitoring circuit, an integrated circuit and a monitoring protection method thereof. The monitoring circuit comprises a quieting filter, a voltage sensor and a latch. The quieting filter is configured to absorb energy of a first voltage signal terminal and a second voltage signal terminal. The voltage sensor is configured to detect a voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the quieting filter absorbs the energy of the first voltage signal terminal and the second voltage signal terminal, and output an adjustment signal to the latch when the voltage fluctuation meets a set condition. The latch is configured to output a first logic state at an output end after receiving the adjustment signal, so as to determine that an electrostatic discharge event occurs. The monitoring circuit of the application monitors the electrostatic discharge event by identifying the change of the power supply voltage, and then triggers a protection mechanism to protect the integrated circuit, thereby avoiding damage to the integrated circuit caused by the electrostatic discharge event.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more specifically, to a monitoring circuit, an integrated circuit, and a monitoring and protection method thereof. Background Technology

[0002] ESD (Electrostatic Discharge) is a sudden, transient current flowing between two objects at different potentials. In solid-state electronic products such as integrated circuits, ESD events are a serious problem. Integrated circuits are manufactured using semiconductor materials, typically silicon, which can suffer permanent damage when subjected to the high voltages caused by ESD events.

[0003] During the manufacturing process of integrated circuits, ESD events may occur. After an ESD event occurs, the voltage applied to the integrated circuit can easily reach more than 5,000 volts, which is enough to damage many integrated circuits. In actual production, once an ESD event occurs, it will lead to the damage of integrated circuits. Summary of the Invention

[0004] This application addresses the shortcomings of existing methods by proposing a monitoring circuit, integrated circuit, and monitoring and protection method thereof for monitoring ESD events, thereby solving the technical problem of integrated circuit damage caused by ESD events in the prior art.

[0005] In a first aspect, this application provides a monitoring circuit, including: a noise filter, a voltage sensor, and a latch;

[0006] The noise reduction filter is connected to the first voltage signal terminal and the second voltage signal terminal respectively, and is used to absorb the energy of the first voltage signal terminal and the second voltage signal terminal.

[0007] The voltage sensor is used to detect the voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the noise filter absorbs the energy of the first voltage signal terminal and the second voltage signal terminal. When the voltage fluctuation meets the set conditions, it outputs an adjustment signal to the latch.

[0008] The latch is configured to output a first logic state upon receiving the adjustment signal, in order to determine that an electrostatic discharge event has occurred.

[0009] Optionally, a reset module and a current limiting module may also be included;

[0010] The first voltage corresponding to the first voltage signal terminal is a high-level voltage, and the second voltage corresponding to the second voltage signal terminal is a low-level voltage;

[0011] The reset module is used to control the output terminal of the latch to output a second logic state according to the reset signal during the reset phase. The second logic state is the opposite of the first logic state.

[0012] The current limiting module is used to block the current flowing from the second voltage signal terminal to the first voltage signal terminal when an electrostatic discharge event occurs, and to generate a monitoring signal based on the output of the latch.

[0013] Optionally, if the voltage fluctuation satisfies the condition that the voltage difference between the first voltage and the second voltage increases and is within a first preset range, the voltage sensor outputs an adjustment signal to the latch, and the latch is configured to change its output from a second logic state to a first logic state after receiving the adjustment signal.

[0014] If the voltage difference between the first voltage and the second voltage decreases and falls within a second preset range, and the latch's current output is in the first logic state, the latch is further configured to maintain the first logic state at its output; and,

[0015] If the voltage difference between the first voltage and the second voltage decreases and falls within a third preset range, the latch is in a non-operating state, and the latch is also configured to have its output in a floating state or to output a negative potential signal to determine that an electrostatic discharge event has occurred.

[0016] Optionally, the noise suppression filter includes: a first resistor, a second resistor, and a first capacitor;

[0017] The first end of the first resistor is connected to the first voltage signal terminal, and the second end of the first resistor is connected to the first end of the first capacitor.

[0018] The first end of the second resistor is connected to the second voltage signal terminal, and the second end of the second resistor is connected to the second terminal of the first capacitor;

[0019] The voltage sensor includes: a second capacitor, a third resistor, and a first transistor;

[0020] The first terminal of the second capacitor is connected to the second terminal of the first resistor, and the second terminal of the second capacitor is connected to the first terminal of the third resistor and the gate of the first transistor, respectively.

[0021] The second end of the third resistor is connected to the second end of the second resistor;

[0022] The first terminal of the first transistor is connected to the second terminal of the third resistor, and the second terminal of the first transistor is connected to the input terminal of the latch.

[0023] Optionally, the latch includes: a second transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0024] The gate of the second transistor is connected to the input terminal of the latch, the first terminal of the second transistor is connected to the first terminal of the noise filter, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, and the output terminal of the latch.

[0025] The gate of the third transistor is connected to the input terminal of the latch, and the first terminal of the third transistor is connected to the second terminal of the noise reduction filter;

[0026] The first terminal of the fourth transistor is connected to the first terminal of the noise reduction filter, and the second terminal of the fourth transistor is connected to the input terminal of the latch and the second terminal of the fifth transistor;

[0027] The first terminal of the fifth transistor is connected to the second terminal of the noise reduction filter.

[0028] Optionally, the current limiting module includes: a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor;

[0029] The gate of the sixth transistor is connected to the output terminal of the latch, the first terminal of the sixth transistor is connected to the first terminal of the noise suppression filter, and the second terminal of the sixth transistor is connected to the second terminal of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor, respectively.

[0030] The gate of the seventh transistor is connected to the output terminal of the latch, and the first terminal of the seventh transistor is connected to the second terminal of the noise reduction filter.

[0031] The first terminal of the eighth transistor is connected to the first terminal of the noise reduction filter, and the second terminal of the eighth transistor is connected to the second terminal of the ninth transistor and the output terminal of the monitoring signal, respectively.

[0032] The first terminal of the ninth transistor is connected to the second terminal of the noise reduction filter.

[0033] The reset module includes a tenth transistor;

[0034] The gate of the tenth transistor is connected to a reset signal, the first terminal of the tenth transistor is connected to the second terminal of the noise filter, and the second terminal of the tenth transistor is connected to the output terminal of the latch, which is used to adjust the output terminal of the latch according to the reset signal.

[0035] Optionally, the monitoring circuit further includes a critical condition monitoring circuit, used to filter the first voltage and the second voltage when the voltage fluctuation only reduces the voltage difference between the first voltage signal and the second voltage signal, and control the logic state of the monitoring signal to a first logic state based on the voltage difference between the first voltage signal and the filtered first voltage.

[0036] Optionally, the critical condition monitoring circuit includes a third capacitor, a fourth resistor, and at least an eleventh transistor;

[0037] The first end of the fourth resistor is connected to the first voltage signal terminal, and the second end of the fourth resistor is connected to the first end of the third capacitor and the first end of the eleventh transistor.

[0038] The second terminal of the third capacitor is connected to the second voltage signal terminal;

[0039] The gate of the eleventh transistor is connected to the first voltage signal terminal, and the second terminal of the eleventh transistor is connected to the output terminal of the monitoring signal.

[0040] In a second aspect, embodiments of this application provide an integrated circuit including multiple monitoring circuits as described in the first aspect, as well as a register, logic circuit, and power-on reset circuit.

[0041] The register is used to output multiple reference signals to the logic circuit according to the monitoring level;

[0042] The logic circuit is used to receive multiple monitoring signals output by the multiple monitoring circuits, and output control signals to the power-on reset circuit according to the monitoring signals and the reference signals;

[0043] The power-on reset circuit is used to power-on reset the integrated circuit according to the control signal, so as to release the charge accumulated in the integrated circuit.

[0044] Optionally, in the plurality of monitoring circuits, each voltage sensor includes a first transistor, and the first transistors included in each voltage sensor have different turn-on voltages. The plurality of monitoring circuits also include a critical condition monitoring circuit, which includes a third capacitor, a fourth resistor, and a plurality of eleventh transistors.

[0045] The first end of the fourth resistor is connected to the first voltage signal terminal, and the second end of the fourth resistor is connected to the first end of the third capacitor and the first end of the plurality of eleventh transistors;

[0046] The second terminal of the third capacitor is connected to the second voltage signal terminal;

[0047] The gates of the plurality of eleventh transistors are connected to the first voltage signal terminal.

[0048] The multiple eleventh transistors have different turn-on voltages, and the second terminals of the multiple eleventh transistors with different turn-on voltages are connected to the output terminals of the monitoring signals in a one-to-one correspondence with the turn-on voltages of the first transistors included in the monitoring circuit.

[0049] In a third aspect, embodiments of this application provide a monitoring and protection method for an integrated circuit as described in the first aspect, used to monitor electrostatic discharge events and release charge based on the monitoring results, including:

[0050] The monitoring circuit outputs a monitoring signal based on the voltage fluctuations of the first voltage and the second voltage;

[0051] The register outputs multiple reference signals according to the monitoring level, and the logic circuit outputs control signals according to the monitoring signals and the reference signals.

[0052] The power-on reset circuit performs a power-on reset on the integrated circuit according to the control signal to release the charge accumulated in the integrated circuit.

[0053] Optionally, the monitoring circuit outputs a monitoring signal based on the voltage fluctuations of the first voltage and the second voltage, including:

[0054] The noise reduction filter absorbs energy from the first voltage signal terminal and the second voltage signal terminal;

[0055] The voltage sensor detects the voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal. When the voltage fluctuation meets the set conditions, it outputs an adjustment signal to the latch.

[0056] After receiving the adjustment signal, the latch outputs a first logic state to determine that an electrostatic discharge event has occurred.

[0057] When an electrostatic discharge event occurs, the current limiting module blocks the current flowing from the second voltage signal terminal to the first voltage signal terminal and generates a monitoring signal based on the output of the latch.

[0058] The beneficial technical effects of the technical solutions provided in this application include:

[0059] The monitoring circuit provided in this application embodiment absorbs energy from the first and second voltage signal terminals through a noise filter. After the voltage sensor absorbs energy from the first and second voltage signal terminals through the noise filter, it detects the voltage fluctuation between the first and second voltage signal terminals. When the voltage fluctuation meets a set condition, it outputs an adjustment signal to a latch. The latch is configured to output a first logic state upon receiving the adjustment signal to determine that an electrostatic discharge (ESD) event has occurred in the integrated circuit. Upon determining the ESD event, it can trigger the ESD protection mechanism of the integrated circuit, thereby preventing damage to the integrated circuit. Furthermore, the monitoring circuit provided in this application embodiment can identify ESD events of different degrees by changing the sensitivity of the voltage sensor, thereby triggering the ESD protection mechanism of the integrated circuit. This achieves the monitoring, graded control, and release of ESD events, thus protecting the integrated circuit.

[0060] The above description is merely an overview of the technical solutions of the embodiments of this application. In order to better understand the technical means of the embodiments of this application and to implement them in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the embodiments of this application more obvious and understandable, specific implementation methods of the embodiments of this application are described below. Attached Figure Description

[0061] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0062] Figure 1 A schematic diagram of a monitoring circuit provided in an embodiment of this application;

[0063] Figure 2 Another monitoring circuit schematic diagram provided in the embodiments of this application;

[0064] Figure 3 This is a waveform diagram of a positive VDD ESD event.

[0065] Figure 4 This is a waveform diagram of a negative VDD ESD event.

[0066] Figure 5 This is a power waveform diagram of a positive VSS ESD event;

[0067] Figure 6 This is a power waveform diagram of a negative VSS ESD event;

[0068] Figure 7 A schematic diagram of the parasitic PN junction principle of a monitoring circuit provided in this application embodiment;

[0069] Figure 8Here is a waveform diagram of another positive VDD ESD event;

[0070] Figure 9 Here is a waveform diagram of another negative VDD ESD event;

[0071] Figure 10 This is another positive VSS ESD event power waveform diagram;

[0072] Figure 11 Here is a waveform diagram of another negative VSS ESD event;

[0073] Figure 12 A schematic diagram of a monitoring circuit including a critical condition monitoring circuit is provided for an embodiment of this application;

[0074] Figure 13 A schematic diagram of an integrated circuit structure provided in an embodiment of this application;

[0075] Figure 14 A schematic diagram of a critical condition monitoring circuit provided in an embodiment of this application;

[0076] Figure 15 This is a flowchart of a monitoring method provided in an embodiment of this application. Detailed Implementation

[0077] This application is described in detail below. Examples of embodiments of this application are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar components or components having the same or similar functions throughout. Furthermore, detailed descriptions of known technologies that are unnecessary for the features of this application are omitted. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0078] It will be understood by those skilled in the art that, unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that terms such as those defined in general dictionaries should be understood to have the same meaning as in the context of the prior art, and should not be interpreted in an idealized or overly formal sense unless specifically defined as herein.

[0079] Those skilled in the art will understand that, unless specifically stated otherwise, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the term “comprising” as used in this application’s specification means the presence of the stated features, integers, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. It should be understood that when we say an element is “connected” to another element, it can be directly connected to the other element, or there may be intermediate elements. Furthermore, the term “connected” as used herein can include wireless connections. The term “and / or” as used herein includes all or any units and all combinations of one or more associated listed items.

[0080] Static electricity is a natural phenomenon that exists objectively and can be generated in various ways, such as through contact, friction, and induction between electrical appliances. ESD (electrostatic discharge) damage to electronic products can be categorized into two types: sudden damage and latent damage. Sudden damage refers to severe damage to components, resulting in loss of function. This type of damage is usually detected during quality inspections in the production process, thus primarily incurring rework and repair costs for the factory. Latent damage, on the other hand, refers to partial damage to components, where function is not yet lost and cannot be detected during production inspections. However, it can cause instability during use, leading to intermittent malfunctions and posing a greater threat to product quality. Of these two types of damage, latent failures account for 90%, while sudden failures account for only 10%. In other words, 90% of electrostatic damage is undetectable and only becomes apparent when the device reaches the user. For example, the vast majority of problems with mobile phones, such as frequent crashes and automatic shutdowns, are related to electrostatic damage.

[0081] Therefore, it is particularly important to set up ESD event monitoring circuits in the actual design of electronic devices and integrated circuits. When an ESD event is detected, the protection device can be triggered to release the generated static electricity, thereby achieving the purpose of protecting electronic devices and integrated circuits.

[0082] According to tests, when an ESD event occurs, the power supply voltage of the integrated circuit decays in a manner similar to a damped oscillation, lasting for approximately less than 1000 ns. Based on actual measured waveforms, a sinusoidal decaying waveform can be used to simulate the voltage waveform after an ESD event.

[0083] Based on this, this application proposes a monitoring circuit for monitoring ESD events occurring in integrated circuits.

[0084] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments.

[0085] like Figure 1As shown, the monitoring circuit 100 provided in this embodiment includes: a noise suppressor filter 110, a voltage sensor 120, and a latch 130; the noise suppressor filter 110 is connected to a first voltage signal terminal (corresponding to the signal terminal connected to VDD in the figure) and a second voltage signal terminal (corresponding to the signal terminal connected to VSS in the figure), respectively, for absorbing energy from the first voltage signal terminal and the second voltage signal terminal; the voltage sensor 120 is used to detect the voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal after the noise suppressor filter 110 absorbs energy from the first voltage signal terminal and the second voltage signal terminal, and when the voltage fluctuation meets the set conditions, it outputs an adjustment signal to the latch 130; the latch 130 is configured to output a first logic state at its output terminal out0 after receiving the adjustment signal, to determine that an ESD event has occurred.

[0086] The monitoring circuit 100 provided in this embodiment absorbs energy from the first and second voltage signal terminals through a noise filter 110. After the noise filter 110 absorbs energy from the first and second voltage signal terminals, the voltage sensor 120 detects voltage fluctuations at the first and second voltage signal terminals. When the voltage fluctuation meets a set condition, it outputs an adjustment signal to the latch 130. The latch 130 is configured to output a first logic state at its output terminal out0 upon receiving the adjustment signal, thus determining that an electrostatic discharge (ESD) event has occurred in the integrated circuit. Upon determining the ESD event, it can trigger the ESD protection mechanism of the integrated circuit, thereby preventing damage to the integrated circuit. Furthermore, the monitoring circuit 100 provided in this embodiment can identify ESD events of different degrees by changing the sensitivity of the voltage sensor 120, thereby triggering the ESD protection mechanism of the integrated circuit. This achieves the monitoring, graded control, and release of ESD events, ultimately protecting the integrated circuit.

[0087] Furthermore, such as Figure 2 As shown, the monitoring circuit 100 also includes a reset module 140 and a current limiting module 150; the first voltage corresponding to the first voltage signal terminal is a high-level voltage VDD, and the second voltage corresponding to the second voltage signal terminal is a low-level voltage VSS; the reset module 140 is used to control the output terminal out0 of the latch 130 to output a second logic state according to the reset signal reset during the reset phase, the second logic state being the opposite of the first logic state; the current limiting module 150 is used to block the current flowing from the second voltage signal terminal (the signal terminal connected to VSS) to the first voltage signal terminal (the signal terminal connected to VDD) when an ESD event occurs, and to generate a monitoring signal out according to the output of the latch 140.

[0088] Specifically, this application embodiment takes a first logic state of logic 1 and a second logic state of logic 0 as an example for explanation. That is, when the output terminal out0 of latch 130 outputs logic 1, it is considered that an electrostatic discharge event has occurred. When the output terminal out0 of latch 130 outputs logic 0, it is considered that no electrostatic discharge event has occurred.

[0089] Continue to refer to Figure 2 As shown, in one specific embodiment, the noise suppression filter 110 includes: a first resistor R1, a second resistor R2, and a first capacitor C1. The first end of the first resistor R1 is connected to a first voltage signal terminal (the signal terminal connected to VDD in the figure), and the second end of the first resistor R1 is connected to the first end of the first capacitor C1. The first end of the second resistor R2 is connected to a second voltage signal terminal (the signal terminal connected to VSS in the figure), and the second end of the second resistor R2 is connected to the second end of the first capacitor C1. The voltage sensor 120 includes a second capacitor C2, a third resistor R3, and a first transistor M1. The first end of the second capacitor C2 is connected to the second end of the first resistor R1, and the second end of the second capacitor C2 is connected to the first end of the third resistor R3 and the gate of the first transistor M1. The second end of the third resistor R3 is connected to the second end of the second resistor R2. The first end of the first transistor M1 is connected to the second end of the third resistor R3, and the second end of the first transistor M1 is connected to the input terminal in0 of the latch 130.

[0090] Specifically, the first terminal of the first transistor M1 refers to the source of the first transistor M1, and the second terminal of the first transistor M1 refers to the drain of the first transistor M1. In practical applications, the source and drain of the first transistor M1 can be interchanged, that is, the first terminal of the first transistor M1 refers to the drain of the first transistor M1, and the second terminal of the first transistor M1 refers to the source of the first transistor M1.

[0091] Those skilled in the art can set the first transistor M1 to be an N-type transistor or a P-type transistor according to the actual situation. This application does not impose any restrictions. The specific embodiment of this application takes the first transistor M1 as an N-type transistor as an example for illustration. Optionally, the size of the first transistor M1 is set to 0.2um / 0.1um, that is, the width-to-length ratio of the first transistor M1 is set to 0.2 micrometers to 0.1 micrometers.

[0092] In one specific embodiment, assuming a 1.0V power supply (used to provide a high-level voltage VDD to the integrated circuit) has four internal leads connected to the die pins, the loop between the integrated circuit and the power supply has a 0.5nH (nanohenry) inductance, and the connection between the 1.0V power supply and ground is assumed to be a 1nF (nanofa) capacitor, the resonant frequency of the LC network is estimated to be approximately 200MHz to 300MHz. If an ESD event occurs, energy in the 200MHz to 300MHz frequency range is most easily detected by the monitoring circuit 100. Therefore, in this embodiment, the bandwidth of the squelch filter 110 is set to the 300MHz range, so that power supply noise with frequency components higher than this bandwidth will be filtered out.

[0093] Specifically, such as Figure 2 As shown, the resistance values ​​of the first resistor R1 and the second resistor R2 are set to 50 ohms, the capacitance value of the first capacitor C1 is 4 pF, the capacitance value of the second capacitor C2 is 2 pF, and the resistance value of the third resistor R3 is 10 kΩ. This configuration enables the bandwidth of the noise filter 110 to be on the order of 300 MHz, which can filter out noise with a frequency higher than 300 MHz, thereby giving the monitoring circuit 100 a better monitoring effect.

[0094] It should be noted that those skilled in the art can set the bandwidth of the noise filter 110 according to actual needs, so that the monitoring circuit 100 can have a better monitoring effect.

[0095] In one specific embodiment, reference continues to... Figure 2 As shown, if the voltage fluctuation satisfies the condition that the voltage difference between the first voltage and the second voltage increases and is within a first preset range, the voltage sensor 120 outputs an adjustment signal to the latch 130. The latch 130 is configured to change its output terminal out0 from the second logic state to the first logic state after receiving the adjustment signal (in this embodiment, the output terminal out0 is changed from logic 0 to logic 1 as an example). If the voltage difference between the first voltage and the second voltage decreases and is within a second preset range, and the current output terminal of the latch is in the first logic state (specifically logic 1), the latch is also configured to maintain the output terminal out0 in the first logic state (specifically logic 1). And if the voltage difference between the first voltage and the second voltage decreases and is within a third preset range, the latch 130 is in a non-working state, and the latch 130 is also configured to have its output terminal out0 in a floating state or output a negative potential signal to determine that an electrostatic discharge event has occurred (at this time, it is considered that a relatively serious ESD event has occurred).

[0096] In specific implementation, refer to Figure 2As shown, latch 130 includes a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5. The gate of the second transistor M2 is connected to the input terminal in0 of latch 130 (i.e., connected to the second terminal of the first transistor M1). The first terminal of the second transistor M2 is connected to the first terminal of noise filter 110 (referring to the first terminal of the first capacitor C1 and the second terminal of the first resistor R1). The second terminal of the second transistor M2 is connected to the second terminal of the third transistor M3, the gate of the fourth transistor M4, the gate of the fifth transistor M5, and the output terminal out0 of latch 130. The gate of the third transistor M3 is connected to the input terminal in0 of latch 130. The first terminal of the third transistor M3 is connected to the second terminal of noise filter 110 (referring to the second terminal of the first capacitor C1 and the second terminal of the second resistor R2). The first terminal of the fourth transistor M4 is connected to the first terminal of noise filter 110. The second terminal of the fourth transistor M4 is connected to the input terminal in0 of latch 130 and the second terminal of the fifth transistor M5. The first terminal of the fifth transistor M5 is connected to the second terminal of noise filter 110.

[0097] Optionally, in specific implementation, the second transistor M2 and the fourth transistor M4 are set to P-type transistors, and the third transistor M3 and the fifth transistor M5 are set to N-type transistors, so that the latch 130 can maintain the logic state of the input terminal in0 and the logic state of the output terminal out0 during normal operation, and make the two logic states always opposite. For example, when the input terminal in0 is logic 1, the output terminal out0 is logic 0, and when the output terminal out0 is logic 1, the input terminal in0 is logic 0.

[0098] like Figure 2 As shown, the voltage difference between the first voltage and the second voltage within the first preset range means that as long as the voltage difference value is within the first preset range, the first transistor M1 can be turned on. After the first transistor M1 is turned on, the logic state of the latch input terminal in0 changes from logic 1 to logic 0. That is, if the voltage difference value exceeds the first preset range, the voltage difference value cannot turn on the first transistor M1. The voltage difference between the first voltage VDD and the second voltage VSS within the second preset range means that the voltage difference range that makes the gate voltage of the first transistor M1 in the voltage sensor 120 less than its gate turn-on voltage means that the first transistor M1 cannot be turned on. The voltage difference between the first voltage VDD and the second voltage VSS within the third preset range means that the voltage range that makes the latch 130 unable to work normally means that the first voltage VDD is within the third preset range.

[0099] In specific implementation, please continue to refer to Figure 2As shown, the current limiting module 150 includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9. The gate of the sixth transistor M6 is connected to the output terminal out0 of the latch 130, the first terminal of the sixth transistor M6 is connected to the first terminal of the noise filter 110, and the second terminal of the sixth transistor M6 is connected to the second terminal of the seventh transistor M7, the gate of the eighth transistor M8, and the gate of the ninth transistor M9, respectively. The gate of the seventh transistor M7 is connected to the output terminal out0 of the latch 130, and the first terminal of the seventh transistor M7 is connected to the second terminal of the noise filter 110. The first terminal of the eighth transistor M8 is connected to the first terminal of the noise filter 110, and the second terminal of the eighth transistor M8 is connected to the second terminal of the ninth transistor M9 and the output terminal out of the monitoring signal, respectively. The first terminal of the ninth transistor M9 is connected to the second terminal of the noise filter 110. The reset module 140 includes a tenth transistor M10; the gate of the tenth transistor M10 is connected to the reset signal reset, the first terminal of the tenth transistor M10 is connected to the second terminal of the noise filter 110, and the second terminal of the tenth transistor M10 is connected to the output terminal out0 of the latch 130 (i.e., connected to the gate of the sixth transistor M6 and the gate of the seventh transistor M7).

[0100] Specifically, the sixth transistor M6 and the eighth transistor M8 can be configured as P-type transistors, and the seventh transistor M7 and the ninth transistor M9 can be configured as N-type transistors. This allows the current limiting module 150 to prevent current from flowing from the second voltage signal terminal (the signal terminal connected to VSS) to the first voltage signal terminal (the signal terminal connected to VDD) when an ESD event occurs. The tenth transistor M10 can be configured as an N-type transistor or a P-type transistor depending on the actual situation. This application does not impose any restrictions. This document describes the tenth transistor M10 as an N-type transistor.

[0101] The working principle of the monitoring circuit provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0102] This application uses a 1V power supply as an example for description. In this application embodiment, the first voltage is a high-level voltage VDD, and the second voltage is a low-level voltage VSS. The specific voltage value of the first voltage is 1V, and the specific voltage value of the second voltage is 0V.

[0103] After an ESD event occurs, the first voltage may initially oscillate in the positive direction (i.e., oscillate in the direction of increasing voltage) or initially oscillate in the negative direction (i.e., oscillate in the direction of decreasing voltage). Similarly, the second voltage may initially oscillate in the positive direction or initially oscillate in the negative direction. Therefore, there is a possibility... Figure 3 , Figure 4 , Figure 5 and Figure 6 Four voltage fluctuation scenarios.

[0104] Specifically, such as Figure 3 As shown, after an ESD event occurs, the first voltage VDD oscillates in the positive direction initially, which can... Figure 3 Consider it as a positive VDD ESD event power supply waveform; such as Figure 4 As shown, after an ESD event occurs, the first voltage VDD initially oscillates in the negative direction, which can... Figure 4 Consider it as a negative VDD ESD event power supply waveform; such as Figure 5 As shown, after an ESD event occurs, the second voltage VSS first oscillates in the positive direction, which can... Figure 5 Consider it as a positive VSS ESD event power waveform; such as Figure 6 As shown, after an ESD event occurs, the second voltage VSS first oscillates in the negative direction, which can... Figure 6 View it as a negative VSS ESD event power waveform.

[0105] by Figure 3 Taking the positive VDD ESD event power supply waveform as an example, during the entire decay oscillation process after the ESD event, there are stages where the first voltage VDD fluctuates positively relative to the second voltage VSS, causing the voltage difference between the two to increase, and there are also stages where the first voltage VDD fluctuates negatively relative to the second voltage VSS, causing the voltage difference between the two to decrease. Finally, the decay process ends, the first voltage VDD stabilizes at 1V before the ESD event, and the second voltage VSS stabilizes at 0V before the ESD event.

[0106] like Figure 2 and Figure 3 As shown, the first occurrence is a positive fluctuation of the first voltage VDD relative to the second voltage VSS, which is called the first positive fluctuation of the first voltage VDD relative to the second voltage VSS. This change will cause the voltage difference between the first voltage VDD and the second voltage VSS to increase. The rise in the value of the first voltage VDD affects the gate of the first transistor M1 through the second capacitor C2, and the gate potential of the first transistor M1 rises accordingly. When the gate voltage of the first transistor M1 rises to a level that can turn on the first transistor M1, the state of the latch 130 will change, causing the input terminal in0 of the latch 130 to change from the initial logic 1 to logic 0, and then causing the output terminal out0 of the latch 130 to change from the initial logic 0 to logic 1.

[0107] Next, the first voltage VDD undergoes its first negative fluctuation relative to the second voltage VSS, reducing the voltage difference between VDD and VSS. The decrease in the value of the first voltage VDD also causes the gate potential of the first transistor M1 to decrease through the second capacitor C2. The voltage difference between the gate potential of the first transistor M1 and the second voltage VSS will decrease, so the first transistor M1 will eventually be turned off. Thus, the input terminal in0 of latch 130 maintains a logic 0 state, and the output terminal out0 of latch 130 maintains a logic 1 state. Because the negative fluctuation of the first voltage VDD relative to the second voltage VSS reduces the voltage difference between them, although the output terminal out0 of latch 130 maintains a logic 1 state, the potential of the output terminal out0 of latch 130 decreases along with the first voltage VDD. Therefore, as long as the voltage difference between the first voltage VDD and the second voltage VSS does not decrease to the point that latch 130 cannot work (i.e., the gate-source voltage difference of the transistor in latch 130 is too small to conduct), the input terminal in0 of latch 130 will maintain a logic 0 state, and the output terminal out0 of latch 130 will maintain a logic 1 state.

[0108] If the voltage difference between the first voltage VDD and the second voltage VSS continues to decrease to the point that the latch 130 cannot work, then the transistors in the latch 130 will all enter the cut-off state, and the input terminal in0 and the output terminal out0 of the latch 130 will be in a floating state, both of which will be close to the second voltage VSS in terms of potential.

[0109] If the first voltage VDD continues to fluctuate negatively relative to the second voltage VSS, and the value of the first voltage VDD falls below the value of the second voltage VSS, this will cause a parasitic PN junction to conduct between the transistors in latch 130, such as... Figure 7 As shown, in this case, the input terminal in0 and the output terminal out0 of latch 130 will no longer be in a floating state. The potentials of input terminal in0 and output terminal out0 will be determined by the PN junction voltage divider circuit, so the potentials at both points will decrease to negative. Figure 7 As shown, the PN junction of the first transistor M1 is connected in parallel with the PN junction of the fifth transistor M5 and then in series with the PN junction of the fourth transistor M4 to form a path. The PN junction of the third transistor M3 is connected in parallel with the PN junction of the tenth transistor M10 and then in series with the PN junction of the second transistor M2 to form another path.

[0110] Subsequently, the first voltage VDD will fluctuate positively again relative to the second voltage VSS, which is called the second positive fluctuation of the first voltage VDD relative to the second voltage VSS. The value of the first voltage VDD will rise again, gradually closing this parasitic path of the PN junction. The potentials of the input terminal in0 and the output terminal out0 of latch 130 will rise from negative potentials to approach the second voltage VSS. The value of the first voltage VDD continues to rise, and latch 130 will resume its working state. At the same time, the first transistor M1 may also be turned on again, thus giving latch 130 a definite logic state. Specifically, this means that the input terminal in0 and the output terminal out0 of latch 130 have a definite logic state. However, if... Figure 3 As shown, the first voltage exhibits a decaying oscillation process. The positive fluctuation amplitude of the first voltage VDD relative to the second voltage VSS in the second time will not be as large as the first time. Although the gate potential of the first transistor M1 will increase as the value of the first voltage VDD increases again, the first transistor M1 may not be able to be turned on this time. At this time, the potentials of the input terminal in0 and the output terminal out0 of the latch 130 depend entirely on the characteristics of the latch 120 in the process of recovering from a non-working state to a working state.

[0111] It should be noted that during the process of voltage difference fluctuation between the first voltage VDD and the second voltage VSS after an ESD event, once the voltage difference decreases to the point where latch 130 cannot function properly, a very serious ESD event can be considered to have occurred. Therefore, by selecting appropriate second transistor M2 and appropriate fourth transistor M4, during the second positive fluctuation of the first voltage VDD relative to the second voltage VSS, the charging speed of the output terminal out0 of latch 130 is faster than that of the input terminal in0 of latch 130. When latch 130 recovers from the state where the voltage difference between the first voltage VDD and the second voltage VSS does not meet the operating state of latch 130 to the state where the operating state of latch 130 is met, the input terminal in0 of latch 130 can be set to logic 0 and the output terminal out0 of latch 130 can be set to logic 1.

[0112] Specifically, such as Figure 2As shown, the state of the current limiting module 150 changes with the state of the latch 130. Specifically, the logic state of the monitoring signal 'out' changes according to the logic state of the output terminal 'out0' of the latch 130. When the output terminal 'out0' is logic 1, the monitoring signal 'out' is also logic 1; when the output terminal 'out0' is logic 0, the monitoring signal 'out' is also logic 0, thus triggering the electrostatic discharge (ESD) protection mechanism of the integrated circuit. It should be noted that the transistor in the current limiting module 150 can limit the current direction when an ESD event occurs, preventing current from flowing from the second voltage VSS to the first voltage VDD when an ESD event occurs.

[0113] It should be noted that there are various types of electrostatic discharge (ESD) protection for integrated circuits, and those skilled in the art can select appropriate ESD protection mechanisms according to actual conditions. This embodiment does not impose any limitations.

[0114] like Figure 2 As shown, the reset module 140 is used to initialize the output terminal out0 of latch 130 from logic 1 to logic 0 according to the reset signal reset after the ESD event ends, so that latch 130 returns to its initial state and monitoring circuit 100 can continue to monitor ESD events. The reset signal reset is used in a manner similar to the prior art. Since it does not involve the improvement points of this application, it will not be described in detail here.

[0115] It should be noted that, as Figure 3As shown, during the first positive fluctuation, when the voltage difference between the first voltage VDD and the second voltage VSS increases and falls within the first preset range, the first transistor M1 turns on, causing the output terminal out0 to change from the initial logic 0 to logic 1, thus confirming that an electrostatic discharge event has occurred. Then, during the first negative fluctuation, when the voltage difference between the first voltage VDD and the second voltage VSS decreases and falls within the second preset range, the first transistor M1 is turned off. At this time, the output terminal out0 of latch 130 maintains logic 1, confirming that an electrostatic discharge event has occurred. When the voltage difference between the first voltage VDD and the second voltage VSS continues to decrease to the point that latch 130 cannot operate, it is considered that the voltage difference has fallen within the third preset range, and at this time, the output terminal out0 of latch 130 will be in a state of... The system is in a floating state to determine if a serious ESD event has occurred. Furthermore, the third preset range in this application also includes the voltage difference range when the first voltage VDD is lower than the second voltage VSS. At this time, the output terminal out0 of latch 130 outputs a negative potential signal to determine if a serious ESD event has occurred. Then, during the second positive fluctuation process, if the voltage difference between the first voltage VDD and the second voltage VSS cannot fall within the first preset range, but only within the second and third preset ranges, when the voltage difference falls within the second preset range, latch 130 returns to its working state. Latch 130 is capable of setting its own state without relying on voltage sensor 120, setting input terminal in0 to logic 0 and output terminal out0 to logic 1, thus confirming that an ESD event has been detected.

[0116] Similarly, for Figure 4 , Figure 5 , Figure 6 The ESD event of the waveform shown has both a phase where the voltage difference increases and a phase where the voltage difference decreases during the entire attenuation process. The working principle of the monitoring circuit 100 is similar to that described above, so it will not be repeated here.

[0117] During an ESD event, the voltage fluctuations of the first voltage VDD and the second voltage VSS are not entirely as described. Figures 3 to 6 As shown, the entire attenuation process resembles a sine wave, with both phases of increasing and decreasing voltage difference. The voltage fluctuations of the first voltage VDD and the second voltage VSS, along with the very rapid attenuation process, exhibit characteristics such as... Figures 8-11 The four voltage fluctuation scenarios shown are as follows: Figure 8 The image shows the power supply waveform of a positive VDD ESD event with a very rapid decay process; as shown... Figure 9 The image shows the power supply waveform of a negative VDD ESD event with a very rapid decay process; as shown... Figure 10The figure shows the positive VSS ESD event power waveform with a very rapid decay process; as shown. Figure 11 The diagram shows the negative VSS ESD event power waveform, which decays very rapidly.

[0118] for Figure 9 as well as Figure 10 The ESD event power waveform shown is because... Figure 10 The first positive fluctuation in and Figure 9 During the first negative fluctuation, the voltage difference between the first voltage VDD and the second voltage VSS is always less than the gate turn-on voltage of the first transistor M1. That is, the voltage difference between the first voltage VDD and the second voltage VSS is within a second preset range or a third preset range. If the voltage difference between the first voltage VDD and the second voltage VSS fluctuates only within the second preset range... Figure 2 The monitoring circuit 100 shown cannot detect... Figure 9 and Figure 10 Both waveforms respond effectively.

[0119] In one specific embodiment, such as Figure 12 As shown, the monitoring circuit 100 also includes a critical condition monitoring circuit 160, which is used to filter the first voltage VDD and the second voltage VSS when the voltage fluctuation only reduces the voltage difference between the first voltage VDD and the second voltage VSS, and control the logic state of the monitoring signal out to the first logic state (specifically logic 1) according to the voltage difference between the first voltage VDD and the filtered first voltage VDDfilter; the second voltage in this embodiment is the common ground voltage.

[0120] In specific implementation, the critical condition monitoring circuit includes a third capacitor C3, a fourth resistor R4, and at least one eleventh transistor M11; the first end of the fourth resistor R4 is connected to the first voltage signal terminal (VDD signal terminal), the second end of the fourth resistor R4 is connected to the first end of the third capacitor C3 and the first end of the eleventh transistor M11; the second end of the third capacitor C3 is connected to the second voltage signal terminal (VSS signal terminal); the gate of the eleventh transistor M11 is connected to the first voltage signal terminal (VDD signal terminal), and the second end of the eleventh transistor M11 is connected to the output terminal out of the monitoring signal.

[0121] Those skilled in the art can configure the eleventh transistor M11 as a P-type transistor or an N-type transistor according to the actual situation. This article uses the eleventh transistor M11 as a P-type transistor for illustration. Optionally, the eleventh transistor M11 can be configured to have the same sensitivity as the first transistor M1.

[0122] It should be noted that the above-mentioned same sensitivity means that when the first transistor M1 and the eleventh transistor M11 are turned on, the change in the first voltage VDD or the second voltage VSS is the same.

[0123] Similar to setting the bandwidth of the noise filter 110, the bandwidth of the RC circuit (composed of the fourth resistor R4 and the third capacitor C3) in the critical condition monitoring circuit 160 can be adjusted by setting the capacitance of the third capacitor C3 and the resistance of the fourth resistor R4, so that the critical condition monitoring circuit 160 has a better monitoring effect. For example, assuming that the resonant frequency of the RC circuit is about 200 to 300 MHz, the capacitance of the third capacitor C3 can be set to 4 pF (picofarads) and the resistance of the fourth resistor R4 can be set to 100 Kohm (kiloohms).

[0124] for Figure 9 The waveform shows that the first voltage VDD undergoes its first negative fluctuation relative to the second voltage VSS, reducing the voltage difference between them. The first voltage VDD passes through a low-pass filter network consisting of the fourth resistor R4 and the third capacitor C3 to obtain a filtered first voltage VDD_filter. If the voltage difference between the first voltage VDD and the filtered first voltage VDD_filter can activate the eleventh transistor M11, then the output of the monitoring signal out will be charged to a high potential, resulting in a logic 1 output. Figure 10 The waveform shows that the second voltage VSS makes the first positive fluctuation relative to the first voltage VDD, and the voltage difference between the first voltage VDD and the second voltage VSS decreases. The second voltage VSS affects the filtered first voltage VDD_filter through the high-pass filter network of the third capacitor C3 and the fourth resistor R4. If the voltage difference between the first voltage VDD and the filtered first voltage VDD_filter can turn on the eleventh transistor M11, then the output terminal of the monitoring signal out will be charged to a high potential, and the output logic 1 state will be output.

[0125] Based on the same inventive concept, embodiments of this application propose an integrated circuit, such as... Figure 13 As shown, the system includes multiple monitoring circuits as described above (the figure shows four monitoring circuits: the first monitoring circuit 101, the second monitoring circuit 102, the third monitoring circuit 103, and the fourth monitoring circuit 104), and also includes a register 200, a logic circuit 300, and a power-on reset circuit 400; the register 200 is used to output multiple reference signals (such as...) according to the monitoring level. Figure 13 The first reference signal register1, the second reference signal register2, and the third reference signal register3 are shown in the diagram. The logic circuit 300 receives multiple monitoring signals (such as...) output from multiple monitoring circuits. Figure 13The monitoring circuit 101 corresponds to the first monitoring signal bit0, the second monitoring circuit 102 corresponds to the second monitoring signal bit1, the third monitoring circuit 103 corresponds to the third monitoring signal bit2, and the fourth monitoring circuit 104 corresponds to the fourth monitoring signal bit3. Based on the monitoring signals and the reference signal, the monitoring circuit 101 outputs a control signal to the power-on reset circuit 400. The power-on reset circuit 400 is used to power-on reset the integrated circuit according to the control signal to release the charge accumulated in the integrated circuit.

[0126] It should be noted that the specific circuit diagrams of the first monitoring circuit 101, the second monitoring circuit 102, the third monitoring circuit 103, and the fourth monitoring circuit 104 are as follows: Figure 2 As shown, for the first monitoring circuit 101, Figure 2 The monitoring signal output terminal 'out' is denoted as the first monitoring signal output terminal 'out1'. The first monitoring signal output terminal 'out1' is connected to... Figure 13 The logic circuit 300 includes an AND gate at its top, and the first monitoring signal output terminal out1 outputs the first monitoring signal bit0; for the second monitoring circuit 102, Figure 2 The monitoring signal output terminal 'out' is denoted as the second monitoring signal output terminal 'out2'. The second monitoring signal output terminal 'out2' is connected to... Figure 13 The intermediate logic circuit 300 includes an AND gate in the middle, and the second monitoring signal output terminal out2 outputs the second monitoring signal bit1; for the third monitoring circuit 103, Figure 2 The monitoring signal output terminal OUT is denoted as the third monitoring signal output terminal OUT3. The third monitoring signal output terminal OUT3 is connected to... Figure 13 The logic circuit 300 includes an AND gate at its bottom, and the third monitoring signal output terminal out3 outputs the third monitoring signal bit2; for the fourth monitoring circuit 104, Figure 2 The monitoring signal output terminal OUT is denoted as the fourth monitoring signal output terminal OUT4. The fourth monitoring signal output terminal OUT4 is connected to... Figure 13 The logic circuit 300 includes a bottom OR gate connection, and the fourth monitoring signal output terminal out4 outputs the fourth monitoring signal bit3. The logic states of the first monitoring signal bit0, the second monitoring signal bit1, the third monitoring signal bit2 and the fourth monitoring signal bit3 have been discussed in detail in the monitoring circuit section above, and will not be repeated here.

[0127] The integrated circuit provided in this embodiment outputs multiple reference signals through register 200. The logic circuit 300 outputs control signals to the power-on reset circuit 400 based on the monitoring signals and reference signals for initialization. This allows the integrated circuit to freely select the monitoring range, achieving graded control and release of ESD events, thus protecting the integrated circuit. Simultaneously, it avoids noise interference from falsely triggering the power-on reset circuit 400, improving monitoring accuracy.

[0128] Optionally, multiple monitoring circuits (first monitoring circuit 101, second monitoring circuit 102, third monitoring circuit 103, and fourth monitoring circuit 104) share the same noise suppression filter 110 to save on circuit layout and reduce costs.

[0129] In one specific embodiment, reference Figure 13 , 14 As shown, multiple monitoring circuits (first monitoring circuit 101, second monitoring circuit 102, third monitoring circuit 103, and fourth monitoring circuit 104) include first transistors M1 with different turn-on voltages. The multiple monitoring circuits include a critical condition monitoring circuit 160, which includes a third capacitor C3, a fourth resistor R4, and multiple eleventh transistors (first eleventh transistor M11-1, second eleventh transistor M11-2, third eleventh transistor M11-3, and fourth eleventh transistor M11-4). The first terminal of the fourth resistor R4 is connected to the first voltage signal terminal (VDD signal terminal), and the second terminal of the fourth resistor R4 is connected to the first terminal of the third capacitor C3 and the first terminals of the multiple eleventh transistors. The second terminal of the third capacitor C3 is connected to the second voltage signal terminal (VSS signal terminal). The gates of the multiple eleventh transistors are connected to the first voltage signal terminal (VDD signal terminal). The multiple eleventh transistors have different turn-on voltages, and the second terminals of the multiple eleventh transistors with different turn-on voltages are connected to the output terminals of the monitoring signals according to the turn-on voltages of the first transistors included in the monitoring circuit.

[0130] For details, please refer to Figure 13 , Figure 14As shown, assuming the integrated circuit includes four different monitoring circuits (first monitoring circuit 101, second monitoring circuit 102, third monitoring circuit 103, and fourth monitoring circuit 104), the integrated critical condition monitoring circuit 170 includes four eleventh transistors (first eleventh transistor M11-1, second eleventh transistor M11-2, third eleventh transistor M11-3, and fourth eleventh transistor M11-4). Optionally, all four eleventh transistors are P-type transistors with a size of 2µm / 80nm, i.e., an aspect ratio of 2µm to 80nm. The first eleventh transistor M11-1 and the first transistor M1 in the first monitoring circuit 101 are transistors with the same sensitivity. 1. The second terminal is connected to the first monitoring signal output terminal out1; the second eleventh transistor M11-2 and the first transistor M1 in the second monitoring circuit 102 are transistors with the same sensitivity, and the second terminal of the second eleventh transistor M11-2 is connected to the second monitoring signal output terminal out2; the third eleventh transistor M11-3 and the first transistor M1 in the third monitoring circuit 103 are transistors with the same sensitivity, and the second terminal of the third eleventh transistor M11-3 is connected to the third monitoring signal output terminal out3; the fourth eleventh transistor M11-4 and the first transistor M1 in the fourth monitoring circuit 104 are transistors with the same sensitivity, and the second terminal of the fourth eleventh transistor M11-4 is connected to the fourth monitoring signal output terminal out4.

[0131] It should be noted that the above-mentioned same sensitivity means that when the first transistor M1 and the eleventh transistor M11 are turned on, the change in the first voltage VDD or the second voltage VSS is the same.

[0132] Specifically, those skilled in the art can design the turn-on voltage of the first transistor M1 in multiple monitoring circuits according to actual needs, so that the multiple monitoring circuits in the integrated circuit have different sensitivities to monitoring ESD events.

[0133] In one specific embodiment, reference Figure 13As shown, assuming the integrated circuit includes four different monitoring circuits, the turn-on voltage of the first transistor M1 included in the first monitoring circuit 101 to the fourth monitoring circuit 104 increases sequentially, that is, the first transistor M1 included in the first monitoring circuit 101 has the highest sensitivity, and the first transistor M1 included in the fourth monitoring circuit 104 has the lowest sensitivity. Specifically, assuming that the first transistor included in the first monitoring circuit 101 turns on when the first voltage VDD or the second voltage VSS fluctuates beyond 0.25V, then the first monitoring circuit 101 can monitor ESD events exceeding 0.25V. Similarly, assuming that the second transistor included in the second monitoring circuit 102 turns on when the first voltage VDD or the second voltage VSS fluctuates beyond 0.35V, then the second monitoring circuit 102 can monitor ESD events exceeding 0.35V. Assuming that the third transistor included in the third monitoring circuit 103 turns on when the first voltage VDD or the second voltage VSS fluctuates beyond 0.45V, then the third monitoring circuit 103 can monitor ESD events exceeding 0.45V. Assuming that the fourth transistor included in the fourth monitoring circuit 104 turns on when the first voltage VDD or the second voltage VSS fluctuates beyond 0.55V, then the fourth monitoring circuit 104 can monitor ESD events exceeding 0.55V.

[0134] When the monitoring circuit detects an ESD event, the output state of the corresponding monitoring signal changes from logic 0 to logic 1. When there is no ESD event or only a minor ESD event occurs, such as a voltage fluctuation of less than 0.25V for the first voltage VDD or the second voltage VSS, it can be considered that no ESD event has occurred. The output of latch 130 (out0) remains at logic 0, and the output states of all four monitoring signals (bit0-bit3) are logic 0. If a severe ESD event occurs, such as a voltage fluctuation so large that latch 130 cannot function properly, after the voltage recovers to the point where latch 130 can function normally, referring to the latch 130 setting principles described above, the output states of all four monitoring signals (bit0-bit3) will change to 1. ESD events between these two extreme cases can be further subdivided into four levels, with bit0 having the lowest weight and bit3 having the highest weight.

[0135] Referring to Table 1 below, which shows a specific embodiment of setting the turn-on voltage of multiple first transistors M1, the fluctuation of the first voltage VDD or the second voltage VSS corresponds to the change in the monitoring signal. 'Swing' refers to the voltage fluctuation amplitude occurring on VDD or VSS, and 'abs(swing)' represents the absolute value of the amplitude.

[0136]

[0137] Table 1

[0138] Table 1 above shows the correspondence between the logic state of the monitoring signal bits and the voltage swing of a die using transistors with process corners of FF (Fast NMOS and Fast PMOS), SS (Slow NMOS and Slow PMOS), and TT (Typical NMOS and Typical PMOS) at -45 degrees Celsius, 60 degrees Celsius, and 125 degrees Celsius, respectively. Those skilled in the art can determine the monitoring range of each monitoring circuit by obtaining the table above, and then select the monitoring range of the integrated circuit through register 200.

[0139] Specifically, referring to the table above, in some specific embodiments, for chips using the aforementioned integrated circuits and with a transistor process angle of FF, at -45 degrees Celsius, when the voltage fluctuation is greater than 0.29V, the first monitoring signal bit0 is logic 1; when the voltage fluctuation is greater than 0.35V, both the first monitoring signal bit0 and the second monitoring signal bit1 are logic 1; when the voltage fluctuation is greater than 0.45V, the first monitoring signal bit0, the second monitoring signal bit1, and the third monitoring signal bit2 are all logic 1; when the voltage fluctuation is greater than 0.48V, the first monitoring signal bit0, the second monitoring signal bit1, the third monitoring signal bit2, and the fourth monitoring signal bit4 are all logic 1.

[0140] Similarly, for a chip using the aforementioned integrated circuit with a transistor process angle of TT, at 60 degrees Celsius, when the voltage fluctuation is greater than 0.28V, the first monitoring signal bit0 is logic 1; when the voltage fluctuation is greater than 0.35V, both the first monitoring signal bit0 and the second monitoring signal bit1 are logic 1; when the voltage fluctuation is greater than 0.45V, the first monitoring signal bit0, the second monitoring signal bit1, and the third monitoring signal bit2 are all logic 1; when the voltage fluctuation is greater than 0.5V, the first monitoring signal bit0, the second monitoring signal bit1, the third monitoring signal bit2, and the fourth monitoring signal bit4 are all logic 1.

[0141] For a chip using the aforementioned integrated circuit and with a transistor process angle of SS, at 125 degrees Celsius, when the voltage fluctuation is greater than 0.32V, the first monitoring signal bit0 is logic 1; when the voltage fluctuation is greater than 0.38V, both the first monitoring signal bit0 and the second monitoring signal bit1 are logic 1; when the voltage fluctuation is greater than 0.47V, the first monitoring signal bit0, the second monitoring signal bit1, and the third monitoring signal bit2 are all logic 1; when the voltage fluctuation is greater than 0.55V, the first monitoring signal bit0, the second monitoring signal bit1, the third monitoring signal bit2, and the fourth monitoring signal bit4 are all logic 1.

[0142] Therefore, according to the table above, when bit0 is logic 1, ESD events exceeding 0.28V can be monitored; when bit1 is logic 1, ESD events exceeding 0.35V can be monitored; when bit2 is logic 1, ESD events exceeding 0.45V can be monitored; and when bit3 is logic 1, ESD events exceeding 0.48V can be monitored. Furthermore, when the internal design register value is 0001, it means ESD events exceeding 250V can be monitored; when the internal design register value is 0011, it means ESD events exceeding 350V can be monitored; when the internal design register value is 0111, it means ESD events exceeding 450V can be monitored; and when the internal design register value is 1111, it means ESD events exceeding 550V can be monitored.

[0143] Specifically, such as Figure 13 As shown, the three monitoring signals bit0-bit2 are ANDed with the first reference signal register1, the second reference signal register1, and the third reference signal register3 from register 200, respectively. An RC low-pass filter network is added to the lines of the first reference signal register1, the second reference signal register1, and the third reference signal register3 to prevent the ESD event from causing the state of the reference signal register connected to the AND gate to change.

[0144] By setting the logic states of the first reference signal register1, the second reference signal register2, and the third reference signal register3, the range of ESD event voltage fluctuations monitored by the integrated circuit is selected. This design aims to cover as much as possible the voltage generated during normal use and some destructive experiments. Assuming that the first monitoring circuit 101 outputs a first monitoring signal bit0 with a logic state of 1 when the first voltage VDD or the second voltage VSS fluctuation exceeds 0.25V, and the first reference signal register1 is set to logic 1 through register 200, the integrated circuit can monitor all ESD events where the first voltage VDD or the second voltage VSS fluctuation exceeds 0.25V. When an ESD event occurs where the first voltage VDD or the second voltage VSS fluctuation exceeds 0.25V, the logic circuit 300 outputs a control signal with a logic state of 1 to control the power-on reset circuit 400 to perform a power-on reset, thereby releasing the charge accumulated in the integrated circuit.

[0145] Similarly, suppose the second monitoring circuit 102 outputs a second monitoring signal bit1 with a logic state of 1 when the first voltage VDD or the second voltage VSS fluctuates beyond 0.35V, and sets the first reference signal register1 to logic 0 and the second reference signal register2 to logic 1 through register 200, so that the integrated circuit can monitor all ESD events where the first voltage VDD or the second voltage VSS fluctuates beyond 0.35V; suppose the third monitoring circuit 103 outputs a third monitoring signal bit2 with a logic state of 1 when the first voltage VDD or the second voltage VSS fluctuates beyond 0.45V, and sets the first reference signal register1 and the second reference signal register2 to logic 1 through register 200. The first reference signal register2 is set to logic 0, and the second reference signal register3 is set to logic 1, enabling the integrated circuit to monitor all ESD events where the first voltage VDD or the second voltage VSS fluctuates more than 0.45V. Assuming that the fourth monitoring circuit 104 outputs the fourth monitoring signal bit3 with a logic state of 1 when the first voltage VDD or the second voltage VSS fluctuates more than 0.55V, the first reference signal register1, the second reference signal register2, and the third reference signal register3 are all set to logic 0 through register 200, enabling the integrated circuit to monitor all ESD events where the first voltage VDD or the second voltage VSS fluctuates more than 0.55V.

[0146] In addition, if the integrated circuit is triggered by noise interference when no ESD event occurs, the corresponding reference signal register is set to logic 0 to prevent the three monitoring signals bit0-bit2 from triggering the power-on reset circuit 400 due to noise interference.

[0147] For details, please refer to Figure 13 As shown, assuming that the first monitoring signal bit0 will be affected by noise interference and trigger the power-on reset circuit 400, but no ESD event actually occurs, the first reference signal register1 corresponding to the monitoring signal bit0 can be set to logic 0 to avoid noise interference. Similarly, those skilled in the art can set the second reference signal register2 and the third reference signal register3 corresponding to the second monitoring signal bit1 and the third monitoring signal bit2 to logic 0 respectively according to the actual noise interference situation to avoid triggering the power-on reset circuit 400 due to noise interference.

[0148] The power-on reset circuit performs a power-on reset on the integrated circuit according to the control signal to initialize the integrated circuit. This initialization process is the action of the MCU (Microcontroller Unit) inside the integrated circuit. During the power-off process of the initialization process, the pins of the integrated circuit are grounded, and the charge is released to protect the integrated circuit.

[0149] Based on the same inventive concept, embodiments of this application provide a monitoring and protection method for integrated circuits, used to monitor electrostatic discharge events and release charge based on the monitoring results, such as... Figure 15 As shown, the monitoring and protection method includes:

[0150] S100: The monitoring circuit outputs a monitoring signal based on the fluctuations of the first voltage signal and the second voltage signal;

[0151] S200: The register outputs multiple reference signals according to the monitoring level, and the logic circuit outputs control signals according to the monitoring signals and reference signals;

[0152] S300: The power-on reset circuit performs a power-on reset on the integrated circuit according to the control signal to release the charge accumulated in the integrated circuit.

[0153] The monitoring and protection method provided in this application has the same beneficial effects as the integrated circuit described above, and therefore will not be described in detail again.

[0154] Specifically, in one embodiment, the monitoring circuit outputs a monitoring signal based on voltage fluctuations of the first voltage and the second voltage, including:

[0155] S110: The noise reduction filter absorbs energy from the first voltage signal terminal and the second voltage signal terminal;

[0156] S120: The voltage sensor detects the voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal. When the voltage fluctuation meets the set conditions, it outputs an adjustment signal to the latch.

[0157] S130: After receiving the adjustment signal, the latch outputs the first logic state to determine that an electrostatic discharge event has occurred.

[0158] S140: When an electrostatic discharge event occurs, the current limiting module blocks the current flowing from the second voltage signal terminal to the first voltage signal terminal and generates a monitoring signal based on the output of the latch.

[0159] The specific method by which the monitoring circuit of this application outputs a monitoring signal based on the voltage fluctuations of the first voltage and the second voltage has been described in detail above, and will not be repeated here.

[0160] In this embodiment of the application, the register outputs multiple reference signals according to the monitoring level. Specifically, when it is necessary to monitor an ESD event where the fluctuation of the first voltage VDD or the second voltage VSS is greater than 0.25V, the register outputs the first reference signal register1 as logic 1, and the second reference signal register1 and the third reference signal register3 as logic 0. The specific setting method has been described above and will not be repeated here.

[0161] In summary, the technical solution provided by the embodiments of this application can achieve at least the following beneficial effects:

[0162] The monitoring circuit 100 provided in this embodiment absorbs energy from the first and second voltage signal terminals through a noise filter 110. After the noise filter 110 absorbs energy from the first and second voltage signal terminals, the voltage sensor 120 detects voltage fluctuations at the first and second voltage signal terminals. When the voltage fluctuation meets a set condition, it outputs an adjustment signal to the latch 130. The latch 130 is configured to output a first logic state at its output terminal out0 upon receiving the adjustment signal, thus determining that an electrostatic discharge (ESD) event has occurred in the integrated circuit. Upon determining the ESD event, it can trigger the ESD protection mechanism of the integrated circuit, thereby preventing damage to the integrated circuit. Furthermore, the monitoring circuit 100 provided in this embodiment can identify ESD events of different degrees by changing the sensitivity of the voltage sensor 120, thereby triggering the ESD protection mechanism of the integrated circuit. This achieves the monitoring, graded control, and release of ESD events, ultimately protecting the integrated circuit.

[0163] In the description of this application, it should be understood that the terms "center", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0164] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0165] The above description is only a partial embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. An integrated circuit, characterized in that, It includes multiple monitoring circuits, as well as registers, logic circuits, and power-on reset circuits; Each monitoring circuit, used for monitoring electrostatic discharge events, includes: a noise suppression filter, a voltage sensor, and a latch; the noise suppression filter includes: a first resistor, a second resistor, and a first capacitor; a first terminal of the first resistor is connected to a first voltage signal terminal, and a second terminal of the first resistor is connected to a first terminal of the first capacitor; a first terminal of the second resistor is connected to a second voltage signal terminal, and a second terminal of the second resistor is connected to a second terminal of the first capacitor, for absorbing energy from the first voltage signal terminal and the second voltage signal terminal; the voltage sensor is used to detect voltage fluctuations between the first voltage signal terminal and the second voltage signal terminal after the noise suppression filter absorbs energy from the first voltage signal terminal and the second voltage signal terminal, and when the voltage fluctuation reaches a certain value... When the set conditions are met, an adjustment signal is output to the latch; the latch is configured to output a first logic state upon receiving the adjustment signal to determine that an electrostatic discharge event has occurred; the voltage sensor includes: a second capacitor, a third resistor, and a first transistor; the first terminal of the second capacitor is connected to the second terminal of the first resistor, and the second terminal of the second capacitor is connected to the first terminal of the third resistor and the gate of the first transistor respectively; the second terminal of the third resistor is connected to the second terminal of the second resistor; the first terminal of the first transistor is connected to the second terminal of the third resistor, and the second terminal of the first transistor is connected to the input terminal of the latch; in the plurality of monitoring circuits, the turn-on voltage of the first transistor included in each voltage sensor is different; The register is used to output multiple reference signals to the logic circuit according to the monitoring level; The logic circuit is used to receive multiple monitoring signals output by the multiple monitoring circuits, and output control signals to the power-on reset circuit according to the monitoring signals and the reference signals; The power-on reset circuit is used to power-on reset the integrated circuit according to the control signal, so as to release the charge accumulated in the integrated circuit.

2. The integrated circuit as described in claim 1, characterized in that, It also includes a reset module and a current limiting module; The first voltage corresponding to the first voltage signal terminal is a high-level voltage, and the second voltage corresponding to the second voltage signal terminal is a low-level voltage; The reset module is used to control the output terminal of the latch to output a second logic state according to the reset signal during the reset phase. The second logic state is the opposite of the first logic state. The current limiting module is used to block the current flowing from the second voltage signal terminal to the first voltage signal terminal when an electrostatic discharge event occurs, and to generate a monitoring signal based on the output of the latch.

3. The integrated circuit as described in claim 2, characterized in that, If the voltage fluctuation satisfies the condition that the voltage difference between the first voltage and the second voltage increases and is within a first preset range, the voltage sensor outputs an adjustment signal to the latch. The latch is configured to change its output state from the second logic state to the first logic state after receiving the adjustment signal. If the voltage difference between the first voltage and the second voltage decreases and falls within a second preset range, and the latch's current output is in the first logic state, the latch is further configured to maintain the first logic state at its output; and, If the voltage difference between the first voltage and the second voltage decreases and falls within a third preset range, the latch is in a non-operating state, and the latch is also configured to have its output in a floating state or to output a negative potential signal to determine that an electrostatic discharge event has occurred.

4. The integrated circuit as described in claim 2, characterized in that, The latch includes: a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The gate of the second transistor is connected to the input terminal of the latch, the first terminal of the second transistor is connected to the first terminal of the noise filter, and the second terminal of the second transistor is connected to the second terminal of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor, and the output terminal of the latch. The gate of the third transistor is connected to the input terminal of the latch, and the first terminal of the third transistor is connected to the second terminal of the noise reduction filter; The first terminal of the fourth transistor is connected to the first terminal of the noise reduction filter, and the second terminal of the fourth transistor is connected to the input terminal of the latch and the second terminal of the fifth transistor; The first terminal of the fifth transistor is connected to the second terminal of the noise reduction filter.

5. The integrated circuit as described in claim 2, characterized in that, The current limiting module includes: a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; The gate of the sixth transistor is connected to the output terminal of the latch, the first terminal of the sixth transistor is connected to the first terminal of the noise filter, and the second terminal of the sixth transistor is connected to the second terminal of the seventh transistor, the gate of the eighth transistor, and the gate of the ninth transistor, respectively. The gate of the seventh transistor is connected to the output terminal of the latch, and the first terminal of the seventh transistor is connected to the second terminal of the noise reduction filter. The first terminal of the eighth transistor is connected to the first terminal of the noise reduction filter, and the second terminal of the eighth transistor is connected to the second terminal of the ninth transistor and the output terminal of the monitoring signal, respectively. The first terminal of the ninth transistor is connected to the second terminal of the noise reduction filter; The reset module includes a tenth transistor; The gate of the tenth transistor is connected to a reset signal, the first terminal of the tenth transistor is connected to the second terminal of the noise filter, and the second terminal of the tenth transistor is connected to the output terminal of the latch, which is used to adjust the output terminal of the latch according to the reset signal.

6. The integrated circuit according to any one of claims 2-5, characterized in that, It also includes a critical condition monitoring circuit, which is used to filter the first voltage and the second voltage when the voltage fluctuation only reduces the voltage difference between the first voltage signal and the second voltage signal, and control the logic state of the monitoring signal to a first logic state based on the voltage difference between the first voltage and the filtered first voltage.

7. The integrated circuit as described in claim 6, characterized in that, The critical condition monitoring circuit includes a third capacitor, a fourth resistor, and at least an eleventh transistor. The first end of the fourth resistor is connected to the first voltage signal terminal, and the second end of the fourth resistor is connected to the first end of the third capacitor and the first end of the eleventh transistor. The second terminal of the third capacitor is connected to the second voltage signal terminal; The gate of the eleventh transistor is connected to the first voltage signal terminal, and the second terminal of the eleventh transistor is connected to the output terminal of the monitoring signal.

8. The integrated circuit as claimed in claim 1, characterized in that, The plurality of monitoring circuits also include a critical condition monitoring circuit, which includes a third capacitor, a fourth resistor and a plurality of eleventh transistors. The first end of the fourth resistor is connected to the first voltage signal terminal, and the second end of the fourth resistor is connected to the first end of the third capacitor and the first end of the plurality of eleventh transistors; The second terminal of the third capacitor is connected to the second voltage signal terminal; The gates of the plurality of eleventh transistors are connected to the first voltage signal terminal. The plurality of eleventh transistors have different turn-on voltages, and the second terminals of the plurality of eleventh transistors with different turn-on voltages are connected to the output terminals of the monitoring signals in a one-to-one correspondence with the turn-on voltages of the first transistors included in the monitoring circuit.

9. A monitoring and protection method for an integrated circuit as described in any one of claims 2 to 8, used to monitor electrostatic discharge events and release charge based on the monitoring results, characterized in that, include: The monitoring circuit outputs a monitoring signal based on the voltage fluctuations of the first voltage and the second voltage; The register outputs multiple reference signals according to the monitoring level, and the logic circuit outputs control signals according to the monitoring signals and the reference signals. The power-on reset circuit performs a power-on reset on the integrated circuit according to the control signal to release the charge accumulated in the integrated circuit.

10. The monitoring and protection method as described in claim 9, characterized in that, The monitoring circuit outputs a monitoring signal based on the voltage fluctuations of the first voltage and the second voltage, including: The noise reduction filter absorbs energy from the first voltage signal terminal and the second voltage signal terminal; The voltage sensor detects the voltage fluctuation between the first voltage signal terminal and the second voltage signal terminal. When the voltage fluctuation meets the set conditions, it outputs an adjustment signal to the latch. After receiving the adjustment signal, the latch outputs a first logic state to determine that an electrostatic discharge event has occurred. When an electrostatic discharge event occurs, the current limiting module blocks the current flowing from the second voltage signal terminal to the first voltage signal terminal and generates a monitoring signal based on the output of the latch.

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