Binary translation method, processor and electronic device

Abstract

An embodiment of the present invention provides a binary translation method, processor, and electronic device, which are applied to a binary translation system. The method includes: obtaining a first jump instruction, where the first jump instruction is an instruction of a target program in a host machine, the first jump instruction corresponding to a first jump address and a second jump address, the first jump address being a target jump address to be jumped to when the first jump instruction meets a jump condition, and the second jump address being a target jump address to be jumped to when the first jump instruction does not meet the jump condition; during the execution of the first jump instruction, counting the number of jumps from the first jump instruction to the second jump address; if the number of jumps is greater than a first preset threshold, reordering the first jump address and the second jump address. The embodiment of the present invention can reduce the overall hardware overhead of the binary translation system and improve the operating efficiency of the binary translation system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, a processor, and an electronic device. Background Art

[0002] Based on the complexity of the instructions, the CPU (Central Processing Unit) instruction set can be divided into Complex Instruction Set Computer (CISC) instructions and Reduced Instruction Set Computer (RISC) instructions. CISC instructions are numerous, have widely varying application frequencies, and have varying instruction lengths; RISC instructions are fewer, have similar application frequencies, and have fixed instruction lengths. The simpler RISC instruction set makes it easier to design multi-stage pipelines and multi-level processor caches, thereby improving microprocessor performance.

[0003] With the continuous development of microprocessor technology, the performance of microprocessors has become increasingly powerful. In order to enable computers to process different CPU instruction sets at the same time and improve processing efficiency, binary translation technology has emerged. This technology can enable the source program to be translated of one CPU architecture to run on another CPU architecture. For example, the software ecosystem of a mature CPU architecture can be quickly migrated to a new CPU architecture. However, this technology still has technical problems such as low translation efficiency and excessive redundant operations. In order to solve the problem of low efficiency of binary translators, some microprocessors provide additional binary translators in the processor core to support the optimization of translation code. However, the existing binary translators have large hardware overhead and low operating efficiency, and their performance needs to be improved. Summary of the Invention

[0004] The embodiments of the present invention provide a binary translation method, a processor, and an electronic device, which can solve the problems of large hardware overhead and low operating efficiency of binary translators in the prior art.

[0005] To solve the above problems, an embodiment of the present invention discloses a binary translation method, which is applied to a binary translation system. The binary translation system is used to translate a source program in a client into a target program in a host. The method includes:

[0006] Obtaining a first jump instruction, where the first jump instruction is an instruction of a target program in the host machine, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address being a target jump address to which the first jump instruction is to jump when a jump condition is satisfied, and the second jump address being a target jump address to which the first jump instruction is to jump when the jump condition is not satisfied;

[0007] During execution of the first jump instruction, counting the number of jumps from the first jump instruction to the second jump address;

[0008] If the jump number is greater than a first preset threshold, instructions are rearranged for the first jump address and the second jump address.

[0009] On the other hand, an embodiment of the present invention discloses a processor for use in a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host. The microprocessor includes:

[0010] an instruction fetch unit, configured to obtain a first jump instruction, where the first jump instruction is an instruction of a target program in the host machine, and the first jump instruction corresponds to a first jump address and a second jump address, where the first jump address is a target jump address to which the first jump instruction is to jump when a jump condition is satisfied, and the second jump address is a target jump address to which the first jump instruction is to jump when the jump condition is not satisfied;

[0011] A processing unit is used to count the number of jumps from the first jump instruction to the second jump address during the execution of the first jump instruction; if the number of jumps is greater than a first preset threshold, reorder the instructions of the first jump address and the second jump address.

[0012] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to execute the aforementioned binary translation method by one or more processors.

[0013] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned binary translation method.

[0014] The embodiments of the present invention include the following advantages:

[0015] In an embodiment of the present invention, during the execution of a first jump instruction in a host machine, the number of jumps from the first jump instruction to a second jump address is counted, wherein the number of jumps from the first jump instruction to the second jump address can also be referred to as the number of times the first jump instruction does not meet a jump condition, or the number of misses of the first jump instruction. Then, when the number of jumps to the second jump address is greater than a first preset threshold, the first jump address and the second jump address are reordered so that addresses with a large number of jumps are on a jump path with a smaller overhead, thereby reducing the overall hardware overhead of the binary translation system and improving the operating efficiency of the binary translation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 is a flowchart of the steps of an embodiment of a binary translation method of the present invention;

[0018] Figure 2 It is a schematic diagram of the execution flow of a target program of the present invention;

[0019] Figure 3 It is a schematic diagram of a jump instruction reordering flow of the present invention;

[0020] Figure 4 It is a schematic diagram of the execution flow of another target program of the present invention;

[0021] Figure 5 It is a schematic diagram of the execution flow of another target program of the present invention;

[0022] Figure 6 It is a schematic diagram of a jump refill table of the present invention;

[0023] Figure 7 It is a flowchart of the steps of binary translation processing of the present invention;

[0024] Figure 8 is a structural block diagram of a processor of the present invention;

[0025] Figure 9 is a structural block diagram of another processor of the present invention;

[0026] Figure 10 This is a structural block diagram of an electronic device for binary translation according to the present invention. DETAILED DESCRIPTION

[0027] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0028] Method Example

[0029] Reference Figure 1 , shows a flowchart of a binary translation method embodiment of the present invention, which is applied to a binary translation system. The method may specifically include the following steps:

[0030] Step 101: Obtain a first jump instruction, where the first jump instruction is an instruction of a target program in a host machine, and the first jump instruction corresponds to a first jump address and a second jump address.

[0031] Step 102: During the execution of the first jump instruction, count the number of jumps from the first jump instruction to the second jump address.

[0032] Step 103: If the jump number is greater than a first preset threshold, reorder the instructions of the first jump address and the second jump address.

[0033] The binary translation method provided in an embodiment of the present invention can be applied to a binary translation system. The binary translation system is used to translate a source program in a client into a target program in a host. The first jump instruction is a corresponding instruction in the host, and the first jump instruction corresponds to a first jump address and a second jump address. The first jump address is the target jump address to which the first jump instruction is to jump if a jump condition is met, and the second jump address is the target jump address to which the first jump instruction is to jump if the jump condition is not met.

[0034] It should be noted that the source program is binary code. During the translation process, the binary translation system can only obtain the compiled binary code (i.e., the source program), and after disassembling the binary code, obtain the assembly-level code; at this time, it is impossible to segment the code based on the function in the source program as the basic unit. Normally, the binary translation system segments the obtained source program into translation units one after another, and the last instruction of each translation unit is usually the jump instruction in the source program. The binary translation system works based on the translation unit as the basic unit.

[0035] In an embodiment of the present invention, the first jump instruction is an instruction of a target program in a host machine, and a client jump instruction corresponding to the first jump instruction exists in a source program on a client machine. In the source program, a jump instruction corresponds to two jump directions: one when the jump condition is met, and the other when the jump condition is not met. Each jump direction corresponds to a jump address. Assume that for jump instruction A1 in the source program, the offset address is offset0 when the jump condition is met, and the offset address is offset1 when the jump condition is not met. In the source program, after the processor determines the jump instruction, it can directly jump to the target jump address based on the jump condition, the offset address, and the address of the jump instruction. In other words, in the source program, the cost of going to offset0 and offset1 is the same. However, after the two-level translation system translates the source program, the original instruction sequence is disrupted. In the target program on the host machine, the next instruction of the currently executed jump instruction does not necessarily belong to the same instruction sequence as the jump instruction. In addition, a large number of B instructions will be inserted into the translated target program. When the target program in the host machine goes to the target jump address corresponding to offset1, it needs to run one or more "b offset1" instructions first. The B instruction is also a jump instruction. Therefore, when the target program goes to the target jump address corresponding to offset1, it often needs to perform continuous jumps. Continuous jumps will produce bubbles, which can easily cause errors in the host machine when prefetching instructions, affecting the operating efficiency of the binary translation system.

[0036] For example, assuming that the jump condition of the first jump instruction A1 is a=b, the offset address corresponding to the first jump address is offset0, the offset address corresponding to the second jump address is offset1, the instruction stored in the first jump address is instruction A2, and the instruction stored in the second jump address is instruction A3. Figure 2 , shows a schematic diagram of the execution flow of a target program provided by an embodiment of the present invention. Figure 2 As shown, when the processor executes the first jump instruction A1, it determines whether the first jump instruction A1 meets the jump condition. If the jump condition is met (a=b), it jumps directly to the first jump address, obtains instruction A2 from the first jump address and executes it; if the jump condition is not met (a≠b), before going to the second jump address, it needs to run one or more "b offset1" instructions, and then obtain instruction A3 from the second jump address and execute it, which increases the hardware overhead of the binary translation system and affects the operating efficiency of the binary translation system.

[0037] To solve this problem, an embodiment of the present invention, during the process of executing the first jump instruction in the target program, firstly, counts the number of jumps from the first jump instruction to the second jump address, where the number of times the first jump instruction jumps to the second jump address can also be referred to as the number of times the first jump instruction does not meet the jump condition, or the number of misses of the first jump instruction; then, when the number of jumps from the first jump instruction to the second jump address (the number of misses of the first jump instruction) is greater than a first preset threshold, the first jump address and the second jump address are reordered, so that the target program minimizes the number of times it goes to the jump address corresponding to offset1, thereby reducing the number of times the "b offset1" instruction is run, reducing the hardware overhead of the binary translation system, and improving the operating efficiency of the binary translation system.

[0038] As an example, the instruction reordering of the first jump address and the second jump address described in step 103 includes: setting an exception to execute a custom exception service program when the number of jumps is greater than a first preset threshold, so as to modify the jump direction of the first jump instruction in the memory pool, and exchange the instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

[0039] It's important to note that during program execution, exceptions are typically handled based on the exception mechanism. For example, division by zero overflow, array out-of-bounds errors, and file not found errors occur. If an exception occurs during program execution, an object representing the exception is generated, containing detailed information about the exception. This object is then passed to the runtime system, which searches for the appropriate code to handle the exception.

[0040] In an embodiment of the present invention, the first jump address and the second jump address of the first jump instruction can be rearranged by executing a custom exception service program. Figure 3 , shows a schematic diagram of a jump instruction reordering process provided by an embodiment of the present invention. Figure 3As shown, before executing the target program in the host machine, a first preset threshold of the jump refill table can be set first. The jump refill table is used to record the number of runs and the number of misses of the first jump instruction (that is, the number of times the first jump instruction does not meet the jump condition). PC is the address of the first jump instruction, and the address of the first jump instruction can be used as the instruction identifier of the first jump instruction. Each time the first jump instruction is executed, the number of runs and the number of misses corresponding to the first jump instruction are updated in the jump refill table according to the PC of the first jump instruction. In an embodiment of the present invention, the number of misses of the first jump instruction being greater than the first preset threshold can be regarded as an abnormal event. If the number of misses of the first jump instruction is greater than the first preset threshold, an exception is triggered, and the instruction reordering of the first jump address and the second jump address of the first jump instruction is achieved by executing a custom exception service program. Specifically, as Figure 3 As shown, by executing a custom exception service routine, the first jump address and the second jump address recorded in the memory pool can be swapped to change the jump direction of the first jump instruction, so that the first jump instruction goes to the second jump address when the jump condition is met, and goes to the first jump address when the jump condition is not met; and the instructions stored in the first jump address and the second jump address are swapped. For example, before the instruction reordering is performed, the first jump address stores instruction A2, and the second jump address stores instruction A3. After the instruction reordering, the instruction stored in the first jump address becomes instruction A3, and the instruction stored in the second jump address becomes instruction A2.

[0041] Reference Figure 4 , shows a schematic diagram of the execution flow of another target program provided by an embodiment of the present invention. Figure 4 As shown, when the processor determines that the first jump instruction meets the jump condition (a=b), it goes to the second jump address to fetch instruction A2 and executes it; when it determines that the first jump instruction does not meet the jump condition (a≠b), it goes to the first jump address to fetch instruction A3 and executes it. Figure 2The execution flow of the target program before the instruction reordering shown in the figure, after the present invention performs instruction reordering on the first jump address and the second jump address, when a=b, the next instruction to be executed by the target program is still instruction A2, and when a≠b, the next instruction to be executed is still instruction A3, and the execution logic of the target program has not been changed. However, after the instruction reordering, when the first jump instruction does not meet the jump condition, the target program no longer needs to go to the second jump address corresponding to offset1, and can directly obtain instruction A3 from the first jump address corresponding to offset0 and execute it. Although the target jump program still needs to execute the "b offset1" instruction when going to the second jump address when the first jump instruction meets the jump condition, since the number of misses of the first jump instruction is greater than the first preset threshold, it means that within the same time, the number of times the first jump instruction meets the jump condition is less than the number of times the jump condition is not met, compared to Figure 2 The execution flow shown, Figure 4 In the execution flow shown, the number of times the "b offset1" instruction is executed is effectively reduced, thereby reducing the hardware overhead of the binary translation system and improving the operating efficiency of the binary translation system.

[0042] As another example, the reordering of the first jump address and the second jump address in step 103 includes: inverting the jump condition of the first jump instruction, and exchanging the instructions stored in the first jump address and the second jump address.

[0043] In the embodiment of the present invention, the instructions of the first jump address and the second jump address may be rearranged by inverting the jump condition of the first jump instruction and exchanging the instructions stored in the first jump address and the second jump address.

[0044] Assume that the original jump condition for first jump instruction A1 is a=b. After negating the jump condition, the jump condition for first jump instruction A1 becomes a≠b. Before instruction reordering, instruction A2 is stored at the first jump address, and instruction A3 is stored at the second jump address. After instruction reordering, the instruction stored at the first jump address becomes instruction A3, and the instruction stored at the second jump address becomes instruction A2.

[0045] Reference Figure 5 , shows another schematic diagram of the execution flow of a target program provided by an embodiment of the present invention. Figure 5 As shown, when the processor determines that the first jump instruction meets the jump condition (a≠b), it goes to the first jump address to fetch instruction A3 and executes it; when it determines that the first jump instruction does not meet the jump condition (a=b), it goes to the second jump address to fetch instruction A2 and executes it. Figure 2The execution flow of the target program before the instruction reordering shown in the figure, after the present invention performs instruction reordering on the first jump address and the second jump address, when a=b, the next instruction to be executed by the target program is still instruction A2, and when a≠b, the next instruction to be executed is still instruction A3, and the execution logic of the target program has not been changed. However, after the instruction reordering, when a≠b, the target program no longer needs to go to the second jump address corresponding to offset1, and can directly obtain instruction A3 from the first jump address corresponding to offset0 and execute it. Although the target jump program still needs to execute the "b offset1" instruction when going to the second jump address when a=b, the number of misses of the first jump instruction before the instruction reordering is greater than the first preset threshold, which means that in the same time, the number of times the first jump instruction satisfies a=b is less than the number of times it satisfies a≠b. Compared with Figure 2 The execution flow shown in FIG. 4 effectively reduces the number of times the "b offset 1" instruction is executed, reduces the hardware overhead of the binary translation system, and improves the operating efficiency of the binary translation system.

[0046] In an optional embodiment of the present invention, the method further includes:

[0047] Step S11, if the jump number is less than or equal to a first preset threshold, and the currently executed instruction is the first jump instruction, determining whether the first jump instruction meets the jump condition;

[0048] Step S12: If the first jump instruction satisfies the jump condition, jump to the first jump address, obtain the target instruction from the first jump address and execute it;

[0049] Step S13: If the first jump instruction does not meet the jump condition, then jump to the second jump address after executing the expansion instruction, obtain the target instruction from the second jump address and execute it; wherein, the expansion instruction is generated during the translation process of the source program to be translated by the binary translation system.

[0050] In an embodiment of the present invention, if the number of jumps from the first jump instruction to the second jump address, i.e., the number of misses for the first jump instruction, is less than a first preset threshold, the first jump address and the second jump address of the first jump instruction are not rearranged, and the first jump instruction is still executed according to the processing in the existing binary translator. Specifically, a determination is made as to whether the first jump instruction satisfies a jump condition. If so, the instruction directly jumps to the first jump address, retrieves the target instruction from the first jump address, and executes it. If not, the instruction executes the expanded instruction and then jumps to the second jump address, retrieves the target instruction from the second jump address, and executes it.

[0051] As an example, assume that in the target program, the first offset address corresponding to the first jump address is offset0, and the second offset address corresponding to the second jump address is offset1. If the number of misses for the first jump instruction is less than or equal to a first preset threshold, then when the first jump instruction meets the jump condition, the first jump address is directly used to obtain the target instruction; when the first jump instruction does not meet the jump condition, a "b offset1" instruction is first executed, and then the second jump address is used to obtain the target instruction. Because the number of jumps required for the first jump instruction to jump to the second jump address is less than or equal to the first preset threshold, that is, a "b offset1" instruction must be executed before each jump to the second jump address, the number of times the "b offset1" instruction is executed is also less than the first preset threshold, resulting in limited hardware overhead and a minimal impact on the operating efficiency of the binary translation system. Therefore, embodiments of the present invention set a first preset threshold and adopt corresponding instruction execution strategies based on the relationship between the number of misses for the jump instruction and the first preset threshold, thereby effectively controlling the hardware overhead of the binary translation system.

[0052] In an optional embodiment of the present invention, in step 102, counting the number of jumps from the first jump instruction to the second jump address during execution of the first jump instruction includes:

[0053] Step S21, during the execution of the first jump instruction, counting the number of executions of the first jump instruction and the number of jumps to the second jump address;

[0054] Step S22: Record the number of runs and the number of jumps in a preset jump refill table.

[0055] In an embodiment of the present invention, the number of executions of the first jump instruction and the number of jumps to the second jump address (hereinafter referred to as "miss count") can be recorded by a pre-set jump refill table. Figure 6 , shows a schematic diagram of a jump refill table provided by an embodiment of the present invention. Figure 6 As shown, the address (PC) of the first jump instruction in the target program can be used as the instruction identifier of the first jump instruction, so as to distinguish each first jump instruction according to the address and record the number of misses (Not taken times) and run times (run times) of each first jump instruction.

[0056] As an example, based on actual needs, the first jump instruction in the target program whose number of misses needs to be counted can be marked. During the execution of the target program, only the number of misses of the marked first jump instruction is counted, that is, the number of jumps to the second jump address and the number of times the first jump instruction is executed are counted, and the statistical results are recorded in a jump refill table. The binary translation system can determine whether the first jump address and the second jump address of the first jump instruction need to be reordered by querying the jump refill table, thereby improving the information query efficiency of the binary translation system.

[0057] In an optional embodiment of the present invention, after the instructions of the first jump address and the second jump address are rearranged, the method further includes: converting the first jump instruction into a second jump instruction, and continuing to execute the next instruction sequentially, wherein the binary translation system does not count the number of executions and jumps of the second jump instruction.

[0058] It should be noted that in the embodiment of the present invention, only the number of runs and jumps of the marked first jump instruction are counted and recorded in the jump refill table, and the number of runs and jumps of other jump instructions in the target program, that is, the number of runs and jumps of the second jump instruction, are not counted. The second jump instruction is the first jump instruction after instruction reordering. Compared with the first jump instruction, when executing the second jump instruction, regardless of whether the second jump instruction meets the jump condition, the number of times the processor executes instruction B has been effectively reduced. Therefore, there is no need to perform any processing on the second jump instruction, and there is no need to record the number of runs and jumps of the second jump instruction in the jump refill table, so as to avoid excessive occupation of table entries in the jump refill table and improve the utilization rate of the jump refill table.

[0059] After converting the first jump instruction into the second jump instruction, the next instruction can be executed according to the order of the instructions in the target program.

[0060] In an optional embodiment of the present invention, the method further includes:

[0061] If the execution count of the first jump instruction is greater than a second preset threshold, the execution count and the jump count of the first jump instruction in the jump refill table are cleared to zero.

[0062] In an embodiment of the present invention, the execution count and jump count of the first jump instruction in the jump refill table can be cleared to zero when the execution count of the first jump instruction exceeds a second preset threshold value, thereby ensuring the timeliness of the execution count and jump count recorded in the jump refill table and avoiding data redundancy. The first preset threshold value and the second preset threshold value can both be set according to actual needs and are not specifically limited in the embodiment of the present invention. Typically, the first preset threshold value is less than the second preset threshold value.

[0063] In addition, in an embodiment of the present invention, when the jump refill table is full, that is, when there are no free table entries, the information corresponding to the earliest recorded first jump instruction can be overwritten based on the time when each first jump instruction is recorded; or, based on the information update frequency of each first jump instruction within a preset time, the information corresponding to the first jump instruction with the lowest information update frequency can be overwritten to ensure that the information of the currently executed first jump instruction, such as the number of runs and the number of jumps, is recorded in real time in the jump refill table.

[0064] In an optional embodiment of the present invention, before obtaining the first jump instruction in step 101, the method further includes:

[0065] Step S31, obtaining a source program to be translated, wherein the source program includes at least one jump instruction;

[0066] Step S32, segmenting the source program based on the jump instruction to obtain at least one translation unit;

[0067] Step S33, disassembling the at least one translation unit to obtain an assembly program corresponding to each translation unit;

[0068] Step S34 , calling the translation function to translate the assembly program corresponding to each translation unit to obtain the target program corresponding to each translation unit.

[0069] The target program in the host machine is obtained by translating the source program in the client machine through the binary translation system. Figure 7 , shows a flowchart of the steps of binary translation processing provided by an embodiment of the present invention. Figure 7As shown, specifically, after the binary translation system obtains the source program to be translated, it first divides the source program based on the jump instructions in the source program to obtain translation units, which are the basic working units of the binary translation system. Then, the binary translation system disassembles the translation units to obtain the assembler corresponding to each translation unit. Each translation unit corresponds to an assembler. Finally, the binary translation system calls the corresponding translation function to translate the obtained assembler to obtain the target program corresponding to the translation unit. The translation function can be any function in this field that is good at instruction translation, and this embodiment of the present invention does not specifically limit this.

[0070] It should be noted that when the binary translation system processes the source program to be translated, it processes it in sequence according to the segmented translation units and the order between the translation units. Specifically, after obtaining the target program corresponding to each translation unit, the binary translation system executes the target program corresponding to each translation unit in sequence according to the order of the translation units. In an optional embodiment of the present invention, the method further includes:

[0071] Step S41, determining whether the assembly program corresponding to the current translation unit has been translated;

[0072] Step S42: If the translation of the assembly program corresponding to the current translation unit is completed, the next translation unit is translated according to a preset sequence.

[0073] For the assembler corresponding to the current translation unit, the binary translation system first determines whether the assembler has been translated. If the assembler has been translated, the next translation unit is translated according to the order of the translation units, i.e., the preset order. The preset termination condition can be that the translation program exit logic of the binary translation system is satisfied, or that there are no other translation units after the current translation unit according to the preset order, etc.

[0074] In an optional embodiment of the present invention, the step S32 of segmenting the source program to be translated based on the jump instruction to obtain at least one translation unit includes:

[0075] Sub-step S321, searching and marking jump instructions in the source program to be translated;

[0076] Sub-step S322, determining whether there is a fourth jump instruction before the third jump instruction in the source program;

[0077] Sub-step S323, if the fourth jump instruction exists before the third jump instruction, extracting the third jump instruction from the source program, and extracting instructions between the third jump instruction and the fourth jump instruction to obtain a translation unit;

[0078] Sub-step S324 : If there is no fourth jump instruction before the third jump instruction, extract the first jump instruction and each instruction before it from the source program to obtain a translation unit.

[0079] The third jump instruction and the fourth jump instruction are both any jump instruction in the source program, and the fourth jump instruction is located before the third jump instruction.

[0080] In an embodiment of the present invention, the jump instructions in the source program to be translated can be used as a segmentation point to segment the source program. Specifically, the jump instructions in the source program are first searched, and the jump instructions found are marked for easy identification. Then, for each marked jump instruction, that is, the third jump instruction, it is determined whether there is a fourth jump instruction located before it. If there is a fourth jump instruction before the third jump instruction, the third jump instruction and the instructions between the third jump instruction and the fourth jump instruction are extracted from the source program to obtain a translation unit; if there is no fourth jump instruction before the third jump instruction, it means that the third jump instruction is the first jump instruction in the source program, and the third jump instruction and the instructions before it are extracted from the source program to obtain a translation unit.

[0081] In summary, an embodiment of the present invention provides a binary translation method, which can count the number of jumps from the first jump instruction to the second jump address during the execution of the first jump instruction in the host machine, wherein the number of times the first jump instruction jumps to the second jump address can also be referred to as the number of times the first jump instruction does not meet the jump condition, or the number of misses of the first jump instruction. Then, when the number of jumps to the second jump address is greater than a first preset threshold, the first jump address and the second jump address are reordered so that the address with a large number of jumps is on a jump path with a smaller overhead, thereby reducing the overall hardware overhead of the binary translation system and improving the operating efficiency of the binary translation system.

[0082] It should be noted that for the sake of simplicity, the method embodiments are described as a series of actions. However, those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in this specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0083] Device embodiment

[0084] Reference Figure 8, shows a structural block diagram of a processor of the present invention, which is applied to a binary translation system for translating a source program in a client into a target program in a host. The processor 80 may specifically include:

[0085] an instruction fetch unit 801 configured to obtain a first jump instruction, where the first jump instruction is a target program instruction in the host machine, and the first jump instruction corresponds to a first jump address and a second jump address, where the first jump address is a target jump address to which the first jump instruction is to be jumped when a jump condition is satisfied, and the second jump address is a target jump address to which the first jump instruction is to be jumped when the jump condition is not satisfied;

[0086] The processing unit 802 is used to count the number of jumps from the first jump instruction to the second jump address during the execution of the first jump instruction; if the number of jumps is greater than a first preset threshold, reorder the instructions of the first jump address and the second jump address.

[0087] In an optional embodiment of the present invention, the processing unit is specifically configured to:

[0088] Execute a custom exception service program to modify the jump direction of the first jump instruction in the memory pool, and exchange the instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

[0089] In an optional embodiment of the present invention, the processing unit is specifically configured to:

[0090] The jump condition of the first jump instruction is inverted, and the instructions stored in the first jump address and the second jump address are exchanged.

[0091] In an optional embodiment of the present invention, the processing unit is specifically configured to:

[0092] During execution of the first jump instruction, counting the number of executions of the first jump instruction and the number of jumps to the second jump address;

[0093] The number of runs and the number of jumps are recorded in a preset jump refill table.

[0094] In an optional embodiment of the present invention, the processing unit is further configured to:

[0095] If the execution count of the first jump instruction is greater than a second preset threshold, the execution count and the jump count of the first jump instruction in the jump refill table are cleared to zero.

[0096] In an optional embodiment of the present invention, the processing unit is further configured to:

[0097] The first jump instruction is converted into a second jump instruction, and the next instruction is sequentially executed, wherein the binary translation system does not count the number of executions and jumps of the second jump instruction.

[0098] In an optional embodiment of the present invention, the processing unit is further configured to:

[0099] If the jump number is less than or equal to a first preset threshold, and the currently executed instruction is the first jump instruction, determining whether the first jump instruction satisfies a jump condition;

[0100] If the first jump instruction satisfies the jump condition, jump to the first jump address, obtain the target instruction from the first jump address and execute it;

[0101] If the first jump instruction does not meet the jump condition, the expansion instruction is executed and then the program jumps to the second jump address, and the target instruction is obtained and executed from the second jump address; wherein the expansion instruction is generated during the translation process of the source program to be translated by the binary translation system.

[0102] In an optional embodiment of the present invention, the instruction fetch unit is further configured to:

[0103] Obtaining a source program to be translated, wherein the source program includes at least one jump instruction;

[0104] The processing unit is further configured to:

[0105] Splitting the source program based on the jump instruction to obtain at least one translation unit;

[0106] Disassembling the at least one translation unit to obtain an assembly program corresponding to each translation unit;

[0107] The translation function is called to translate the assembly program corresponding to each translation unit to obtain the target program corresponding to each translation unit.

[0108] In an optional embodiment of the present invention, the processing unit is specifically configured to:

[0109] Find and mark jump instructions in the source program to be translated;

[0110] Determine whether there is a fourth jump instruction before the third jump instruction in the source program, where the third jump instruction and the fourth jump instruction are any jump instructions in the source program, and the fourth jump instruction is located before the third jump instruction;

[0111] If the fourth jump instruction exists before the third jump instruction, extracting the third jump instruction from the source program to be translated, and extracting instructions between the third jump instruction and the fourth jump instruction to obtain a translation unit;

[0112] If there is no fourth jump instruction before the third jump instruction, the first jump instruction and each instruction before it are extracted from the source program to obtain a translation unit.

[0113] In an optional embodiment of the present invention, the processing unit is further configured to:

[0114] Determine whether the assembly program corresponding to the current translation unit has been translated;

[0115] If the translation of the assembler program corresponding to the current translation unit is completed, the next translation unit will be translated according to the preset order.

[0116] It should be noted that the processor 80 may further include a decoding unit 803. The decoding unit 803 is configured to decode instructions to be executed.

[0117] The processing unit 802 may include an execution unit 8021. The execution unit 8021 is configured to perform arithmetic operations.

[0118] Optionally, the processing unit 802 may further include a physical register file 8022. During instruction execution, the instruction may include source operands that need to be read from the physical register file 8022. The physical register file may also store other data related to instruction execution. For example, the execution result of the execution unit 8021 is written back to the physical register file 8022.

[0119] Optionally, the execution unit 8021 may include at least one arithmetic unit. The at least one arithmetic unit may be of different types, for example, a fixed-point arithmetic unit, a floating-point arithmetic unit, etc.

[0120] Optionally, the processor provided in the embodiment of the present invention may be a single-issue processor. A single-issue processor refers to a processor that fetches only one instruction from memory, decodes only one instruction, executes only one instruction, and writes only one operation result in one clock cycle.

[0121] It should be noted that the embodiment of the present invention does not limit the type and implementation of the processor. For example, the processor may be a microprocessor, a chip, etc.

[0122] Figure 9 Another structural block diagram of a processor provided by an embodiment of the present invention. Figure 9 The processor shown, compared to Figure 8The processor shown in FIG. 1 may be a multi-issue processor. A multi-issue processor is one that can fetch multiple instructions from memory and decode multiple instructions simultaneously within one clock cycle. Figure 9 As shown, the processor provided by the embodiment of the present invention, Figure 8 Based on the processor shown, it can also include a renaming unit 8023, a transmitting unit 8024 and a reordering unit 8025.

[0123] The renaming unit 8023 is used to rename the address of the instruction written back to the physical register file 8022.

[0124] The issuing unit 8024 is used to determine to which unit to send the instruction for execution, for example, to the execution unit for execution, or to the fixed-point operation unit in the execution unit for execution, or to the floating-point operation unit in the execution unit for execution, etc.

[0125] The reordering unit 8025 is used to mark the data of the write-back address of the instruction in the physical register file 8022 as committed according to the order of the instructions.

[0126] In summary, an embodiment of the present invention provides a processor that can count the number of jumps from the first jump instruction to the second jump address during the execution of the first jump instruction in the host machine, wherein the number of times the first jump instruction jumps to the second jump address can also be referred to as the number of times the first jump instruction does not meet the jump condition, or the number of misses of the first jump instruction. Then, when the number of jumps to the second jump address is greater than a first preset threshold, the first jump address and the second jump address are reordered so that the address with a large number of jumps is on a jump path with a smaller overhead, thereby reducing the overall hardware overhead of the binary translation system and improving the operating efficiency of the binary translation system.

[0127] As for the processor embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0128] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0129] An embodiment of the present invention provides an electronic device for binary translation. The electronic device is applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host. The electronic device includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors. The one or more programs include instructions for performing the following operations: obtaining a first jump instruction, where the first jump instruction is an instruction of the target program in the host, the first jump instruction corresponding to a first jump address and a second jump address, where the first jump address is a target jump address to which the first jump instruction is to jump when a jump condition is met, and the second jump address is a target jump address to which the first jump instruction is to jump when the jump condition is not met; during execution of the first jump instruction, counting the number of jumps from the first jump instruction to the second jump address; and if the number of jumps is greater than a first preset threshold, reordering instructions for the first jump address and the second jump address.

[0130] Figure 10 FIG2 is a block diagram of an electronic device 300 for binary translation according to an exemplary embodiment. For example, the electronic device 300 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0131] Reference Figure 10 , electronic device 300 may include one or more of the following components: a processing component 302 , a memory 304 , a power component 306 , a multimedia component 308 , an audio component 310 , an input / output (I / O) interface 312 , a sensor component 314 , and a communication component 316 .

[0132] The processing component 302 generally controls the overall operation of the electronic device 300, such as operations associated with display, phone calls, data communications, camera operation, and recording operations. The processing component 302 may include one or more processors 80 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 302 may include one or more modules to facilitate interaction between the processing component 302 and other components. For example, the processing component 302 may include a multimedia module to facilitate interaction between the multimedia component 308 and the processing component 302.

[0133] The memory 304 is configured to store various types of data to support operations on the electronic device 300. Examples of such data include instructions for any application or method operating on the electronic device 300, contact data, phone book data, messages, pictures, videos, etc. The memory 304 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0134] The power supply assembly 306 provides power to the various components of the electronic device 300. The power supply assembly 306 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 300.

[0135] The multimedia component 308 includes a screen that provides an output interface between the electronic device 300 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 308 includes a front camera and / or a rear camera. When the electronic device 300 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have a focal length and optical zoom capability.

[0136] The audio component 310 is configured to output and / or input audio signals. For example, the audio component 310 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 300 is in an operating mode, such as a call mode, a recording mode, and a voice information processing mode. The received audio signal can be further stored in the memory 304 or transmitted via the communication component 316. In some embodiments, the audio component 310 also includes a speaker for outputting audio signals.

[0137] I / O interface 312 provides an interface between processing component 302 and peripheral interface modules, such as a keyboard, click wheel, buttons, etc. These buttons may include but are not limited to: a home button, volume buttons, a start button, and a lock button.

[0138] The sensor assembly 314 includes one or more sensors for providing various aspects of status assessment for the electronic device 300. For example, the sensor assembly 314 can detect the open / closed state of the electronic device 300, the relative positioning of components, such as the display and keypad of the device 300. The sensor assembly 314 can also detect changes in the position of the electronic device 300 or a component of the electronic device 300, the presence or absence of user contact with the electronic device 300, the orientation or acceleration / deceleration of the electronic device 300, and temperature changes of the electronic device 300. The sensor assembly 314 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 314 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 314 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0139] The communication component 316 is configured to facilitate wired or wireless communication between the electronic device 300 and other devices. The electronic device 300 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 316 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 316 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0140] In an exemplary embodiment, the electronic device 300 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described methods.

[0141] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 304 including instructions, and the instructions can be executed by the processor 320 of the electronic device 300 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0142] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to perform Figure 1 The binary translation method shown.

[0143] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0144] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, apparatus, or computer program products. Thus, embodiments of the present invention may take the form of a fully hardware embodiment, a fully software embodiment, or an embodiment combining software and hardware. Furthermore, embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0145] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the process in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0146] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0147] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0148] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they become aware of the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0149] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or terminal device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0150] The above is a detailed introduction to a binary translation method, device, and electronic device provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. A binary translation method, characterized in that: Applied to a binary translation system for translating a source program in a client into a target program in a host, the method comprises: Obtaining a first jump instruction, where the first jump instruction is an instruction of a target program in the host machine, the first jump instruction corresponds to a first jump address and a second jump address, the first jump address being a target jump address to which the first jump instruction is to jump when a jump condition is satisfied, and the second jump address being a target jump address to which the first jump instruction is to jump when the jump condition is not satisfied; During execution of the first jump instruction, counting the number of jumps from the first jump instruction to the second jump address; If the jump number is greater than a first preset threshold, reordering instructions on the first jump address and the second jump address; The step of reordering the first jump address and the second jump address includes: Execute a custom exception service program to modify the jump direction of the first jump instruction in the memory pool, and exchange the instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

2. The method according to claim 1, characterized in that The step of reordering the first jump address and the second jump address further includes: The jump condition of the first jump instruction is inverted, and the instructions stored in the first jump address and the second jump address are exchanged.

3. The method according to claim 1, characterized in that The step of counting the number of jumps from the first jump instruction to the second jump address during execution of the first jump instruction includes: During execution of the first jump instruction, counting the number of executions of the first jump instruction and the number of jumps to the second jump address; The number of runs and the number of jumps are recorded in a preset jump refill table.

4. The method according to claim 3, characterized in that The method further comprises: If the execution count of the first jump instruction is greater than a second preset threshold, the execution count and the jump count of the first jump instruction in the jump refill table are cleared to zero.

5. The method according to claim 3, characterized in that After reordering the first jump address and the second jump address, the method further includes: The first jump instruction is converted into a second jump instruction, and the next instruction is sequentially executed, wherein the binary translation system does not count the number of executions and jumps of the second jump instruction.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: If the jump number is less than or equal to a first preset threshold, and the currently executed instruction is the first jump instruction, determining whether the first jump instruction satisfies a jump condition; If the first jump instruction satisfies the jump condition, jump to the first jump address, obtain the target instruction from the first jump address and execute it; If the first jump instruction does not meet the jump condition, the expansion instruction is executed and then the program jumps to the second jump address, and the target instruction is obtained and executed from the second jump address; wherein the expansion instruction is generated during the translation process of the source program to be translated by the binary translation system.

7. The method according to any one of claims 1 to 5, characterized in that Before obtaining the first jump instruction, the method further includes: Obtaining a source program to be translated, wherein the source program includes at least one jump instruction; Splitting the source program based on the jump instruction to obtain at least one translation unit; Disassembling the at least one translation unit to obtain an assembly program corresponding to each translation unit; The translation function is called to translate the assembly program corresponding to each translation unit to obtain the target program corresponding to each translation unit.

8. The method according to claim 7, characterized in that The source program is segmented based on the jump instruction to obtain at least one translation unit, including: Find and mark jump instructions in the source program to be translated; Determine whether there is a fourth jump instruction before the third jump instruction in the source program, where the third jump instruction and the fourth jump instruction are any jump instructions in the source program, and the fourth jump instruction is located before the third jump instruction; If the fourth jump instruction exists before the third jump instruction, extracting the third jump instruction from the source program, and extracting instructions between the third jump instruction and the fourth jump instruction to obtain a translation unit; If there is no fourth jump instruction before the third jump instruction, the first jump instruction and each instruction before it are extracted from the source program to obtain a translation unit.

9. The method according to claim 7, characterized in that The method further comprises: Determine whether the assembly program corresponding to the current translation unit has been translated; If the translation of the assembler program corresponding to the current translation unit is completed, the next translation unit will be translated according to the preset order.

10. A processor, characterized in that: Applied to a binary translation system for translating a source program in a client into a target program in a host, the processor includes: an instruction fetch unit, configured to obtain a first jump instruction, where the first jump instruction is an instruction of a target program in the host machine, and the first jump instruction corresponds to a first jump address and a second jump address, where the first jump address is a target jump address to which the first jump instruction is to jump when a jump condition is satisfied, and the second jump address is a target jump address to which the first jump instruction is to jump when the jump condition is not satisfied; a processing unit configured to count, during execution of the first jump instruction, the number of jumps from the first jump instruction to the second jump address; and reorder the first jump address and the second jump address if the number of jumps is greater than a first preset threshold; The processing unit is specifically configured to: Execute a custom exception service program to modify the jump direction of the first jump instruction in the memory pool, and exchange the instructions stored in the first jump address and the second jump address, so that the first jump instruction jumps to the second jump address when the jump condition is met, and jumps to the first jump address when the jump condition is not met.

11. The processor according to claim 10, wherein: The processing unit is further specifically configured to: The jump condition of the first jump instruction is inverted, and the instructions stored in the first jump address and the second jump address are exchanged.

12. An electronic device, characterized in that: The electronic device includes a memory and one or more programs, wherein the one or more programs are stored in the memory and configured to execute the binary translation method according to any one of claims 1 to 9 by one or more processors.

13. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the processor is enabled to perform the binary translation method according to any one of claims 1 to 9.

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