Branch prediction method, processor and electronic device

Abstract

The embodiment of the present invention provides a branch prediction method, a processor and an electronic device, which are applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host machine, and the method comprises: when it is determined that the source program to be translated meets a preset condition, obtaining an auxiliary jump instruction and a jump instruction; wherein the jump instruction and the auxiliary jump instruction are corresponding instructions of the host machine; the auxiliary jump instruction comprises an operand, and the operand is determined according to the predicted jump address of the client in the source program to be translated; executing the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction. The embodiment of the present invention can effectively reduce the bubbles generated by continuous jumps in the target program, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a branch prediction method, a processor and an electronic device. Background Art

[0002] The instruction set of the central processing unit (CPU) can be divided into complex instruction set computer (CISC) instructions and reduced instruction set computer (RISC) instructions from the perspective of the complexity of the instructions. Among them, CISC instructions are numerous, the applicable frequencies vary greatly, and the instruction lengths vary; RISC instructions are few, the applicable frequencies are similar, and the instruction lengths are fixed. The simpler RISC instruction set makes it easier to design multi-level pipelines and multi-level processor caches, thereby improving the performance of the microprocessor.

[0003] With the continuous development of microprocessor technology, the performance of microprocessors has become stronger and stronger. In order to enable computers to process different CPU instruction sets at the same time and improve processing efficiency, binary translation technology has emerged. This technology enables the source program of one CPU architecture to run on another CPU architecture. For example, the software ecosystem of a mature CPU architecture can be quickly migrated to a new CPU architecture. However, this technology still has technical problems such as low translation efficiency and too many redundant operations. In order to solve the problem of low efficiency of binary translators, some microprocessors provide additional binary translators in the processor core to support the optimization of translation codes. However, the hardware overhead of existing binary translators is large, and their performance needs to be improved. Summary of the invention

[0004] The embodiments of the present invention provide a branch prediction method, a processor and an electronic device, which can solve the problems of low prediction efficiency of a branch predictor and low operating efficiency of a binary translation system in the prior art.

[0005] In order to solve the above problems, an embodiment of the present invention discloses a branch prediction method, which is applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host. The method includes:

[0006] When it is determined that the source program to be translated meets the preset condition, an auxiliary jump instruction and a jump instruction are obtained; wherein the jump instruction and the auxiliary jump instruction are instructions corresponding to the host machine; the auxiliary jump instruction includes an operand, and the operand is determined according to the predicted jump address of the client in the source program to be translated;

[0007] The auxiliary jump instruction is executed to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction.

[0008] On the other hand, an embodiment of the present invention discloses a processor applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host, wherein the processor includes:

[0009] A data selector, used for obtaining an auxiliary jump instruction and a jump instruction when it is determined that the source program to be translated meets a preset condition; wherein the jump instruction and the auxiliary jump instruction are instructions corresponding to the host machine; the auxiliary jump instruction includes an operand, and the operand is determined according to a predicted jump address of the client in the source program to be translated;

[0010] A controller is used to execute the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction.

[0011] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the aforementioned branch prediction method.

[0012] An embodiment of the present invention further discloses a readable storage medium. When instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned branch prediction method.

[0013] The embodiments of the present invention include the following advantages:

[0014] The embodiment of the present invention obtains an auxiliary jump instruction and a jump instruction when it is determined that the source program to be translated meets a preset condition; the auxiliary jump instruction includes an operand, and the operand is determined according to the client predicted jump address in the source program to be translated; then, the auxiliary jump instruction is executed to modify the predicted jump address generated when the jump instruction is executed according to the operand. In the embodiment of the present invention, regardless of whether the jump instruction meets the jump condition, the target program can directly jump according to the modified predicted jump address, thereby simulating the jump process of the client jump instruction in the source program, without executing the B instruction generated by the translation, thereby effectively reducing the bubbles generated by continuous jumps, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0016] Figure 1 is a flow chart of steps of a branch prediction method embodiment of the present invention;

[0017] Figure 2 It is a branch prediction schematic diagram of a jump instruction of the present invention;

[0018] Figure 3 It is another branch prediction schematic diagram of jump instruction of the present invention;

[0019] Figure 4 is a structural block diagram of a processor of the present invention;

[0020] Figure 5 is a structural block diagram of another processor of the present invention;

[0021] Figure 6 It is a structural block diagram of an electronic device for branch prediction provided by an example of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] Method Embodiment

[0024] Reference Figure 1 , shows a flow chart of the steps of a branch prediction method embodiment of the present invention, the method is applied to a binary translation system, and the method may specifically include the following steps:

[0025] Step 101, when it is determined that the source program to be translated meets a preset condition, an auxiliary jump instruction and a jump instruction are obtained; the auxiliary jump instruction includes an operand, and the operand is determined according to a predicted jump address of the client in the source program to be translated.

[0026] Step 102, executing the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction.

[0027] The branch prediction method provided by the embodiment of the present invention is applied to a binary translation system, and the binary translation system is used to translate a source program in a client into a target program in a host machine.

[0028] It should be noted that the source program is a binary code. The binary translation system translates the source program in the client to obtain the target program in the host. The auxiliary jump instruction and the jump instruction in the embodiment of the present invention are both host corresponding instructions. Among them, the jump instruction is a common jump instruction in the host target program, and the auxiliary jump instruction is used to adjust the predicted jump address of the jump instruction.

[0029] The jump instruction is a commonly used instruction in the instruction set. It is used to convert program execution from executing the first instruction sequence to executing the second instruction sequence / second instruction. When the binary translation system obtains the jump instruction from the instruction memory, it determines whether the jump instruction meets the jump condition. If the jump condition is met, it jumps to the target jump address and starts executing the second instruction sequence / second instruction; if the jump condition is not met, it continues to execute the next instruction in the first instruction sequence.

[0030] In the embodiment of the present invention, since the target program in the host machine is translated from the source program in the client machine, the host machine jump instruction in the present invention has a corresponding client jump instruction in the source program of the client machine. In other words, in the embodiment of the present invention, the binary translation system translates the client jump instruction in the source program to obtain the auxiliary jump instruction and the jump instruction in the target program. Among them, the source program to be translated meets the preset conditions, and there can be at least one client jump instruction in the source program, so that it can be guaranteed that the auxiliary jump instruction and the jump instruction must exist in the target program.

[0031] Optionally, for a jump instruction, its corresponding predicted jump address can be guessed by a branch predictor. Normally, the branch predictor will determine two predicted jump addresses based on the historical jump data of the jump instruction: one is the jump address when the jump condition is met; the other is the address of the instruction after the jump instruction in the instruction memory when the jump condition is not met. Exemplarily, it is assumed that of the two predicted jump addresses determined by the branch predictor, the predicted jump address when the jump condition is met is PC+offset0, and the predicted jump address when the jump condition is not met is recorded as PC+offset1; wherein PC is the address of the jump instruction, and offset0 and offset1 are both offset addresses. The next instruction to be executed is taken out from the storage space corresponding to one of the predicted jump addresses, and the predicted jump address used to take out the next instruction is recorded as the target jump address.

[0032] In the source program, after the processor judges the client jump instruction, it can directly jump to the target jump address according to the jump condition, offset address and address of the jump instruction. In the source program, the cost of going to PC+offset0 and PC+offset1 is the same. However, after the binary translation system translates the source program, the original instruction sequence is disrupted. In the target program of the host machine, the next instruction of the currently executed jump instruction and the jump instruction do not necessarily belong to the same instruction sequence. In addition, a large number of B instructions will be inserted into the translated target program. When the target program in the host machine goes to the target jump address corresponding to offset1, it needs to run one or more "b offset1" instructions first. The B instruction is also a jump instruction. Therefore, when the target program goes to the target jump address corresponding to offset1, it often needs to perform continuous jumps, and continuous jumps will produce bubbles, affecting the prediction rate of the branch predictor, and easily cause errors in the host machine when prefetching instructions, affecting the operating efficiency of the binary translation system.

[0033] Reference Figure 2 , shows a schematic diagram of branch prediction of a jump instruction provided by an embodiment of the present invention. Figure 2 As shown, in the prior art, for the general branch instruction A1 (General Branch Instruction) in the target program, it carries an offset address offset0. After the general jump instruction A1 is decoded, the branch predictor determines the two predicted jump addresses of the general jump instruction A1 according to the decoding result: PC+offset0 and PC+4, and the next instruction is taken from one of the predicted jump addresses. Among them, PC+4 is the instruction in the instruction memory whose address is adjacent to the general jump instruction A1 and is located after the general jump instruction A1. If the general jump instruction A1 meets the jump condition, the next instruction is taken from PC+offset0; if the general jump instruction A1 does not meet the jump condition, the next instruction is taken from the storage space corresponding to PC+4. By Figure 2 It can be seen that the target program cannot directly go to the target jump address corresponding to offset1. In addition, if the next instruction is taken from PC+4, since binary translation will insert a large number of B instructions, the next instruction taken out is very likely to be a B instruction, which will cause the target program to perform continuous jumps and generate bubbles, affecting the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

[0034] In order to solve this problem, the branch prediction method provided by the embodiment of the present invention adds an auxiliary jump instruction to the instruction set corresponding to the host machine, and is limited to the target program of the host machine. The auxiliary jump instruction is executed earlier than the jump instruction, so that before executing the jump instruction, the auxiliary jump instruction is executed first to modify the predicted jump address of the jump instruction according to the operand of the auxiliary jump instruction, so that when the jump instruction jumps, the target jump address to be jumped to is determined according to the modified predicted jump address and the jump condition. In the embodiment of the present invention, the operand of the auxiliary jump instruction is determined according to the predicted jump address of the client in the source program, and the predicted jump address of the client jump instruction in the source program is the predicted jump address of the client jump instruction in the source program, which is used to indicate the jump direction of the client jump instruction. Taking the client predicted jump address in the source program as an example, the predicted jump address includes PC+offset0 and PC+offset1, wherein the predicted jump address when the jump condition is met is PC+offset0, and the predicted jump address when the jump condition is not met is recorded as PC+offset1, and the operand of the auxiliary jump instruction can be determined according to PC+offset1. Before executing the jump instruction, the auxiliary jump instruction is executed first, and the predicted jump address of the jump instruction is modified according to the operand of the auxiliary jump instruction.

[0035] Reference Figure 3 , shows another branch prediction schematic diagram of a jump instruction provided by an embodiment of the present invention. Figure 3 As shown in the figure, there are two predicted jump addresses after the jump instruction (LongBranch Instruction) is modified: one is PC+offset 0, and the other is PC+offset 1. The next instruction to be executed is taken from one of the predicted jump addresses. Specifically, it is determined whether the jump instruction meets the jump condition. If the jump instruction meets the jump condition, the next instruction is taken from PC+offset 0; if the jump instruction does not meet the jump condition, the next instruction is taken from PC+offset1. Figure 3 It can be seen that by executing the auxiliary jump instruction before executing the jump instruction to modify the predicted jump address of the jump instruction, when the jump instruction does not meet the jump condition, the target program no longer executes the instruction corresponding to the default PC+4, but can directly jump to PC+offset1, thereby realizing the simulation of the jump process of the client jump instruction in the source program, without the need to execute the B instruction generated by the translation, thereby effectively reducing the bubbles caused by continuous jumps, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

[0036] In an optional embodiment of the present invention, the step 101 of obtaining the auxiliary jump instruction and the jump instruction includes:

[0037] Step S11, acquiring the auxiliary jump instruction in a first clock cycle, and acquiring the jump instruction in a second clock cycle; wherein the first clock cycle is earlier than the second clock cycle; or

[0038] Step S12: Acquire the auxiliary jump instruction and the jump instruction in the same clock cycle.

[0039] It should be noted that there are two types of processor execution modes: sequential execution and out-of-order execution. Sequential execution refers to executing instructions one by one in the order of PC fetching instructions. Out-of-order execution refers to the CPU allowing multiple instructions to be sent to each corresponding circuit unit for processing separately without following the order specified by the program.

[0040] For each instruction, it usually goes through five processing stages: the instruction fetch (IF) stage, in which instructions are read from the memory and stored in the register; the instruction decode (ID) stage, in which the fetched instructions are split and interpreted according to the predetermined instruction format; the execute (EX) stage, in which various operations specified by the instruction are completed to specifically implement the functions of the instruction; the memory access (MEM) stage, in which the address of the operand in the memory is obtained according to the instruction address code, and the operand is read from the memory for calculation; the writeback (WB) stage, in which the running result data of the execution stage is written back to the register so that it can be quickly accessed by subsequent instructions.

[0041] If the auxiliary jump instruction and the jump instruction in the present invention are executed in a sequential manner, the auxiliary jump instruction can be obtained in the first clock cycle, and the auxiliary jump instruction can be decoded, executed, accessed, written back, etc. Then, the jump instruction is obtained in the second clock cycle. The first clock cycle is earlier than the second clock cycle.

[0042] If the auxiliary jump instruction and the jump instruction in the present invention are executed in an out-of-order manner, the auxiliary jump instruction and the jump instruction can be obtained in the same clock cycle. It should be noted that the processor of out-of-order execution is disordered only in the execution stage. Before the execution stage, it is sequential, fetching instructions in order and decoding in order. In the execution stage, the prepared instructions and the instructions without correlation can be executed first. In the embodiment of the present invention, the auxiliary jump instruction is executed earlier than the jump instruction. Therefore, even if the out-of-order execution method is adopted, after the jump instruction is decoded, before the jump target is obtained, the auxiliary jump instruction has been executed. Therefore, it can be ensured that before the jump target of the jump instruction is obtained, the processor has modified the predicted jump address generated when the jump instruction is executed according to the operand of the auxiliary jump instruction, and ensures that the target jump address of the jump instruction finally determined is determined from the modified predicted jump address.

[0043] Optionally, the auxiliary jump instruction and the jump instruction satisfy the following conditions: the memory address where the auxiliary jump instruction is located is continuously adjacent to the memory address where the jump instruction is located, and the memory address of the auxiliary jump instruction is before the memory address of the jump instruction; wherein, the memory address where the auxiliary jump instruction is located and the memory address where the jump instruction is located are both within the memory storage area where the target program is located.

[0044] In an embodiment of the present invention, the memory address where the auxiliary jump instruction is located can be continuously adjacent to the memory address of the jump instruction, and the memory address of the auxiliary jump address is before the memory address of the jump instruction, so that whether it is executed in sequence or in disorder, it can be ensured that the auxiliary jump instruction is executed earlier than the jump instruction.

[0045] In an optional embodiment of the present invention, the step 101 of determining that the source program to be translated meets a preset condition includes:

[0046] Step S21, segmenting the source program to generate at least one translation unit; wherein the source program is a binary code and contains a client jump instruction;

[0047] Step S22, disassembling the translation unit to generate an assembly language translation unit;

[0048] Step S23: When the assembly language translation unit includes the disassembled client jump instruction, it is determined that the source program to be translated meets a preset condition.

[0049] The target program in the embodiment of the present invention is obtained by translating the source program in the client by the binary translation system. Specifically, after the binary translation system obtains the source program, it first divides the source program to obtain the translation unit, which is the basic working unit of the binary translation system. Then, the binary translation system disassembles the translation unit to obtain the assembly language translation unit corresponding to each translation unit. Finally, the binary translation system calls the corresponding translation function to translate the obtained assembly language translation unit to obtain the target program in the host machine. Among them, the translation function can be selected from any function in the field that is good at binary translation, and the embodiment of the present invention does not make specific limitations on this.

[0050] The branch prediction method provided by the present invention modifies the predicted jump address of the jump instruction in the target program based on the auxiliary jump instruction. Therefore, it is necessary to ensure that the target program processed in the present invention contains the jump instruction, which further requires that the source program to be translated contains the client jump instruction. It should be noted that the binary translation system performs translation processing based on the translation unit as the basic unit. Specifically, after the binary translation system translates the current translation unit, it executes each host machine instruction obtained based on the translation unit; after all the host machine instructions corresponding to the current translation unit are executed, the next translation unit is translated. Therefore, in order to ensure the effectiveness of the present invention, it can be determined that the source program to be translated meets the preset conditions when it is determined that the assembly language translation unit obtained after the current translation unit is disassembled contains the disassembled client jump instruction. If and only if the source program to be translated meets the preset conditions, it can be guaranteed that the binary translation system can obtain the auxiliary jump instruction and the jump instruction from the host machine.

[0051] Optionally, in an embodiment of the present invention, the client jump instruction in the source program to be translated can be used as a segmentation point to segment the source program, so that each generated assembly language translation unit can be guaranteed to contain the disassembled client jump instruction.

[0052] In an optional embodiment of the present invention, the client jump instruction includes a client predicted jump address to jump to; after obtaining the auxiliary jump instruction and the jump instruction, before executing the auxiliary jump instruction, the method further includes:

[0053] Step S31, translating the assembly language translation unit to obtain a target program;

[0054] Step S32, obtaining the client predicted jump address corresponding to the host predicted jump address in the target program;

[0055] Step S33, calculating an immediate number according to the host machine's predicted jump address;

[0056] Step S34, determining the immediate number as the operand of the auxiliary jump instruction.

[0057] In an embodiment of the present invention, the client predicted jump address of the client jump instruction in the source program can be used to determine the operand of the auxiliary jump instruction in the host. Specifically, before executing the auxiliary jump instruction, the host predicted jump address corresponding to the client predicted jump address in the target program can be obtained; then, an immediate number is calculated based on the host predicted jump address, and the calculated immediate number is used as the operand of the auxiliary jump instruction.

[0058] Optionally, the predicted jump address generated when the jump instruction is executed includes a first predicted jump address and a second predicted jump address; wherein the first predicted jump address is the storage address of the next assembly language translation unit adjacent to the assembly language translation unit where the jump instruction is located when the jump condition is not met; and the second predicted jump address is the storage address of the target program to which the jump instruction will jump when the jump condition is met.

[0059] In an optional embodiment of the present invention, the auxiliary jump instruction also includes an operation code; step 102 of modifying the predicted jump address generated when the jump instruction is executed according to the operand includes: according to the operation code, writing the operand into the first predicted jump address position of the branch predictor to modify the first predicted jump address of the jump instruction.

[0060] It should be noted that the branch prediction method provided by the embodiment of the present invention is mainly used to avoid the need to execute one or more B instructions additionally to perform continuous jumps when the jump instruction in the host machine does not meet the jump condition, resulting in empty bubbles. Therefore, the predicted jump address of the jump instruction is modified, mainly for the predicted jump address when the jump instruction does not meet the jump condition. Specifically, the auxiliary jump instruction is executed, and according to the operation code of the auxiliary jump instruction, the operand of the auxiliary jump instruction is written into the first predicted jump address position of the branch predictor to modify the first predicted jump address of the jump instruction. Among them, the first predicted jump address is the storage address of the next assembly language translation unit adjacent to the assembly language translation unit where the jump instruction is located when the jump instruction does not meet the jump condition.

[0061] In an optional embodiment of the present invention, writing the operand into the first predicted jump address position of the branch predictor includes:

[0062] Step S41, determining the operand as a first offset address corresponding to the first predicted jump address;

[0063] Step S42: Write the first offset address into the first predicted jump address position of the branch predictor.

[0064] The jump instruction in the present invention may be a relative jump instruction. For a relative jump instruction, its predicted jump address is determined according to the memory address and offset address of the jump instruction itself. Therefore, in an embodiment of the present invention, the operand of the auxiliary jump instruction may be determined as the first offset address corresponding to the first predicted jump address of the jump instruction, so that when the operand of the auxiliary jump instruction is written into the first predicted jump address position of the branch predictor, the determined first offset address may be written into the first predicted jump address of the branch predictor, thereby realizing the modification of the first predicted jump address of the jump instruction.

[0065] Exemplarily, assume that for a client jump instruction in a source program, the branch predictor determines that the two client predicted jump addresses of the client jump instruction are: PC+offset0 and PC+offset1. PC+offset0 is the predicted jump address when the client jump instruction meets the jump condition; PC+offset1 is the predicted jump address when the client jump instruction does not meet the jump condition; PC is the address of the client jump instruction, and offset0 and offset1 are both offset addresses. In an embodiment of the present invention, the operand of the auxiliary jump instruction in the target program is determined based on the client predicted jump address in the original source program, and the offset address offset1 in the predicted jump address when the client jump instruction does not meet the jump condition can be determined as the operand of the auxiliary jump instruction. Then, the auxiliary jump instruction is executed, and the operand is used as the first offset address corresponding to the first predicted jump address of the jump instruction in the target program, and the first offset address is written into the first predicted jump address position of the branch predictor. Figure 3 As shown, compared to Figure 2 The branch predictor determines two predicted jump addresses PC+offset0 and PC+4 for the jump instruction in the target program. After modifying the first predicted jump address of the jump instruction according to the operand offset1 of the auxiliary jump instruction, the two predicted jump addresses for the jump instruction in the branch predictor become PC+offset0 and PC+offset1. When the jump instruction does not meet the jump condition, the target program no longer executes the instruction corresponding to the default PC+4, but can directly jump to PC+offset1, realizing the simulation of the jump process of the client jump instruction in the source program.

[0066] In summary, an embodiment of the present invention provides a branch prediction method, which obtains an auxiliary jump instruction and a jump instruction when determining that a source program to be translated meets a preset condition; the auxiliary jump instruction includes an operand, and the operand is determined according to the client predicted jump address in the source program to be translated; then, the auxiliary jump instruction is executed to modify the predicted jump address generated when the jump instruction is executed according to the operand. In an embodiment of the present invention, regardless of whether the jump instruction meets the jump condition, the target program can directly jump according to the modified predicted jump address, thereby simulating the jump process of the client jump instruction in the source program, without executing the B instruction generated by the translation, thereby effectively reducing the bubbles generated by continuous jumps, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

[0067] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0068] Device Embodiment

[0069] Reference Figure 4 , shows a structural block diagram of a processor of the present invention, which is applied to a binary translation system, wherein the binary translation system is used to translate a source program in a client into a target program in a host, and the processor 40 includes:

[0070] The instruction fetch unit 401 is used to obtain the auxiliary jump instruction and the jump instruction when it is determined that the source program to be translated meets the preset condition; wherein the jump instruction and the auxiliary jump instruction are the host machine corresponding instructions; the auxiliary jump instruction includes an operand, and the operand is determined according to the client predicted jump address in the source program to be translated;

[0071] The processing unit 402 is used to execute the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction.

[0072] Optionally, the instruction fetch unit is specifically used for:

[0073] Acquire the auxiliary jump instruction in a first clock cycle, and acquire the jump instruction in a second clock cycle; wherein the first clock cycle is earlier than the second clock cycle; or

[0074] The auxiliary jump instruction and the jump instruction are acquired in the same clock cycle.

[0075] Optionally, the auxiliary jump instruction and the jump instruction satisfy the following conditions:

[0076] The memory address where the auxiliary jump instruction is located is continuously adjacent to the memory address where the jump instruction is located, and the memory address of the auxiliary jump instruction is before the memory address of the jump instruction; wherein, the memory address where the auxiliary jump instruction is located and the memory address where the jump instruction is located are both located within the memory storage area where the target program is located.

[0077] Optionally, the processing unit is specifically configured to:

[0078] The source program is segmented to generate at least one translation unit; wherein the source program is a binary code and contains a client jump instruction;

[0079] Disassembling the translation unit to generate an assembly language translation unit;

[0080] When the assembly language translation unit includes a disassembled client jump instruction, it is determined that the source program to be translated meets a preset condition.

[0081] Optionally, the client jump instruction includes a client predicted jump address to jump to;

[0082] The processing unit is also used for:

[0083] Translating the assembly language translation unit to obtain a target program; and

[0084] Obtaining the client predicted jump address corresponding to the host predicted jump address in the target program;

[0085] Calculate an immediate value according to the host machine's predicted jump address;

[0086] The immediate value is determined as an operand of the auxiliary jump instruction.

[0087] Optionally, the predicted jump address generated when the jump instruction is executed includes a first predicted jump address and a second predicted jump address;

[0088] Among them, the first predicted jump address is the storage address of the next assembly language translation unit adjacent to the assembly language translation unit where the jump instruction is located when the jump condition is not met; the second predicted jump address is the storage address of the target program to which the jump instruction will jump when the jump condition is met.

[0089] Optionally, the auxiliary jump instruction further includes an operation code; and the processing unit is specifically configured to:

[0090] The operand is written into a first predicted jump address location of a branch predictor according to the operation code to modify the first predicted jump address of the jump instruction.

[0091] Optionally, the processing unit is specifically configured to:

[0092] Determine the operand as a first offset address corresponding to the first predicted jump address;

[0093] The first offset address is written into a first predicted jump address location of the branch predictor.

[0094] It should be noted that the processor 40 may further include a decoding unit 403. The decoding unit 403 is used to decode the instruction to be executed.

[0095] The processing unit 402 may include an execution unit 4021. The execution unit 4021 is used to perform arithmetic operations.

[0096] Optionally, the processing unit 402 may further include a physical register file 4022. During the execution of an instruction, the instruction may include a source operand, which needs to be read from the physical register file 4022. The physical register file may also store other data related to the execution of the instruction. For example, the execution result of the execution unit 4021 is written back to the physical register file 4022.

[0097] Optionally, the execution unit 4021 may include at least one operation unit. The at least one operation unit may be of different types, for example, a fixed-point operation unit, a floating-point operation unit, etc.

[0098] Optionally, the processor provided by the embodiment of the present invention may be a single-issue processor. A single-issue processor refers to a processor that only fetches one instruction from a memory in one clock cycle, only decodes one instruction, only executes one instruction, and only writes one operation result.

[0099] It should be noted that the embodiment of the present invention does not limit the type and implementation of the processor. For example, the processor may be a microprocessor, a chip, etc.

[0100] Figure 5 Another structural block diagram of a processor provided by an embodiment of the present invention. Figure 5 The processor shown, compared to Figure 4 The processor shown in FIG. 1 may be a multi-issue processor. A multi-issue processor is a processor that can fetch multiple instructions from a memory and decode multiple instructions simultaneously in one clock cycle. Figure 5As shown, the processor provided by the embodiment of the present invention, Figure 4 Based on the processor shown, it can also include a renaming unit 4023, a transmitting unit 4024 and a reordering unit 4025.

[0101] The renaming unit 4023 is used to rename the address of the instruction written back to the physical register file 4022.

[0102] The issuing unit 4024 is used to determine which unit to send the instruction to for execution, for example, to the execution unit for execution, or to the fixed-point operation unit in the execution unit for execution, or to the floating-point operation unit in the execution unit for execution, and so on.

[0103] The reordering unit 4025 is used to mark the data of the write-back address of the instruction in the physical register file 4022 as committed according to the order of the instruction.

[0104] In summary, an embodiment of the present invention provides a processor, which obtains an auxiliary jump instruction and a jump instruction when determining that a source program to be translated meets a preset condition; the auxiliary jump instruction includes an operand, and the operand is determined according to the client predicted jump address in the source program to be translated; then, the auxiliary jump instruction is executed to modify the predicted jump address generated when the jump instruction is executed according to the operand. In an embodiment of the present invention, regardless of whether the jump instruction meets the jump condition, the target program can directly jump according to the modified predicted jump address, thereby simulating the jump process of the client jump instruction in the source program, without executing the B instruction generated by the translation, thereby effectively reducing the bubbles generated by continuous jumps, which is beneficial to improving the prediction rate of the branch predictor and the operating efficiency of the binary translation system.

[0105] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0106] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0107] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0108] An embodiment of the present invention provides an electronic device for branch prediction, the electronic device is applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host machine, the electronic device includes a memory, and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors, wherein the one or more programs include instructions for performing the following operations: when it is determined that the source program to be translated meets a preset condition, obtaining an auxiliary jump instruction and a jump instruction; wherein the jump instruction and the auxiliary jump instruction are corresponding instructions of the host machine; the auxiliary jump instruction includes an operand, and the operand is determined according to a predicted jump address of the client in the source program to be translated; the auxiliary jump instruction is executed to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction.

[0109] Figure 6 1 is a block diagram of an electronic device 500 for branch prediction according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0110] Reference Figure 6 , the electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input / output (I / O) interface 512 , a sensor component 514 , and a communication component 516 .

[0111] The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 may include one or more processors 40 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 502 may include one or more modules to facilitate the interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0112] The memory 504 is configured to store various types of data to support operations on the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, videos, etc. The memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0113] The power supply component 506 provides power to the various components of the electronic device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

[0114] The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera. When the electronic device 500 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0115] The audio component 510 is configured to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC), and when the electronic device 500 is in an operating mode, such as a call mode, a recording mode, and a voice information processing mode, the microphone is configured to receive an external audio signal. The received audio signal can be further stored in the memory 504 or sent via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

[0116] I / O interface 512 provides an interface between processing component 502 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0117] The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. For example, the sensor assembly 514 can detect the open / closed state of the electronic device 500, the relative positioning of the components, such as the display and keypad of the device 500, and the sensor assembly 514 can also detect the position change of the electronic device 500 or a component of the electronic device 500, the presence or absence of user contact with the electronic device 500, the orientation or acceleration / deceleration of the electronic device 500, and the temperature change of the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of a nearby object without any physical contact. The sensor assembly 514 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0118] The communication component 516 is configured to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, 2G or 3G, or a combination thereof. In an exemplary embodiment, the communication component 516 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency information processing (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0119] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, processors, or other electronic components to perform the above methods.

[0120] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, and the instructions can be executed by the processor 40 of the electronic device 500 to complete the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0121] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), enables the processor to execute Figure 1 The branch prediction method shown.

[0122] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0123] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0124] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0125] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0126] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0127] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0128] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0129] The branch prediction method, device and electronic device provided by the present invention are introduced in detail above. The principles and implementation methods of the present invention are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A branch prediction method, characterized in that: Applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host, the method comprising: When it is determined that the source program to be translated meets the preset condition, an auxiliary jump instruction and a jump instruction are obtained; wherein the jump instruction and the auxiliary jump instruction are instructions corresponding to the host machine; the auxiliary jump instruction includes an operand, and the operand is determined according to the predicted jump address of the client in the source program to be translated; Executing the auxiliary jump instruction to modify the predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction; The step of determining that the source program to be translated meets a preset condition includes: The source program is segmented to generate at least one translation unit; wherein the source program is a binary code and contains a client jump instruction; Disassembling the translation unit to generate an assembly language translation unit; The predicted jump address generated when the jump instruction is executed includes a first predicted jump address and a second predicted jump address; the first predicted jump address is the storage address of the next assembly language translation unit adjacent to the assembly language translation unit where the jump instruction is located when the jump condition is not met; the second predicted jump address is the storage address of the target program to which the jump instruction will jump when the jump condition is met; the auxiliary jump instruction also includes an operation code; the modifying the predicted jump address generated when the jump instruction is executed according to the operand includes: The operand is written into a first predicted jump address location of a branch predictor according to the operation code to modify the first predicted jump address of the jump instruction.

2. The method according to claim 1, characterized in that Get auxiliary jump instructions and jump instructions, including: Acquire the auxiliary jump instruction in a first clock cycle, and acquire the jump instruction in a second clock cycle; wherein the first clock cycle is earlier than the second clock cycle; or The auxiliary jump instruction and the jump instruction are acquired in the same clock cycle.

3. The method according to claim 1, characterized in that The auxiliary jump instruction and the jump instruction meet the following conditions: The memory address where the auxiliary jump instruction is located is continuously adjacent to the memory address where the jump instruction is located, and the memory address of the auxiliary jump instruction is before the memory address of the jump instruction; wherein, the memory address where the auxiliary jump instruction is located and the memory address where the jump instruction is located are both located within the memory storage area where the target program is located.

4. The method according to any one of claims 1 to 3, characterized in that: Determining that the source program to be translated meets the preset condition also includes: when the assembly language translation unit includes a deassembled client jump instruction, determining that the source program to be translated meets the preset condition.

5. The method according to claim 4, characterized in that The client jump instruction includes a client predicted jump address to jump to; After acquiring the auxiliary jump instruction and the jump instruction and before executing the auxiliary jump instruction, the method further includes: Translating the assembly language translation unit to obtain a target program; and Obtaining the client predicted jump address corresponding to the host predicted jump address in the target program; Calculate an immediate value according to the host machine's predicted jump address; The immediate value is determined as an operand of the auxiliary jump instruction.

6. The method according to claim 1, characterized in that Writing the operand into a first predicted jump address location of a branch predictor comprises: Determine the operand as a first offset address corresponding to the first predicted jump address; The first offset address is written into a first predicted jump address location of the branch predictor.

7. A processor, characterized in that: Applied to a binary translation system, the binary translation system is used to translate a source program in a client into a target program in a host, the processor comprising: An instruction fetch unit, configured to obtain an auxiliary jump instruction and a jump instruction when determining that the source program to be translated meets a preset condition; wherein the jump instruction and the auxiliary jump instruction are instructions corresponding to the host machine; the auxiliary jump instruction includes an operand, and the operand is determined according to a predicted jump address of the client in the source program to be translated; A processing unit, configured to execute the auxiliary jump instruction to modify a predicted jump address generated when the jump instruction is executed according to the operand; wherein the auxiliary jump instruction is executed earlier than the jump instruction; The instruction fetch unit is specifically used to segment the source program to generate at least one translation unit; wherein the source program is a binary code and contains a client jump instruction; disassemble the translation unit to generate an assembly language translation unit; The predicted jump address generated when the jump instruction is executed includes a first predicted jump address and a second predicted jump address; the first predicted jump address is the storage address of the next assembly language translation unit adjacent to the assembly language translation unit where the jump instruction is located when the jump condition is not met; the second predicted jump address is the storage address of the target program to which the jump instruction will jump when the jump condition is met; the auxiliary jump instruction also includes an operation code; the processing unit is specifically used to: according to the operation code, write the operand into the first predicted jump address position of the branch predictor to modify the first predicted jump address of the jump instruction.

8. The processor according to claim 7, characterized in that The instruction fetch unit is specifically used for: Acquire the auxiliary jump instruction in a first clock cycle, and acquire the jump instruction in a second clock cycle; wherein the first clock cycle is earlier than the second clock cycle; or The auxiliary jump instruction and the jump instruction are acquired in the same clock cycle.

9. The processor according to claim 7, characterized in that: The auxiliary jump instruction and the jump instruction meet the following conditions: The memory address where the auxiliary jump instruction is located is continuously adjacent to the memory address where the jump instruction is located, and the memory address of the auxiliary jump instruction is before the memory address of the jump instruction; wherein, the memory address where the auxiliary jump instruction is located and the memory address where the jump instruction is located are both located within the memory storage area where the target program is located.

10. The processor according to any one of claims 7 to 9, characterized in that: The processing unit is specifically used for: The source program is segmented to generate at least one translation unit; wherein the source program is a binary code and contains a client jump instruction; Disassembling the translation unit to generate an assembly language translation unit; When the assembly language translation unit includes a disassembled client jump instruction, it is determined that the source program to be translated meets a preset condition.

11. The processor according to claim 10, characterized in that The client jump instruction includes a client predicted jump address to jump to; The processing unit is also used for: Translating the assembly language translation unit to obtain a target program; and Obtaining the client predicted jump address corresponding to the host predicted jump address in the target program; Calculate an immediate value according to the host machine's predicted jump address; The immediate value is determined as an operand of the auxiliary jump instruction.

12. An electronic device, characterized in that: The electronic device comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to execute the branch prediction method according to any one of claims 1 to 6 by one or more processors.

13. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the processor is enabled to execute the branch prediction method according to any one of claims 1 to 6.

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