An instruction processing method, system, device, and medium

Abstract

The application discloses an instruction processing method, comprising the following steps: in response to obtaining a to-be-executed memory access instruction, sending the to-be-executed memory access instruction to a corresponding execution unit according to a preset field in the to-be-executed memory access instruction; in response to the corresponding execution unit receiving the to-be-executed memory access instruction, pre-processing according to the to-be-executed memory access instruction; in response to pre-processing being completed, judging whether a handshake signal sent by a control module is received; and in response to the handshake signal being received, occupying a bus to perform data memory access according to the to-be-executed memory access instruction. The application further discloses a system, a computer device and a readable storage medium. The scheme provided by the application can optimize instruction space, reduce scheduling logic, improve memory access speed, increase the flexibility of instruction execution and reduce hardware complexity.

Description

Technical Field

[0001] This invention relates to the field of processors, and more specifically to an instruction processing method, system, device, and storage medium. Background Technology

[0002] RISC-V (an open instruction set architecture based on the principles of Reduced Instruction Set Computing (RISC), with V indicating the fifth generation of RISC) is a brand-new instruction set built on the basis of continuous development and maturation of instructions. It has the advantage of being a latecomer, with a clear and simple structure. Its modular design can be freely combined as needed, making it flexible, convenient, and highly scalable. It has a complete toolchain, and due to the openness of its BSD protocol, more and more countries and companies are investing in RISC-V research.

[0003] Like other RISC architectures, the RISC-V architecture uses dedicated load and store instructions to access memory, preventing other ordinary instructions from accessing memory. This strategy simplifies processor hardware design. However, RISC-V processors do not support sequential memory access in increment or decrement modes. While this reduces hardware design complexity, high-performance superscalar processors require complex dynamic hardware scheduling to improve performance. On the other hand, commonly used vector processing involves significant data interaction and computation, demanding fast memory access and processing. RISC-V has introduced a vector extension instruction set, which includes vector memory access instructions and allows for modular customization of enabling and disabling the instruction set. Achieving compatibility between vector and ordinary memory access instructions to achieve more efficient data access processing remains a challenge in RISC-V processor implementation.

[0004] Currently, RISC-V general-purpose data access relies solely on integer memory access instructions. For hardware simplicity, it does not support sequential data access with incrementing and decrementing instructions. The need for vector operations necessitates extending RISC-V's vector memory access instructions. However, the modular nature of RISC-V's instruction set means that vector memory access instructions may be disabled with configuration changes and are not applicable to other execution units. Therefore, achieving compatibility between vector memory access and regular memory access instructions, and implementing sequential data access for general-purpose data without increasing hardware complexity to achieve higher data access efficiency, are urgent problems to be solved. Summary of the Invention

[0005] In view of this, in order to overcome at least one aspect of the above problems, embodiments of the present invention propose an instruction processing method, comprising the following steps:

[0006] In response to receiving a memory access instruction to be executed, the memory access instruction to be executed is sent to the corresponding execution unit according to the preset fields in the memory access instruction to be executed;

[0007] In response to the corresponding execution unit receiving the memory access instruction to be executed, preprocessing is performed according to the memory access instruction to be executed;

[0008] In response to the completion of preprocessing, determine whether a handshake signal sent by the control module has been received;

[0009] In response to receiving the handshake signal, the bus is occupied to access the memory according to the memory access instruction to be executed.

[0010] In some embodiments, sending the memory access instruction to be executed to the corresponding execution unit according to a preset field in the memory access instruction to be executed further includes:

[0011] In response to the fact that the memory access instruction to be executed is a first type of memory access instruction, the memory access instruction to be executed is sent to the first instruction execution unit;

[0012] In response to the memory access instruction to be executed being a second type of memory access instruction, the memory access instruction to be executed is sent to the second instruction execution unit.

[0013] In some embodiments, it also includes:

[0014] In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

[0015] In some embodiments, in response to the memory access instruction to be executed being a second type of memory access instruction, sending the memory access instruction to be executed to a second instruction execution unit further includes:

[0016] Configure the register group;

[0017] The register set is used to cache the data to be accessed.

[0018] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide an instruction processing system, comprising:

[0019] The sending module is configured to, in response to receiving a memory access instruction to be executed, send the memory access instruction to be executed to the corresponding execution unit according to a preset field in the memory access instruction to be executed;

[0020] The preprocessing module is configured to perform preprocessing based on the memory access instruction to be executed in response to the corresponding execution unit receiving the memory access instruction to be executed;

[0021] The judgment module is configured to determine whether a handshake signal sent by the control module has been received in response to the completion of preprocessing.

[0022] The memory access module is configured to, in response to receiving the handshake signal, occupy the bus to access data according to the memory access instruction to be executed.

[0023] In some embodiments, the sending module is further configured to:

[0024] In response to the fact that the memory access instruction to be executed is a first type of memory access instruction, the memory access instruction to be executed is sent to the first instruction execution unit;

[0025] In response to the memory access instruction to be executed being a second type of memory access instruction, the memory access instruction to be executed is sent to the second instruction execution unit.

[0026] In some embodiments, the sending module is further configured to:

[0027] In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

[0028] In some embodiments, the sending module is further configured to:

[0029] Configure the register group;

[0030] The register set is used to cache the data to be accessed.

[0031] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer device, comprising:

[0032] At least one processor; and

[0033] A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing steps of any of the instruction processing methods described above.

[0034] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of any of the instruction processing methods described above.

[0035] The present invention has one of the following beneficial technical effects: the solution proposed in the present invention can optimize the instruction space, reduce scheduling logic, improve memory access speed, increase the flexibility of instruction execution, and reduce hardware complexity. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart illustrating the instruction processing method provided in an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of a processor instruction pipeline architecture provided for an embodiment of the present invention;

[0039] Figure 3 A schematic diagram of the structure of an instruction processing system provided for an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of the structure of a computer device provided for an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0043] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities or parameters with the same name but different names. It is clear that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0044] According to one aspect of the present invention, embodiments of the present invention provide an instruction processing method, such as... Figure 1 As shown, it may include the following steps:

[0045] S1, in response to obtaining a memory access instruction to be executed, the memory access instruction to be executed is sent to the corresponding execution unit according to the preset field in the memory access instruction to be executed;

[0046] S2, in response to the corresponding execution unit receiving the memory access instruction to be executed, preprocessing is performed according to the memory access instruction to be executed;

[0047] S3, in response to the completion of preprocessing, determines whether a handshake signal sent by the control module has been received;

[0048] S4, in response to receiving the handshake signal, occupy the bus to access the data according to the memory access instruction to be executed.

[0049] The proposed solution adds an independent memory contiguous data access instruction execution unit to the instruction pipeline. This unit is compatible with both vector-extended memory access instructions and integer contiguous memory access instructions (custom extended instructions added by modifying the optimizer). It operates independently from the general integer memory access instruction (Load / Store) execution unit. Under the control of the memory access module, it maximizes the parallelism of memory access instructions, thereby improving memory access speed and processor execution efficiency. This optimizes the instruction space, reduces scheduling logic, increases memory access speed, enhances instruction execution flexibility, and reduces hardware complexity.

[0050] In some embodiments, such as Figure 2 As shown, based on the research of RISC-V processors, and taking into account the characteristics of vector memory access instructions, extended instructions suitable for continuous data access in memory are designed. A continuous data access instruction execution unit is designed in the instruction pipeline, which is compatible with both vector memory access instructions and custom continuous memory access instructions. It is relatively independent of the basic integer memory access instruction execution unit of RISC-V. Based on the characteristics of memory access by the two execution units, the memory access control module is used to regulate and maximize the parallelism and continuity of data access, thereby improving data access speed and ultimately increasing the processor's execution efficiency.

[0051] In some embodiments, sending the memory access instruction to be executed to the corresponding execution unit according to a preset field in the memory access instruction to be executed further includes:

[0052] In response to the fact that the memory access instruction to be executed is a first type of memory access instruction, the memory access instruction to be executed is sent to the first instruction execution unit;

[0053] In response to the memory access instruction to be executed being a second type of memory access instruction, the memory access instruction to be executed is sent to the second instruction execution unit.

[0054] In some embodiments, it also includes:

[0055] In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

[0056] Specifically, during instruction execution, after instruction fetch (IF) and decode (ID), the instruction is issued to the corresponding instruction execution unit after register decorrelation during the issue phase. Simultaneously, instruction information is cached in the scoreboard for unified instruction tracing management. At this time, as long as the Continuous Data Memory Access Instruction Execution Unit (DLSU) and the RISC-V General Integer Memory Access Instruction Execution Unit (LSU) are idle, the Issue module will not stop issuing these two types of memory access instructions, delegating memory access conflict control to the memory access control module (LSCtrl). The DLSU execution unit handles continuous data access, which involves relatively large data volumes and infrequent data exchange. Therefore, this design bypasses the L1 cache and directly connects to the L2 cache via the bus for data interaction. During communication, only the write address of the continuous write instruction needs to be returned to the L1 cache to update its status; continuous read instructions remain unaffected. In this way, on the one hand, frequent flushing of data in the L1 Cache for large amounts of data can be avoided, improving the hit rate of general memory access instructions; on the other hand, when memory access instructions conflict, their parallelism can be improved to a certain extent: when memory access instructions do not conflict, the DLSU and LSU modules execute instructions normally. When memory access instructions conflict, the address calculation process in DLSU and the virtual address translation and L1 Cache hit lookup process in LSU can be performed in parallel. Then, through the LSCtrl module, if LSU has occupied the bus first, DLSU will pause and wait when it is preparing to occupy the bus; if DLSU has occupied the bus first, LSU will continue to execute when the Load instruction hits; if it misses, it will pause and wait; when executing the Store instruction, data can be directly written to the L1 Cache, and updated to subsequent stages when the bus is idle, without affecting the execution of the Store instruction.

[0057] In some embodiments, in response to the memory access instruction to be executed being a second type of memory access instruction, sending the memory access instruction to be executed to a second instruction execution unit further includes:

[0058] Configure the register group;

[0059] The register set is used to cache the data to be accessed.

[0060] Specifically, firstly, continuous data access instructions (DLOAD / DSTORE, designed according to the reserved or predefined encoding space of the RISC-V architecture; the specific format is not detailed here) can be designed to obtain information such as the starting address, access length, and data width of the accessed memory from general-purpose registers. A register set DR (or a small FIFO / RAM) is set up for storing data to be read from or written to memory by continuous data access instructions. By modifying and optimizing the compiler, the code involving continuous data access in the application code can be compiled into code related to this instruction, optimizing the instruction space.

[0061] Secondly, a DLSU execution unit compatible with both sequential and vector memory access instructions is designed. Because it is designed for sequential memory access, the AddrGen module calculates and outputs the memory address and length of the AW or AR channel of the AXI bus based on preset memory access start address, access length, data width, and AXI data bus width. The DLDU / DSTU module receives / outputs AXI bus R / W / B channel information to complete memory data access (the specific AXI bus address and data interaction process is not detailed here). When executing sequential data access instructions, the register set DR is similar to a general-purpose register capable of storing a set of data. When executing vector memory access instructions, the register set DR is a decoupling module between the DLSU unit and the vector register set. The vector extension instruction execution unit does not need to implement other memory access execution units; it can share the DLSU and, based on the instruction information it executes, interacts with the vector registers through decoupling via DR. In other words, when data needs to be read, it can first be put into the DR from the DDR, and then the data can be fed back from the DR. When data needs to be stored, the data to be stored can first be put into the DR, and then the data can be written into the DDR from the DR.

[0062] Based on the same inventive concept, according to another aspect of the present invention, embodiments of the present invention also provide an instruction processing system 400, such as... Figure 3 As shown, it includes:

[0063] The sending module 401 is configured to send the memory access instruction to be executed to the corresponding execution unit in response to receiving the memory access instruction to be executed, according to the preset field in the memory access instruction to be executed;

[0064] The preprocessing module 402 is configured to perform preprocessing based on the memory access instruction to be executed in response to the corresponding execution unit receiving the memory access instruction to be executed.

[0065] The judgment module 403 is configured to determine whether a handshake signal sent by the control module has been received in response to the completion of preprocessing.

[0066] The memory access module 404 is configured to, in response to receiving the handshake signal, occupy the bus to access data according to the memory access instruction to be executed.

[0067] In some embodiments, the sending module 401 is further configured to:

[0068] In response to the fact that the memory access instruction to be executed is a first type of memory access instruction, the memory access instruction to be executed is sent to the first instruction execution unit;

[0069] In response to the memory access instruction to be executed being a second type of memory access instruction, the memory access instruction to be executed is sent to the second instruction execution unit.

[0070] In some embodiments, the sending module 401 is further configured to:

[0071] In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

[0072] In some embodiments, the sending module 401 is further configured to:

[0073] Configure the register group;

[0074] The register set is used to cache the data to be accessed.

[0075] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 4 As shown, embodiments of the present invention also provide a computer device 501, comprising:

[0076] At least one processor 520; and

[0077] The memory 510 stores a computer program 511 that can be run on the processor. When the processor 520 executes the program, it performs the steps of any of the instruction processing methods described above.

[0078] Based on the same inventive concept, according to another aspect of the present invention, such as Figure 5 As shown, embodiments of the present invention also provide a computer-readable storage medium 601, which stores computer program instructions 610. When the computer program instructions 610 are executed by a processor, they perform the steps of any of the instruction processing methods described above.

[0079] Finally, it should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods.

[0080] Furthermore, it should be understood that the computer-readable storage medium (e.g., memory) described herein may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.

[0081] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0082] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0083] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0084] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0085] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0086] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. An instruction processing method, characterized in that, Includes the following steps: In response to obtaining a memory access instruction to be executed, the memory access instruction to be executed is sent to the corresponding execution unit according to a preset field in the memory access instruction to be executed. If the memory access instruction to be executed is a vector extended memory access instruction or an integer contiguous memory access instruction, it is sent to the first instruction execution unit; if the memory access instruction to be executed is a RISC-V general integer memory access instruction, it is sent to the RISC-V general second instruction execution unit. In response to the corresponding execution unit receiving the memory access instruction to be executed, preprocessing is performed according to the memory access instruction to be executed; In response to the completion of preprocessing, determine whether a handshake signal sent by the control module has been received; In response to receiving the handshake signal, the bus is occupied to perform data access according to the memory access instruction to be executed. If the execution unit is the first instruction execution unit, for continuous data access, the data does not go through the L1 cache, but directly connects to the L2 cache through the bus to complete the data interaction with the DDR. Only the write address of the continuous write instruction is returned to the L1 cache update status. If the first instruction execution unit executes the vector extension memory access instruction, the data is decoupled using the preset register group to realize the data interaction with the DDR. If the first instruction execution unit executes the integer continuous memory access instruction, the register group is used for data storage. If the execution unit is the second instruction execution unit, the memory access operation is performed according to the memory access rules of the general integer memory access instruction under the RISC-V architecture.

2. The method as described in claim 1, characterized in that, Also includes: In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

3. An instruction processing system, characterized in that, include: The sending module is configured to, in response to receiving a memory access instruction to be executed, send the memory access instruction to be executed to the corresponding execution unit according to a preset field in the memory access instruction to be executed. If the memory access instruction to be executed is a vector extended memory access instruction or an integer contiguous memory access instruction, it is sent to the first instruction execution unit; if the memory access instruction to be executed is a RISC-V general integer memory access instruction, it is sent to the RISC-V general second instruction execution unit. The preprocessing module is configured to perform preprocessing based on the memory access instruction to be executed in response to the corresponding execution unit receiving the memory access instruction to be executed; The judgment module is configured to determine whether a handshake signal sent by the control module has been received in response to the completion of preprocessing. The memory access module is configured to, in response to receiving the handshake signal, occupy the bus to perform data access according to the memory access instruction to be executed. Specifically, if the execution unit is a first instruction execution unit, for continuous data access, the data does not pass through the L1 cache but directly connects to the L2 cache via the bus to complete data interaction with the DDR. Only the write address of the continuous write instruction is returned to the L1 cache update status. If the first instruction execution unit executes a vector extension memory access instruction, a preset register group is used for data decoupling to achieve data interaction with the DDR. If the first instruction execution unit executes an integer continuous memory access instruction, the register group is used for data storage. If the execution unit is a second instruction execution unit, the memory access operation is performed according to the memory access rules of general integer memory access instructions under the RISC-V architecture.

4. The system as described in claim 3, characterized in that, The sending module is also configured as follows: In response to the control module detecting that the first instruction execution unit and / or the second instruction execution unit are in a non-idle state, a signal is sent to the instruction issuing module to stop sending memory access instructions to be executed to the first instruction execution unit and / or the second instruction execution unit.

5. A computer device, comprising: At least one processor; as well as A memory storing a computer program executable on the processor, characterized in that the processor executes the program by performing the steps of the method as described in any one of claims 1-2.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it performs the steps of the method as described in any one of claims 1-2.

Images