Error resilience using adaptive LLR lookup tables

Abstract

A system and method for performing error recovery using LLRs generated from multiple read operations is provided. The method may include selecting a set of decoding factors for multiple read operations of a non-volatile memory device. The set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the results of the multiple reads, and whether the read results include soft data. The method may also include issuing a command to read user data to the non-volatile memory device based on the set of decoding factors, generating a plurality of log-likelihood ratio (LLR) values ​​from a set of preselected LLR magnitudes based on the set of decoding factors using a mapping engine, obtaining an aggregated read result according to the aggregation mode, and obtaining an LLR value from the plurality of LLR values ​​using the aggregated read result as an index.

Description

Technical Field

[0001] The present disclosure relates to error recovery in error correcting code (ECC) decoding, and more particularly to adaptively generating log-likelihood ratio (LLR) values ​​for error recovery. Background Art

[0002] The development of modern computing systems has been driven in part by the advent of storage systems based on non-volatile memory (e.g., NAND or NOR) storage devices, such as solid-state drives (SSDs) and USB flash drives, which offer improved speed and latency compared to traditional hard drives or floppy disks. A problem with these storage systems is data corruption, so error correction codes (ECC) are often used to encode the data. ECC adds redundant data, or parity data, to the user data so that a reading system can recover the user data even when many errors have been introduced (depending on the capabilities of the code used).

[0003] The encoded data retrieved from the storage device needs to be decoded. ECC decoding includes hard decision decoding and soft decision decoding. Soft decision decoding is more powerful than hard decision decoding and can recover errors that hard decision decoding cannot recover. Soft decision decoding relies on soft decision information, which is used to indicate the reliability of the bit value and is usually in the form of log-likelihood ratio (LLR). Some non-volatile storage devices can provide soft decision information, but many non-volatile storage devices cannot. In addition, the storage controller is usually used to control the error recovery process and should be able to determine which LLR values ​​may be most suitable for soft decoding operations. Therefore, there is a need in the art for the storage controller to generate LLRs based on the configuration details of the error recovery process. Summary of the Invention

[0004] The present disclosure provides a system and method for generating log-likelihood ratios (LLRs) for soft decision decoding. Various embodiments of a non-volatile memory controller can implement complex error recovery processes that require reading the same user data multiple times and generating soft decision information from the multiple read results. In some embodiments, the error recovery process can include an extended re-read operation or a multi-read operation. In a multi-read operation, a set of decoding factors can be selected and can be used from different reference voltages (V ref ) is configured to perform multiple reads from a non-volatile storage device (e.g., a NAND device) to retrieve additional data (or information associated with the original user data). Log-likelihood ratio (LLR) values ​​can be generated by an LLR engine based on a set of decoding factors. An aggregate read result can be obtained from the multiple read results and used as an index to retrieve an LLR value from the LLR values ​​generated by the LLR engine. The retrieved LLR value can be used in a soft decision decoder to recover the original failed codeword.

[0005] In one exemplary embodiment, a method is provided that may include selecting a set of decoding factors for multiple read operations to read a non-volatile memory device multiple times. The set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the results of the multiple reads, and whether the read results include soft data. The method may also include issuing a command to read user data to the non-volatile memory device based on the set of decoding factors, generating a plurality of log-likelihood ratio (LLR) values ​​using a mapping engine, the mapping engine generating the plurality of LLR values ​​from a set of preselected LLR magnitudes based on the set of decoding factors, obtaining an aggregated read result according to the aggregation mode, and obtaining an LLR value from the plurality of LLR values ​​using the aggregated read result as an index.

[0006] In another exemplary embodiment, a storage system controller is provided. The storage system controller may include a processor configured to: select a set of decoding factors for multiple read operations to read a non-volatile storage device multiple times; and issue a command to read user data to the non-volatile storage device based on the set of decoding factors. A set of decoding factors may include, but is not limited to, the total number of reads, an aggregation mode for aggregating multiple read results, and whether the read results include soft data. The storage system controller may also include a mapping engine and a soft decision decoder. The mapping engine may be configured to generate multiple log-likelihood ratio (LLR) values ​​from a set of preselected LLR amplitudes based on the set of decoding factors. The soft decision decoder may be configured to use the aggregated read result as an index to obtain an LLR value from the multiple LLR values, and perform soft decision decoding using the obtained LLR value. The aggregated read result may be obtained according to the aggregation mode.

[0007] In another exemplary embodiment, a method is provided that includes preselecting a set of log-likelihood ratio (LLR) magnitudes, initiating multiple read operations by selecting a corresponding set of decoding factors for each of multiple read operations, and issuing read instructions corresponding to the multiple read operations. Each corresponding set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the multiple read results, and whether the read results include soft data. The method may also include processing the multiple read operations in a pipelined manner using a mapping engine and a soft decision decoder. In a first stage of the pipeline, the mapping engine may generate an LLR lookup table (LUT) from the set of LLR magnitudes based on a set of decoding factors corresponding to one of the multiple read operations that have completed data reading. And in a second stage of the pipeline, the soft decision decoder may perform soft decision decoding using LLR values ​​retrieved from the LLR lookup table using the aggregated read result as an index. The aggregated read result may be obtained based on the aggregation mode in the set of decoding factors corresponding to one of the multiple read operations that have completed data reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A nonvolatile storage system according to an embodiment of the present disclosure is schematically shown.

[0009] Figure 2 Multiple reads of a single-level cell (SLC) according to one embodiment of the present disclosure are schematically illustrated.

[0010] Figure 3 Multiple reads of a multi-level cell (MLC) according to one embodiment of the present disclosure are schematically illustrated.

[0011] Figure 4 An LLR engine according to one embodiment of the present disclosure is schematically illustrated.

[0012] Figure 5 is a flowchart of a process for performing multiple read operations according to one embodiment of the present disclosure.

[0013] Figure 6 is a flowchart of a process for performing multiple multi-read operations according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0014] Now, the specific embodiment according to the present application will be described in detail with reference to the accompanying drawings. For consistency, the same elements in various figures are represented by the same reference numerals.

[0015] The present disclosure provides apparatus, systems, and methods for performing multiple read operations on data stored in a non-volatile memory (NVM) storage device that is encoded with an error correction code (ECC) (e.g., Turbo, low-density parity check (LDPC), Polar, etc.). Figure 1 A nonvolatile storage system 100 according to one embodiment of the present disclosure is schematically illustrated. The nonvolatile storage system 100 may include a nonvolatile storage controller 102 and a nonvolatile storage device 104. When the nonvolatile storage system 100 is coupled to a host, the nonvolatile storage system 100 may provide the host with data storage and / or access to stored data. The nonvolatile storage device 104 may be a nonvolatile memory (NVM)-based storage device, such as a NAND device. It should be noted that the nonvolatile storage system 100 may include multiple nonvolatile storage devices, and the nonvolatile storage device 104 may be shown as a representative of the multiple nonvolatile storage devices.

[0016] The non-volatile memory controller 102 may include a processor 106, a memory 108, an ECC engine 110, and an LLR engine 112. The processor 106 may be a computer processor, such as, but not limited to, a microprocessor or a microcontroller. The memory 108 may be a non-transitory computer-readable storage medium, such as DRAM or SRAM, to store computer-executable instructions to be executed by the processor 106.

[0017] The ECC engine 110 may include one or more ECC encoders and may also include one or more ECC decoders. The one or more ECC encoders may generate ECC data based on input data to be stored, and the ECC data (including the input data) may be stored in the non-volatile storage device 104 during a write (program) operation. The one or more ECC decoders may decode the ECC data retrieved from the non-volatile storage device 104 during a read operation and correct errors in the stored data retrieved from the non-volatile storage device 104.

[0018] In some embodiments, the non-volatile storage controller 102 may be configured to use multiple reads to generate soft decision information (e.g., LLRs), and use the generated soft decision information to feed the soft decision decoder of the ECC engine 110 to perform soft decision decoding. For example, if the hard decision decoder in the ECC engine 110 fails to decode the read result of a read operation, multiple reads may be required for the same data. In the multiple read process, multiple reads may be performed from different V refThe non-volatile device 104 is configured to perform multiple reads to retrieve additional data (or information associated with the original user data). In one embodiment, the processor 106 may execute instructions in the memory 108 to initiate multiple read operations to read the same data multiple times.

[0019] Soft decision information (e.g., LLRs) can be generated based on multiple read results from multiple read operations. The LLR engine 112 can be configured to generate multiple LLR values ​​based on characteristics of the non-volatile memory device 104, parameters of a decoding method used in the multiple read process, or both. The multiple LLR values ​​can be referred to as an LLR lookup table (LUT), and each of the multiple LLR values ​​can be accessed via an index. The characteristics of the non-volatile memory device 104 and the decoding method that affect the LLR values ​​can be referred to as decoding factors. The LLR engine 112 can generate different LLR LUTs for different sets of decoding factors, where each LLR LUT is generated based on a set of decoding factors. In various embodiments, the multiple read results from a multiple read operation can be aggregated and used as an index to retrieve an LLR value from the LLR LUT.

[0020] The non-volatile memory controller 102 may be configured to select a set of decoding factors for multiple read operations and issue a command to the non-volatile memory device 104 to read the data stored therein based on the selected set of decoding factors. For example, the processor 106 may execute software instructions in the memory 108 to select the decoding factors. The LLR engine 112 may be configured to generate soft decision information in the form of LLR values ​​based on the selected decoding factors. The ECC engine 110 may include at least one soft decision decoder, which may be configured to use the LLR values ​​obtained from the LLR engine 112 to perform soft decision decoding for multiple read operations. It should be noted that although Figure 1 The LLR engine 112 is shown external to the ECC engine 110 , but in some embodiments, the LLR engine 112 may be part of the ECC engine 110 .

[0021] Figure 2 Multiple reads of a single-level cell (SLC) according to one embodiment of the present disclosure are schematically illustrated. Figure 2 The horizontal axis in can be voltage. Figure 2 The vertical axis in can be the probability of threshold voltage. Figure 2 Curve 202 in may indicate the probability that data in a memory cell is in a first logic state, eg, logic one (eg, “1”), which may also be referred to as an erased (ER) state. Figure 2 Curve 204 in may indicate the probability of data being in a second logic state, eg, logic zero (eg, “0”), which may also be referred to as a P1 state.

[0022] The data stored in the memory cell can be read by applying a reference voltage V ref The first logic state and the second logic state can be read by the reference voltage V ref To distinguish the two adjacent states. If the threshold voltage of the memory cell is less than the read reference voltage V ref , a logic one can be obtained as a hard decision read result. If the threshold voltage of the memory cell is greater than the read reference voltage V ref , a logic zero can be obtained as a hard decision read result.

[0023] like Figure 2 As shown, curve 202 may have a value extending beyond the read reference voltage V ref and enters the tail portion 208 which can be considered to be in the second logic state region, and the curve 204 can have a voltage extending beyond the read reference voltage V ref And enters the tail portion 206 which can be regarded as being in the first logic state region. In the tail portion 206, although the threshold voltage is less than the read reference voltage V ref And the read result may be logic one (eg, “1”), the correct logic state may be the second logic state (eg, “0”). In the tail 208, although the threshold voltage is greater than the read reference voltage V ref And the hard decision read result may be logic zero (eg, “0”), and the correct logic state may be the first logic state (eg, “1”).

[0024] During the decoding process, the incorrectly marked bits can be corrected. That is, during the decoding process of the decoder in the ECC engine 110, bits in portion 306 having a threshold voltage that may have been incorrectly marked as the first logical state are flipped to the second logical state. Furthermore, bits in portion 308 having a threshold voltage that may have been incorrectly marked as the second logical state can be flipped to the first logical state. Multiple reads can help the non-volatile storage controller 102 generate soft decision information for soft decision decoding.

[0025] Figure 2 shows three read reference voltages V ref , V ref1 and V ref2 Can be used for multiple read operations. V ref1 and V ref2 Can be close to the original read reference voltage V ref and are respectively less than and greater than the original read reference voltage V ref The reference voltage for reading. Figure 2 As shown, the reference voltage V ref Compared to the reference voltage V ref1The probability of the first logic state increases and the probability of the second logic state decreases. ref Compared to the reference voltage V ref2 The probability of the second logic state increases and the probability of the first logic state decreases. Therefore, if the three reading reference voltages V ref 、V ref1 and V ref2 If all three read results are "1", then "1" may have a stronger reliability than if two-thirds or one-third of the read results are "1". ref 、V ref1 and V ref2 If three read results are all "0", then "0" may have a stronger reliability than if two-thirds or one-third of the read results are "0". It should be noted that each read reference voltage can be used to read a page of memory cells at the same time, so the same read reference voltage (e.g., V ref 、V ref1 and V ref2 ) read the same page.

[0026] In addition to providing hard decision read results, some non-volatile memory devices can also provide soft decision read results, also known as soft data. The hard decision read result can also be called hard data, and is the bit value obtained by whether the threshold voltage is less than (e.g., logic one) or greater than (e.g., logic zero) the read reference voltage. When using the original read reference voltage (e.g., V ref ), then an XOR operation may be applied to the bit values ​​obtained from the two read reference voltages on either side of the original read reference voltage. In embodiments where the nonvolatile memory device 104 can provide soft decision read results, by applying V ref1 and V ref2 The obtained bit value can be XORed. In some embodiments, the non-volatile memory device 104 can provide the XOR result as a soft-decision read result. In some other embodiments, the non-volatile memory device 104 can flip the XOR result and provide the flipped XOR result as a soft-decision read result. Regardless of whether the XOR result is flipped before being provided as a soft-decision read result, the specification of the non-volatile memory device 104 can specify whether one of "1" or "0" indicates whether the bit value obtained by the original read reference voltage can be considered reliable.

[0027] It should be noted that for subsequent reads with hard decision results, the read reference voltages other than the original read reference voltage do not need to be evenly distributed around the original read reference voltage. For example, the nonvolatile memory controller 102 may select the read reference voltage Vref1 and V ref2 are less than or greater than V ref In addition, even if the reference voltage V ref1 and V ref2 May be located at the original read reference voltage V ref On both sides, they read the original reference voltage V ref The distances may be equal, but this is not required.

[0028] Figure 3 Schematically illustrates multiple reads of a memory cell of a multi-level cell (MLC) according to an embodiment of the present disclosure. An MLC can store two data bits, which may be referred to as a least significant bit (LSB) and a most significant bit (MSB). Each MLC can be in one of four separate states S0, S1, S2, and S3. These four separate states S0, S1, S2, and S3 may have corresponding probability distribution curves 302, 304, 306, and 308. Reading data in the MLC may require three read reference voltages VR1, VR2, and VR3, where VR2 is used to read the LSB page and VR1 and VR3 are used to read the MSB page. In a multiple read operation with three reads, the read reference voltages VR2, VR3, and VR4 may be used to read the data in the MLC. 21 and VR 22 Can be used to read the LSB page, where VR2 is the original read reference voltage of the LSB page, VR 21 and VR 22 The reading reference voltages VR1 and VR2 are respectively smaller and larger than the original reading reference voltage of the LSB page. 11 and VR 12 As well as VR3, VR 31 and VR 32 Can be used to read the MSB page, where VR1 and VR3 are used as the original read reference voltages for the MSB page, VR 11 and VR 12 less than and greater than VR1, VR 31 and VR 32 smaller and larger than VR3 respectively.

[0029] In some embodiments, a memory cell may store three or more bits of data value. For example, a triple-level cell (TLC) may store three bits per cell, while a quad-level cell (QLC) may store four bits per cell. These memory cells may require more read reference voltages to read the data stored therein. For example, a TLC may require seven read reference voltages to read data in the LSB page, center significant bit (CSB) page, and MSB page, which may also be referred to as the lower page, middle page, and upper page. Embodiments using these memory cells (e.g., TLC or QLC) may also use multiple reads with different read reference voltages.

[0030] Figure 4 An LLR mapping engine 400 according to one embodiment of the present disclosure is schematically illustrated. LLR mapping engine 400 may be an embodiment of LLR engine 112. LLR mapping engine 400 may be configured to automatically and adaptively generate a table of LLR values ​​from a set of preselected LLR magnitudes based on a set of decoding factors. The mapping relationship may be fully determined by the set of decoding factors. When one set of decoding factors is changed to another set of decoding factors, LLR mapping engine 400 may also generate another table of LLR values ​​from the preselected set of LLR magnitudes.

[0031] In some embodiments, the set of preselected LLR magnitudes may also change according to a decoding factor and / or based on characteristics of the non-volatile memory device 104. For example, the set of preselected LLR magnitudes may change as the non-volatile memory device 104 undergoes more program / erase (P / E) cycles during the lifetime of the non-volatile memory device 104. In various embodiments, the set of preselected LLR magnitudes may be derived from NVM vendor specifications and NVM characterization results.

[0032] The set of preselected LLR magnitudes may be stored in a register file having a plurality of registers with LLR magnitudes of 0 to LLR magnitude M-1, where M is a positive integer. In some embodiments, the number M may be 16. In a non-exclusive example, the 16 LLR magnitudes in the plurality of registers with LLR magnitudes of 0 to LLR magnitude 15 are 0 to 15. The table of LLR values ​​generated by the LLR mapping engine 400 may include entries from LUT index 0 to LUT index N-1, where N is a positive integer. In some embodiments, the number of entries in the generated LLR value table may depend on the size of the index. For example, if the index has 9 bits, the number of entries in the generated LLR value table may be 2 to the power of 9, i.e., N may be 512. The LLR values ​​generated by the LLR mapping engine 400 may include a sign bit and, therefore, may have one more bit than the LLR magnitudes in the plurality of registers with LLR magnitudes of 0 to LLR magnitude 15. For example, if the LLR magnitudes in the plurality of registers of LLR magnitude 0 to LLR magnitude 15 have 4 bits, the LLR values ​​in the entries of LUT index 0 to LUT index N-1 may have 5 bits.

[0033] Many decoding factors may affect the LLR values ​​output from the LLR mapping engine 400. The decoding factors may determine how M inputs are mapped to N outputs, where each of the M inputs may be mapped to one or more outputs, but each of the N outputs may be mapped to only one of the M inputs. Exemplary decoding factors may include, but are not limited to, the total number of reads in a multi-read operation, the availability of hard and soft data, the reliability bit representation in soft reads (i.e., using 0 or 1 to represent a strong or weak bit in a soft read), how read results are aggregated for processing, and page type (e.g., lower / middle / upper / extra pages from different non-volatile memory device vendors). Decoding factors 0 through K-1 coupled to the LLR mapping engine 400 may be a subset of all possible decoding factors and are selected by the non-volatile memory controller 102 for each multi-read operation, where K is a positive integer. In one embodiment, a set of decoding factors (e.g., 0 through K-1) may change for each multi-read operation.

[0034] In some embodiments, the LLR mapping engine 400 can generate an LLR LUT based on a mapping algorithm using weighted index values. In this mapping algorithm, the index of each entry in the LLR LUT can be represented as a binary number, and the weighted index value can be calculated by assigning a weight to each bit value of the binary number. The sum of the weighted bit values ​​can be obtained as a weighted index value and mapped to one of the set of preselected LLR amplitudes. The weight and mapping can be uniquely determined by the set of decoding factors and based on the feature data. During operation, multiple read results of a user data bit can be aggregated to generate an aggregated read result, and this aggregated read result can be used as an index to obtain an LLR value from the generated LLR LUT.

[0035] The decoding factor regarding how the read results are aggregated for processing can be referred to as an aggregation mode. In some embodiments, the aggregation mode can be one of two modes: direct mode and indirect mode. In an embodiment where the index is 9 bits wide, the read result of one user data bit aggregate can have a bit width of 9 bits and can be represented as a 9-bit binary number: 9′b(A8A7A6A5A4A3A2A1A0). In direct mode, each read result can be individually packaged into an aggregated read result, with each read result occupying a single bit position. The first read result (e.g., A0) can be hard data, while the remaining read results (e.g., A1 to A8) can be hard data or soft data. Therefore, in direct mode, a 9-bit wide index can have a maximum of 9 reads, that is, for an LLR LUT with a 9-bit index, the maximum total number of reads in direct mode can be 9. In indirect mode, the first read result (e.g., A0) at the first position can be hard data, while the remaining read results can be accumulated (e.g., added). In one embodiment, the indirect mode can support up to 32 reads, where the results of the 2nd to 32nd reads are accumulated and placed at positions 2 to 6 (e.g., A1 to A5). That is, for an LLR LUT with a 9-bit index, the maximum total number of reads in the indirect mode can be 32.

[0036] In some embodiments, bit weights may be assigned based on the total number of reads and whether subsequent read results after the first read contain soft data. In one embodiment, if subsequent read results after the first read contain soft data, the first hard decision read result may be used as the sign bit of the obtained LLR value, the weight of the first bit may be assigned to zero (0), each weight of the other bits containing the read result may be assigned to one (1), and each weight of the remaining bits may be assigned to zero (0). If subsequent read results after the first read do not contain soft data, that is, all read results are hard data. Each weight of all bits containing the read result may be assigned to one (1), each weight of the remaining bits may be assigned to zero (0), and the sign of the obtained LLR value may be determined based on the weighted index value.

[0037] In one example, a positive LLR value may indicate that the user data bit is more likely to be a "0," while a negative LLR value may indicate that it is more likely to be a "1." The absolute value of the LLR value may provide a relative degree of confidence that the bit is a "1" or a "0." The larger the magnitude of the LLR value, the more likely the user data bit is a "1" (if the LLR is negative) or a "0" (if the LLR is positive).

[0038] In one example, referred to as Example 1, the non-volatile storage controller 102 may select a set of decoding factors for multiple read operations as follows: the total number of reads is 5, the aggregation mode is direct mode, the read results are the hard data of the first read and the soft data of the other reads, and the soft data is represented by "1" as reliable. The weights α with subscripts "i" from zero to eight are i It can be as follows: α0 is zero (0), α1 to α4 are one (1), and α5 to α8 are zero (0). For any LLR_LUT index A, its 9-bit representation is 9′b(A8A7A6A5A4A3A2A1A0), and the weighted index value can be calculated according to the following formula:

[0039] Based on the value of V, one of the preselected LLR magnitudes may be mapped to a specific LLR_LUT index. For example, for an LLR_LUT index having a decimal number of 158 (e.g., 'd158), the 9-bit binary number may be 9'b010011110, and the weighted index value may be obtained as The LLR value can be obtained by looking up a mapping table (eg, mapping table 1 below). For example, the LLR value of LLR_LUT index 'd158' can be "+15" (A0 is 0), and the binary output of mapping engine 400 is "5'b01111".

[0040] V LLR amplitude Sign bit of the LLR value 0. 1. <![CDATA[A0]]> 1. 2. <![CDATA[A0]]> 2. 3. <![CDATA[A0]]> 3. 4. <![CDATA[A0]]> 4. 15. <![CDATA[A0]]>

[0041] Mapping Table 1

[0042] In another example, referred to as Example 2, the nonvolatile storage controller 102 may select a set of decoding factors for a multi-read operation in the following manner: the total number of reads is 6, the aggregation mode is direct mode, and the read results are all hard data. i It can be as follows: α0-α5 are one (1), and α6-α8 are zero (0). For the example LLR_LUT index decimal number 158 (eg, 'd158), the 9-bit binary number can be 9'b010011110, and the weighted index value can be obtained as The LLR value can be obtained by looking up a mapping table such as Mapping Table 2 below. For example, the LLR value of LLR_LUT index 'd158 can be "-3" (V is 4, sign bit is 1) and the binary output of mapping engine 400 is "5'b10011".

[0043] V LLR amplitude Sign bit of the LLR value 0. 15. 0 1. 12. 0 2. 7. 0 3. 3. 0 4. 3. 1 5. 7. 1. 6. 15. 1.

[0044] Mapping Table 2

[0045] In some embodiments, the LLR mapping engine 400 can be a circuit block generated from a hardware description language (e.g., VHDL or VERILOG). That is, the logic for calculating weighted index values ​​from LLR indices and mapping weighted index values ​​to LLR magnitudes can be implemented in a hardware description language, and the gate units implementing the logic can be generated from the hardware description language. In some embodiments, the weights used to calculate weighted index values ​​from LLR LUT indices can be determined based on decoding factors (e.g., the total number of reads, the aggregation mode, whether the read result contains soft data, etc.). The mapping relationship can be generated by characterizing a non-volatile memory device (e.g., non-volatile memory device 104) and then converting the characterization data into an error model, which is then used to generate an application-specific LLR LUT.

[0046] Using a hardware LLR engine 112 (such as the LLR mapping engine 400) to dynamically and adaptively generate LLR LUTs can be a better solution than storing many sets of LLR LUTs and switching between them when conditions change. For example, in conventional designs, firmware needs to manage all possible LLR LUT sets and select the appropriate LUT based on different configurations. As a result, conventional designs require a large amount of storage space (e.g., in the memory 108) to store LUTs for each possible LUT set. Furthermore, when new settings are applied, the LUTs need to be reprogrammed or reconfigured. In practical applications, it is impractical for the firmware or the user to find the optimal time slot to refresh the LUT contents without affecting overall system performance.

[0047] Compared to conventional designs, embodiments of the nonvolatile memory controller 102 can adaptively fit possible decoding factor combinations to generate a complete LLR_LUT (with N entries) for decoding operations without requiring any firmware intervention. In embodiments where M is 4, only 16 LLR magnitudes need to be stored, and the firmware can update the LLR magnitudes based on the lifetime of the nonvolatile memory device. The LLR engine 112 itself (e.g., gate cells) may occupy some space within the silicon die of the nonvolatile memory controller 102, but the slight increase in die area required for LLR LUT management is well worth the cost. In embodiments of the nonvolatile memory system 100, firmware (e.g., processor 106 executing instructions from memory 108) can be configured to select decoding factor sets for multiple multi-read operations and send commands for the multi-read operations to hardware (e.g., nonvolatile memory device 104, ECC engine 110, and LLR engine 112). For example, in one embodiment, 32 commands for 32 multi-read operations can be sent to the hardware before data decoding is complete for any of the 32 commands.

[0048] For commands to be executed, the hardware of an embodiment can perform multiple read operations in a pipelined manner. The non-volatile storage device 104 can read data according to the multiple read operations, and the data can be received at the non-volatile storage controller 102 in the order of the commands or out of order. Once a command has completed the read data operation from the non-volatile storage device (e.g., 104), in one stage of the pipeline, the LLR engine 112 can generate an LLR_LUT for the multiple read operations based on the decoding factor group of the completed command. In another stage of the pipeline, the ECC engine 110 can use the aggregated read result as an index to obtain an LLR value from the adaptively generated LLR LUT and use the LLR value to decode the data completed by the command.

[0049] Figure 5 5 is a flow chart of a process 500 for performing multiple read operations according to one embodiment of the present disclosure. At block 502, a set of decoding factors may be selected for a multiple read operation to perform multiple reads of a non-volatile memory device. The set of decoding factors may include a total number of reads, an aggregation mode for aggregating the multiple read results, and whether the read results include soft data. In one embodiment, the non-volatile memory controller 102 may be configured to select multiple decoding factors for the multiple read operations. The total number of reads may specify the number of times a user data bit is read. The aggregation mode may specify whether direct mode or indirect mode is used to aggregate the multiple read results.

[0050] At block 504, a command is issued to the nonvolatile memory device to read the user data based on the set of decoding factors. For example, the nonvolatile memory controller 102 may issue a read command to the nonvolatile memory device 104 to read the user data. The read command may specify the number of times the user data should be read and whether soft data should be used based on the set of decoding factors. At block 506, a mapping engine may be used to generate a plurality of log-likelihood ratio (LLR) values. The mapping engine outputs a plurality of LLR values ​​from a set of preselected LLR magnitudes based on the set of decoding factors. Example 1 and Example 2 illustrate two examples of how the LLR mapping engine 400 may generate corresponding LLR LUTs.

[0051] At block 508, an aggregated read result may be obtained according to the aggregation mode. For example, multiple read results of multiple read operations may be received from the non-volatile storage device 104, and the read results may be aggregated according to the aggregation mode (e.g., direct mode or indirect mode). For example, if the total number of reads is 5, the results from the first read to the fifth read are 0, 1, 1, 1, 1, and the aggregation mode is direct mode, then the aggregated read result that may be obtained is 9'b000011110. If the total number of reads is 6, the results from the first read to the sixth read are 0, 1, 1, 1, 1, 0, and the aggregation mode is direct mode, then the aggregated read result that may be obtained is 9'b000011110.

[0052] At block 510, an LLR value may be obtained from the plurality of LLR values ​​using the aggregated read result as an index. In one example, if the aggregated read result for a read instruction having the decoding factor of Example 1 is a binary number 9'b000011110, the binary number 9'b000011110 may be a decimal number 'd30, and the LLR value of the LLR_LUT index 'd30 may be "+15" (A0 is 0), and a binary output "5'b01111" may be obtained from the mapping engine 400 as the LLR value. In another example, if the aggregated read result for a read instruction having the decoding factor of Example 2 is a binary number 9'b000011110, the binary number 9'b000011110 may be a decimal number 'd30, and the LLR value of the LLR_LUT index 'd30 may be "-3," and a binary output "5'b10011" may be obtained from the mapping engine 400 as the LLR value.

[0053] Figure 6FIG6 is a flow chart of a process 600 for performing multiple read operations according to one embodiment of the present disclosure. At block 602, a set of log-likelihood ratio (LLR) magnitudes may be preselected. For example, the LLR mapping engine 400 may receive the set of preselected LLR magnitudes as input. In one embodiment, firmware of the non-volatile memory controller 102 (e.g., software instructions in the memory 108 executed by the processor 106) may preselect the set of LLR magnitudes to be placed in a register bank of a plurality of registers ranging from LLR magnitude 0 to LLR magnitude M-1 based on characteristics of the non-volatile memory device and / or LLR magnitudes provided by the memory device vendor.

[0054] At block 604, a plurality of multi-read operations may be initiated. For example, firmware of the non-volatile storage controller 102 (e.g., software instructions in the memory 108 executed by the processor 106) may select a corresponding set of decoding factors for each of the plurality of multi-read operations and issue read instructions corresponding to the plurality of multi-read operations. In at least one embodiment, each corresponding set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the multi-read results, and whether the read results include soft data.

[0055] At block 606, data from the plurality of multi-read operations is processed in a pipelined manner using a mapping engine and a soft decision decoder. For example, when performing a plurality of multi-read operations, the non-volatile memory device (e.g., NVM 104) may return data from the multi-read operations separately, which may occur in the order of the read commands or out of order. When one of the plurality of multi-read operations has completed reading the data (e.g., all data from the multi-read operation has been received), in the first stage of the pipeline, the LLR engine 112 may generate an LLR lookup table (LUT) from a set of LLR magnitudes based on a set of decoding factors corresponding to the command that completed the multi-read operation. Then, in the second stage of the pipeline, the soft decision decoder may perform soft decision decoding using the LLR values ​​retrieved from the LLR LUT using the aggregated read result as an index.

[0056] The processes 500 and 600 and features of the non-volatile storage system 100 associated with multiple read operations may be implemented using software (e.g., executable by a computer processor (CPU, GPU, or both)), hardware (e.g., a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC)), firmware, or any suitable combination of the three. For example, in one embodiment, certain steps of the processes 500 and 600 and features of the non-volatile storage system 100 associated with the selection of LLR magnitudes to be fed into the LLR engine and the selection of decoding factors may be programmed into computer processor-executable instructions, stored in a non-transitory machine-readable medium (e.g., memory 108, non-volatile storage device 104, hard drive, CD, DVD, etc.), and executed by the processor 106 (e.g., a microprocessor or microcontroller) executing the executable instructions. Certain steps of processes 500 and 600 and features of non-volatile storage system 100 , such as generation of the LLR LUT and decoding using LLR values ​​from the LLR LUT, may be performed by hard circuit blocks such as LLR engine 112 and ECC engine 110 .

[0057] In one exemplary embodiment, a method is provided that may include selecting a set of decoding factors for multiple read operations to read a non-volatile memory device multiple times. The set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the results of the multiple reads, and whether the read results include soft data. The method may also include: issuing a command to read user data to the non-volatile memory device based on the set of decoding factors, generating a plurality of log-likelihood ratio (LLR) values ​​using a mapping engine, the mapping engine outputting the plurality of LLR values ​​from a set of preselected LLR magnitudes based on the set of decoding factors, obtaining an aggregated read result according to the aggregation mode, and obtaining an LLR value from the plurality of LLR values ​​using the aggregated read result as an index.

[0058] In one embodiment, the read result may include soft data, and the set of decoding factors may further include whether the soft data uses one (1) or zero (0) to indicate reliability.

[0059] In one embodiment, the aggregation mode can be a direct mode, in which multiple read results are individually placed in the aggregate read result, each read result occupying one bit position, or an indirect mode, in which the first read result is placed in the first bit position and the remaining read results are accumulated into a sum and placed in subsequent bit positions in the aggregate read result.

[0060] In one embodiment, the set of preselected LLR magnitudes may be placed into a plurality of registers of a register bank, and the register bank may be coupled to the mapping engine as an input to the mapping engine.

[0061] In one embodiment, the multiple LLR values ​​generated by the mapping engine can be entries of an LLR lookup table, and each entry of the LLR lookup table can be mapped to one of the set of preselected LLR amplitudes by a weighted index value calculated from the index of the entry, and the weighted index value is calculated and generated by a set of weighted index entries, and the weighted index entries are determined by the decoding factors and a mapping relationship determined by a mapping table.

[0062] In one embodiment, the mapping table may define a sign bit to be added to each entry in the LLR lookup table.

[0063] In one embodiment, the method may further include performing soft decision decoding using a soft decision decoder having LLR values ​​obtained from the plurality of LLR values.

[0064] In one embodiment, the mapping engine and soft decision decoder may be a two-stage pipeline of a hardware pipeline for processing data of multiple read operations.

[0065] In another exemplary embodiment, a storage system controller is provided. The storage system controller may include a processor configured to: select a set of decoding factors for multiple read operations to read a non-volatile storage device multiple times; and issue a command to read user data to the non-volatile storage device based on the set of decoding factors. A set of decoding factors may include, but is not limited to, the total number of reads, an aggregation mode for aggregating multiple read results, and whether the read results include soft data. The storage system controller may also include a mapping engine and a soft decision decoder, the mapping engine being configured to generate multiple log-likelihood ratio (LLR) values ​​from a set of preselected LLR amplitudes based on the set of decoding factors. The soft decision decoder may be configured to obtain an LLR value from the multiple LLR values ​​using the aggregated read result as an index, and perform soft decision decoding using the LLR value. The aggregated read result may be obtained according to the aggregation mode.

[0066] In one embodiment, the read result may include soft data, and the set of decoding factors may further include whether the soft data uses one (1) or zero (0) to indicate reliability.

[0067] In one embodiment, the aggregation mode can be a direct mode, in which multiple read results are individually placed in the aggregate read result, each read result occupying one bit position, or an indirect mode, in which the first read result is placed in the first bit position and the remaining read results are accumulated into a sum and placed in subsequent bit positions of the aggregate read result.

[0068] In one embodiment, the set of preselected LLR magnitudes may be placed into a plurality of registers of a register bank, and the register bank may be coupled to the mapping engine as input to the mapping engine.

[0069] In one embodiment, the multiple LLR values ​​generated by the mapping engine can be entries of an LLR lookup table, and each entry of the LLR lookup table can be mapped to one of the set of preselected LLR value amplitudes by a weighted index value calculated from the index of the entry, and the weighted index value is calculated and generated by a set of weighted index entries, and the weighted index entries are determined by the decoding factors and a mapping relationship determined by a mapping table.

[0070] In one embodiment, the mapping table may define a sign bit to be added to each entry in the LLR lookup table.

[0071] In one embodiment, the mapping engine and soft decision decoder may be a two-stage pipeline of a hardware pipeline for processing data of multiple read operations.

[0072] In another exemplary embodiment, a method is provided that includes preselecting a set of log-likelihood ratio (LLR) magnitudes, initiating multiple read operations by selecting a corresponding set of decoding factors for each of the multiple read operations, and issuing read commands corresponding to the multiple read operations. Each corresponding set of decoding factors may include, but is not limited to, a total number of reads, an aggregation mode for aggregating the multiple read results, and whether the read results include soft data. The method may also include processing the multiple read operations in a pipelined manner using a mapping engine and a soft decision decoder. In a first stage of the pipeline, the mapping engine may generate an LLR lookup table (LUT) from a set of LLR magnitudes based on a set of decoding factors corresponding to one of the multiple read operations that have completed reading data. In a second stage of the pipeline, the soft decision decoder may perform soft decision decoding using an LLR value obtained from the LLR lookup table using the aggregated read result as an index. The aggregated read result may be obtained based on the aggregation mode in the set of decoding factors corresponding to one of the multiple read operations that have completed reading data.

[0073] In one embodiment, the read result of at least one of the multiple read operations may include soft data, and a set of decoding factors corresponding to at least one of the multiple read operations may further include the soft data using one (1) or zero (0) to indicate reliability.

[0074] In one embodiment, the aggregation mode in each corresponding set of decoding factors can be a direct mode, in which multiple read results are individually placed in the aggregated read result, where each read result occupies one bit position, or an indirect mode, in which the first read result is placed in the first bit position, and the remaining read results are accumulated into a sum and placed in subsequent bit positions of the aggregated read result.

[0075] In one embodiment, the set of LLR magnitudes may be placed into a plurality of registers of a register file, and the register file may be coupled to the mapping engine as an input to the mapping engine.

[0076] In one embodiment, each entry of the LLR lookup table may be mapped to one of a set of preselected LLR magnitudes by a weighted index value calculated from the index of the entry, a weight for calculating the weighted index value may be determined based on the set of decoding factors, and the mapping may be determined based on a mapping table, and the mapping table may define a sign bit to be added to each entry of the LLR lookup table.

[0077] Any of the disclosed methods (e.g., process 600) and operations can be implemented in software comprising computer-executable instructions stored on one or more computer-readable storage media. The one or more computer-readable storage media may include non-transitory computer-readable media (e.g., removable or non-removable disks, magnetic tapes or cartridges, solid-state drives (SSDs), hybrid hard drives, CD-ROMs, CD-RWs, DVDs, or any other tangible storage media), volatile storage components (e.g., DRAM or SRAM), or non-volatile storage components (e.g., hard drives). The computer-executable instructions can be executed on a computer (e.g., any commercial computer, including a smartphone or other mobile device including computer hardware) by a computer processor (e.g., a CPU, a GPU, or both).

[0078] Embodiments according to the present disclosure may be implemented for any type of ECC code, such as, but not limited to, rectangular parity check, Turbo, low-density parity check (LDPC), Polar, and Hamming codes.

[0079] Although various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for illustrative purposes only and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

1. A method for reading data, characterized in that: include: selecting a set of decoding factors for multiple read operations to multiple read a non-volatile memory device, the set of decoding factors including a total number of reads, an aggregation mode for aggregating results of the multiple reads, and whether the read results include soft data; issuing a command to read user data to the non-volatile storage device according to the set of decoding factors; generating a plurality of log-likelihood ratio (LLR) values ​​using a mapping engine, the mapping engine outputting the plurality of LLR values ​​from a set of preselected LLR magnitudes based on the set of decoding factors; Obtaining an aggregated reading result according to the aggregation mode; as well as An LLR value is obtained from the plurality of LLR values ​​using the aggregated read result as an index.

2. The method according to claim 1, characterized in that The read result includes soft data, and the set of decoding factors also includes whether the soft data indicates reliability using one (1) or zero (0).

3. The method according to claim 1, characterized in that The aggregation mode is a direct mode or an indirect mode, wherein in the direct mode, multiple results are individually placed in the aggregate read result, each read result occupying a bit position; In the indirect mode, the first read result is placed in the first bit position, and the remaining read results are accumulated into a sum and placed in subsequent bit positions of the aggregate read result.

4. The method according to claim 1, wherein The set of preselected LLR magnitudes are placed into a plurality of registers of a register bank, and the register bank is coupled to the mapping engine as an input to the mapping engine.

5. The method according to claim 1, characterized in that The multiple LLR values ​​generated by the mapping engine are entries of an LLR lookup table, each entry of the LLR lookup table is mapped to one of the set of preselected LLR amplitudes by a weighted index value calculated from the index of the entry, the weighted index value is calculated and generated by a set of weighted index entries, and the weighted index entries are determined by the decoding factors and a mapping relationship determined by a mapping table.

6. The method according to claim 5, characterized in that The mapping table defines a sign bit to be added to each entry of the LLR lookup table.

7. The method according to claim 1, characterized in that Also included is performing soft decision decoding using a soft decision decoder having a function to obtain LLR values ​​from the plurality of LLR values.

8. The method according to claim 7, characterized in that The mapping engine and the soft decision decoder are two-stage pipelines of a hardware pipeline for processing a plurality of multiple read operation data.

9. A storage system controller, characterized in that: include: A processor configured to: selecting a set of decoding factors for multiple read operations to multiple read a non-volatile memory device, the set of decoding factors including a total number of reads, an aggregation mode for aggregating results of the multiple reads, and whether the read results include soft data; issuing a command to read user data to the non-volatile storage device according to the set of decoding factors; a mapping engine configured to generate a plurality of log-likelihood ratio (LLR) values ​​from a set of preselected LLR magnitudes based on the set of decoding factors; as well as A soft decision decoder configured to: obtaining an LLR value from the plurality of LLR values ​​using an aggregated read result as an index, the aggregated read result being obtained according to the aggregation mode; and Soft decision decoding is performed using the LLR values.

10. The storage system controller according to claim 9, wherein: The read result includes soft data, and the set of decoding factors also includes whether the soft data indicates reliability using one (1) or zero (0).

11. The storage system controller according to claim 9, wherein: The aggregation mode is a direct mode or an indirect mode, wherein in the direct mode, multiple results are individually placed in the aggregate read result, each read result occupying a bit position; In the indirect mode, the first read result is placed in the first bit position, and the remaining read results are accumulated into a sum placed in subsequent bit positions of the aggregate read result.

12. The storage system controller according to claim 9, wherein: The set of preselected LLR magnitudes are placed into a plurality of registers of a register bank, and the register bank is coupled to the mapping engine as an input to the mapping engine.

13. The storage system controller according to claim 9, wherein: The multiple LLR values ​​generated by the mapping engine are entries of an LLR lookup table, each entry of the LLR lookup table is mapped to one of the set of preselected LLR amplitudes by a weighted index value calculated from the index of the entry, the weighted index value is calculated and generated by a set of weighted index entries, and the weighted index entries are determined by the decoding factors and a mapping relationship determined by a mapping table.

14. The storage system controller according to claim 13, wherein: The mapping table defines a sign bit to be added to each entry of the LLR lookup table.

15. The storage system controller according to claim 9, wherein: The mapping engine and the soft decision decoder are two-stage pipelines of a hardware pipeline for processing a plurality of multiple read operation data.

16. A method for reading data, characterized in that: include: Preselect a set of log-likelihood ratio (LLR) values; Initiating a plurality of multi-read operations by selecting a corresponding set of decoding factors for each of the plurality of multi-read operations and issuing a read command corresponding to the plurality of multi-read operations, each corresponding set of decoding factors including a total number of reads, an aggregation mode for aggregating multi-read results, and whether the read results include soft data; as well as Processing the plurality of multiple read operations in a pipeline manner using a mapping engine and a soft decision decoder, wherein, in a first stage pipeline, the mapping engine generates an LLR lookup table (LUT) from a set of LLR magnitudes based on a set of decoding factors corresponding to one of a plurality of multiple read operations that have completed reading the data, and In the second stage pipeline, the soft decision decoder performs soft decision decoding using the LLR value obtained from the LLR lookup table using the aggregated read result as an index, and the aggregated read result is obtained according to the aggregation mode in a set of decoding factors corresponding to one of the multiple read operations that have completed reading data.

17. The method according to claim 16, characterized in that A read result of at least one of the plurality of read operations includes soft data, and a set of decoding factors corresponding to at least one of the plurality of read operations also includes whether the soft data indicates reliability using one (1) or zero (0).

18. The method according to claim 16, characterized in that The aggregation mode in each corresponding set of decoding factors is a direct mode or an indirect mode; in the direct mode, multiple results are placed individually in the aggregated read result, each read result occupying one bit position; in the indirect mode, the first read result is placed in the first bit position, and the remaining read results are accumulated into a sum and placed in subsequent bit positions of the aggregated read result.

19. The method according to claim 16, wherein The set of LLR magnitudes are placed into a plurality of registers of a register bank, and the register bank is coupled to the mapping engine as an input to the mapping engine.

20. The method according to claim 16, wherein Each entry of the LLR lookup table is mapped to one of a set of preselected LLR magnitudes by a weighted index value calculated from the index of the entry, the weight used to calculate the weighted index value is determined by the set of decoding factors, the mapping relationship is determined by a mapping table, and the mapping table defines a sign bit to be added to each entry of the LLR lookup table.

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