Pixel circuit

Abstract

The present invention relates to a pixel circuit. The pixel circuit includes: a light-emitting element; a driving transistor including a first electrode, a second electrode and a gate electrode, the first electrode being electrically connected to the light-emitting element; a second transistor including a first electrode electrically connected to a line transmitting a power supply voltage, a second electrode electrically connected to the second electrode of the driving transistor, and a gate electrode receiving a first signal; a third transistor including a first electrode electrically connected to the second electrode of the driving transistor, a second electrode electrically connected to the gate electrode of the driving transistor, and a gate electrode receiving a second signal; a storage capacitor including a first electrode and a second electrode, the first electrode of the storage capacitor being electrically connected to the gate electrode of the driving transistor; and a switching transistor including a first electrode, a second electrode and a gate electrode receiving a third signal, the first electrode of the switching transistor being electrically connected to a data line.

Description

[0001] This application is a divisional application of the patent application with application number 201710239919.X and title “Pixel circuit and driving method thereof” filed on April 13, 2017. Technical Field

[0002] Example embodiments relate to a display device. More particularly, embodiments of the inventive concept relate to a pixel circuit included in a display device and a method of driving the display device. Background Art

[0003] The pixel circuit can emit light based on the data voltage and includes a transistor (e.g., a thin film transistor, TFT) for driving the pixel circuit. According to the material used, the transistor can be divided into an amorphous silicon (a-Si) transistor, a polycrystalline silicon (poly-Si) transistor, an oxide transistor, etc.

[0004] Silicon transistors (e.g., low temperature polysilicon thin film transistors, LTPS TFTs) have high electron mobility, which enables silicon transistors to achieve high resolution of display devices. However, the mask process of silicon transistors is complex and has high manufacturing costs. Oxide transistors have high electron mobility and low leakage current, which enables oxide transistors to achieve low power of display devices. In addition, oxide transistors have a simpler mask process than the mask process of silicon transistors and have lower manufacturing costs. However, oxide transistors are typically implemented as N-type transistors (e.g., NMOS transistors) based on oxygen vacancies and zinc gaps, and it is difficult to dope P-type dopants in oxide transistors.

[0005] Because the data signal supplied to the pixel circuit is reduced due to the capacitance of the light emitting element, the pixel circuit may not emit light having a target brightness corresponding to the data signal. A new pixel circuit including an external compensation circuit has been proposed to prevent the data signal loss. Summary of the invention

[0006] Some example embodiments provide a pixel circuit having an N-type transistor and preventing a data signal from being lost.

[0007] Some example embodiments provide a method of driving a pixel circuit.

[0008] According to an example embodiment, a pixel circuit may include: a light emitting element electrically connected between a first node and a second power supply voltage; a driving transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the second node, and a gate electrode electrically connected to a third node; a first transistor including a first electrode receiving a third voltage, a second electrode electrically connected to the first node, and a gate electrode receiving a second light emitting control signal; a second transistor including a first electrode electrically connected to a first line transmitting a first power supply voltage, a second electrode electrically connected to the second node, and a gate electrode receiving the first light emitting control signal; a third transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to the third node, and a gate electrode receiving a compensation control signal; a first storage capacitor electrically connected between the third node and a fourth node; a second storage capacitor electrically connected between the fourth node and the first node; and a switching transistor including a first electrode electrically connected to a data line, a second electrode electrically connected to the fourth node, and a gate electrode receiving a scan signal.

[0009] In example embodiments, each of the driving transistor, the first transistor, the second transistor, the third transistor, and the switching transistor may be an N-channel metal oxide semiconductor (NMOS) transistor, wherein the first power supply voltage has a voltage level lower than that of the second power supply voltage.

[0010] In an example embodiment, the second transistor may be turned on in the first period and in the fourth period in response to the first light emitting control signal, and turned off in the second period and in the third period. Here, the first period may be used to initialize the third node voltage at the third node, the second period may be used to compensate the threshold voltage of the driving transistor, the third period may be used to receive the data voltage, the fourth period may be used for the light emitting element to emit light, and the first to fourth periods may be included in the operation period and may be different from each other.

[0011] In example embodiments, the first transistor may be turned on in the first period, in the second period, and in the third period, and turned off in the fourth period in response to the second light emitting control signal.

[0012] In example embodiments, the third transistor may be turned on in the first period and in the second period, and turned off in the third period and in the fourth period in response to the compensation control signal.

[0013] In example embodiments, the switching transistor may be turned on in the first period, in the second period, and in the third period in response to the scan signal, and may charge the data voltage into the first storage capacitor and the second storage capacitor.

[0014] In example embodiments, the first storage capacitor may store a threshold voltage of the driving transistor in the second period.

[0015] In example embodiments, the switching transistor may be turned on in the third period in response to the scan signal and transmit the data voltage to the fourth node.

[0016] In example embodiments, the second storage capacitor may store the data voltage in the third period.

[0017] In example embodiments, the third voltage may be equal to or lower than a threshold voltage of the light emitting element.

[0018] According to an example embodiment, a pixel circuit may include: a light emitting element electrically connected between a first node and a second power supply voltage; a driving transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to a first line transmitting the first power supply voltage, and a gate electrode electrically connected to a third node; a first transistor including a first electrode receiving a third voltage, a second electrode electrically connected to the first node, and a gate electrode receiving a second light emitting control signal; a third transistor including a first electrode receiving a reference voltage, a second electrode electrically connected to the third node, and a gate electrode receiving a compensation control signal; a storage capacitor electrically connected between the third node and a fourth node; a fifth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the fourth node, and a gate electrode receiving the first light emitting control signal; and a switching transistor including a first electrode electrically connected to a data line, a second electrode electrically connected to the fourth node, and a gate electrode receiving a scan signal.

[0019] In an example embodiment, the pixel circuit may further include: a second transistor including a first electrode electrically connected to the first line, a second electrode electrically connected to the second electrode of the driving transistor, and a gate electrode receiving the first light emission control signal. Here, the first electrode of the third transistor may be electrically connected to the second node, and the second node may be electrically connected to the second electrode of the driving transistor and the second electrode of the second transistor.

[0020] In an example embodiment, the second transistor may be turned on in the first period and in the fourth period in response to the first light emitting control signal, and turned off in the second period and in the third period. Here, the first period may be used to initialize the third node voltage at the third node, the second period may be used to compensate the threshold voltage of the driving transistor, the third period may be used to receive the data voltage, the fourth period may be used for the light emitting element to emit light, and the first to fourth periods may be included in the operation period and may be different from each other.

[0021] In example embodiments, the first transistor may be turned on in the first period, in the second period, and in the third period, and turned off in the fourth period in response to the second light emitting control signal.

[0022] In example embodiments, the third transistor may be turned on in the first period and in the second period in response to the compensation control signal, and turned off in the third period and in the fourth period.

[0023] In example embodiments, the switching transistor may be turned on in the second period in response to the scan signal, and may charge the storage capacitor.

[0024] In example embodiments, the storage capacitor may store a threshold voltage of the driving transistor in the second period.

[0025] In example embodiments, the switching transistor may be turned on in the third period in response to the scan signal and transmit the data voltage to the fourth node.

[0026] In example embodiments, the reference voltage may be equal to the third voltage, and the second light emitting control signal may have an on-level voltage during the first period, the second period, and the third period.

[0027] In an example embodiment, the third transistor may be turned on in the first period and in the second period in response to the compensation control signal, and turned off in the third period and the fourth period. Here, the first period may be used to initialize the third node voltage at the third node, and the second period may be used to compensate for the threshold voltage of the driving transistor, the third period may be used to receive the data voltage, the fourth period may be used for the light emitting element to emit light, and the third to fifth periods may be included in the operation period and may be different from each other.

[0028] In example embodiments, the fifth transistor may be turned on in the fifth period and in the fourth period in response to the first light emitting control signal, and turned off in the third period.

[0029] In example embodiments, the storage capacitor may store a threshold voltage of the driving transistor in the fifth period.

[0030] In example embodiments, the first transistor may be turned on in the third period in response to the scan signal and may transmit the third voltage to the first node, and the switching transistor may be turned on in the third period in response to the scan signal and may transmit the data voltage to the fourth node.

[0031] In example embodiments, the pixel circuit may further include a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the fourth node, and a gate electrode receiving the compensation control signal.

[0032] In an example embodiment, each of the third transistor and the sixth transistor may be turned on in the fifth period based on the compensation control signal, and may be turned off in the third period and the fourth period. Here, the fifth period may be used to initialize the third node voltage at the third node and may be used to compensate for the threshold voltage of the driving transistor, the third period may be used to receive the data voltage, the fourth period may be used for the light emitting element to emit light, and the third to fifth periods may be included in the operation period and may be different from each other.

[0033] In example embodiments, the fifth transistor may be turned on in the fourth period in response to the first light emitting control signal, and may be turned off in the fifth period and the third period.

[0034] In example embodiments, the first transistor may be turned on in the third period in response to the scan signal and may transmit the third voltage to the first node, and the switching transistor may be turned on in the third period in response to the scan signal and may transmit the data voltage to the fourth node.

[0035] According to an example embodiment, a method for driving a pixel circuit can drive a pixel circuit, the pixel circuit including: a light emitting element; a driving transistor; and a first storage capacitor and a second storage capacitor electrically connected in series between a first electrode of the driving transistor and a gate electrode of the driving transistor. The method may include: when the second electrode of the driving transistor is electrically connected to a first line transmitting a first power supply voltage, a third node voltage applied to the gate electrode of the driving transistor is initialized by electrically connecting the second electrode of the driving transistor and the gate electrode of the driving transistor; a first node voltage at a first node is maintained at a third voltage by applying a third voltage to a first node, the first node being electrically connected to the light emitting element and the first electrode of the driving transistor; when the third voltage is supplied to a fourth node, a threshold voltage of the driving transistor is compensated by disconnecting the first line from the second electrode of the driving transistor, wherein the first storage capacitor is electrically connected to the second storage capacitor at the fourth node; applying a data voltage to the fourth node; stopping supplying the third voltage to the first node; and transmitting a driving current corresponding to the third node voltage to the light emitting element by electrically connecting the first line to the second electrode of the driving transistor.

[0036] According to an example embodiment, a method for driving a pixel circuit can drive a pixel circuit, the pixel circuit including: a light emitting element; a driving transistor; and a storage capacitor electrically connected in series between a first electrode of the driving transistor and a gate electrode of the driving transistor. The method may include: when a second electrode of the driving transistor is electrically connected to a first line transmitting a first power supply voltage, initializing a third node voltage applied to the gate electrode of the driving transistor by electrically connecting the second electrode of the driving transistor and the gate electrode of the driving transistor; maintaining a first node voltage at a first node at a third voltage by applying a third voltage to the first node, the first node being electrically connected to the light emitting element and the first electrode of the driving transistor; applying a data voltage to a terminal of the storage capacitor; stopping supplying the third voltage to the first node; and transmitting a driving current corresponding to the third node voltage to the light emitting element.

[0037] According to an example embodiment, a pixel circuit may include: a light emitting element electrically connected between a first node and a second power supply voltage; a driving transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the second node, and a gate electrode electrically connected to a third node; a first transistor including a first electrode electrically connected to a first line transmitting a first power supply voltage, a second electrode electrically connected to the second node, and a gate electrode receiving a first light emitting control signal; a first storage capacitor electrically connected between the third node and a fourth node; and a switching transistor including a first electrode electrically connected to a data line, a second electrode electrically connected to the fourth node, and a gate electrode receiving a scan signal.

[0038] In example embodiments, the pixel circuit may further include a second transistor including a first electrode receiving the third voltage, a second electrode electrically connected to the first node, and a gate electrode receiving the second light emitting control signal.

[0039] In example embodiments, the pixel circuit may further include a third transistor including a first electrode electrically connected to the second node, a second electrode electrically connected to the third node, and a gate electrode receiving the compensation control signal.

[0040] In example embodiments, the pixel circuit may further include a second storage capacitor electrically connected between the first node and the fourth node.

[0041] In example embodiments, the pixel circuit may further include a fourth transistor electrically connected between the first node and the fourth node.

[0042] According to an example embodiment, a pixel circuit may include: a light emitting element electrically connected between a first node and a second power supply voltage; a driving transistor including a first electrode electrically connected to the first node, a second electrode directly connected to a first line transmitting the first power supply voltage, and a gate electrode electrically connected to a third node; a storage capacitor electrically connected between the third node and a fourth node; and a switching transistor including a first electrode electrically connected to a data line, a second electrode electrically connected to the fourth node, and a gate electrode receiving a scan signal.

[0043] In example embodiments, the pixel circuit may further include a first transistor including a first electrode receiving the third voltage, a second electrode electrically connected to the first node, and a gate electrode receiving the second light emitting control signal.

[0044] In example embodiments, the pixel circuit may further include: a second transistor including a first electrode receiving the third voltage, a second electrode electrically connected to the third node, and a gate electrode receiving the initialization signal.

[0045] In example embodiments, the pixel circuit may further include a third transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the fourth node, and a gate electrode receiving the first light emission control signal.

[0046] In example embodiments, the pixel circuit may further include a fourth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the fourth node, and a gate electrode receiving the initialization signal.

[0047] Therefore, the pixel circuit according to example embodiments may remove the influence of the parasitic capacitor (or parasitic capacitance) of the light emitting element for writing a data signal by including a first transistor for supplying a third voltage to the light emitting element in a non-light emitting period of light.

[0048] In addition, the pixel circuit can store a pixel, by including a first storage capacitor and a second storage capacitor electrically connected in series between the gate electrode and the source electrode of the driving transistor, and by receiving a data signal via a node to which the first storage capacitor and the second storage capacitor are connected, the pixel can store a compensated data signal that compensates for the threshold voltage of the driving transistor. Therefore, the pixel circuit can prevent the loss of the data signal.

[0049] Furthermore, the method of driving a pixel circuit according to example embodiments may effectively drive the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0051] Figure 1is a block diagram illustrating a display device according to example embodiments.

[0052] Figure 2A It is shown that the Figure 1 A circuit diagram of a comparative example of a pixel in a display device.

[0053] Figure 2B It is shown in Figure 2A Graph of the data voltage measured at a pixel of FIG.

[0054] Figure 3A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0055] Figure 3B It is shown Figure 3A Waveform diagram of the pixel operation.

[0056] Figure 3C It is shown in Figure 3A Graph of the data voltage measured at a pixel of FIG.

[0057] Figure 4A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0058] Figure 4B It is shown Figure 4A Waveform diagram of the pixel operation.

[0059] Figure 4C It is shown Figure 4A Waveform diagram of the pixel operation.

[0060] Figure 5A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0061] Figure 5B It is shown Figure 5A Waveform diagram of the pixel operation.

[0062] Fig. 6A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0063] Figure 6B It is shown Figure 5A Waveform diagram of the pixel operation.

[0064] Figure 7 Is shown driving Figure 3A A flowchart of an example of a method for generating pixels.

[0065] Figure 8 Is shown driving Figure 4AA flowchart of an example of a method for generating pixels. DETAILED DESCRIPTION

[0066] Hereinafter, the inventive concept will be described in detail with reference to the accompanying drawings.

[0067] Figure 1 is a block diagram illustrating a display device according to example embodiments.

[0068] refer to Figure 1 , the display device 100 may include: a display panel 110, a timing controller 120, a data driver 130, a scan driver 140, an emission driver 150 (or a light emitting driver), and a power supply 160 (or a power supply). The display device 100 may display an image based on image data provided from an external component (e.g., a graphics card). For example, the display device 100 may be an organic light emitting display device.

[0069] The display panel 110 may include scan lines S1 to Sn, data lines D1 to Dm, light emission control lines E1 to En, and pixels 111 (or pixel circuits), where each of n and m is an integer greater than or equal to 2. The pixels 111 may be disposed in crossing regions of the scan lines S1 to Sn, the data lines D1 to Dm, and the light emission control lines E1 to En, respectively.

[0070] Each of the pixels 111 may store a data signal in response to a scan signal and may emit light based on the stored data signal. FIG. 2A to FIG. 6B The configuration of the pixel 111 is described in detail.

[0071] The timing controller 120 may control the data driver 130, the scan driver 140, and the emission driver 150. The timing controller 120 may generate a scan driving control signal, a data driving control signal, and a light emitting driving control signal, and may control the data driver 130, the scan driver 140, and the emission driver 150 using the generated signals.

[0072] The data driver 130 may generate a data signal based on the image data (eg, second data DATA2) provided from the timing controller 120. The data driver 130 may provide the data signal generated in response to the data driving control signal to the display panel 110. That is, the data driver 130 may provide the data signal to the pixel 111 through the data lines D1 to Dm.

[0073] In some example embodiments, when the display device 100 adopts a digital driving technology, the data driver 130 may generate a first data voltage (e.g., a high data voltage) and a second data voltage (e.g., a low data voltage). Here, the digital driving technology may be one of the methods of driving the display device 100, providing the first data voltage and / or the second data voltage to the pixel 111 and representing a grayscale by changing the light emission time of the pixel 111.

[0074] The scan driver 140 may generate a scan signal based on a scan drive control signal. The scan drive control signal may include a start pulse and a clock signal. The scan driver 140 may include a shift register that sequentially generates a scan signal based on the start pulse and the clock signal.

[0075] The emission driver 150 may generate a light emission control signal and may provide the light emission control signal to the pixel 111 through the light emission control lines E1 to En. The pixel 111 may emit light in response to the light emission control signal having a logic high level or a logic low level depending on the type of the thin film transistor.

[0076] The power supplier 160 may generate a first power voltage ELVDD and a second power voltage ELVSS. Each of the first power voltage ELVDD and the second power voltage ELVSS may be used to drive the display panel 110 (or the display device 100). The second power voltage ELVSS may have a voltage level lower than that of the first power voltage ELVDD.

[0077] Figure 2A It is shown that the Figure 1 A circuit diagram of a comparative example of a pixel in a display device.

[0078] refer to Figure 2A , the pixel 200 may include: a driving transistor M0, a first transistor M1, a switching transistor M2, a storage capacitor CST, and a light emitting element OLED.

[0079] The driving transistor M0 may include: a first electrode electrically connected to the light emitting element OLED, a second electrode electrically connected to the first transistor M1, and a gate electrode electrically connected to the second electrode of the switching transistor M2. The first transistor M1 may include: a first electrode electrically connected to the first power supply voltage ELVDD, a second electrode electrically connected to the second electrode of the driving transistor M0, and a gate electrode receiving a light emitting control signal GC (or electrically connected to the light emitting control line En). The switching transistor M2 may include: a first electrode electrically connected to the data line Dm, a second electrode electrically connected to the gate electrode of the driving transistor M0, and a gate electrode receiving a scan signal SCAN[n] (or electrically connected to the scan line Sn). The storage capacitor CST may be electrically connected between the gate electrode of the driving transistor M0 and the first electrode of the driving transistor M0.

[0080] The switching transistor M2 may be turned on in response to the scan signal SCAN[n], and may transmit the data signal DATA to the gate electrode of the driving transistor M0. The storage capacitor CST may temporarily store the data signal DATA. The first transistor M1 may form a current path (or current flow path) between the first power supply voltage ELVDD and the driving transistor M0 in response to the light emitting control signal GC. In this case, the driving transistor M0 may transmit the driving current to the light emitting element OLED in response to the data signal DATA (i.e., the data signal DATA stored in the storage capacitor CST). The light emitting element OLED may emit light based on the driving current. Here, the light emitting element OLED may be an organic light emitting diode.

[0081] Figure 2B It is shown in Figure 2A Graph of the data voltage measured at a pixel of FIG.

[0082] refer to Figure 2B , the measurement levels V'data_H and V'data_L of the data voltages measured at the pixel 200 may be different from the supply levels Vdata_H and Vdata_L of the data voltages provided from the data driver 130. Figure 2B As shown, a first measurement level V'data_H of the data voltage measured at the pixel 200 may be lower than a first supply level Vdata_H of the data voltage supplied from the data driver 130. Similarly, a second measurement level V'data_L of the data voltage measured at the pixel 200 may be lower than a second supply level Vdata_L of the data voltage supplied from the data driver 130. Therefore, a voltage difference ΔV'data between the data voltages measured at the pixel 200 may be different from a voltage difference ΔVdata between the data voltages supplied from the data driver 130. As a result, the pixel 200 may emit light having a brightness different from a target brightness corresponding to a specific gray level.

[0083] exist Figure 2A Not shown, the light emitting element OLED may include a parasitic capacitor C OLED (or parasitic capacitance), and thus the data signal DATA supplied to the gate electrode of the driving transistor M0 may be stored in the storage capacitor CST and the parasitic capacitor C of the light emitting element OLED. OLED That is, the gate-to-source voltage Vgs of the driving transistor M0 may be different from the data signal DATA (or the data voltage Vdata). For example, the gate-to-source voltage Vgs (V'data) of the driving transistor M0 may be expressed as the following [Formula 1].

[0084] [Formula 1]

[0085]

[0086] Here, V'data represents the gate-to-source voltage of the driving transistor M0 (or the measured level V'data of the data signal DATA measured at the pixel 200), Coled represents the parasitic capacitance of the light-emitting element OLED, Cst represents the capacitance of the storage capacitor CST, and Vdata represents the supply level Vdata of the data signal DATA provided to the pixel 200.

[0087] As reference Figure 2A and 2B As described above, the pixel 200 according to the comparative example can store the data signal DATA (or the data voltages Vdata_H and Vdata_L) in the storage capacitor CST, but the stored data signal may be lost due to the parasitic capacitor CST of the light emitting element OLED. OLED and smaller than the data signal DATA provided from the data driver 130 .

[0088] Figure 3A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0089] refer to Figure 3A , the pixel 300 may include: a light emitting element OLED, a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a first storage capacitor CST1, a second storage capacitor CST2, and a switch transistor M4.

[0090] The light emitting element OLED may be electrically connected between the first node S and the second power voltage ELVSS. The light emitting element OLED may emit light corresponding to the driving current flowing through the first node S. For example, the light emitting element OLED may be an organic light emitting diode.

[0091] The driving transistor M0 may include: a first electrode electrically connected to the first node S, a second electrode electrically connected to the second node D, and a gate electrode electrically connected to the third node G. Here, the second electrode may be a drain electrode, and the first electrode may be a source electrode. The driving transistor M0 may transmit a driving current to the light emitting element OLED based on a third node voltage Vg at the third node G.

[0092] The first transistor M1 may include: a first electrode receiving a third voltage Vinit, a second electrode electrically connected to the first node S, and a gate electrode receiving a second light emitting control signal EM2. Here, the third voltage Vinit may be a parasitic capacitor C for the light emitting element OLED. OLED (or parasitic capacitance), and may be generated by the data driver 130 or by the power supply 160. The second light emitting control signal EM2 may be generated by the emission driver 150. The first transistor M1 may provide the third voltage Vinit to the first node S in response to the second light emitting control signal EM2. Therefore, the first node S may be initialized and maintained to have the third voltage Vinit, and the parasitic capacitor C of the light emitting element OLED may be generated by the data driver 130 or by the power supply 160. OLED The third voltage Vinit may be charged and maintained. In an example embodiment, the third voltage Vinit may have a voltage level equal to or lower than a threshold voltage of the light emitting element OLED. For example, the third voltage Vinit may be 0 volts [V]. Therefore, when the third voltage Vinit is supplied to the first node S, the light emitting element OLED may not emit light.

[0093] The second transistor M2 may include: a first electrode electrically connected to the first line, a second electrode electrically connected to the second node D, and a gate electrode receiving the first light emitting control signal EM1. Here, the first line may supply the first power supply voltage ELVDD. The second transistor M2 may connect the first line to the second node D in response to the first light emitting control signal EM1 (i.e., the second transistor M2 may form a flow path for the driving current).

[0094] The third transistor M3 may include a first electrode electrically connected to the second node D, a second electrode electrically connected to the third node G, and a gate electrode receiving the compensation control signal Comp. The third transistor M3 may electrically connect the second node D and the third node G in response to the compensation control signal Comp.

[0095] The first storage capacitor CST1 may be electrically connected between the third node G and the fourth node C, and the second storage capacitor CST2 may be electrically connected between the fourth node C and the first node S. The first storage capacitor CST1 and the second storage capacitor CST2 may store the data signal DATA provided through the fourth node C.

[0096] The switching transistor M4 may include: a first electrode electrically connected to the data line Dm, a second electrode electrically connected to the fourth node C, and a gate electrode receiving the scan signal SCAN[n]. The gate electrode of the switching transistor M4 may be electrically connected to the scan line Sn. The switching transistor M4 may transmit the data signal DATA to the fourth node C in response to the scan signal SCAN[n].

[0097] In some example embodiments, each of the driving transistor M0 , the first transistor M1 , the second transistor M2 , the third transistor M3 , and the switch transistor M4 may be an N-type transistor.

[0098] Figure 3B It is shown Figure 3A Waveform diagram of the pixel operation.

[0099] refer to Figure 3A and 3B , the pixel 300 may emit light during the light emitting period. The operation period may include a first period T1, a second period T2, a third period T3, and a fourth period T4.

[0100] Here, the first period T1 may be a period for initializing the third node G (or the gate electrode of the driving transistor M0). That is, in the first period T1, the pixel 300 may perform an initialization operation to initialize the data signal DATA written in the previous frame. The second period T2 may be a period for compensating the threshold voltage Vth of the driving transistor M0. That is, in the second period T2, the pixel 300 may perform a compensation operation to compensate the threshold voltage Vth of the driving transistor M0. The third period T3 may be a period for writing the data voltage DATA to the pixel 300. That is, in the third period T3, the pixel 300 may perform a write operation to store the data signal DATA provided from the external component using the first storage capacitor CST1 and the second storage capacitor CST2. The fourth period T4 may be a period for the pixel 300 to emit light. That is, in the fourth period T4, the pixel 300 may perform a light-emitting operation to emit light based on the stored data signal DATA.

[0101] In the first period T1, the first light emitting control signal EM1, the second light emitting control signal EM2, the compensation control signal Comp, and the scan signal SCAN[n] may have a logic high level, respectively. In the first period, the data signal DATA may be equal to the third voltage Vinit. Here, the logic high level may be a turn-on voltage level for turning on the transistor, and the logic low level may be a turn-off voltage level for turning off the transistor.

[0102] The second transistor M2 may be turned on in response to the first light emitting control signal EM1 having a logic high level, and a second node voltage Vd at the second node D may be equal to the first power supply voltage ELVDD.

[0103] The first transistor M1 may be turned on in response to the second light emitting control signal EM2 having a logic high level, and the first node voltage Vs at the first node S may be equal to the third voltage Vinit. In this case, the parasitic capacitor C of the light emitting element OLED OLED The third voltage Vinit may be charged.

[0104] The third transistor M3 may be turned on in response to the compensation control signal having a logic high level, and a third node voltage Vg at the third node G may be equal to the second node voltage Vd at the second node D. That is, the third node voltage Vg at the third node G may be equal to the first power supply voltage ELVDD.

[0105] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level, and a fourth node voltage Vc at the fourth node C may be equal to the third voltage Vinit.

[0106] Therefore, the pixel 300 may initialize the data signal DATA stored in the first storage capacitor CST1 and the second storage capacitor CST2 in the first period T1 (or the data signal DATA stored in the pixel 300 in the previous frame or in the previous light emitting period).

[0107] In the second period T2 , the first light emitting control signal EM1 may be changed to have a logic low level, and the second light emitting control signal EM2 , the compensation control signal Comp, and the scan signal SCAN[n] may have logic high levels, respectively. The data signal DATA may be equal to the third voltage Vinit.

[0108] Because the first transistor M1 and the switching transistor M4 are respectively maintained in the on state, the first node voltage Vs at the first node S and the fourth node voltage Vc at the fourth node C can be respectively maintained (the first node voltage Vs at the first node S in the first period T1 and the fourth node voltage Vc at the fourth node C in the first period T1 (for example, the third voltage Vinit)).

[0109] The second transistor M2 may be turned off in response to the first light emission control signal EM1 having a logic low level, and the third node voltage Vg at the third node G may be expressed as the sum of the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 according to the threshold voltage Vth of the driving transistor M0 (i.e., Vg=Vinit+Vth). In this case, the first storage capacitor CST1 may be charged with a voltage difference between the third node voltage Vg at the third node G and the fourth node voltage Vc at the fourth node C. That is, the threshold voltage Vth of the driving transistor M0 may be charged in the first storage capacitor CST1 (i.e., Vg-Vc=(Vinit+Vth)-Vinit)=Vth).

[0110] The third transistor M3 may be maintained in a turned-on state, and the second node voltage Vd at the second node D may be equal to the third node voltage Vg at the third node G. That is, the second node voltage Vd at the second node D may be represented as the sum of the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (ie, Vd=Vinit+Vth).

[0111] Therefore, the pixel 300 may store the threshold voltage Vth of the driving transistor M0 in the first storage capacitor CST1 in the second period T2. The threshold voltage Vth of the driving transistor M0 stored in the first storage capacitor CST1 may be used in a subsequent period.

[0112] In the third period T3, the first light emitting control signal EM1 may have a logic low level, the second light emitting control signal EM2 may have a logic high level, the compensation control signal Comp may be changed to have a logic low level, and the scan signal SCAN[n] may have a logic high level in a specific period. The data signal DATA may have a data voltage Vdata[n].

[0113] Since the first transistor M1 is maintained in the on state, the first node voltage Vs at the first node S may be maintained at the third voltage Vinit.

[0114] The third transistor M3 may be turned off in response to the compensation control signal Comp having a logic low level, and the second node voltage Vd at the second node D may be equal to the first node voltage Vs at the first node S. That is, the second node voltage Vd at the second node D may be changed to be equal to the third voltage Vinit.

[0115] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level in a specific period, and the fourth node voltage Vc at the fourth node C may be changed to have the data voltage Vdata[n].

[0116] The third node voltage Vg at the third node G can be represented by the fourth node voltage Vc at the fourth node C and the voltage charged in the first storage capacitor CST1. Since the first storage capacitor CST1 is charged with the threshold voltage Vth of the driving transistor M0 in the second period T2, the third node voltage Vg at the third node G can be represented as the sum of the data voltage Vdata[n] and the threshold voltage Vth of the driving transistor M0 according to the capacitor coupling of the first storage capacitor CST1 (i.e., Vg=Vdata[n]+Vth). The second storage capacitor CST2 can be charged with the voltage difference between the data voltage Vdata[n] and the third voltage Vinit (i.e., Vdata[n]-Vinit).

[0117] Therefore, the pixel 300 can use the first storage capacitor CST1 and the second storage capacitor CST2 to store the data voltage Vdata[n] in the third period T3. For example, when the third voltage Vinit is 0V, the pixel 300 can use the first storage capacitor CST1 and the second storage capacitor CST2 to store the data voltage Vdata[n] that compensates for the threshold voltage Vth of the driving transistor M0.

[0118] In the fourth period T4 , the first light emitting control signal EM1 may be changed to have a logic high level, and the second light emitting control signal EM2 , the compensation control signal Comp, and the scan signal SCAN[n] may have a logic low level.

[0119] The second transistor M2 may be turned on in response to the first light emission control signal EM1 having a logic high level, and the driving transistor M0 may transmit a driving current based on a third node voltage Vg at the third node G to the light emitting element OLED.

[0120] Since the third node voltage Vg at the third node G is equal to the sum of the data voltage Vdata[n] and the threshold voltage Vth of the driving transistor M0 (ie, Vg=Vdata[n]+Vth), the driving current may be expressed as the following [Formula 2].

[0121] [Formula 2]

[0122]

[0123] Here, Ioled denotes a driving current, each of μn, Cox, W, and L denotes a constant, Vdata[n] denotes a data voltage, Vth denotes a threshold voltage Vth of the driving transistor M0 , and Vinit denotes a third voltage Vinit.

[0124] Therefore, the driving current Ioled may be proportional to the square of the data voltage Vdata[n].

[0125] As described above, the pixel 300 can remove the parasitic capacitor C of the light emitting element OLED for writing the data voltage Vdata. OLED The first storage capacitor CST1 and the second storage capacitor CST2 can store the data voltage Vdata[n] by compensating the threshold voltage Vth of the driving transistor M0. Therefore, the pixel 300 can emit light having a brightness corresponding to the data voltage Vdata[n] without losing the data voltage Vdata[n].

[0126] Figure 3C It is shown in Figure 3A Graph of the data voltage measured at a pixel of FIG.

[0127] refer to Figure 3C , the measurement levels V'data_H and V'data_L of the data signal DATA measured at the pixel 300 may be equal to the supply levels Vdata_H and Vdata_L of the data signal DATA provided from the data driver 130. Figure 3C As shown, a first measurement level V'data_H of the data voltage measured at the pixel 300 may be equal to a first supply level Vdata_H of the data voltage provided from the data driver 130. Similarly, a second measurement level V'data_L of the data voltage measured at the pixel 300 may be equal to a second supply level Vdata_L of the data voltage provided from the data driver 130. Therefore, the pixel 300 may emit light having a target brightness corresponding to a specific grayscale level.

[0128] Figure 4A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0129] refer to Figure 4A , the pixel 400 may include: a light emitting element OLED, a driving transistor M0, a first transistor M1, a second transistor M2, a third transistor M3, a storage capacitor CST, a fifth transistor M5, and a switch transistor M4.

[0130] The light emitting element OLED, the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the storage capacitor CST and the switch transistor M4 can be connected to the reference Figure 3AThe light emitting element OLED, the driving transistor M0, the first transistor M1, the second transistor M2, the third transistor M3, the first storage capacitor CST1 and the switch transistor M4 described above are substantially the same or similar. Therefore, the repetitive description will not be repeated.

[0131] The fifth transistor M5 may include a first electrode electrically connected to the first node S, a second electrode electrically connected to the fourth node C, and a gate electrode receiving the first light emission control signal EM1. The fifth transistor M5 may electrically connect the first node S to the fourth node C in response to the first light emission control signal EM1. The fifth transistor M5 may be an N-type transistor.

[0132] Figure 4B It is shown Figure 4A Waveform diagram of the pixel operation.

[0133] refer to Figure 4A and 4B , the pixel 400 can emit light during the light-emitting period. Figure 3B As described, the operation period may include a first period T1 , a second period T2 , a third period T3 , and a fourth period T4 .

[0134] In the first period T1 , the first light emitting control signal EM1 , the second light emitting control signal EM2 , the compensation control signal Comp, and the scan signal SCAN[n] may have logic high levels, respectively.

[0135] The second transistor M2 may be turned on in response to the first light emission control signal EM1 having a logic high level, and the second node voltage Vd at the second node D may be equal to the first power supply voltage ELVDD. The first transistor M1 may be turned on in response to the second light emission control signal EM2 having a logic high level, and the first node voltage Vs at the first node S may be equal to the third voltage Vinit. The third transistor M3 may be turned on in response to the compensation control signal Comp having a logic high level, and the third node voltage Vg at the third node G may be equal to the second node voltage Vd at the second node D. That is, the third node voltage Vg at the third node G may be equal to the first power supply voltage ELVDD.

[0136] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level, and the fifth transistor M5 may be turned on in response to the first light emission control signal EM1 having a logic high level. In this case, the fourth node voltage Vc at the fourth node C may be equal to the third voltage Vinit.

[0137] Therefore, the pixel 400 may initialize the data signal DATA stored in the storage capacitor CST (or the data signal DATA stored in the pixel 400 in the previous frame or the previous light emitting period) in the first period T1.

[0138] It is shown that the fifth transistor M5 receives the first light emission control signal EM1 having a logic high level in the first period T1. However, the fifth transistor M5 is not limited thereto. For example, the fifth transistor M5 may receive a specific control signal having a logic low level. In this case, the fifth transistor M5 is turned off, and the data signal DATA may be equal to the third voltage Vinit, but according to the turn-on operation of the switching transistor M4, the fourth node voltage Vc at the fourth node C is equal to the third voltage Vinit. That is, the pixel 400 may perform an initialization operation.

[0139] In the second period T2 , the first light emitting control signal EM1 may be changed to have a logic low level, and the second light emitting control signal EM2 , the compensation control signal Comp, and the scan signal SCAN[n] may have logic high levels, respectively. The data signal DATA may be equal to the third voltage Vinit.

[0140] Because the first transistor M1 and the switching transistor M4 are respectively maintained in the on state, the first node voltage Vs at the first node S and the fourth node voltage Vc at the fourth node C can be respectively maintained (the first node voltage Vs at the first node S in the first period T1 and the fourth node voltage Vc at the fourth node C in the first period T1 (for example, the third voltage Vinit)).

[0141] The fifth transistor M5 may be turned off in response to the first light emitting control signal EM1 having a logic low level, but the fourth node voltage Vc at the fourth node C may be maintained at the third voltage Vinit according to the turn-on state of the switching transistor M4.

[0142] The second transistor M2 may be turned off in response to the first light emission control signal EM1 having a logic low level, and the third node voltage Vg at the third node G may be expressed as the sum of the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 according to the threshold voltage Vth of the driving transistor M0 (i.e., Vg=Vinit+Vth). In this case, the storage capacitor CST may be charged with a voltage difference between the third node voltage Vg at the third node G and the fourth node voltage Vc at the fourth node C. That is, the threshold voltage Vth of the driving transistor M0 may be charged in the storage capacitor CST (i.e., Vg-Vc=(Vinit+Vth)-Vinit)=Vth).

[0143] The third transistor M3 may be maintained in a turned-on state, and the second node voltage Vd at the second node D may be equal to the third node voltage Vg at the third node G. That is, the second node voltage Vd at the second node D may be represented as the sum of the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (ie, Vd=Vinit+Vth).

[0144] Therefore, the pixel 400 may store the threshold voltage Vth of the driving transistor M0 in the storage capacitor CST in the second period T2. The threshold voltage Vth of the driving transistor M0 stored in the storage capacitor CST may be used in a subsequent period.

[0145] In the third period T3, the first light emitting control signal EM1 may have a logic low level, the second light emitting control signal EM2 may have a logic high level, the compensation control signal Comp may be changed to have a logic low level, and the scan signal SCAN[n] may have a logic high level in a specific period. The data signal DATA may have a data voltage Vdata[n].

[0146] Since the first transistor M1 is maintained in the on state, the first node voltage Vs at the first node S may be maintained at the third voltage Vinit.

[0147] The third transistor M3 may be turned off in response to the compensation control signal Comp having a logic low level, and the second node voltage Vd at the second node D may be equal to the first node voltage Vs at the first node S. That is, the second node voltage Vd at the second node D may be changed to be equal to the third voltage Vinit.

[0148] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level in a specific period, and the fourth node voltage Vc at the fourth node C may be changed to have the data voltage Vdata[n].

[0149] The third node voltage Vg at the third node G may be represented by the fourth node voltage Vc at the fourth node C and the voltage charged in the storage capacitor CST. Since the storage capacitor CST is charged with the threshold voltage Vth of the driving transistor M0 in the second period T2, the third node voltage Vg at the third node G may be represented as the sum of the data voltage Vdata[n] and the voltage Vth of the driving transistor M0 according to the capacitor coupling of the storage capacitor CST (i.e., Vg=Vdata[n]+Vth).

[0150] In the fourth period T4 , the first light emitting control signal EM1 may be changed to have a logic high level, the second light emitting control signal EM2 may be changed to have a logic low level, and the compensation control signal Comp and the scan signal SCAN[n] may have a logic low level.

[0151] The second transistor M2 may be turned on in response to the first light emission control signal EM1 having a logic high level, and the driving transistor M0 may transmit a driving current based on a third node voltage Vg at the third node G to the light emitting element OLED.

[0152] Because the third node voltage Vg at the third node G is equal to the sum of the data voltage Vdata[n] and the threshold voltage Vth of the driving transistor M0 (ie, Vg=Vdata[n]+Vth), the driving current Ioled can be proportional to the square of the data voltage Vdata[n] as described in reference [Formula 2].

[0153] As described above, the pixel 400 can remove the parasitic capacitor C of the light emitting element OLED for writing the data voltage Vdata. OLED The storage capacitor CST can store the data voltage Vdata[n] by compensating the threshold voltage Vth of the driving transistor M0. Therefore, the pixel 400 can emit light having a brightness corresponding to the data voltage Vdata[n] without losing the data voltage Vdata[n].

[0154] Figure 4C It is shown Figure 4A Waveform diagram of the pixel operation.

[0155] refer to FIG. 4A to FIG. 4C The waveform of the first light emitting control signal EM1, the waveform of the second light emitting control signal EM2 and the waveform of the compensation control signal Comp can be respectively Figure 4B The waveforms of the first light emitting control signal EM1, the second light emitting control signal EM2, and the compensation control signal Comp described above are substantially the same, and therefore, the repetitive description will not be repeated.

[0156] In the first period T1, the scan signal SCAN[n] may have a logic low level. In this case, the switch transistor M4 may be turned off in response to the scan signal SCAN[n] having a logic low level. However, the fourth node voltage Vc at the fourth node C may be equal to the third voltage Vinit because the fifth transistor M5 is turned on in response to the first light emission control signal EM1 having a logic high level. That is, the pixel 400 may perform an initialization operation in the first period T1.

[0157] As reference Figure 4B As described, the pixel 400 can sequentially perform the compensation operation of the threshold voltage Vth of the driving transistor M0, the writing operation (or storage) of the data signal Vdata[n], and the light emitting operation. Therefore, the pixel 400 can emit light having a brightness corresponding to the data voltage Vdata[n] without losing the data voltage Vdata[n].

[0158] Figure 5A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0159] refer to Figure 5A , the pixel 500 may include: a light emitting element OLED, a driving transistor M0, a first transistor M1, a third transistor M3, a storage capacitor CST, a fifth transistor M5, and a switching transistor M4.

[0160] The light emitting element OLED, the driving transistor M0, the storage capacitor CST and the switching transistor M4 can be connected to the reference Figure 3A The light emitting element OLED, the driving transistor M0, the first storage capacitor CST1 and the switching transistor M4 described are substantially the same, and therefore, the repetitive description will not be repeated.

[0161] The driving transistor M0 may include a first electrode electrically connected to the first node S, a second electrode electrically connected to the first power voltage ELVDD, and a gate electrode electrically connected to the third node G. The driving transistor M0 may transmit a driving current based on a third node voltage Vg at the third node G to the light emitting element OLED.

[0162] The third transistor M3 may include a first electrode electrically connected to the third node G, a second electrode receiving a third voltage Vinit (or a reference voltage), and a gate electrode receiving an initialization signal INIT[n] (or a compensation control signal Comp). The third transistor M3 may provide the third voltage Vinit to the third node G based on the initialization signal INIT[n].

[0163] The fifth transistor M5 may include a first electrode electrically connected to the first node S, a second electrode electrically connected to the fourth node C, and a gate electrode receiving the light emitting control signal EM[n] (or the first light emitting control signal EM1). The fifth transistor M5 may electrically connect the first node S to the fourth node C in response to the light emitting control signal EM[n].

[0164] Each of the driving transistor M0 , the third transistor M3 , and the fifth transistor M5 may be an N-type transistor.

[0165] Figure 5B It is shown Figure 5A Waveform diagram of the pixel operation.

[0166] refer to Figure 5A and 5B , the pixel 500 may emit light during the light emitting period. Here, the operation period may include a fifth period T5, a third period T3, and a fourth period T4. The fifth period T5 may include a reference period Figure 3B The first time period T1 and the second time period T2 described above. The third time period T3 and the fourth time period T4 can be compared with the reference Figure 3B The third time period T3 and the fourth time period T4 described are substantially the same.

[0167] In the fifth period T5 , the initialization signal INIT[n] and the light emitting control signal EM[n] may have a logic high level, and the scan signal SCAN[n] may have a logic low level.

[0168] The third transistor M3 may be turned on in response to the initialization signal INIT[n] having a logic high level, and a third node voltage Vg at the third node G may be equal to the third voltage Vinit.

[0169] The driving transistor M0 may be turned off in response to the third node voltage Vg at the third node G, and the first node voltage Vs at the first node S may be lower than the third node voltage Vg at the third node G by the threshold voltage Vth of the driving transistor M0. That is, the first node voltage Vs at the first node S may be represented as a voltage difference between the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (that is, Vs=Vinit-Vth).

[0170] The fifth transistor M5 may be turned on in response to the light emitting control signal EM[n] having a logic high level, and a fourth node voltage Vc at the fourth node C may be equal to the first node voltage Vs at the first node S. That is, the fourth node voltage Vc at the fourth node C may be a voltage difference between the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (ie, Vc=Vinit-Vth).

[0171] In this case, the storage capacitor CST may be charged with a voltage difference between the third voltage Vinit and the fourth node voltage Vc at the fourth node C. That is, the threshold voltage Vth of the driving transistor M0 may be stored in the storage capacitor CST (ie, Vg-Vc=Vinit-(Vinit-Vth)=Vth).

[0172] Therefore, the pixel 500 may initialize the data signal DATA stored in the storage capacitor CST (or the data signal DATA stored in the pixel 500 in the previous frame or the previous emission period) and may store the threshold voltage Vth of the driving transistor M0 in the fifth period T5.

[0173] In the third period T3 , the initialization signal INIT[n] may be changed to have a logic low level, and the scan signal SCAN[n] may be changed to have a logic high level. The data signal DATA may have a data voltage Vdata[n].

[0174] The third transistor M3 may be turned off in response to the initialization signal INIT[n] having a logic low level, and the fifth transistor M5 may be turned off in response to the light emitting control signal EM[n] having a logic low level.

[0175] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level, and the fourth node voltage Vc at the fourth node C may be changed to have the data voltage Vdata[n].

[0176] A third node voltage Vg at the third node G may be represented as a sum of the data voltage Vdata[N] and the threshold voltage Vth of the driving transistor M0 (ie, Vg=Vdata[n]+Vth) according to capacitor coupling of the storage capacitor CST.

[0177] The first transistor M1 may be turned on in response to the scan signal SCAN[n] having a logic high level, and the first node voltage Vs at the first node S may be equal to the third voltage Vinit. In this case, the parasitic capacitor C of the light emitting element OLED OLED The third voltage Vinit may be charged.

[0178] In the fourth period T4 , the initialization signal INIT[n] may have a logic low level, the light emission control signal EM[n] may be changed to have a logic high level, and the scan signal SCAN[n] may be changed to have a logic low level.

[0179] The third transistor M3 may be maintained in a turned-off state, and each of the first transistor M1 and the switching transistor M4 may be turned off in response to the scan signal SCAN[n] having a logic low level.

[0180] The driving transistor M0 may transmit a driving current based on a third node voltage Vg at the third node G to the light emitting element OLED.

[0181] Because the third node voltage Vg at the third node G is equal to the sum of the data voltage Vdata[n] and the threshold voltage Vth of the driving transistor M0 (i.e., Vg=Vdata[n]+Vth) according to the capacitor coupling of the storage capacitor CST, the driving current Ioled can be proportional to the square of the data voltage Vdata[n] as described in reference [Formula 2].

[0182] Therefore, the pixel 500 may emit light having brightness corresponding to the data voltage Vdata[n] in the third period T3.

[0183] As described above, the pixel 500 can remove the parasitic capacitor C of the light emitting element OLED for writing the data voltage Vdata using the first transistor M1. OLED , and the pixel 500 can use the storage capacitor CST to store the data voltage Vdata[n] that compensates for the threshold voltage Vth of the driving transistor M0. Therefore, the pixel 500 can emit light having a brightness corresponding to the data voltage Vdata[n] without losing the data voltage Vdata[n].

[0184] Fig. 6A It is shown that the Figure 1 A circuit diagram of an example of a pixel in a display device.

[0185] refer to Figure 5A and 6A , except for the sixth transistor M6, the pixel 600 can be connected to the reference Figure 5A The pixels 500 depicted are substantially identical.

[0186] The sixth transistor M6 may include a first electrode electrically connected to the first node S, a second electrode electrically connected to the fourth node C, and a gate electrode receiving an initialization signal INIT[n] (or a compensation control signal Comp). The sixth transistor M6 may electrically connect the first node S and the fourth node C in response to the initialization signal INIT[n].

[0187] Figure 6B It is shown Fig. 6A Waveform diagram of the pixel operation.

[0188] refer to Fig. 6A and 6B , the pixel 600 can emit light during the light-emitting period. Figure 5B As described, the operation period may include a fifth period T5, a third period T3, and a fourth period T4. The fifth period T5 may include reference Figure 3B A first time period T1 and a second time period T2 are described.

[0189] In the fifth period T5 , the initialization signal INIT[n] may have a logic high level, the light emission control signal EM[n] may have a logic low level, and the scan signal SCAN[n] may have a logic low level.

[0190] The third transistor M3 may be turned on in response to the initialization signal INIT[n] having a logic high level, and a third node voltage Vg at the third node G may be equal to the third voltage Vinit.

[0191] The driving transistor M0 may be turned off in response to the third node voltage Vg at the third node G, and the first node voltage Vs at the first node S may be lower than the third node voltage Vg at the third node G by the threshold voltage Vth of the driving transistor M0. That is, the first node voltage Vs at the first node S may be represented as a voltage difference between the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (that is, Vs=Vinit-Vth).

[0192] The fifth transistor M5 may be turned off in response to the light emission control signal EM[n] having a logic low level. However, the sixth transistor M6 may be turned on in response to the initialization signal INIT[n] having a logic high level, so that the fourth node voltage Vc at the fourth node C may be equal to the first node voltage Vs at the first node S. That is, the fourth node voltage Vc at the fourth node C may be a voltage difference between the third voltage Vinit and the threshold voltage Vth of the driving transistor M0 (that is, Vc=Vinit-Vth).

[0193] In this case, the storage capacitor CST may be charged with a voltage difference between the third voltage Vinit and the fourth node voltage Vc at the fourth node C. That is, the threshold voltage Vth of the driving transistor M0 may be stored in the storage capacitor CST (ie, Vg-Vc=Vinit-(Vinit-Vth)=Vth).

[0194] Therefore, the pixel 600 may initialize the data signal DATA stored in the storage capacitor CST (or the data signal DATA stored in the pixel 600 in the previous frame or the previous emission period) and may store the threshold voltage Vth of the driving transistor M0 in the fifth period T5.

[0195] In the third period T3 , the initialization signal INIT[n] may be changed to have a logic low level, the emission control signal EM[n] may have a logic low level, and the scan signal SCAN[n] may be changed to have a logic high level. The data signal DATA may have a data voltage Vdata[n].

[0196] The third transistor M3 and the sixth transistor M6 may be turned off in response to the initialization signal INIT[n] having a logic low level, and the fifth transistor M5 may be turned off in response to the light emitting control signal EM[n] having a logic low level.

[0197] The switching transistor M4 may be turned on in response to the scan signal SCAN[n] having a logic high level, and the fourth node voltage Vc at the fourth node C may be changed to have the data voltage Vdata[n].

[0198] A third node voltage Vg at the third node G may be represented as a sum of the data voltage Vdata[N] and the threshold voltage Vth of the driving transistor M0 (ie, Vg=Vdata[n]+Vth) according to capacitor coupling of the storage capacitor CST.

[0199] The first transistor M1 may be turned on in response to the scan signal SCAN[n] having a logic high level, and the first node voltage Vs at the first node S may be equal to the third voltage Vinit. In this case, the parasitic capacitor C of the light emitting element OLED OLED The third voltage Vinit may be charged.

[0200] In the fourth period T4 , the initialization signal INIT[n] may have a logic low level, the light emission control signal EM[n] may be changed to have a logic high level, and the scan signal SCAN[n] may be changed to have a logic low level.

[0201] The third transistor M3 may be maintained in a turned-off state, and each of the first transistor M1 and the switching transistor M4 may be turned off in response to the scan signal SCAN[n] having a logic low level.

[0202] The driving transistor M0 may transmit a driving current based on a third node voltage Vg at the third node G to the light emitting element OLED.

[0203] Because the third node voltage Vg at the third node G is equal to the sum of the data voltage Vdata[n] and the threshold voltage Vth of the driving transistor M0 (ie, Vg=Vdata[n]+Vth), the driving current Ioled can be proportional to the square of the data voltage Vdata[n] as described in reference [Formula 2].

[0204] Therefore, the pixel 600 may emit light having brightness corresponding to the data voltage Vdata[n] in the third period T3.

[0205] As described above, the pixel 600 can remove the parasitic capacitor C of the light emitting element OLED for writing the data voltage Vdata using the first transistor M1.OLED , and the pixel 600 can use the storage capacitor CST to store the data voltage Vdata[n] that compensates for the threshold voltage Vth of the driving transistor M0. Therefore, the pixel 600 can emit light having a brightness corresponding to the data voltage Vdata[n] without losing the data voltage Vdata[n].

[0206] Figure 7 Is shown driving Figure 3A A flowchart of an example of a method for generating pixels.

[0207] refer to Figure 3A , 3B and 7, Figure 7 The method can drive Figure 3A Pixels.

[0208] When the second electrode of the driving transistor M0 is electrically connected to the first line transmitting the first power voltage ELVDD, Figure 7 The method may initialize a third node voltage Vg at a third node G by electrically connecting the second electrode of the driving transistor M0 and the gate of the driving transistor M0 ( S710 ).

[0209] Right now, Figure 7 The method can be Figure 3B The third node voltage Vg at the third node G is initialized during the first period T1 shown.

[0210] Figure 7 The method can maintain the first node voltage Vs at the first node S equal to the third voltage Vinit by providing the third voltage Vinit to the first node S (ie, a node where the light emitting element OLED is electrically connected to the first electrode of the driving transistor M0) (S720).

[0211] Figure 7 The method may compensate for the threshold voltage of the driving transistor M0 by supplying the third voltage Vinit to the fourth node C (ie, a node where the first storage capacitor CST1 is electrically connected to the second storage capacitor CST2) and by disconnecting the first line from the second electrode of the driving transistor M0 (S730).

[0212] Right now, Figure 7 The method can be Figure 3B The threshold voltage Vth of the driving transistor M0 is stored in the first storage capacitor CST1 during the second period T2 shown.

[0213] Figure 7 The method can provide the data voltage Vdata[n] to the fourth node C (S740). That is, Figure 7 The method can be Figure 3B The data voltage Vdata[n] is stored (or written) in the second storage capacitor CST2 during the third period T3 shown.

[0214] Figure 7 The method can transmit a driving voltage corresponding to a third node voltage Vg at a third node G to the light emitting element OLED by cutting off the third voltage Vinit to the first node S and by electrically connecting the first line to the second electrode of the driving transistor M0 (S750).

[0215] Figure 8 Is shown driving Figure 4A A flowchart of an example of a method for generating pixels.

[0216] refer to Figure 4A , 4B and 8, Figure 8 The method can drive Figure 4A Pixels.

[0217] When the second electrode of the driving transistor M0 is electrically connected to the first line transmitting the first power voltage ELVDD, Figure 8 The method may initialize a third node voltage Vg at a third node G by electrically connecting the second electrode of the driving transistor M0 to the gate electrode of the driving transistor M0 (S810).

[0218] Right now, Figure 8 The method can be Figure 4B The third node voltage Vg at the third node G is initialized during the first period T1 shown.

[0219] Figure 8 The method can maintain the first node voltage Vs at the first node S equal to the third voltage Vinit (820) by providing the third voltage Vinit to the first node S (ie, the node where the light emitting element OLED is electrically connected to the first electrode of the driving transistor M0).

[0220] Figure 8 The method can compensate for the threshold voltage Vth of the driving transistor M0 by disconnecting the terminal of the storage capacitor CST (or the fourth node C) from the first electrode of the driving transistor M0, by providing the third voltage Vinit to the terminal of the storage capacitor CST, and by disconnecting the first line from the second electrode of the driving transistor M0 (S830).

[0221] Right now, Figure 8 The method can be Figure 4B The threshold voltage Vth of the driving transistor M0 is stored in the storage capacitor CST during the second period T2 shown.

[0222] Figure 8 The method can provide the data voltage Vdata[n] to the fourth node C (S840). That is, Figure 8 The method can be Figure 4B The data voltage Vdata[n] is stored (or written) in the storage capacitor CST during the third period T3 shown.

[0223] Figure 8 The method can transmit a driving current corresponding to a third node voltage Vg at a third node G to the light emitting element OLED by cutting off the third voltage Vinit to the first node S and by electrically connecting the first line to the second electrode of the driving transistor M0 (S850).

[0224] As reference Figure 7 and 8 As described, the method of driving a pixel circuit according to example embodiments may effectively drive the pixel circuit.

[0225] The inventive concept can be applied to any display device (e.g., an organic light emitting display device, a liquid crystal display device, etc.). For example, the inventive concept can be applied to televisions, computer monitors, laptop computers, digital cameras, cellular phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), MP3 players, navigation systems, video phones, etc.

[0226] The foregoing is an illustration of example embodiments and should not be construed as limiting the inventive concept. Although several example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications may be made to the example embodiments without substantially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims. In the claims, the device-plus-function clause is intended to cover structures described herein as performing the functions, not just structural equivalents, but also equivalent structures. Therefore, it will be understood that the foregoing is an illustration of example embodiments and should not be construed as being limited to the specific embodiments disclosed, and modifications to the disclosed exemplary embodiments and other exemplary embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the appended claims, which include the equivalents of the claims.

Claims

1. A pixel circuit, comprising: Light emitting element; a driving transistor comprising a first electrode, a second electrode and a gate electrode, wherein the first electrode is electrically connected to the light emitting element; a first transistor including a first electrode receiving a third voltage, a second electrode electrically connected to the light emitting element, and a gate electrode receiving a fourth signal; a second transistor including a first electrode electrically connected to a line transmitting a power supply voltage, a second electrode electrically connected to the second electrode of the driving transistor, and a gate electrode receiving a first signal; a third transistor comprising a first electrode electrically connected to the second electrode of the driving transistor, a second electrode electrically connected to the gate electrode of the driving transistor, and a gate electrode receiving a second signal, wherein a timing of the second signal is different from a timing of the fourth signal; a storage capacitor comprising a first electrode and a second electrode, the first electrode of the storage capacitor being electrically connected to the gate electrode of the driving transistor; as well as The switch transistor includes a first electrode, a second electrode and a gate electrode receiving a third signal, wherein the first electrode of the switch transistor is electrically connected to the data line.

2. The pixel circuit according to claim 1, wherein: Each of the driving transistor, the second transistor, the third transistor, and the switching transistor is an N-channel metal oxide semiconductor (NMOS) transistor.

3. The pixel circuit according to claim 1, wherein: the second transistor is turned on in the first period and in the fourth period in response to the first signal, and is turned off in the second period and in the third period, The first period is used to initialize the voltage at the first electrode of the storage capacitor and the gate electrode of the driving transistor. The second period is used to compensate for the threshold voltage of the driving transistor. The third time period is used to receive a data signal. The fourth time period is used for the light emitting element to emit light, and The first to fourth periods are included in the operation period and are different from each other.

4. The pixel circuit according to claim 3, wherein: The first transistor is turned on in the first period, in the second period, and in the third period in response to the fourth signal, and is turned off in the fourth period.

5. The pixel circuit according to claim 4, wherein: The third transistor is turned on in the first period and in the second period in response to the second signal, and is turned off in the third period and in the fourth period.

6. The pixel circuit according to claim 5, wherein: The switching transistor transmits the data signal in response to the third signal so that the data signal is stored in the storage capacitor.

7. The pixel circuit according to claim 6, wherein: The storage capacitor further stores the threshold voltage of the driving transistor in the second period.

8. The pixel circuit according to claim 5, wherein: The switch transistor is turned on in the third period in response to the third signal.

9. The pixel circuit according to claim 1, wherein: The second electrode of the storage capacitor is electrically connected to the light emitting element through an additional capacitor, and The second electrode of the switch transistor is electrically connected to the first electrode of the drive transistor through the additional capacitor.

10. The pixel circuit according to claim 1, wherein: The third voltage is equal to or lower than a threshold voltage of the light emitting element.

11. A pixel circuit comprising: Light emitting element; a driving transistor including a gate electrode, a first electrode electrically connected to the light emitting element, and a second electrode electrically connected to a line transmitting a power supply voltage; a first transistor including a first electrode receiving a third voltage, a second electrode electrically connected to the light emitting element, and a gate electrode receiving a fourth signal; a third transistor comprising a first electrode electrically connected to the second electrode of the driving transistor, a second electrode electrically connected to the gate electrode of the driving transistor, and a gate electrode receiving a second signal, wherein a timing of the second signal is different from a timing of the fourth signal; a storage capacitor comprising a first electrode and a second electrode, the first electrode of the storage capacitor being electrically connected to the gate electrode of the driving transistor; as well as The switch transistor includes a first electrode, a second electrode and a gate electrode receiving a third signal, wherein the first electrode of the switch transistor is electrically connected to the data line.

12. The pixel circuit according to claim 11, further comprising: a second transistor including a first electrode electrically connected to the line transmitting the power supply voltage, a second electrode electrically connected to the second electrode of the driving transistor, and a gate electrode receiving a first signal, The second electrode of the driving transistor is electrically connected to the line transmitting the power supply voltage through the second transistor.

13. The pixel circuit according to claim 12, wherein: the second transistor is turned on in the first period and in the fourth period in response to the first signal, and is turned off in the second period and in the third period, The first period is used to initialize the voltage at the first electrode of the storage capacitor and the gate electrode of the driving transistor. The second period is used to compensate for the threshold voltage of the driving transistor. The third time period is used to receive a data signal. The fourth time period is used for the light emitting element to emit light, and The first to fourth periods are included in the operation period and are different from each other.

14. The pixel circuit according to claim 13, wherein: The first transistor is turned on in the first period, in the second period, and in the third period in response to the fourth signal, and is turned off in the fourth period.

15. The pixel circuit according to claim 14, wherein: The third transistor is turned on in the first period and in the second period in response to the second signal, and is turned off in the third period and in the fourth period.

16. The pixel circuit according to claim 11, further comprising: a fifth transistor including a gate electrode receiving the first signal, wherein the second electrode of the storage capacitor is electrically connected to the light emitting element through the fifth transistor, and The second electrode of the switch transistor is electrically connected to the first electrode of the drive transistor through the fifth transistor.

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