Memory array structure for capacitive sensing NAND memory

Abstract

This application relates to memory array structures for capacitive sensing NAND memory. An array of memory cells includes a plurality of sense lines, each sense line having a respective plurality of pass gates connected in series between a second data line and a source, and having a respective subset of cell column structures coupled to a first channel of its respective plurality of pass gates, wherein for each sense line of the plurality of sense lines, each cell column structure of its respective subset of cell column structures is connected to a respective first data line of a respective subset of first data lines.

Description

[0001] Related applications

[0002] This application relates to: U.S. Patent Application No. 17 / 111,729, entitled “Capacitive Sense NAND Memory,” filed December 4, 2020; U.S. Patent Application No. 17 / 111,751, entitled “Sense Line Structures in Capacitive Sense NAND Memory,” filed December 4, 2020; and U.S. Patent Application No. 17 / 111,770, entitled “Access Operations in Capacitive Sense NAND Memory,” filed December 4, 2020. Each of these applications is jointly assigned and incorporated herein by reference in its entirety, and each of these applications shares a common disclosure. Technical Field

[0003] This disclosure generally relates to integrated circuits, and more particularly, in one or more embodiments, to devices comprising strings of memory cells connected in series, and methods of forming and operating thereof. Background Technology

[0004] Integrated circuit devices encompass a wide range of electronic devices. A specific type includes memory devices, often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has become a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells with high memory density, high reliability, and low power consumption. By programming (often referred to as writing) a charge storage structure (e.g., a floating gate or charge trap) or other physical phenomena (e.g., phase transitions or polarization), changes in the threshold voltage (Vt) of the memory cell determine the data state (e.g., the data value) of each memory cell. Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, appliances, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, hence the term refers to the logical form arranged by the basic memory cell configuration. Typically, the memory cell array of a NAND flash memory is arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns of the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates (e.g., source select transistors and drain select transistors). Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate are known between the memory cell string and the source and / or between the memory cell string and the data line.

[0007] The demand for higher levels of memory storage density has led to longer strings of cascaded memory cells in NAND flash memory. However, common industrial techniques may present challenges in successfully manufacturing such strings of cascaded memory cells, for example, due to practical limitations on the number of memory cells that can be contained within them. Summary of the Invention

[0008] In one aspect, this application provides a memory cell array comprising: a plurality of first data lines; a second data line; a source; a plurality of cell column structures, wherein each of the plurality of cell column structures includes a corresponding plurality of non-volatile memory cells connected in series; a plurality of sensing lines, wherein each of the plurality of sensing lines includes a corresponding plurality of through gates connected in series between the second data line and the source, wherein each of its corresponding plurality of through gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, and wherein each cell column structure in a corresponding subset of the plurality of cell column structures of the sensing lines is capacitively coupled to the first channel of a corresponding through gate in its corresponding plurality of through gates; and a plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of a corresponding through gate in the corresponding plurality of through gates of each of the plurality of sensing lines; wherein, for each of the plurality of sensing lines, each cell column structure in a corresponding subset of its cell column structures is connected to a corresponding first data line in a corresponding subset of the plurality of first data lines.

[0009] In another aspect, this application further provides a memory cell array comprising: a plurality of first data lines; a second data line; a source; a plurality of cell column structures, wherein each of the plurality of cell column structures includes a corresponding plurality of non-volatile memory cells connected in series; a plurality of sensing lines, wherein each of the plurality of sensing lines includes a corresponding plurality of through gates connected in series between the second data line and the source, wherein each of its corresponding plurality of through gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, and wherein the corresponding plurality of cell column structures of the plurality of sensing lines... Each cell column structure in the cell column structure subset is capacitively coupled to the first channel of a corresponding pass-gate in its respective plurality of pass-gates; and a plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of a corresponding pass-gate in the respective plurality of pass-gates of each of the plurality of sensing lines; wherein, for each of the plurality of sensing lines, each cell column structure in its respective cell column structure subset is connected to a corresponding first data line in a corresponding first data line subset of the plurality of first data lines, and wherein, for each of the plurality of sensing lines, each first data line in its respective first data line subset is connected to only one cell column structure in its respective cell column structure subset.

[0010] In another aspect, this application provides a further memory cell array comprising: a plurality of first data lines; a second data line; a source; a plurality of cell column structures, wherein each of the plurality of cell column structures includes a corresponding plurality of non-volatile memory cells connected in series; a plurality of dummy cell column structures; and a plurality of sensing lines, wherein each of the plurality of sensing lines includes a corresponding plurality of access gates connected in series between the second data line and the source, wherein each of its corresponding plurality of access gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, wherein each cell column structure in a corresponding subset of the plurality of cell column structures of the plurality of sensing lines is capacitively coupled to its corresponding plurality of access gates. The first channel of the corresponding through gate, and wherein the corresponding dummy cell column structure of the plurality of dummy cell column structures of the sensing lines of the plurality of sensing lines is capacitively coupled to the first channel of the corresponding through gate of the corresponding plurality of through gates of the plurality of sensing lines; and a plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of the corresponding through gate of the corresponding plurality of through gates of the plurality of sensing lines; wherein for each of the plurality of sensing lines, each cell column structure in its corresponding subset of cell column structures is connected to a corresponding first data line in its corresponding subset of first data lines of the plurality of first data lines; wherein for each of the plurality of sensing lines, each first data line in its corresponding subset of first data lines is connected to more than one cell column structure in its corresponding subset of cell column structures. Attached Figure Description

[0011] Figure 1 This is a simplified block diagram of a memory that communicates with a processor as part of an electronic system, according to an embodiment.

[0012] Figure 2A-2B This is a reference based on the embodiments. Figure 1 A schematic diagram of a portion of the memory cell array of the type of memory.

[0013] Figure 2C It is available for reference according to another embodiment. Figure 1 A conceptual perspective view of a portion of a memory cell array above a peripheral circuitry system of the type of memory.

[0014] Figures 3A-3E The use according to the embodiments is as follows Figure 2A The diagram depicts a portion of the memory cell block of the array structure, showing the layout of the back gate line, sense select line, sense line, common source, and lower data line.

[0015] Figure 3F-3GThis is based on the use of additional embodiments, such as Figure 2B The conceptual diagram depicts a portion of a memory cell block in an array structure, showing the layout of the back-side gate line, sense select line, sense line, common source, and lower data line.

[0016] Figure 4A The use according to the embodiments is as follows Figure 3A and 3B The concept diagram depicts a portion of a memory cell block in an array structure, showing the layout of higher data line connections.

[0017] Figure 4B According to another embodiment of use, such as Figure 3C and 3D The concept diagram depicts a portion of a memory cell block in an array structure, showing the layout of higher data line connections.

[0018] Figure 4C According to another embodiment of use, such as Figure 3C and 3E The concept diagram depicts a portion of a memory cell block in an array structure, showing the layout of higher data line connections.

[0019] Figure 4D According to another embodiment of the use, such as Figure 3F and 3G The concept diagram depicts a portion of a memory cell block in an array structure, showing the layout of higher data line connections.

[0020] Figure 5A-5N The integrated circuit structure during various manufacturing stages according to the embodiments is depicted.

[0021] Figures 6A-6F The integrated circuit structure is depicted during various manufacturing stages according to an additional embodiment.

[0022] Figures 7A-7J Orthogonal views depicting the various structures of the sensing line according to an embodiment.

[0023] Figures 8A-8C The integrated circuit structure during various manufacturing stages according to the embodiments is depicted.

[0024] Figures 9A-9E An integrated circuit structure is depicted during various manufacturing stages according to another embodiment.

[0025] Figures 10A-10B Depicts an integrated circuit structure according to other embodiments.

[0026] Figure 11 This is a timing diagram of a memory operation method according to an embodiment.

[0027] Figure 12 This is a timing diagram of a memory operation method according to another embodiment.

[0028] Figure 13 This is a timing diagram of a memory operation method according to another embodiment.

[0029] Figure 14 This is a timing diagram of a memory operation method according to another embodiment. Detailed Implementation

[0030] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of description. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be regarded in a limiting sense.

[0031] For example, as used herein, the term "semiconductor" can refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0032] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0033] This article should recognize that even when expected values ​​are equal, the variability and precision of industrial processing and operation can lead to differences from the expected values. These variability and precision typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then these values ​​are considered equal regardless of their actual results.

[0034] Figure 1This is a simplified block diagram of a first device in the form of a memory (e.g., a memory device) 100 according to an embodiment, which communicates as part of a third device in the form of an electronic system with a second device in the form of a processor 130. Some examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and so on. The processor 130 is, for example, a controller external to the memory device 100; it can be a memory controller or another external host device.

[0035] Memory device 100 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access lines (typically referred to as word lines), while memory cells in logical columns are typically selectively connected to the same data lines (typically referred to as bit lines). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1 (Not shown) can be programmed into one of at least two target data states. The memory cell array 104 includes an array structure according to one or more embodiments described herein.

[0036] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 for managing inputs of commands, addresses, and data to memory device 100 and outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0037] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to addresses. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a group of memory cells in memory cell array 104, e.g., a reserved block of memory cells.

[0038] Control logic 116 also communicates with cache register 118. Cache register 118 latches incoming or outgoing data, as directed by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; new data from I / O control circuitry 112 can then be latched in cache register 118. During read operations, data can be transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; new data can then be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1 (Not shown in the image) is used to sense the data status of memory cells in memory cell array 104, for example, by sensing the status of data lines connected to the memory cells. Status register 122 can communicate with I / O control circuitry system 112 and control logic 116 to latch status information for output to processor 130.

[0039] The memory device 100 is depicted receiving control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may also be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via the I / O bus 134.

[0040] For example, commands can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the commands can be written to command register 124. Addresses can be received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and then the addresses can be written to address register 114. Data can be received via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device at I / O control circuitry system 112, and then the data can be written to cache register 118. The data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and the data can be written directly to data register 120. Data can also be output via the input / output (I / O) pins [7:0] of an 8-bit device or the input / output (I / O) pins [15:0] of a 16-bit device. While references may be made to the I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via an external device (e.g., processor 130).

[0041] Those skilled in the art should understand that additional circuitry and signals can be provided, and Figure 1 The memory device 100 has been simplified. It should be recognized that the reference... Figure 1 The functionality of the described individual block components may not necessarily need to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device can be used to perform... Figure 1 The functionality can exceed that of a single block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1The functionality of a single block component. Furthermore, while specific I / O pins are described according to popular conventions for the reception and output of various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0042] Figure 2A It can be used for reference. Figure 1 A schematic diagram of a portion of a memory cell array 200A (e.g., a NAND memory array) of the aforementioned type, for example, as part of memory cell array 104. Memory array 200A includes access lines, such as word lines 2020 to 202. N And data lines, such as the first or higher data lines (e.g., the high-level line) 2040 to 204. M And a second or lower data line (e.g., a low-order line) 254. Word line 202 can be connected to a global access line (e.g., a global word line) in a many-to-one relationship. Figure 2A Not shown. In some embodiments, the memory array 200A may be formed above a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity, for example, forming a p-well, or n-type conductivity, for example, forming an n-well. Alternatively, the memory array 200A may be formed above other circuitry, such as peripheral circuitry below the memory array 200A for controlling access to the memory cells of the memory array 200A. It should be noted that the direction descriptors used herein, such as lower, higher, above, below, etc., are relative and do not require any specific orientation in physical space.

[0043] The memory array 200A can be arranged in rows (each row corresponds to word line 202 and lower data line 254) and columns (each column corresponds to higher data line 204). Each column can contain a string of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cell 208 in each NAND string 206 may be selected at gate 210 (e.g., a field-effect transistor) (e.g., select gates 2100 to 210). M One of them (e.g., the lower select gate) and select gate 212 (e.g., a field-effect transistor) (e.g., select gates 2120 to 212) M The lower select gates 2100 to 210 are connected in series. M They can be connected together to select line 214, such as the lower select line LSG, and higher select gates 2120 to 212. MThey can be connected together to select line 215, such as the higher select line USG. Although depicted as conventional field-effect transistors, the lower select gate 210 and the higher select gate 212 can use a similar (e.g., identical) structure to memory cell 208. The lower select gate 210 and the higher select gate 212 can each represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0044] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that can determine the data state of the memory cell (e.g., by changing a threshold voltage) and a control gate 236, such as Figure 2A As shown in the diagram. Data storage structure 234 may include conductive and dielectric structures, while control gate 236 is generally formed of one or more conductive materials. In some cases, memory cell 208 may further have defining source / drain (e.g., source) 230 and defining source / drain (e.g., drain) 232. Memory cells 208 connect their control gate 236 to (and in some cases form) word lines 202.

[0045] The lower select gate 210 of each NAND string 206 can be located in its memory cell 208 and the corresponding capacitor 226 (e.g., capacitors 2260 to 226). M Each lower select gate 210 is connected in series with the corresponding capacitor 226. Each lower select gate 210 may be connected (e.g., directly connected) to its corresponding capacitor 226. Each lower select gate 210 may be further connected (e.g., directly connected) to the memory cell 2080 of its corresponding NAND string 206. For example, a lower select gate 2100 may be connected to capacitor 2260, and a lower select gate 2100 may be connected to the memory cell 2080 of the corresponding NAND string 2060. Thus, each lower select gate 210 may be configured to selectively connect the corresponding NAND string 206 to the corresponding capacitor 226. The control gate of each lower select gate 210 may be connected to select line 214.

[0046] The higher selection gate 212 of each NAND string 206 may be located in its memory cell 208 and GIDL (gate-induced drain leakage) generator gate 220 (e.g., field-effect transistor) (e.g., GIDL generator (GG) gates 2200 to 220). M One of them is connected in series. GG gate 2200 to 220 M It can be connected (e.g., directly) to their respective higher data lines 2040 to 204. M And selectively connected to their respective NAND strings 2060 to 206 M For example, through the corresponding higher select gates 2120 to 212M conduct.

[0047] GG gate 2200 to 220 M They can be connected together to control line 224, such as the GG control line. Although depicted as a conventional field-effect transistor, GG gate 220 can use a structure similar to (e.g., identical to) memory cell 208. GG gate 220 can represent multiple GG gates connected in series, wherein each GG gate in series is configured to receive the same or independent control signal. Generally, GG gate 220 can have a threshold voltage different from (e.g., lower than) the threshold voltage of the higher select gate 212. The threshold voltage of GG gate 220 can have the opposite polarity to the threshold voltage of the higher select gate 212, and / or can be lower than the threshold voltage of the higher select gate 212. For example, the higher select gate 212 can have a positive threshold voltage (e.g., 2V to 4V), while GG gate 220 can have a negative threshold voltage (e.g., -1V to -4V). GG gate 220 can be provided to help generate GIDL current in the channel region of their corresponding NAND string 206, for example, during read or erase operations.

[0048] Each GG gate 220 may be connected (e.g., directly connected) to the higher data line 204 of its corresponding NAND string 206. For example, a GG gate 2200 may be connected to the higher data line 2040 of its corresponding NAND string 2060. Each GG gate 220 may be connected (e.g., directly connected) to the higher select gate 212 of its corresponding NAND string 206. For example, a GG gate 2200 may be connected to the higher select gate 2120 of its corresponding NAND string 2060. Each higher select gate 212 may be further connected (e.g., directly connected) to the memory cell 208 of its corresponding NAND string 206. N For example, the higher select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each higher select gate 212 and GG gate 220 corresponding to NAND string 206 can be cooperatively configured to selectively connect the NAND string 206 to the corresponding higher data line 204. The control gate of each GG gate 220 can be connected to control line 224. The control gate of each higher select gate 212 can be connected to select line 215.

[0049] One electrode of each capacitor 226 can be connected to a control line 228, such as control line CAP. The other electrode of each capacitor 226 can be capacitively coupled to a corresponding pass gate 238, such as pass gates 2380 to 238. MFor example, capacitor 2260 may be capacitively coupled to or electrically connected to the first control gate 240 of pass-through gate 2380, and thus capacitively coupled to the channel of pass-through gate 2380. The second control gate 242 of each pass-through gate 238 may be connected (e.g., directly connected) to a corresponding back-side gate line 244, such as back-side gate lines 2440 to 244. M For example, the second control gate 242 of gate 2380 can be connected to the back-side gate line 2440. Gate 238 can be connected in series between a source 216 (e.g., common-source SRC) as a voltage node and a lower data line 254 as another voltage node; the resulting current path can be referred to as sensing line 258. One gate 238 (e.g., gate 2380) can be selectively connected to the lower data line 254 via a first sense-select gate (e.g., field-effect transistor) 246. The control gate of the first sense-select gate 246 can be connected to the first sense-select line 248. Another gate 238 (e.g., gate 238...) M The second sense select gate (e.g., a field-effect transistor) 250 can be selectively connected to the common source 216. The control gate of the second sense select gate 250 can be connected to the second sense select line 252.

[0050] Gate 238 can be viewed as two field-effect transistors connected in parallel in response to two control gates (e.g., first control gate 240 and second control gate 242). The two field-effect transistors through gate 238 may have discrete channels, for example, one channel capacitively coupled to the first control gate 240 and the other capacitively coupled to the second control gate 242. Alternatively, the first channel of gate 238 capacitively coupled to the first control gate 240 and the second channel of gate 238 capacitively coupled to the second control gate 242 may be the same channel of gate 238.

[0051] Sensing device 268 can be connected to lower data line 254 for sensing the data state of memory cell 208, for example, by sensing the state of lower data line 254. For example, sensing device 268 can be used to detect whether lower data line 254 is experiencing a current or a voltage level change to determine that the cell column structure 256 containing the selected memory cell 208 stores a charge level sufficient to activate the first control gate 240 of its corresponding pass-through gate 238 while deactivating the second control gate 242 of said pass-through gate 238. During such sensing, the remaining pass-through gates in sensing line 258 can activate their second control gates 242. In this way, electrically connecting the lower data line to common source 216 via sensing line 258 indicates that the selected memory cell has one data state, while electrically isolating the lower data line from common source 216 indicates that the selected memory cell has another data state.

[0052] Although each capacitor 226 is depicted as a single capacitor for each NAND string 206, each capacitor 226 may represent several field-effect transistors connected in series, and each such transistor may use a similar (e.g., identical) structure to the memory cell 208. An example of this configuration is... Figure 2B This is described in further detail. Generally, for a given NAND string 206, the cell column structure 256 refers to the elements between its memory cells 208 and the higher data lines 204, its memory cells 208, and the elements between its memory cells 208 and the access gate 238, which are connected to each other (e.g., selectively connected). For example, refer to... Figure 2A A given NAND string 206 cell column structure 256 may include its GG gate 220, higher select gate 212, memory cell 208, lower select gate 210 and capacitor 226, which are connected in series between higher data line 204 and pass gate 238.

[0053] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and higher data line 204 extend in a generally parallel plane. Alternatively, Figure 2A The memory array in the array can be a three-dimensional memory array, for example, in which higher data lines 204 are selectively connected to more than one NAND string 206, and in which back-side gate lines 244 are connected to more than one pass-through gate 238.

[0054] A column of memory cell 208 may be one or more NAND strings 206 selectively connected to a given higher data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may, but need not, contain all memory cells 208 commonly connected to a given word line 202.

[0055] Memory cell 208 is programmable as a single-level cell (SLC). An SLC can use a single memory cell to represent a single data digit (e.g., a bit). For example, in an SLC, a Vt of 2.5V or higher can indicate a programmable memory cell (e.g., representing logic 0), while a Vt of -0.5V or lower can indicate an eraseable memory cell (e.g., representing logic 1). Higher levels of storage capacity can be achieved by including multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and combinations thereof, where the memory cells have multiple levels, allowing more data digits to be stored in each memory cell. For example, an MLC can be configured to store two data digits per memory cell, represented by four Vt ranges; a TLC can be configured to store three data digits per memory cell, represented by eight Vt ranges; a QLC can be configured to store four data digits per memory cell, represented by sixteen Vt ranges, and so on. Although the number of binary digits of data stored in a memory cell is typically an integer value representing the binary number of the data state for each memory cell, the memory cell can be manipulated to store non-integer digits of data. For example, when the memory cell operates using three Vt ranges, each memory cell can store 1.5 data digits, where two memory cells together can represent one of eight data states.

[0056] The memory cells 208 of a given NAND string 206 can be configured to store data at various storage densities. For example, the NAND string 206 may contain some memory cells (e.g., dummy memory cells) 208 configured to store data at a first storage density (e.g., 0 bits per memory cell). Dummy memory cells 208 are typically incorporated into the NAND string 206 to gain operational advantages, are generally not accessible to memory users, and are generally not intended to store user data. For example, the operational characteristics of memory cells 208 formed at a particular location in the NAND string 206 may differ from those of memory cells formed at other locations. Such differences in operational characteristics can be largely mitigated by operating these memory cells as dummy memory cells. Additionally, dummy memory cells can be used to buffer select gates from high-voltage levels that can be applied to main memory cells (e.g., those intended to store user data) during a particular operation. The NAND string 206 may further contain other memory cells 208 configured to store data at one or more additional (e.g., higher) storage densities.

[0057] Figure 2B It is based on another embodiment and can be used as a reference. Figure 1 Another schematic diagram of a portion of the memory cell array 200B in the memory of the aforementioned type, for example, as part of the memory cell array 104. Figure 2BThe similar numbered elements in the text correspond to, for example, regarding... Figure 2A The description provided. For clarity, specific components are not numbered, but their identification references are provided. Figure 2A The description in the text will be obvious. Figure 2B Additional details are provided for an example of the structure of capacitor 226, as well as the incorporation of a dummy cell column structure 257 in addition to the cell column structure (e.g., the main cell column structure) 256.

[0058] Cell column structures 2560 to 2567 and dummy cell column structure 257 may be portions of memory cell blocks sharing the same word line 202. Cell column structures 2560 to 2563 may be portions of a first memory cell sub-block 2620 corresponding to a memory cell block of back-side gate lines 2440 to 2443. Cell column structures 2564 to 2567 may be portions of a second memory cell sub-block 2621 corresponding to a memory cell block of back-side gate lines 2444 to 2447. Dummy cell column structure 257 may have the same association with pass-through gate 238 as cell column structures 2560 to 2567, and may connect the second control gate 242 of its associated pass-through gate 238 to the dummy back-side gate line 260. When dummy cell column structure 257 is not connected to the higher data line 204, the first control gate 240 of its associated pass-through gate 238 may be electrically floating, for example, permanently electrically floating.

[0059] Cell column structures 2560 to 2567 and dummy cell column structure 257 may each contain access lines 2020 to 202 respectively. N Memory cells 2080 to 208 (e.g., having a control gate connected thereto) N Cell column structures 2560 to 2567 and dummy cell column structure 257 may each include select gates (e.g., lower select gates) 2100 to 2102, which may have the same structure as memory cell 208. Select gates 2100 to 2102 may be connected to select lines 2140 to 2142 (e.g., with control gates connected thereto), respectively.

[0060] Cell column structures 2560 to 2567 and dummy cell column structure 257 may each include an optional compensation gate 211 between the select gate 210 and the memory cell 208, and may have the same structure as the memory cell 208. The compensation gate 211 may be connected (e.g., its control gate is connected to) control line 213.

[0061] Cell column structures 2560 to 2567 and dummy cell column structure 257 may each contain capacitors 2260 to 226. K They can have the same structure as memory cell 208. Capacitors 2260 to 226...K They can be connected to control lines 2280 to 228 respectively. K (For example, having a control gate connected thereto). Formation Figure 2B The control gate of the field-effect transistor forming capacitor 226 may correspond to the first electrode of capacitor 226, and the channel (e.g., body) of the field-effect transistor forming capacitor 226 may correspond to the second electrode of capacitor 226. When acting as a capacitor (e.g., a common capacitor), the field-effect transistor of capacitor 226 may be operated to supply power to each control line 2280 to 228 of each cell column structure 2560 to 2567. K Apply the same voltage level, for example, it could be 2-3V.

[0062] Cell column structures 2560 to 2567 and dummy cell column structure 257 may each include a GIDL generator gate 220, which may have the same structure as memory cell 208. The GIDL generator gate 220 may be connected to control line 224 (e.g., having a control gate connected thereto). The GIDL generator gates 220 of cell column structures 2560 to 2563 may be connected to higher data lines 2040 to 2043 (e.g., having source / drain regions connected thereto). The GIDL generator gates 220 of cell column structures 2564 to 2567 may be connected to higher data lines 2043 to 2040 (e.g., having source / drain regions connected thereto). Although depicted and described, the GIDL generator gate 220 may be removed. Because dummy cell column structure 257 is not intended to store data, it may not be connected to higher data line 204, but connection is permitted.

[0063] Cell column structures 2560 to 2567 and dummy cell column structure 257 may each include select gates (e.g., higher select gates) 2120 to 2122, and they may have the same structure as memory cell 208. 00 Up to 215 02 (For example, having a control gate connected thereto). The select gates 2120 to 2122 of the cell column structures 2564 to 2567 can be respectively connected to the select line 215. 10 Up to 215 12(For example, having a control gate connected thereto). The select gates 2120 to 2122 of the dummy cell column structure 257 can be respectively connected to dummy select lines 2170 to 2172 (e.g., having a control gate connected thereto). Because the dummy cell column structure 257 is not intended to store data, the dummy select lines 2170 to 2172 can each be electrically floating. For example, a continuous conductive structure can be formed, from which a first select line 215 (e.g., select line 215) can then be formed. 00 ), second selection line 215 (e.g., selection line 215) 10 And a dummy select line 217 (e.g., dummy select line 2170). As an example, an isolation region may be formed in such a continuous conductive structure to define a first select line 215, a second select line 215, and a dummy select line 217, wherein each select line is electrically isolated from each other. Alternatively, a single isolation region may be formed in a continuous conductive structure such that the dummy select line 217 will remain connected to either the first select line 215 or the second select line 215, but the first select line 215 will be isolated from the second select line 215.

[0064] As mentioned, although Figure 2A and 2B The array portion depicts structures that can be formed in a single plane, but can also be three-dimensional structures. Figure 2C It is based on another embodiment and can be used as a reference. Figure 1 A conceptual perspective view of a portion of the memory cell array 200C above the peripheral circuit system 266 of the type of memory. Figure 2A or Figure 2B The structure can be represented by each sensing line 258 (e.g., sensing lines 2580 to 258). L The unit column structure from 2560 to 256 M (For example, where for) Figure 2B (M=7). For simplicity, the connection from cell column structure 256 to higher data line 204 is... Figure 2C Not described in the text.

[0065] Peripheral circuit system 266 can represent various circuit systems used to access memory array 200C. Peripheral circuit system 266 may include complementary circuit elements. For example, peripheral circuit system 266 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or complementary metal-oxide-semiconductor. Although CMOS typically no longer utilizes a strictly metal-oxide-semiconductor structure due to advancements in integrated circuit manufacturing and design, the CMOS designation is retained for convenience.

[0066] Figures 3A-3E The use according to the embodiments is as follows Figure 2AThe conceptual diagram of a portion of the memory cell block of the array structure depicted in the figure shows the layout of the back gate line 244, sense select lines 248 and 252, sense line 258, common source 216 and lower data line 254.

[0067] Figure 3A A top view depicting a memory array 300A having several cell column structures 256 including cell column structures 2560 to 2567, the cell column structures respectively corresponding to... Figure 2A Back-side gate lines 2440 to 244 M The corresponding cell column structure 256, where M = 7. The memory array 300A further depicts a first sense select line 248, back-side gate lines 2440 to 2447, and a second sense select line 252 in a horizontal orientation, which respectively correspond to... Figure 2A First sensing selection line 248, back gate lines 2440 to 244 M and a second sense selection line 252, where M = 7. It should be appreciated that fewer or more back-side gate lines 244 may be used between sense selection lines 248 and 252, and fewer or more cell column structures may be associated with each back-side gate line 244.

[0068] Figure 3B A top view depicting a memory array 300B, which may contain the same memory array structure as memory array 300A. Memory array 300B has several cell column structures 256, including cell column structures 2560 to 2567, which may correspond to the memory array 300A, respectively. Figure 2A Back-side gate lines 2440 to 244 M The corresponding cell column structure is 256, where M = 7. The memory array 300B further depicts diagonally oriented sensing lines 2580 to 2582, each of which individually corresponds to... Figure 2A The sensing lines 258. It should be recognized that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. The memory array 300B further depicts a common source 216 oriented horizontally and connected to each of the sensing lines 258 via corresponding contacts 366, and lower data lines 2540 to 2542 oriented vertically and each connected to the corresponding sensing lines 2580 to 2582 via corresponding contacts 367. It should be noted that the lower data lines 254 and the common source 216 can be connected to additional memory cell blocks (in Figure 3B Sensing line 258 (not depicted in the text).

[0069] Figure 3C A top view depicting a memory array 300C having several cell column structures 256 including cell column structures 2560 to 2563, the cell column structures respectively corresponding to... Figure 2A Back-side gate lines 2440 to 244 M The corresponding cell column structure 256, where M=3. The memory array 300C further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2443, and a second sense select line 252, which respectively correspond to... Figure 2A First sensing selection line 248, back gate lines 2440 to 244 M and a second sense selection line 252, where M = 3. It should be appreciated that fewer or more back-side gate lines 244 may be used between sense selection lines 248 and 252, and fewer or more cell column structures may be associated with each back-side gate line 244.

[0070] Figure 3D A top view depicting a memory array 300D, which may contain the same memory array structure as memory array 300C. Memory array 300D has several cell column structures 256, including cell column structures 2560 to 2563, which may correspond to the memory array 300C, respectively. Figure 2A Back-side gate lines 2440 to 244 M The corresponding cell column structure is 256, where M = 3. The memory array 300D further depicts diagonally oriented sensing lines 2580 to 2584, each of which individually corresponds to... Figure 2A The sensing lines 258. It should be recognized that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. The memory array 300D further depicts a common source 216 oriented horizontally and connected to each of the sensing lines 258 via corresponding contacts 366, and lower data lines 2540 to 2544 oriented vertically and each connected to the corresponding sensing lines 2580 to 2584 via corresponding contacts 367. It should be noted that the lower data lines 254 and the common source 216 can be connected to additional memory cell blocks (in Figure 3D Sensing line 258 (not depicted in the text).

[0071] Figure 3E A top view depicting memory array 300E is shown, which may contain the same memory array structure as memory array 300C. Memory array 300E has several cell column structures 256, including cell column structures 2560 and 2561, which may correspond to the memory array structure 300C, respectively. Figure 2A Back-side gate lines 2440 to 244 M The corresponding cell column structure is 256, where M=1. The memory array 300E further depicts vertically oriented sensing lines 2580 to 258. 11 Each of them can correspond to individually. Figure 2ASensing lines 258. It should be recognized that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. The memory array 300E may further include horizontally oriented and... Figure 3D The corresponding contact 366 depicted is connected to the common source 216 of each of the sensing lines 258 (in Figure 3E (not depicted in the text), and vertically oriented and each passing through as... Figure 3D The corresponding contact 367 depicted is connected to the lower data line 254 of the corresponding sensing line 258 (in Figure 3E (Not depicted in the text).

[0072] Figure 3F-3G This is based on the use of additional embodiments, such as Figure 2B The conceptual diagram of a portion of the memory cell block of the array structure depicted in the diagram shows the layout of the back-side gate line 244, the dummy back-side gate line 260, the sense select lines 248 and 252, the common source 216, and the lower data line 254.

[0073] Figure 3F A top view depicting a memory array 300F having several cell column structures 256 including cell column structures 2560 to 2567, the cell column structures respectively corresponding to Figure 2B The cell column structures 2560 to 2567. The memory array 300F further has several dummy cell column structures 257, including dummy cell column structure 257', which can correspond to... Figure 2B The dummy cell column structure 257. The memory array 300F further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2443, dummy back-side gate line 260, back-side gate lines 2444 to 2447, and a second sense select line 252, which respectively correspond to... Figure 2B The system includes a first sense select line 248, back-side gate lines 2440 to 2443, dummy back-side gate lines 260, back-side gate lines 2444 to 2447, and a second sense select line 252. It should be understood that fewer or more back-side gate lines 244 and dummy back-side gate lines 260 may be used between sense select lines 248 and 252, and fewer or more cell column structures 256 may be associated with each back-side gate line 244, and fewer or more dummy cell column structures 257 may be associated with each dummy back-side gate line 260.

[0074] Figure 3G A top view depicting a memory array 300G, which may contain the same memory array structure as memory array 300F. Memory array 300G has several cell column structures 256, including cell column structures 2560 to 2567, which may correspond to the memory array 300F, respectively. Figure 2ABack-side gate lines 2440 to 244 M The corresponding cell column structure 256, where M = 7. The memory array 300G further has several dummy cell column structures 257, including dummy cell column structure 257', which can correspond to... Figure 2B The virtual cell column structure 257. The memory array 300G further depicts folded sensing lines 2580 to 2583, each of which can individually correspond to Figure 2B The sensing lines 258. It should be recognized that fewer or more sensing lines 258 can be used, and fewer or more cell array structures can be associated with each sensing line 258. The memory array 300G further depicts a common source 216 oriented horizontally and connected to each of the sensing lines 258 via corresponding contacts 366, and lower data lines 2540 to 2543 oriented vertically and each connected to the corresponding sensing lines 2580 to 2583 via corresponding contacts 367. It should be noted that the lower data lines 254 and the common source 216 can be connected to additional memory cell blocks (in Figure 3D Sensing line 258 (not depicted in the text).

[0075] Figure 4A The use according to the embodiments is as follows Figure 3A and 3B A conceptual diagram of a portion of the memory cell block of the array structure depicted in the image shows the layout of the higher data lines 204 connected.

[0076] Figure 4A A top view depicting a memory array 400A having several cell column structures 256, the cell column structures corresponding to... Figure 3A and 3B The cell column structure 256. The memory array 400A further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2447, and a second sense select line 252, which respectively correspond to... Figure 2A First sensing selection line 248, back gate lines 2440 to 244 M and a second sense selection line 252, where M = 7. It should be recognized that fewer or more back-side gate lines 244 can be used between sense selection lines 248 and 252, and fewer or more cell column structures can be associated with each back-side gate line 244. The memory array 400A further depicts diagonally oriented sense lines 2580 to 2582, each of which can individually correspond to... Figure 2AThe sensing line 258. It should be appreciated that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. The sensing line 258 may not be orthogonal to the back-side gate line 244, for example, it may be tilted relative to the back-side gate line 244. The memory array 400A further depicts a number of vertically oriented higher data lines 204, including higher data lines 2040 to 204. 21 The higher data line 204 can be orthogonal to the back gate line 244.

[0077] Reference corresponds to Figure 2A 258 sensing lines Figure 4A Sensing line 2582, Figure 4A The higher data line 2048 can correspond to Figure 2A The higher data line is 2040. Figure 4A The higher data line 204 10 Can correspond to Figure 2A The higher data line is 2041. Figure 4A The higher data line 204 11 Can correspond to Figure 2A The higher data line is 2042. Figure 4A The higher data line 204 13 Can correspond to Figure 2A The higher data line is 2043. Figure 4A The higher data line 204 16 Can correspond to Figure 2A The higher data line is 2044. Figure 4A The higher data line 204 18 Can correspond to Figure 2A The higher data line is 2045. Figure 4A The higher data line 204 19 Can correspond to Figure 2A The higher data line is 2046, and Figure 4A The higher data line 204 21 Can correspond to Figure 2A The higher data line is 2047, where M = 7. Although the higher data lines are 2043 to 2046... Figure 2A Although not explicitly depicted in the figure, it is clear from the diagram that the higher data lines 204 of the memory cell array 200A can be consecutively numbered from higher data line 2040 to higher data line 204. M Each of the higher data lines 204 can be connected to one or more corresponding cell column structures 256 via a corresponding contact 464. It should be noted that the higher data lines 204 can be connected to additional memory cell blocks (in... Figure 4A The unit column structure 256 (not depicted in the text)

[0078] It should be noted that a set of higher data lines 204 (e.g., higher data lines 2044, 2046, 2047, 2049, 2040) connected to the cell column structure 256, which is capacitively coupled to a sensing line 258 (e.g., sensing line 2581), are also connected to this structure. 12 204 14 204 15 and 204 17 A set of higher data lines 204 (e.g., higher data lines 2048, 204) can be connected to a cell column structure 256 that is capacitively coupled to different sensing lines 258 (e.g., adjacent sensing lines 2582). 10 204 11 204 13 204 16 204 18 204 19 and 204 21 They are mutually exclusive. In this case, one or more of the higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2581 may interleave with one or more higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2582. Additionally, a group of higher data lines 204 (e.g., higher data lines 2040, 2042, 2043, 2045, 2048, 2044) connected to the cell column structure 256 capacitively coupled to a sensing line 258 (e.g., sensing line 2580) may also interleave with the higher data lines 204 connected to the cell column structure 256 capacitively coupled to a sensing line 258 (e.g., sensing line 2580). 10 204 11 and 204 13 It can be partially coupled to a set of higher data lines 204 (e.g., higher data lines 2048, 204) of a cell column structure 256 that are capacitively coupled to different sensing lines 258 (e.g., sensing line 2582). 10 204 11 204 13 204 16 204 18 204 19 and 204 21 They are mutually exclusive. In this case, there may be no crossover at the higher data line 204.

[0079] Figure 4B According to another embodiment of use, such as Figure 3C and 3D A conceptual diagram of a portion of the memory cell block of the array structure depicted in the image shows the layout of the higher data lines 204 connected.

[0080] Figure 4B A top view depicting a memory array 400B having several cell column structures 256, the cell column structures corresponding to... Figure 3Cand 3D The cell column structure 256. The memory array 400B further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2443, and a second sense select line 252, which respectively correspond to... Figure 2A First sensing selection line 248, back gate lines 2440 to 244 M and a second sense selection line 252, where M = 3. It should be recognized that fewer or more back-side gate lines 244 can be used between sense selection lines 248 and 252, and fewer or more cell column structures can be associated with each back-side gate line 244. The memory array 400B further depicts diagonally oriented sense lines 2580 to 2584, each of which can individually correspond to... Figure 2A The sensing line 258. It should be appreciated that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. The sensing line 258 may not be orthogonal to the back-side gate line 244, for example, it may be tilted relative to the back-side gate line 244. The memory array 400B further depicts a plurality of vertically oriented higher data lines 204, including higher data lines 2040 to 204. 23 The higher data line 204 can be orthogonal to the back gate line 244.

[0081] Reference corresponds to Figure 2A 258 sensing lines Figure 4B Sensing line 2584, Figure 4B The higher data line 204 16 Can correspond to Figure 2A The higher data line is 2040. Figure 4B The higher data line 204 18 Can correspond to Figure 2A The higher data line is 2041. Figure 4B The higher data line 204 21 Can correspond to Figure 2A The higher data line is 2042, and Figure 4B The higher data line 204 23 Can correspond to Figure 2A The higher data line 2043, where M=3. It should be noted that the higher data line 204 can be connected to an additional memory cell block (in...). Figure 4B The unit column structure 256 (not depicted in the text)

[0082] It should be noted that a set of higher data lines 204 (e.g., higher data lines 2040, 2042, 2045, and 2047) connected to a cell column structure 256 capacitively coupled to a sensing line 258 (e.g., sensing line 2580) can be connected to a set of higher data lines 204 (e.g., higher data lines 2044, 2046, 2049, and 2041) connected to a cell column structure 256 capacitively coupled to a different sensing line 258 (e.g., adjacent sensing line 2581). 11 They are mutually exclusive. In this case, one or more of the higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2580 may interleave with one or more higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2581. This relationship also applies to each group of higher data lines 204 connected to the cell column structure 256 capacitively coupled to each of the remaining sensing lines 258.

[0083] Figure 4C According to another embodiment of use, such as Figure 3C and 3E A conceptual diagram of a portion of the memory cell block of the array structure depicted in the image shows the layout of the higher data lines 204 connected.

[0084] Figure 4C A top view depicting a memory array 400C having several cell column structures 256, the cell column structures corresponding to... Figure 3C and 3E The cell column structure 256. The memory array 400C further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2443, and a second sense select line 252, which respectively correspond to... Figure 2A First sensing selection line 248, back gate lines 2440 to 244 M and a second sensing selection line 252, where M = 3. It should be appreciated that fewer or more back-side gate lines 244 can be used between sensing selection lines 248 and 252, and fewer or more cell column structures can be associated with each back-side gate line 244. The memory array 400C further depicts vertically oriented sensing lines 2580 to 258. 11 Each of them can correspond to individually. Figure 2A Sensing lines 258. It should be appreciated that fewer or more sensing lines 258 can be used, and fewer or more cell column structures can be associated with each sensing line 258. Sensing lines 258 may be orthogonal to the back-side gate line 244. The memory array 400C further depicts several vertically oriented higher data lines 204, including higher data lines 2040 to 204. 23 The higher data line 204 can be orthogonal to the back gate line 244.

[0085] Reference corresponds to Figure 2A 258 sensing lines Figure 4C 2580 sensing lines Figure 4C The higher data line 2040 can correspond to Figure 2A The higher data line is 2040, and Figure 4C The higher data line 2041 can correspond to Figure 2A The higher data line 2041, where M = 1. It should be noted that the higher data line 204 can be connected to an additional memory cell block (in...). Figure 4C The unit column structure 256 (not depicted in the text)

[0086] It should be noted that a set of higher data lines 204 (e.g., higher data lines 2040 and 2041) connected to a cell column structure 256 capacitively coupled to a single sensing line 258 (e.g., sensing line 2580) may be mutually exclusive with a set of higher data lines 204 (e.g., higher data lines 2042 and 2043) connected to a different sensing line 258 (e.g., adjacent sensing line 2581). In this case, the sets of higher data lines 204 may not be interleaved. This relationship also applies to the sets of higher data lines 204 connected to each of the remaining sensing lines 258 in the cell column structure 256.

[0087] Figure 4D According to another embodiment of use, such as Figure 3F and 3G The conceptual diagram depicts a portion of the memory cell block of the array structure shown, illustrating the layout of the higher data lines 204 connected.

[0088] Figure 4D A top view depicting a memory array 400D having several cell column structures 256 and dummy cell column structures 257, which respectively correspond to Figure 3F and 3G The memory array 400D further depicts a horizontally oriented first sense select line 248, back-side gate lines 2440 to 2443, dummy back-side gate lines 260, back-side gate lines 2444 to 2447, and a second sense select line 252, which respectively correspond to the cell column structure 256 and the dummy cell column structure 257. Figure 2BThe memory array 400D includes a first sense selection line 248, back-side gate lines 2440 to 2443, dummy back-side gate lines 260, back-side gate lines 2444 to 2447, and a second sense selection line 252. It should be understood that fewer or more back-side gate lines 244 and dummy back-side gate lines 260 can be used between sense selection lines 248 and 252, and fewer or more cell column structures 256 can be associated with each back-side gate line 244, and fewer or more dummy cell column structures 257 can be associated with each dummy back-side gate line 260. The memory array 400D further depicts folded sense lines 2580 to 2583, each of which can individually correspond to... Figure 2B The sensing line 258. It should be appreciated that fewer or more sensing lines 258 may be used, and fewer or more cell column structures 256 and dummy cell column structures 257 may be associated with each sensing line 258. The sensing line 258 may not be orthogonal to the back gate line 244, for example, it may be tilted relative to the back gate line 244. The memory array 400D further depicts a number of vertically oriented higher data lines 204, including higher data lines 2040 to 2049. The higher data lines 204 may be orthogonal to the back gate line 244.

[0089] Reference corresponds to Figure 2B 258 sensing lines Figure 4D Sensing line 2583, Figure 4D The higher data line 204 20 Can correspond to Figure 2B The higher data line is 2040. Figure 4D The higher data line 204 18 Can correspond to Figure 2B The higher data line is 2041. Figure 4D The higher data line 204 17 Can correspond to Figure 2B The higher data line is 2042, and Figure 4D The higher data line 204 15 Can correspond to Figure 2B The higher data line 2043. Each of the higher data lines 204 can be connected to one or more corresponding cell column structures 256 via a corresponding contact 464.

[0090] It should be noted that a set of higher data lines 204 (e.g., higher data lines 2043, 2045, 2046, and 2048) connected to a cell column structure 256 capacitively coupled to a sensing line 258 (e.g., sensing line 2580) can be connected to a set of higher data lines 204 (e.g., higher data lines 2047, 2049, and 2040) connected to a different sensing line 258 (e.g., a sensing line 2581 adjacent to, for example, a sensing line 2581). 10 and 20412 They are mutually exclusive. In this case, one or more of the higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2580 may interleave with one or more higher data lines 204 connected to the cell column structure 256 capacitively coupled to the sensing line 2581. This relationship also applies to each pair of adjacent sensing lines 258.

[0091] Figure 5A-5N The illustration depicts integrated circuit structures during various manufacturing stages according to embodiments, such as sensing lines (e.g., Figure 2A Or a portion of the 2B sensing line 258) and associated components. In Figure 5A In this process, conductor 562 may be formed over dielectric 560 (e.g., on it). Conductor 562 may be formed of one or more conductive materials. Conductor 562 may include, consist of, or substantially consist of conductive doped polycrystalline silicon, and / or may include, consist of, or substantially consist of metals, such as refractory metals, or metal-containing materials, such as refractory metal silicides or metal nitrides (e.g., refractory metal nitrides), and any other conductive materials. As an example, conductor 562 may comprise tungsten (W) formed over dielectric 560 and titanium nitride (TiN) formed over tungsten. Dielectric 560 may include, consist of, or substantially consist of oxides, such as silicon dioxide (SiO2), and / or may include, consist of, or substantially consist of high-k dielectric materials, such as aluminum oxide (AlO2). x ), Hafnium oxide (HfO) x ), Hafnium aluminum oxide (HfAlO) x ), hafnium silicon oxide (HfSiO) x ), Lanthanum oxide (LaO) x ), tantalum oxide (TaO) x Zirconium oxide (ZrO) x ), Zirconia aluminum (ZrAlO) x Or yttrium oxide (Y₂O₃), and any other dielectric material. As used herein, a high-k dielectric means a material with a dielectric constant greater than that of silicon dioxide. Dielectric 560 may further comprise, consist of, or substantially consist of spin-coated dielectric materials, such as silsesquioxane (HSQ), hexamethyldisiloxane, octamethyltrisiloxane, etc., or high-density plasma (HDP) oxides. As an example, dielectric 560 may contain silicon dioxide. Dielectric 560 may be formed to overlay other circuit systems, such as… Figure 2C 266. Peripheral circuit system.

[0092] exist Figure 5BIn this process, conductor 562 may be patterned to define lower data lines 254. Patterning may include forming a photomask (not depicted) over conductor 562 (e.g., on it) to define a removal area, followed by a removal process, such as anisotropic etching. The mask may then be removed, for example, by ashing.

[0093] exist Figure 5C In this embodiment, dielectric 564 may be formed over dielectric 560 and lower data line 254 (e.g., on thereon). Dielectric 564 may contain one or more dielectric materials, such as the dielectric material described with reference to dielectric 560. As an example, dielectric 564 may contain silicon dioxide. Conductor 566 may be formed over dielectric 564 (e.g., on thereon). Conductor 566 may contain one or more conductive materials, such as the conductive material described with reference to conductor 562. As an example, conductor 566 may contain tungsten. Dielectric 568 may be formed over conductor 566 (e.g., on thereon). Dielectric 568 may contain one or more dielectric materials, such as the dielectric material described with reference to dielectric 560. As an example, dielectric 568 may contain silicon dioxide. As another example, dielectric 568 may comprise a SiO2 / SiN / SiO2 structure, commonly referred to as ONO. The sacrificial material 570 may be formed over (e.g., on) the dielectric 568. The sacrificial material 570 may contain a material that can withstand removal without significantly affecting the dielectric 568. As an example, the sacrificial material 570 may contain silicon nitride (SiN).

[0094] exist Figure 5D In this process, conductor 566, dielectric 568, and sacrificial material 570 may be patterned to define back-side gate line 244. 00 up to 244 02 First sensor selection line 248 00 And the first choice line 248 10 Examples of dielectric 568 and sacrificial material 570 overlying each other. For example, a patterned mask can be formed over the sacrificial material 570 to define a removal region, and the respective instances can be defined using an anisotropic removal process (e.g., reactive ion etching (RIE)). The spaces or gaps between these instances can be filled with dielectric 572. Dielectric 572 may contain one or more dielectric materials, such as the dielectric material described with reference to dielectric 560. As an example, after patterning, silicon dioxide can be formed over the resulting structure, and any excess silicon dioxide overlying the sacrificial material 570 can be removed using chemical mechanical polishing (CMP) to produce Figure 5D The structure depicted in the text.

[0095] For the first memory cell block Figure 5D Back gate line 24400 up to 244 02 Can correspond to Figure 2A Or the back-side gate lines 2440 to 2442 of 2B. For the first memory cell block, Figure 5D First sensing selection line 248 00 Can correspond to Figure 2A Or the first sensing selection line 248 of 2B. For the second memory cell block that shares the connection to the same lower data line 254, Figure 5D First sensing selection line 248 10 Can correspond to Figure 2A Or the first sensing selection line 248 of 2B.

[0096] exist Figure 5E In this embodiment, a via can be formed in dielectric 572 using, for example, a resonant interconnect (RIE), and can be filled with a conductive material to form a contact 574 to the lower data line 254. The contact 574 may contain one or more conductive materials, such as those described with reference to conductor 562. In one embodiment, the contact 574 may comprise conductive-doped polysilicon (e.g., N+ type conductivity) formed over the lower data line 254 and titanium nitride (TiN) formed over the conductive-doped polysilicon. Figure 5F In this context, instances of sacrificial material 570 may be removed, for example, using isotropic removal processes (such as chemical or plasma etching) to define voids 576.

[0097] exist Figure 5G In this embodiment, semiconductor 578 may be formed as an example of dielectric 568, dielectric 572, and contact 574 (e.g., on it). Semiconductor 578 may comprise, consist of, or be substantially composed of polycrystalline silicon, monocrystalline silicon, or amorphous silicon, and any other semiconducting material, such as germanium, silicon-germanium, or silicon-germanium-carbon semiconductor. Semiconductor 578 may be formed, for example, using chemical vapor deposition (CVD), low-pressure CVD (LPCVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The semiconductor may have a conductivity type, for example, a first conductivity type. As an example, semiconductor 578 may contain amorphous silicon. Semiconductor 578 may be doped during or after its formation. As an example, semiconductor 578 may be a p-type semiconductor. For example, diborane (B₂H₆) can be added to the reaction gas in a CVD process to form amorphous silicon, thereby incorporating sufficient boron into semiconductor 578 to achieve the required threshold voltage for future passage through gate 238, for example, a dopant concentration of 1E¹⁸ / cm². 3As an alternative example, semiconductor 578 can be an n-type semiconductor. For instance, phosphine (PH3) can be added to the reaction gas of a CVD process to form amorphous silicon, thereby incorporating sufficient phosphorus into semiconductor 578 to achieve the desired threshold voltage for future passage through gate 238, for example, a dopant concentration of 5E18 / cm³. 3 Although not depicted, semiconductor 578 may be patterned to define future sensing lines 258.

[0098] exist Figure 5H In this embodiment, dielectric 580 may be formed over (e.g., on) semiconductor 578 and fill voids 576. Dielectric 580 may contain one or more dielectric materials, such as the dielectric materials described with reference to dielectric 560. As an example, silicon dioxide may be formed over semiconductor 578, and any excess silicon dioxide overlying semiconductor 578 may be removed using chemical mechanical polishing (CMP) to produce... Figure 5H The structure depicted in the text.

[0099] exist Figure 5IIn this context, portions of semiconductor 578 may be conductively doped with dopant impurities of a second conductivity type, which may be the same as or different from the first conductivity type, for example, to form source / drain regions. For the purposes of this document, dopant impurities are ions, elements, or molecules, or some combination of ions, elements, and / or molecules, added to semiconductor 578 to apply bulk conductivity to the affected portions. Such doping may involve acceleration of the dopant impurities, as conceptually depicted by arrow 582. As an example, the dopant impurity may be an n-type impurity, such as ions of arsenic (As), antimony (Sb), phosphorus (P), or another n-type impurity. Examples of such doping processes may include plasma doping (PLAD) and / or wire implantation. An annealing process may be used to diffuse implanted dopant impurities within portions of semiconductor 578 not covered by dielectric 580, thereby defining examples of semiconductors (e.g., channels) 584 having a first conductivity type and examples of conductively doped semiconductors 586 having a second conductivity type. For example, instances of semiconductor 584 overlying the back-side gate line 244 or the sense select line 248 can respectively form a channel region for future access gate 238 or the first sense select gate 246, each having the back-side gate line 244 or the sense select line 248 as its control gate and a corresponding instance of dielectric 568 as its gate dielectric. Continuing with the example, instances of conductively doped semiconductor 586 on both sides of the back-side gate line 244 or the sense select line 248 can respectively form the source / drain regions of the access gate 238 or the first sense select gate 246. It should be noted that the doping level of the instances of conductively doped semiconductor 586 can be one or more orders of magnitude higher than the doping level of the instances of semiconductor 584. As an example, for a semiconductor 578 with p-type conductivity, the doping level of the instances of conductively doped semiconductor 586 can be 3E19 / cm^3, while the doping level of the instances of semiconductor 584 is 1E18 / cm^3. 3 For other embodiments, such as the embodiment having a semiconductor 578 with n-type conductivity, additional doping can be removed so that the doping level of the example of semiconductor 586 and the example of semiconductor 584 can be maintained at 5E18 / cm², respectively. 3 And have the same conductivity type. For such embodiments, the dielectric 568 having an ONO or similar charge trap structure can be programmed to adjust the threshold voltage through gate 238.

[0100] exist Figure 5JIn this embodiment, semiconductor 588 may be formed as an exposed portion (e.g., thereon) of an example of dielectric 580 and an example of conductively doped semiconductor 586. Semiconductor 588 may comprise, consist of, or substantially consist of polycrystalline silicon, monocrystalline silicon, or amorphous silicon, and any other semiconducting material, such as germanium, silicon-germanium, or silicon-germanium-carbon semiconductor. Semiconductor 588 may be formed as described with reference to semiconductor 578 and may have the same conductivity type, such as a first conductivity type, or a different conductivity type, such as a second conductivity type. As an example, semiconductor 588 may be p-type amorphous silicon. For other embodiments, semiconductor 588 may be n-type amorphous silicon. For some embodiments, semiconductor 588 may have a density of 5E18 / cm. 3 The doping level. When semiconductor 588 and conductively doped semiconductor 586 have the same conductivity type, the resulting transistor can be a depletion-mode or normally-on transistor. When semiconductor 588 and conductively doped semiconductor 586 have different conductivity types, the resulting transistor can be an enhancement-mode or normally-off transistor, or a depletion-mode or normally-on transistor. For some embodiments, semiconductor 588 can be referenced... Figure 5I The described doping is formed prior to the formation and can be received in parallel with the conductive doped semiconductor 586. As used herein, the first and second actions are performed in parallel when the first action is performed simultaneously with the second action for at least a portion of the duration of the second action.

[0101] Dielectric 590 may be formed over (e.g., on) semiconductor 588. Dielectric 590 may contain one or more dielectric materials, such as the dielectric material described with reference to dielectric 560. As an example, dielectric 590 may contain silicon dioxide. Alternatively or additionally, dielectric 590 may contain a high-k dielectric. Sacrificial material 592 may be formed over (e.g., on) dielectric 590. Sacrificial material 592 may contain a material that can withstand removal without significantly affecting the dielectric 590. As an example, sacrificial material 592 may contain silicon nitride (SiN).

[0102] exist Figure 5KIn this structure, semiconductor 588, dielectric 590, and sacrificial material 592 may be patterned to define instances of semiconductor (e.g., channel) 589, and instances of dielectric 590 and sacrificial material 592 overlying each other. For example, a patterned mask may be formed over sacrificial material 592 to define a removal region, and the respective instances may be defined using an anisotropic removal process (e.g., reactive ion etching (REI)). The spaces or gaps between these instances may be filled with dielectric 594. Dielectric 594 may contain one or more dielectric materials, such as those described with reference to dielectric 560. As an example, silicon dioxide may be formed over the resulting structure, and any excess silicon dioxide overlying the instance of sacrificial material 592 may be removed using chemical mechanical polishing (CMP) to produce... Figure 5K The structure is depicted in the diagram. In some embodiments, the exposed portion of the conductive-doped semiconductor 586 may receive additional doping of the same conductivity type prior to the formation of the dielectric 594.

[0103] exist Figure 5L In this context, instances of sacrificial material 592 can be removed, for example, using isotropic removal processes (e.g., chemical or plasma etching) to define voids 596. Figure 5M In the middle, a plug 598 can be formed in the gap 596. 00 Up to 598 02 As an example, a conductive material (e.g., titanium nitride on tungsten) may be formed over an example of dielectric 590 and an example of dielectric 594 (e.g., on top of them) to fill voids 596, and CMP may be used to remove any excess conductive material over an example of dielectric 594 to produce Figure 5M The structure is depicted in the image. Plug 598 can be formed from a material selected to act as a termination layer during subsequent processing, as shown in the reference. Figure 6B As described, and can be sacrificed and removed during subsequent processing, for example, see reference. Figure 6C As described. (600 in parentheses) Figure 5M In the integrated circuit structure, it can be Figures 6A-6F The part depicted in the text.

[0104] although Figure 5A-5M Depicting what can correspond to a sensing line (e.g., Figure 2A An integrated circuit structure comprising a portion of the sensing line 258 (or 2B) and associated elements at the end of the lower data line 254, but Figure 5N Can depict sensing lines (e.g., Figure 2A The associated element at the other end (e.g., the end adjacent to the common source 216) of the sensing line 258 of 2B. Figure 5N The structure can be with Figure 5M The structures are formed in parallel, and the back-side gate lines 244 are depicted accordingly.0(M-1) and 244 0M and the corresponding 598 0(M-1) and 598 0M The second select line 252, and the common source 216 and its connection via conductive contact 574 to an instance of conductive doped semiconductor 586. The common source 216 and the second sense select line 252 may be connected in parallel with the first sense select line 248 and the back-side gate line 244 by conductor 566 (e.g., as shown in...). Figures 5C-5D (Formed in the middle)

[0105] Figures 6A-6F Depicting corresponding to various manufacturing stages according to additional embodiments Figure 2A Or a portion of a 2B cell column structure 256 integrated circuit structure. For example, Figures 6A-6F Can be used to depict in formation Figure 5M Further processing following the structure. It should be understood that... Figures 6A-6F This can be equally applied to the formation of the virtual unit column structure 257, wherein Figures 6A-6F Back gate line 244 X In reality, the back-side gate line 260 is a dummy line.

[0106] exist Figure 6A In the middle, the back gate line 244 X This corresponds to gate 238 X The second control gate 242, where X can be any integer value from zero to M, and the number of cell column structures 256 associated with the sensing line 258 is equal to M+1. (Passing through gate 238) X It may further include a channel formed by semiconductors 584 and 589, a gate dielectric formed by dielectrics 568 and 590, and a source / drain region formed by conductive doped semiconductor 586. (Through gate 238) X The first control gate 240 may not yet be formed, but its future location may correspond to plug 598. X The location.

[0107] exist Figure 6A In this process, examples of dielectric 602 (e.g., 6020 to 6024) and examples of sacrificial material 604 (e.g., 6040 to 6043) may be formed alternately over the plug 598. Xand dielectric 594 (e.g., thereon). Examples of dielectric 602 may each contain one or more dielectric materials, such as the dielectric materials described with reference to dielectric 560. As an example, an example of dielectric 602 may contain silicon dioxide. Examples of sacrificial material 604 may contain a material that can be removed without significantly affecting the material of dielectric 602. As an example, an example of sacrificial material 604 may contain silicon nitride. Additional examples of dielectric 602 and examples of sacrificial material 604 may be formed according to the number of transistors (e.g., memory cells, GIDL generator gates, select gates, and capacitors) intended to be formed for a future cell column structure. Although all anticipated examples of dielectric 602 and examples of sacrificial material 604 may be formed in progress Figure 6B The process is formed before the process, but the typical process for such stacked structures can be performed in stages because the aspect ratio of the through-hole 606 may be too large to reliably form the entire structure into a continuous solid.

[0108] exist Figure 6B In the middle, through hole 606 can be plugged with plug 598. X Examples of terminating elements passing through dielectric 602 and sacrificial material 604 are formed. For example, an anisotropic removal process (e.g., RIE) can be used, wherein plug 598 X It acts as an etch stop layer. Therefore, via 606 can extend to plug 598. X The surface or below it.

[0109] exist Figure 6C China, Serbia 598 X The via 606 can be removed after its formation to complete the void 607. The channel material structure 610 can be formed via sidewalls that line the void 607, for example, along the sidewalls of instances of dielectric 602 and sacrificial material 604, and along the sidewalls of dielectric 594 and the surface (e.g., the upper surface) of dielectric 590. In some embodiments, dielectric 590 can also be removed prior to the formation of the channel material structure 610, and portions of the channel material structure 610 can be used as the gate dielectric leading to the resulting through gate 238.

[0110] A portion 608 of the channel material structure 610 is depicted in further detail in the extended portion 608'. As depicted, the channel material structure 610 may include a charge-blocking material 612 formed with an inner lining void 607, a charge storage material 614 formed on the charge-blocking material 612, a dielectric (e.g., a gate dielectric) 616 formed on the charge storage material 614, and a channel material (e.g., a semiconductor) 618 formed on the dielectric 616. The charge storage material 614 may contain a dielectric or conductive charge storage material. The charge storage material 614 may further contain both dielectric and conductive materials, for example, conductive nanoparticles in a dielectric bulk material. For a charge storage material 614 containing a conductive material as its bulk or continuous structure, the resulting memory cell is generally referred to as a floating-gate memory cell. For a charge storage material 614 containing a dielectric material as its bulk or continuous structure, the resulting memory cell is generally referred to as a charge-trapping memory cell. In one embodiment, the charge blocking material 612, the charge storage material 614, and the dielectric 616 may form an ONO structure. The channel material 618 may be part of a continuous semiconductor structure of each transistor in a future cell array structure, or may be otherwise electrically connected to the channel of each transistor in the future cell array structure, which may include selective electrical connection to the channel.

[0111] Charge blocking material 612 can be used as a charge blocking node for future memory cells and other transistors with the same cell array structure, and may contain one or more dielectric materials, such as those described with reference to dielectric 560. For example, charge blocking material 612 may contain a high-k dielectric material. Charge storage material 614 can be used as a charge storage node for future memory cells and other transistors with the same cell array structure, and may contain one or more conductive or dielectric materials capable of storing charge. For example, charge storage material 614 may contain polysilicon, which may be conductively doped. Dielectric 616 can be used as a gate dielectric for future memory cells and other transistors with the same cell array structure, and may contain one or more dielectric materials, such as those described with reference to dielectric 568. For example, dielectric 568 may contain silicon dioxide. Channel material 618 can be used as a channel for future memory cells and other transistors with the same cell array structure, and may contain one or more semiconductors, such as those described with reference to semiconductor 578.

[0112] exist Figure 6D In this process, an instance of sacrificial material 604 can be removed to define voids 620, for example, voids 6200 to 6203. Removal may include isotropic removal processes, such as plasma etching. Figure 6EIn this embodiment, optional examples of charge-blocking material 622 (e.g., examples of charge-blocking materials 6220-6223) may be formed to respectively line voids 620, such as voids 6200 to 6203. Examples of charge-blocking material 622 may comprise one or more dielectric materials, such as those described with reference to dielectric 560, and may comprise high-k dielectric materials. For embodiments having charge-blocking material 612, examples of charge-blocking material 622 may be used as additional charge-blocking material for future memory cells and other transistor charge-blocking nodes having the same cell-row structure. For embodiments without charge-blocking material 612, examples of charge-blocking material 622 may be used alone as charge-blocking nodes for future memory cells and other transistors having the same cell-row structure. For embodiments with and without examples of charge-blocking material 612, charge-blocking material 612 may be used alone as charge-blocking nodes for future memory cells and other transistors having the same cell-row structure. Examples of conductor 624 (e.g., examples of conductors 6240 to 6243) may be formed to fill voids 620, such as voids 6200 to 6203. Examples of conductor 624 may contain one or more conductive materials, such as the conductive materials described with reference to conductor 562.

[0113] A transistor may be formed at each intersection of an instance of conductor 624 and channel material 618, wherein an instance of conductor 624 may serve as the control gate of the transistor, an adjacent channel material 618 may serve as the channel of the transistor, and instances of charge blocking material 622 and / or charge blocking material 612, charge storage material 614, and dielectric 616 between instances of conductor 624 and adjacent channel material 618 may serve as the charge blocking node, charge storage node, and gate dielectric of the transistor, respectively. For example, such a transistor may include a memory cell 208 of a future cell column structure, a GIDL generator gate 220, a higher select gate 212, a lower select gate 210, and / or a capacitor 226. For example, the channel material 618 adjacent to dielectric 590 may serve as a first control gate 240 having a semiconductor 589 as its channel and dielectric 590 as its gate dielectric.

[0114] Figure 6F Descendable in Figure 6E The opposite ends of the unit column structure depicted in the diagram. For example, although Figure 6E The closest associated element of the unit column structure can be depicted through the end of gate 238, but Figure 6F The end of the cell column structure that is closest to the associated higher data line 204 can be depicted. Figure 6F Other alternative instances of dielectric 602 may be described (e.g., dielectric 602) K-5 Up to 602K+1 Examples of charge blocking materials 622 (e.g., charge blocking material 622) K-5 To 622 K Examples of conductors, and examples of conductors 624 (e.g., conductor 624). K-5 To 624 K (Example), where K can be equal to the total number of memory cells 208 (including any dummy memory cells), GIDL generator gate 220, higher select gate 212, lower select gate 210 and capacitor 226 in the cell column structure minus 1. Figure 6F The channel material structure 610 described in the text can be used with... Figure 6E The channel material structure 610 depicted is continuous. The higher data line 204 can be connected to the channel material 618 of the channel material structure 610 via contact 464. Contact 464 may contain one or more conductive materials, such as the conductive material described with reference to conductor 562. In some embodiments, contact 464 may contain n + Type-doped conductive polysilicon. In other embodiments, contact 464 may include n-type conductive doped polysilicon formed as a coating over the channel material structure 610. + Type conductive doped polycrystalline silicon, formed as an overlay on n + The conductive doped polycrystalline silicon is composed of titanium nitride (TiN) and tungsten (W) formed as a coating on the titanium nitride. In other embodiments, the upper portion of the channel material 618 of the channel material structure 610 may be doped with n-type conductive doped polycrystalline silicon. + The contact 464 may contain titanium nitride (TiN) formed as a coating over the channel material structure 610 and tungsten (W) formed as a coating over the titanium nitride. Although Figures 6A-6F An example method for forming multiple series-connected and stacked transistors is described, wherein each transistor corresponds to a corresponding conductor 6240 to 624. K However, other methods of forming such transistors and other transistor structures in which the channel material can be used as capacitor electrodes can be used in conjunction with various embodiments.

[0115] It should be noted that, for example Figures 6A-6FThe channel material 618 of the cell array structure depicted is dead-headed at the bottom of the gap 607. Therefore, the channels of individual transistors in the cell array structure can be selectively connected to only one voltage node, such as the higher data line 204, to supply or sink current to those channels, and will be electrically floating (e.g., permanently electrically floating) unless connected (e.g., selectively connected) to the higher data line 204. This contrasts sharply with conventional NAND structures, where the channels of memory cells are selectively connected to voltage nodes at both ends of a series-connected string of memory cells, for example, selectively connected to a data line at one end and selectively connected to the source at the other end.

[0116] Figures 7A-7J Orthogonal views depicting the various structures of the sensing line according to an embodiment. Figure 7B Depicting the section intercepted along line BB′ Figure 7A A view of the structure. Figure 7D Depicting the section intercepted along line DD′ Figure 7C A view of the structure. Figure 7F Depicting the section intercepted along line FF′ Figure 7E A view of the structure. Figure 7H Draw the section intercepted along line HH′ Figure 7G A view of the structure. Figure 7J Depicting the section intercepted along line JJ′ Figure 7I A view of the structure.

[0117] Although semiconductor 588 is patterned in parallel with dielectric 590 and sacrificial material 592 to define instances of semiconductor 589 as having the same coverage area as the corresponding future channel material structure 610, Figure 7A and 7B An example is depicted in which semiconductor 588 can be patterned first in parallel with semiconductor 578 and then in parallel with dielectric 590 and sacrificial material 592. In this way, the physical width of semiconductor 589 (e.g., Figure 7B The distance from left to right in the middle can be the same as that of semiconductor 584 and conductive doped semiconductor 586 given through gate 238. The physical length of semiconductor 589 (e.g., Figure 7A The distance from left to right in the middle may differ from the physical length of semiconductor 584, but may provide a similar electrical channel length to semiconductor 584 due to the conductivity level of conductive doped semiconductor 586.

[0118] exist Figure 7C and 7D In this process, semiconductor 578 can be formed as a planarization layer, rather than as... Figure 5GThe serpentine layer depicted. The conductive-doped semiconductor 586 can be formed as an additional layer overlying the semiconductor 578 as a semiconductor material, such as conductive-doped polysilicon, subsequently patterned to define blocks of the conductive-doped semiconductor 586, as shown. Figure 7C and 7D As depicted in [reference needed]. These blocks of conductive doped semiconductor 586 can serve as source / drain regions of pass-through gate 238 and can extend to the next pass-through gate 238 or the first sense-select gate 246 or the second sense-select gate 250. Examples of semiconductor 588 patterned to define semiconductor 589 can be seen in [reference needed]. Figure 7A and 7B Perform as described to produce Figure 7C and 7D The structure depicted in the text. Relative to... Figures 7A-7B Implementation examples, Figures 7C-7D The addition of a substrate to the conductive doped semiconductor 586 can reduce the risk of damage to the conductive doped semiconductor 586 during the patterning of semiconductor 588 to form semiconductor 589.

[0119] exist Figure 7E and 7F In this process, semiconductor 578 can be formed as a planarization layer, rather than as... Figure 5G The serpentine layer depicted herein may be selectively conductively doped to define instances of semiconductor 584 and conductively doped semiconductor 586. An instance of semiconductor 584 may be used as a channel for the resulting two control gates through gate 238, for example, without the need to form semiconductor 589.

[0120] exist Figure 7G and 7H In this configuration, semiconductor 578 may be formed around the raised portion of the back-side gate line 244X and selectively conductively doped to define instances of semiconductor 584 and conductively doped semiconductor 586. An instance of semiconductor 584 may be used as a channel for the resulting two control gates through gate 238, for example, without the need to form semiconductor 589.

[0121] exist Figure 7I and 7J In this context, the two channels through gate 238 can be formed from separate, continuous semiconductor materials. For example, Figure 5C and 5D The processing can be performed without forming sacrificial material 570, and an example of semiconductor 578 can be formed as an example overlying dielectric 568 and dielectric 572 after patterning conductor 566 and dielectric 568 and forming dielectric 572. This example of semiconductor 578 can be selectively conductively doped to define semiconductor 584. lower and conductive doped semiconductor 586 lowerAn example. Then, a dielectric can be formed over the semiconductor 584. lower and conductive doped semiconductor 586 lower Examples of semiconductor 578 are patterned to define each instance of dielectric 726 passing through gate 238. Another instance of semiconductor 578 may then be formed as an exposed instance overlying dielectric 726 and conductively doped semiconductor 586. This instance of semiconductor 578 may be selectively conductively doped to define semiconductor 584. upper and conductive doped semiconductor 586 upper Examples.

[0122] Figures 8A-8C The integrated circuit structure during various manufacturing stages according to the embodiments is depicted. Figure 8A Descendable similar to Figure 6A The structure shown is structurally similar and can be formed in a similar manner. However, conductive doped polysilicon 830 and optional barrier layer 832 can be formed between dielectric 590 and plug 598. For example, conductive doped polysilicon 830 can be formed as an inner liner. Figure 5L A void 596 is formed in the silicon, and then a plug 598 can be formed to fill the remaining portion of the void 596. Optionally, a barrier layer 832 can be formed between the conductive doped polysilicon and the plug 598. Figure 8B In the middle, gap 607 can be similar to the reference. Figure 6B and 6C The described method involves the removal of plug 598 and barrier layer 832. The channel material structure can then be referenced. Figure 6C Formed as described, it comprises a charge blocking material 612, a charge storage material 614, a dielectric 616, and a channel material 618. In this embodiment, the first control gate 240 through gate 238 may be a discrete conductive element (e.g., conductively doped polysilicon 830) between the electrode of capacitor 226 (e.g., a field-effect transistor or the channel of channel material 618) and the channel of said through gate 238 (e.g., semiconductor 589).

[0123] although Figures 8A-8C The example uses conductive-doped polycrystalline silicon, but other conductive materials can also be used, such as the conductive materials described in reference conductor 562. Additionally, although... Figures 8A-8C The examples depict an embodiment using two discrete channels through gate 238 to form, for example, a separate semiconductor 589; however, such a structure can also be used in embodiments using a single channel. Furthermore, although the conductive doped polysilicon 830 is formed below the channel material 618 and adjacent to its sidewalls, it can be formed as a point that does not extend to the sidewalls adjacent to the channel material 618.

[0124] Figures 9A-9EAn integrated circuit structure is depicted during various manufacturing stages according to another embodiment. Figure 9A Descendable similar to Figure 6A The structure shown is as described above and can be formed in a similar manner. However, dielectric 594 can be formed as a first dielectric 9400, a second dielectric 942, and a third dielectric 9401. Dielectrics 9400 and 9401 can be the same dielectric material, while dielectric 942 can be a different dielectric material. For example, dielectrics 9400 and 9401 can contain silicon carbon nitride (SiCN), while dielectric 942 can contain silicon dioxide. Additionally, conductive doped polysilicon 944 can be formed between dielectric 590 and plug 598. For example, conductive doped polysilicon 944 can be formed to fill... Figure 5L The bottom of the void 596 is filled with a plug 598, which can then be formed to fill the remaining portion of the void 596. Optionally, a barrier layer (not shown) can be formed between the conductive doped polysilicon 944 and the plug 598. Figure 9B In the middle, gap 607 can be similar to the reference. Figure 6B and 6C The described method is formed, including the removal of 598 and any barrier layer.

[0125] exist Figure 9C In the middle, the channel material structure can be followed up like the reference. Figure 6C As described, it comprises a charge-blocking material 612, a charge-storing material 614, a dielectric 616, and a channel material 618. Figure 9D In this process, the exposed portions of dielectric 942 and charge-blocking material 612, charge storage material 614, and dielectric 616 can be removed in a manner sufficient to remove the thickness of these materials, for example, leaving a recessed portion between channel material 618 and conductive-doped polysilicon 944. For example, an isotropic etching process can be used in conjunction with a material-selective chemical reaction to remove material from channel material 618, conductive-doped polysilicon 944, and dielectrics 9400 and 9401. Figure 9E In this embodiment, conductive doped polysilicon 946 can be selectively grown on the exposed surfaces of channel material 618 and conductive doped polysilicon 944 to bridge gaps and form electrical connections between channel material 618 and conductive doped polysilicon 944. In this embodiment, the first control gate 240 through gate 238 can be a discrete conductive element (e.g., conductive doped polysilicon 944 and 946) between the electrode of capacitor 226 (e.g., a field-effect transistor or the channel of channel material 618) and the channel of said through gate 238 (e.g., semiconductor 589). In this way, channel material 618 can be electrically connected to the first gate 240 through gate 238 instead of capacitively coupled to the first gate 240.

[0126] although Figures 9A-9EThe examples depict embodiments using two discrete channels through gate 238 to form, for example, a separate semiconductor 589; however, such structures can also be used in embodiments using a single channel. Furthermore, although the conductive doped polysilicon 946 is formed below the channel material 618 and adjacent to its sidewalls, it can be formed as a point that does not extend to the adjacent sidewalls of the channel material 618. For example, forming the dielectric 9401 thicker could limit the conductive doped polysilicon 946 to be formed only below the channel material 618.

[0127] Figure 10A and 10B The integrated circuit structure at a specific manufacturing stage is depicted according to other embodiments. Figure 10A The embodiments can be described as similar to Figure 6C The structure shown is structurally similar and can be formed in a similar manner. However, a high-k dielectric 1050 can be formed between the semiconductor 589 and the plug 598. For example, the high-k dielectric 1050 can be formed by forming an inner liner. Figure 5L The lower portion (e.g., the bottom) of the gap 596 is filled, and then a plug 598 may be formed to fill the remaining portion of the gap 596. In some embodiments, dielectric 590 may be omitted, wherein the high-k dielectric 1050 serves as the gate dielectric through the first control gate 240 of gate 238. Gap 607 may be similar to reference [reference missing]. Figure 6B and 6C The described method involves the removal of plug 598. Furthermore, the channel material structure 610 can be connected as in the reference... Figure 6C It forms as described.

[0128] Figure 10B The embodiments can also depict similar Figure 6C The structure shown is structurally similar and can be formed in a similar manner. However, a high-k dielectric 1050 can be formed between the semiconductor 589 and the plug 598. For example, the high-k dielectric 1050 can be formed by forming an inner liner. Figure 5L A void 596, such as the bottom and sidewalls of void 596, is formed, and then a plug 598 may be formed to fill the remainder of said void 596. In some embodiments, dielectric 590 may be omitted, wherein high-K dielectric 1050 serves as the gate dielectric through the first control gate 240 of gate 238. In other embodiments, dielectric 590 may be de minimis, for example, with a thickness of approximately 1 nm. Void 607 may be similar to reference [reference]. Figure 6B and 6C The described method involves the removal of plug 598. Furthermore, the channel material structure 610 can be connected as in the reference... Figure 6C It forms as described. Figure 10A and 10BIn this embodiment, the use of a high-k dielectric helps suppress electron tunneling backward from the sensing line 258. Although Figures 10A-10B The examples depict an embodiment using two discrete channels through gate 238 to form, for example, a separate semiconductor 589, but such a structure can also be used in embodiments using a single channel.

[0129] Erasing memory cells in the cell column structure of the erase embodiment can be performed similarly to a typical serially connected string of memory cells. In a typical erase operation, an erase voltage level can be applied to both ends of the string, while the select gate and GG gate are operated to induce GIDL current into the string. However, because one end of the cell column structure is floating, inducing GIDL current from both ends is not feasible. Therefore, according to the embodiment, an erase voltage level can be applied to the higher data line 204, while the GG gate 220 and the higher select gate 212 are operated to induce GIDL current into the cell column structure. For example, the GG gate 220 can receive a voltage level on the control line 224, for example, 11V lower than the erase voltage level, while the higher select gate 212 can receive a voltage level on the select line 215, for example, 4V lower than the erase voltage level. The access line 202 can receive a nominal voltage level, for example, 0.5V, configured to remove charge from the charge storage node. In some embodiments, the lower select gate 210 and capacitor 226 may receive a control gate voltage level configured to disable erasure, for example, 4V lower than the erase voltage level.

[0130] Figure 11 This is a timing diagram of a memory operation method according to an embodiment. For example, Figure 11 This can represent a method of programming one or more memory cells (e.g., logical pages of memory cells). The method can be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions can be executed by a controller, for example, control logic 116, to cause the memory (e.g., associated components of the memory) to perform the method.

[0131] Trace 1101 depicts the voltage level selectively connected to a higher data line 204 (e.g., selected higher data line 204) for memory cells selected for programming during a programming operation (e.g., selected memory cells that are enabled for programming). Trace 1103 depicts the voltage level selectively connected to a higher data line 204 (e.g., unselected higher data line 204) for memory cells not selected for programming during a programming operation (e.g., unselected memory cells that are disabled for programming). Trace 1105 depicts the voltage level of the selection line 215. Trace 1107 depicts the voltage level of the access line 202 connected to the selected memory cell, and trace 1109 depicts the voltage level of the access line 202 connected to the unselected memory cell.

[0132] At time t0, during the optional seeding phase of the programming operation, traces 1101 (e.g., selecting a higher data line) and 1103 (e.g., not selecting a higher data line) can be increased from an initial voltage level (e.g., ground or 0V) to an inhibit voltage level (e.g., 2.3V). Trace 1105 can be increased from the initial voltage level (e.g., ground or 0V) to a voltage level sufficient to activate the higher select gate (e.g., 4V). Although not depicted, control line 224 can also receive a voltage level sufficient to activate the GG gate. Trace 1107 (e.g., selecting an access line) and trace 1109 (e.g., not selecting an access line) can be increased from the initial voltage level (e.g., ground or 0V) to an intermediate voltage level between the pass voltage level of the programming operation and the initial voltage level. For example, traces 1107 and 1109 can be increased to 4V.

[0133] At time t1, during the optional setup phase of the programming operation, trace 1101 may return to its initial voltage level. In some embodiments, trace 1101 may decrease to an intermediate voltage level between the disabled voltage level and its initial voltage level. The use of different voltage levels on the higher data lines that are enabled for programming can be performed in a programming scheme known as Selective Slow Programming Convergence (SSPC), in which memory cells closer to the corresponding expected data state (e.g., partially enabled for programming) are programmed more slowly than memory cells further away from the corresponding expected data state (e.g., fully enabled for programming) when the same voltage level is received at the corresponding control gate. Different intermediate voltage levels can be used for different target data states. Trace 1105 may decrease to a voltage level configured to activate the higher select gate selectively connected to the selected higher data line and configured to deactivate the higher select gate selectively connected to the unselected higher data line. The remaining traces 1103, 1107, and 1109 may remain at their current voltage levels.

[0134] At time t2, traces 1107 and 1109 may be increased to the pass voltage level for programming operation. The pass voltage level is a voltage level higher than the expected threshold voltage level of each memory cell connected to the selected and unselected access lines, for example, a voltage level configured to activate each memory cell regardless of its data state. For example, traces 1107 and 1109 may be increased to 9V. At time t3, trace 1107 may be increased to the programming voltage level, for example, 15V or higher. The application of the programming voltage level from time t3 to time t4 may be referred to as a programming pulse.

[0135] At time t4, the programming operation can be completed, and the voltage levels can reach the corresponding recovery levels. For example, traces 1101 and 1103 can each transition to 0.5V, and traces 1105, 1107, and 1109 can each transition to 4V. During the programming operation, the voltage levels to the compensation gate, lower select gate, and control gate of the capacitor can remain at their initial voltage levels, such as ground or 0V.

[0136] A verification operation can be performed after each programming pulse to determine if any memory cells have reached their corresponding expected data state and / or, in the case of SSPC programming, their corresponding intermediate data state. Any memory cells that fail to reach their corresponding expected data state can be enabled for subsequent programming pulses at higher programming voltage levels. In the case of SSPC programming, memory cells that have not reached their corresponding intermediate data state can be fully enabled for programming during subsequent memory pulses, and memory cells that have reached their corresponding intermediate data state but not their corresponding expected data state can be partially enabled for programming during subsequent memory pulses.

[0137] Figure 12 This is a timing diagram of a memory operation method according to an embodiment. For example, Figure 12 A method may represent sensing (e.g., reading or verifying) one or more memory cells (e.g., logical pages of memory cells). The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller, for example, control logic 116, to cause the memory (e.g., associated components of the memory) to perform the method. Figure 12 Special reference Figure 2B The components described herein are for informational purposes only; however, it should be understood that this description may be used in conjunction with other memory array structures disclosed herein.

[0138] Trace 1211 can depict the voltage level of a higher data line 204 (e.g., higher data line 204) selectively connected to a memory cell (e.g., a selected memory cell) chosen for sensing during a sensing operation. For example, trace 1211 can correspond to higher data lines 2040-2043. Trace 1213 can depict the voltage level of an access line 202 (e.g., a selected access line 202) connected to a selected memory cell, and trace 1215 can depict the voltage level of an access line 202 (e.g., an unselected access line 202) not connected to a selected memory cell. For example, if a memory cell 208 selected for a sensing operation is connected to access line 2021, then trace 1213 can correspond to access line 2021, and trace 1215 can correspond to access lines 2020-202 that are not access lines 2021. NTrace 1217 depicts the voltage level of control line 213 connected to compensation gate 211. Trace 1219 depicts the voltage level of lower select line 214 connected to lower select gate 210. Trace 1221 depicts the voltage level of control line 228 connected to capacitor 226.

[0139] Traces 12230 and 12231 may depict the voltage levels of the channels (e.g., sensing nodes) of capacitors 226 through the first control gate 240 of gate 238 of cell column structure 256, which is deactivated in response to a read voltage level and whose selected memory cells are activated in response to a read voltage level. Traces 12250 to 12253 may depict the voltage levels of back-side gate lines 244, for example, the voltage levels of back-side gate lines 2440 to 2443 of memory cell subblock 2620 when selected memory cells are included in cell column structures 2560 to 2563.

[0140] At time t0, trace 1211 may increase from an initial voltage level (e.g., ground or 0V) to a precharge voltage level. The precharge voltage level may be a voltage level configured, for example, to activate the first control gate 240 of pass gate 238 for an enhancement-type device or, for example, to deactivate the first control gate 240 of pass gate 238 for a depletion-type device. For example, the precharge voltage level may be 4V. Traces 1213 and 1215 may increase from an initial voltage level (e.g., ground or 0V) to a pass voltage level for sensing operation. The pass voltage level is a voltage level higher than a predetermined threshold voltage level for each memory cell connected to selected and unselected access lines, for example, a voltage level configured to activate each memory cell regardless of its data state. For example, traces 1213 and 1215 may increase to 9V.

[0141] At time t0, traces 1217, 1219, and 1221 can each increase from an initial voltage level (e.g., ground or 0V) to a voltage level configured to activate their corresponding compensation gate 211, lower select gate 210, and capacitor 226. Although not depicted, higher select line 215 and control line 224 can also receive voltage levels configured to activate their respective higher select gate 212 and GG gate 220. Because these transistors are generally not programmed to the same threshold voltage level as memory cells, this voltage level may be low, for example, 2-3V.

[0142] As each transistor in the cell array structure 256 is activated from capacitor 226 to gate 220, traces 12230 and 12231 may increase the voltage level toward trace 1211 at time t0. At time t0, traces 12250 to 12253 may increase to a voltage level configured to activate the second select gate 242 of each corresponding pass gate 238. Although not depicted, the voltage levels applied to back-side gate lines 2444 to 2447 and the dummy back-side gate line 260 may also be configured to activate their corresponding pass gates 238.

[0143] At time t1, trace 1213 can be reduced to a read voltage level for sensing operations. The read voltage level can be configured to distinguish adjacent data states. Therefore, depending on the data state of the memory cell programmed to receive the read voltage at the control gate, the memory cell can remain active or inactive.

[0144] At time t2, trace 1211 may decrease from a pre-charge voltage level to a lower voltage level. This lower voltage level may be a voltage level configured, for example, to deactivate the first control gate 240 of gate 238 for an enhancement-type device or, for example, to activate the first control gate 240 of gate 238 for a depletion-type device. For example, the lower voltage level may be its initial voltage level. If a selected memory cell of cell column structure 256 is deactivated at time t2, its sensing node may be represented by trace 12230. If a selected memory cell of cell column structure 256 is activated at time t2, its sensing node may be represented by trace 12231.

[0145] At time t3, trace 1219 can be reduced to a voltage level, such as its initial voltage level, that deactivates its corresponding lower select gate 210. This can be used to isolate the charge of its corresponding sensing node from its corresponding higher data line (e.g., to capture charge from the higher data line). At this time, trace 1217 can be increased such that compensation gate 211 can absorb displacement charge from the lower select gate 210. It should be noted that this discussion of trace 1217 may not be practically meaningful for embodiments that do not use compensation gate 211.

[0146] When a sensing node captures charge on the first control gate 240 of its corresponding passgate 238, configured to activate or deactivate it, the selective activation of the second control gate 242 of that corresponding passgate 238 can be used to determine whether a selected memory cell is activated or deactivated at time t2, thus determining the corresponding data state of those memory cells. Specifically, the second control gate 242 of each passgate 238 can be deactivated sequentially while the second control gates 242 of the remaining passgates 238 remain activated. Although the second control gate 242 of a particular passgate 238 is deactivated and the second control gates 242 of the remaining passgates 238 are activated, the electrical connection of the lower data line 254 to the source 216 may depend solely on whether the first control gate 240 of that particular passgate 238 is activated.

[0147] Therefore, at time t4, trace 12250 can transition to the voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238, while traces 12251 to 12253 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) can remain at the voltage level configured to activate the second control gate 242 of their respective pass gates 238. The presence of an electrical path between the lower data line 254 and the common source 216 can then be detected in a readily understandable manner, for example, by sensing the current flowing through the lower data line 254 or a voltage change in the lower data line 254. This, in turn, indicates whether the corresponding selected memory cell is activated or deactivated in response to a read voltage, thus indicating its data state in a manner similar to that of a typical NAND memory. Trace 12250 can then return to the voltage level configured to activate the second control gate 242 of its corresponding pass gate 238, and this process can be repeated for each of the remaining traces 12251 to 12253.

[0148] For example, trace 12251 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t5, trace 12252 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t6, and trace 12253 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t7, while the remaining traces 1225 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) may remain at a voltage level configured to activate the second control gate 242 of their respective pass gates 238 when they do not transition to low.

[0149] Figure 13 This is a timing diagram of a memory operation method according to another embodiment. For example, Figure 13A method may represent sensing (e.g., reading or verifying) one or more memory cells (e.g., logical pages of memory cells). The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller, for example, control logic 116, to cause the memory (e.g., associated components of the memory) to perform the method. Figure 13 Special reference Figure 2B The components described herein are for informational purposes only; however, it should be understood that this description may be used in conjunction with other memory array structures disclosed herein.

[0150] Trace 1331 can depict the voltage level of a higher data line 204 (e.g., higher data line 204) selectively connected to a memory cell (e.g., a selected memory cell) chosen for sensing during a sensing operation. For example, trace 1331 can correspond to higher data lines 2040-2043. Trace 1333 can depict the voltage level of an access line 202 (e.g., selected access line 202) connected to a selected memory cell, and trace 1335 can depict the voltage level of an access line 202 (e.g., an unselected access line 202) not connected to a selected memory cell. For example, if a memory cell 208 selected for a sensing operation is connected to access line 2021, then trace 1333 can correspond to access line 2021, and trace 1335 can correspond to access lines 2020-202 that are not access line 2021. N Trace 1337 depicts the voltage level of control line 213 connected to compensation gate 211. Trace 1339 depicts the voltage level of lower select line 214 connected to lower select gate 210. Trace 1341 depicts the voltage level of control line 228 connected to capacitor 226.

[0151] Traces 13430 and 13431 may depict the voltage levels of the channels (e.g., sensing nodes) of capacitors 226 through the first control gate 240 of gate 238 of cell column structures 256 that are deactivated in response to a read voltage level and cell column structures 256 that are activated in response to a read voltage level of their selected memory cells. Traces 13450 to 13453 may depict the voltage levels of back-side gate lines 244, for example, the voltage levels of back-side gate lines 2440 to 2443 of memory cell sub-block 2620 when selected memory cells are included in cell column structures 2560 to 2563.

[0152] At time t0, trace 1331 may increase from an initial voltage level (e.g., ground or 0V) to a voltage level selectable to mitigate drain-induced barrier reduction (DIBL) and read interference. For example, trace 1331 may increase to 1V. Traces 13430 and 13431 may increase due to the increase in trace 1331. Traces 1333 and 1335 may increase from an initial voltage level (e.g., 1V) to a pass voltage level for sensing operation. The pass voltage level is a voltage level higher than the expected threshold voltage level of each memory cell connected to selected and unselected access lines, for example, a voltage level configured to activate each memory cell regardless of its data state. For example, traces 1333 and 1335 may increase to 9V.

[0153] At time t0, traces 1337, 1339, and 1341 can increase from initial voltage levels (e.g., ground or 0V) to voltage levels configured to activate their corresponding compensation gate 211, lower select gate 210, and capacitor 226. Although not depicted, higher select line 215 and control line 224 can also receive voltage levels configured to activate their higher select gate 212 and GG gate 220, respectively. Because these transistors are generally not programmed to the same threshold voltage levels as memory cells, this voltage level may be low, for example, 2-3V.

[0154] At time t1, trace 1339 can be reduced to a voltage level that deactivates its corresponding lower select gate 210, such as its initial voltage level. This can be used to isolate capacitors 226 and their corresponding higher data lines 204. At this time, trace 1337 can be increased. It should be noted that this discussion of trace 1337 may not be practically meaningful for embodiments that do not use compensation gate 211.

[0155] At time t2, control line 228 can be biased to boost the channel of capacitor 226, allowing traces 13430 and 13431 to increase further. The increase in voltage level of trace 1341 can be sufficient to boost traces 13430 and 13431 to a precharge voltage level configured, for example, to activate the first control gate 240 of gate 238 for enhancement-type devices or, for example, to deactivate the first control gate 240 of gate 238 for depletion-type devices. For example, the precharge voltage level could be 4V.

[0156] At time t4, trace 1333 can be reduced to a read voltage level for sensing operations. The read voltage level can be configured to distinguish adjacent data states. Therefore, depending on the data state of the memory cell programmed to receive the read voltage at the control gate, the memory cell can remain active or inactive.

[0157] At time t5, trace 1339 can be increased to a voltage level sufficient to activate the corresponding lower selected gate 210. The voltage level of trace 1339 between times t5 and t6 can be selected to limit the voltage level of the channel of the selected memory cell to a value close to the voltage level of trace 1331 at time t5. If the selected memory cell of cell column structure 256 is deactivated at time t5, its sensing node can be represented by trace 13430. If the selected memory cell of cell column structure 256 is activated at time t5, its sensing node can be represented by trace 13431.

[0158] At time t6, trace 1331 may decrease to a lower voltage level. This lower voltage level may be a voltage level configured, for example, to deactivate the first control gate 240 of gate 238 for an enhancement-type device or, for example, to activate the first control gate 240 of gate 238 for a depletion-type device. For example, the lower voltage level may be its initial voltage level. This may cause the voltage level of trace 13431 to decrease further.

[0159] At time t7, trace 1339 can be reduced to a voltage level configured to deactivate its corresponding lower select gate 210, such as its initial voltage level. This can be used to isolate the charge of its corresponding sensing node from its corresponding higher data line (e.g., to capture charge from the higher data line).

[0160] When the sensing nodes capture the charge of the first control gate 240 configured to activate or deactivate their respective gates 238, the selective activation of the second control gate 242 of their respective gates 238 can be used to determine whether their respective selected memory cells are activated or deactivated at time t6, so that the corresponding data state of those memory cells can be determined.

[0161] Therefore, at time t8, trace 13450 can transition to the voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238, while traces 13451 to 13453 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) can remain at the voltage level configured to activate the second control gate 242 of their respective pass gates 238. The presence of an electrical path between the lower data line 254 and the common source 216 can then be detected in a readily understandable manner, for example, by sensing the current flowing through the lower data line 254 or a voltage change in the lower data line 254. This, in turn, indicates whether the corresponding selected memory cell is activated or deactivated in response to a read voltage, thus indicating its data state in a manner similar to that of a typical NAND memory. Trace 13450 can then return to the voltage level configured to activate the second control gate 242 of its corresponding pass gate 238, and this process can be repeated for each of the remaining traces 13451 to 13453.

[0162] For example, trace 13451 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t9, trace 13452 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t10, and trace 13453 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t11, while the remaining traces 1345 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) may remain at a voltage level configured to activate the second control gate 242 of their respective pass gates 238 when they do not transition to low.

[0163] Figure 14 This is a timing diagram of a memory operation method according to another embodiment. For example, Figure 14 A method may represent sensing (e.g., reading or verifying) one or more memory cells (e.g., logical pages of memory cells). The method may be in the form of computer-readable instructions, for example, stored in instruction register 128. Such computer-readable instructions may be executed by a controller, for example, control logic 116, to cause the memory (e.g., associated components of the memory) to perform the method. Figure 14 Special reference Figure 2B The components described herein are for informational purposes only; however, it should be understood that this description may be used in conjunction with other memory array structures disclosed herein.

[0164] Trace 1451 may depict the voltage level of a higher data line 204 (e.g., higher data line 204) selectively connected to a memory cell (e.g., a selected memory cell) selected for sensing during a sensing operation. For example, trace 1451 may correspond to higher data lines 2040-2043. Trace 1453 may depict the voltage level of an access line 202 (e.g., a selected access line 202) connected to a selected memory cell, and trace 1455 may depict the voltage level of an access line 202 (e.g., an unselected access line 202) not connected to a selected memory cell. For example, if a memory cell 208 selected for a sensing operation is connected to access line 2021, then trace 1453 may correspond to access line 2021, and trace 1455 may correspond to access lines 2020-202 that are not access lines 2021. N Trace 1459 depicts the voltage level of the lower select line 214 connected to the lower select gate 210. Trace 1461 depicts the voltage level of the control line 228 connected to the capacitor 226.

[0165] Traces 14630 and 14631 may depict the voltage levels of the channels (e.g., sensing nodes) of capacitors 226 through the first control gate 240 of gate 238 of cell column structures 256 that are deactivated in response to a read voltage level and cell column structures 256 that are activated in response to a read voltage level of their selected memory cells. Traces 14650 to 14653 may depict the voltage levels of back-side gate lines 244, for example, the voltage levels of back-side gate lines 2440 to 2443 of memory cell subblock 2620 when selected memory cells are included in cell column structures 2560 to 2563.

[0166] At time t0, trace 1451 may increase from an initial voltage level (e.g., ground or 0V) to a precharge voltage level. The precharge voltage level may be a voltage level configured, for example, to activate the first control gate 240 of pass gate 238 for an enhancement-type device or, for example, to deactivate the first control gate 240 of pass gate 238 for a depletion-type device. For example, the precharge voltage level may be 4V. Traces 1453 and 1455 may increase from an initial voltage level (e.g., ground or 0V) to a pass voltage level for sensing operation. The pass voltage level is a voltage level higher than a predetermined threshold voltage level for each memory cell connected to selected and unselected access lines, for example, a voltage level configured to activate each memory cell regardless of its data state. For example, traces 1453 and 1455 may increase to 9V.

[0167] At time t0, traces 1459 and 1461 can increase from initial voltage levels (e.g., ground or 0V) to voltage levels configured to activate their corresponding lower select gate 210 and capacitor 226, respectively. Although not depicted, higher select line 215 and control line 224 can also receive voltage levels configured to activate their higher select gate 212 and GG gate 220, respectively. Because these transistors are generally not programmed to the same threshold voltage levels as memory cells, this voltage level may be low, for example, 2-3V.

[0168] As each transistor in the cell array structure 256 is activated from capacitor 226 to gate 220, traces 14630 and 14631 may increase the voltage level toward trace 1451 at time t0. At time t0, traces 14650 to 14653 may increase to a voltage level configured to activate the second select gate 242 of each corresponding pass gate 238. Although not depicted, the voltage levels applied to back-side gate lines 2444 to 2447 and the dummy back-side gate line 260 may also be configured to activate their corresponding pass gates 238.

[0169] At time t1, trace 1453 can be reduced to a read voltage level for sensing operations. The read voltage level can be a voltage level configured to distinguish adjacent data states. Therefore, depending on the data state of the memory cell programmed to receive the read voltage at the control gate, the memory cell may or may not remain active.

[0170] At time t2, trace 1451 may decrease from a pre-charge voltage level to a lower voltage level. This lower voltage level may be a voltage level configured, for example, to deactivate the first control gate 240 of gate 238 for an enhancement-type device or, for example, to activate the first control gate 240 of gate 238 for a depletion-type device. For example, the lower voltage level may be its initial voltage level. If a selected memory cell of cell column structure 256 is deactivated at time t2, its sensing node may be represented by trace 14630. If a selected memory cell of cell column structure 256 is activated at time t2, its sensing node may be represented by trace 14631.

[0171] At time t3, trace 1459 may be reduced to a voltage level configured to deactivate its corresponding lower select gate 210, such as its initial voltage level. This can be used to isolate the charge of its corresponding sensing node from its corresponding higher data line (e.g., to capture charge from the higher data line). While the sensing nodes are isolated from their corresponding higher data lines, traces 1453 and 1455 may optionally discharge at time t4, such as to their initial voltage level.

[0172] When the sensing nodes capture the charge of the first control gate 240 configured to activate or deactivate their respective gates 238, the selective activation of the second control gate 242 of their respective gates 238 can be used to determine whether their respective selected memory cells are activated or deactivated at time t2, so that the corresponding data state of those memory cells can be determined.

[0173] Therefore, at time t4, trace 14650 can transition to the voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238, while traces 14651 to 14653 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) can remain at the voltage level configured to activate the second control gate 242 of their respective pass gates 238. The presence of an electrical path between the lower data line 254 and the common source 216 can then be detected in a readily understandable manner, for example, by sensing the current flowing through the lower data line 254 or a voltage change in the lower data line 254. This, in turn, indicates whether the corresponding selected memory cell is activated or deactivated in response to a read voltage, thus indicating its data state in a manner similar to that of a typical NAND memory. Trace 14650 can then return to the voltage level configured to activate the second control gate 242 of its corresponding pass gate 238, and this process can be repeated for each of the remaining traces 14651 to 14653.

[0174] For example, trace 14651 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t5, trace 14652 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t6, and trace 14653 may transition to a voltage level configured to deactivate the second control gate 242 of its corresponding pass gate 238 at time t7, while the remaining traces 1465 (and back-side gate lines 2444 to 2447 and dummy back-side gate line 260) may remain at a voltage level configured to activate the second control gate 242 of their respective pass gates 238 when they do not transition to low.

[0175] in conclusion

[0176] Although specific embodiments have been described and illustrated herein, those skilled in the art will understand that any arrangement is expected to achieve the same purpose in lieu of the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory cell array, comprising: Multiple first data lines; Second data line; Source pole; Multiple cell column structures, wherein each cell column structure includes a corresponding plurality of non-volatile memory cells connected in series; Multiple sensing lines, wherein each of the multiple sensing lines includes a plurality of corresponding through gates connected in series between the second data line and the source, wherein each of the respective plurality of through gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel and a second control gate capacitively coupled to its second channel, and wherein each cell column structure in a respective subset of the plurality of cell column structures of the sensing lines of the multiple sensing lines is capacitively coupled to the first channel of the corresponding through gate of the respective plurality of through gates; as well as A plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of a corresponding pass-gate of a corresponding plurality of pass-gates of each of the plurality of sensing lines; Specifically, for each of the plurality of sensing lines, each unit column structure in its corresponding unit column structure subset is connected to the corresponding first data line in the corresponding first data line subset of the plurality of first data lines.

2. The memory cell array according to claim 1, wherein the corresponding subset of the first data lines of the plurality of first data lines of the first sensing line of the plurality of sensing lines mutually excludes the corresponding subset of the first data lines of the plurality of first data lines of the second sensing line of the plurality of sensing lines.

3. The memory cell array according to claim 2, wherein the corresponding subset of the first data lines of the plurality of first data lines of the third sensing line among the plurality of sensing lines does not exclude the corresponding subset of the first data lines of the plurality of first data lines of the first sensing line.

4. The memory cell array of claim 3, wherein the first sensing line is adjacent to the second sensing line, and wherein the second sensing line is between the third sensing line and the first sensing line.

5. The memory cell array of claim 3, wherein at least one first data line in the corresponding first data line subset of the plurality of first data lines of the third sensing line of the plurality of sensing lines is mutually exclusive with the corresponding first data line subset of the plurality of first data lines of the first sensing line.

6. The memory cell array of claim 1, wherein the respective first data line subset of the plurality of first data lines of each of the plurality of sensing lines is mutually exclusive with the respective first data line subset of the plurality of first data lines of each of the remaining sensing lines.

7. The memory cell array of claim 6, wherein each of the plurality of back-side gate lines is orthogonal to each of the plurality of sensing lines.

8. A memory cell array, comprising: Multiple first data lines; Second data line; Source pole; Multiple cell column structures, wherein each cell column structure includes a corresponding plurality of non-volatile memory cells connected in series; Multiple sensing lines, wherein each of the multiple sensing lines includes a plurality of corresponding through gates connected in series between the second data line and the source, wherein each of the respective plurality of through gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel and a second control gate capacitively coupled to its second channel, and wherein each cell column structure in a respective subset of the plurality of cell column structures of the sensing lines of the multiple sensing lines is capacitively coupled to the first channel of the corresponding through gate of the respective plurality of through gates; as well as A plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of a corresponding pass-gate of a corresponding plurality of pass-gates of each of the plurality of sensing lines; Wherein, for each of the plurality of sensing lines, each unit column structure in its corresponding unit column structure subset is connected to the corresponding first data line in the corresponding first data line subset of the plurality of first data lines, and Specifically, for each of the plurality of sensing lines, each first data line in its corresponding first data line subset is connected to only one cell column structure in its corresponding cell column structure subset.

9. The memory cell array of claim 8, wherein each of the plurality of back-side gate lines is not orthogonal to each of the plurality of sensing lines.

10. The memory cell array of claim 9, wherein the respective subsets of the first data lines of the plurality of first data lines of the first sensing line of the plurality of sensing lines are mutually exclusive with the respective subsets of the first data lines of the plurality of first data lines of the second sensing line of the plurality of sensing lines.

11. The memory cell array according to claim 10, wherein, For each of the plurality of sensing lines, the corresponding subset of the plurality of first data lines of the sensing line is mutually exclusive with the corresponding subset of the plurality of first data lines of each of the remaining sensing lines.

12. The memory cell array of claim 10, wherein the respective first data line subsets of the plurality of first data lines of the third sensing line of the plurality of sensing lines do not mutually exclude each other from the respective first data line subsets of the plurality of first data lines of the first sensing line, wherein the first sensing line is adjacent to the second sensing line, wherein the second sensing line is adjacent to the third sensing line, and wherein the second sensing line is between the third sensing line and the first sensing line.

13. The memory cell array of claim 8, wherein each of the plurality of sensing lines is tilted relative to each of the plurality of back-side gate lines.

14. A memory cell array, comprising: Multiple first data lines; Second data line; Source pole; Multiple cell column structures, wherein each cell column structure includes a corresponding plurality of non-volatile memory cells connected in series; Multiple dummy unit column structure; A plurality of sensing lines, wherein each of the plurality of sensing lines includes a plurality of corresponding through gates connected in series between the second data line and the source, wherein each of the plurality of corresponding through gates includes a first channel, a second channel, a first control gate capacitively coupled to its first channel, and a second control gate capacitively coupled to its second channel, wherein each cell column structure in a subset of the plurality of cell column structures of the plurality of sensing lines is capacitively coupled to the first channel of the corresponding through gate of the plurality of corresponding through gates, and wherein the corresponding dummy cell column structure in the plurality of dummy cell column structures of the plurality of sensing lines is capacitively coupled to the first channel of the corresponding through gate of the plurality of corresponding through gates; as well as A plurality of back-side gate lines, wherein each back-side gate line is connected to the second control gate of a corresponding pass-gate of a corresponding plurality of pass-gates of each of the plurality of sensing lines; Wherein, for each of the plurality of sensing lines, each of the cell column structures in its corresponding cell column structure subset is connected to the corresponding first data line in the corresponding first data line subset of the plurality of first data lines; For each of the plurality of sensing lines, each first data line in its corresponding first data line subset is connected to more than one cell column structure in its corresponding cell column structure subset.

15. The memory cell array according to claim 14, wherein, For each of the plurality of sensing lines, its corresponding dummy cell column is not connected to any of the plurality of first data lines.

16. The memory cell array of claim 14, wherein each of the plurality of sensing lines is arranged in a folded orientation.

17. The memory cell array according to claim 14, wherein, For an individual sensing line among the plurality of sensing lines, a specific first data line in its corresponding first data line subset is connected to the first unit column structure in its corresponding unit column structure subset that is adjacent to its corresponding dummy unit column structure in a first direction, and is connected to the second unit column structure in its corresponding unit column structure subset that is adjacent to its corresponding dummy unit column structure in a second direction.

18. The memory cell array according to claim 17, wherein, For each of the plurality of sensing lines, another first data line in its corresponding first data line subset is connected to a third unit column structure in its corresponding unit column structure subset that is adjacent to its first unit column structure in the first direction, and is connected to a fourth unit column structure in its corresponding unit column structure subset that is adjacent to its second unit column structure in the second direction.

19. The memory cell array according to claim 18, wherein, For each of the plurality of sensing lines, one of the first data lines in its corresponding first data line subset is connected to the fifth unit column structure in its corresponding unit column structure subset, which is adjacent to its third unit column structure in the first direction, and is connected to the sixth unit column structure in its corresponding unit column structure subset, which is adjacent to its fourth unit column structure in the second direction.

20. The memory cell array according to claim 14, wherein, For each of the plurality of sensing lines, each first data line in its corresponding first data line subset is connected to two cell column structures in its corresponding cell column structure subset.

21. The memory cell array according to claim 20, wherein, For each of the plurality of sensing lines, each first data line in its corresponding first data line subset is connected to two cell column structures on opposite sides of its corresponding cell column structure subset.

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