Memory device including support structure

Abstract

This application relates to a memory device including a support structure. Some embodiments include an apparatus and a method of forming said apparatus. One of the apparatuses includes: a respective memory cell layer and a control gate, the layers being stacked one on top of the other over a substrate, the control gate including a control gate closest to the substrate, the control gate including a corresponding portion forming a stepped structure; conductive contacts contacting the control gate at a location of the stepped structure, the conductive contacts including conductive contacts in contact with the control gate; a dielectric structure located on a sidewall of the control gate; and a support structure adjacent to the conductive contacts and having a length extending vertically from the substrate, the support structure including a support structure closest to the conductive contacts, the support structure being located at a distance from the edge of the dielectric structure, wherein the ratio of the width of the support structure to the distance is in the range of 1.6 to 2.0.

Description

Technical Field

[0001] The embodiments described herein relate to a memory device that includes a support structure located in a stepped region of the memory device. Background Technology

[0002] The components in a memory device (e.g., a flash memory device) have relatively small structural dimensions (e.g., nanometer-sized). At a certain size, some structures of the memory device may collapse during the manufacturing process. Some conventional techniques use additional chemical processing steps to prevent this collapse. However, these additional steps can increase the cost of manufacturing the memory device. Summary of the Invention

[0003] One aspect of this disclosure provides an apparatus comprising: a substrate; layers stacked one on top of the substrate, the layers including respective memory cells and control gates for the memory cells, the control gates including a control gate closest to the substrate and other control gates, the control gates including corresponding portions forming a stepped structure; conductive contacts contacting the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including a conductive contact contacting a first control gate; a dielectric structure adjacent to a sidewall of the control gate of the layers; and a support structure adjacent to the conductive contacts and electrically isolated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and extending through at least a portion of the control gates, the support structure including a support structure closest to the conductive contacts and other support structures, the support structure being located at a distance from an edge of the dielectric structure, wherein the ratio of the width of the support structure to the distance is in the range of 1.6 to 2.0.

[0004] Another aspect of this disclosure provides an apparatus comprising: a substrate; layers stacked one on top of the substrate, the layers including respective memory cells and control gates for the memory cells, the control gates including a control gate closest to the substrate and other control gates, the control gates including corresponding portions forming a stepped structure; conductive contacts contacting the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including a conductive contact contacting a first control gate; and a support structure adjacent to the conductive contacts and electrically isolated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and extending through at least a portion of the control gates, the support structure including a support structure closest to the conductive contacts and other support structures, wherein the width of the support structure is at least 345 nanometers.

[0005] Another aspect of this disclosure provides an apparatus comprising: a substrate; layers stacked one on top of the substrate, the layers including respective memory cells and control gates for the memory cells, the control gates including a control gate closest to the substrate and other control gates, the control gates including corresponding portions forming a stepped structure; conductive contacts contacting the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including conductive contacts contacting the control gates; a support structure adjacent to the conductive contacts and electrically isolated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and extending through at least a portion of the control gates, the support structure including a support structure closest to the conductive contacts and other support structures; and a dielectric structure adjacent to a sidewall of the control gates, wherein the distance between the edge of the dielectric structure and the edge of the support structure is less than 215 nanometers.

[0006] Another aspect of this disclosure provides a marker comprising: a first edge and a second edge opposite to the first edge; a first pattern adjacent to the first edge, the first pattern comprising a first side parallel to the first edge and a second side connected to the first side and perpendicular to the first edge, the second side having dimensions in the range of 345 nm to 375 nm; and a second pattern adjacent to the second edge, the second pattern comprising a first side parallel to the second edge and a second side connected to the first side of the second pattern and perpendicular to the second edge, the second side of the second pattern having dimensions in the range of 345 nm to 375 nm, wherein the marker is configured to be included in a system for forming a support structure for a memory device such that the dimensions of the support structure are based on the dimensions of the first pattern and the second pattern, the support structure being located at one of the stepped structures in a stepped structure located above a substrate of the memory device, the stepped structure being located closest to the substrate relative to the other stepped structures.

[0007] Another aspect of this disclosure provides a method comprising: forming a stepped structure over a substrate of a memory device, the stepped structure including a first stepped structure and a second stepped structure, the first stepped structure being closest to the substrate relative to the second stepped structure; forming conductive contacts in contact with corresponding conductive material layers of the stepped structures, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including conductive contacts in contact with conductive material layers in the conductive material layers; and forming a support structure adjacent to the conductive contacts and electrically isolated from the conductive material layers and the conductive contacts, the support structure having a length extending vertically from the substrate and extending through at least a portion of the conductive material layers, the support structure including a support structure closest to the conductive contacts and other support structures, wherein the width of the support structure is at least 345 nanometers. Attached Figure Description

[0008] Figure 1 A device in the form of a memory device is shown according to some embodiments described herein.

[0009] Figure 2 A schematic diagram of a device in the form of a memory device having an array of memory cells and blocks of memory cells, according to some embodiments described herein, is shown.

[0010] Figure 3 Some embodiments according to the description herein are shown. Figure 2 A top view of the structure of a memory device, the structure including a memory cell array, a stepped region, and a dielectric structure between memory cell blocks.

[0011] Figure 4A It shows Figure 3 A portion (e.g., a cross-section) of a memory device.

[0012] Figure 4B It shows Figure 4A More details about a part of the memory device.

[0013] Figure 4C It shows Figure 4B A top view of a portion of the memory device 200.

[0014] Figure 5A , Figure 5B and Figure 5C These are examples illustrating some embodiments according to the description herein. Figure 3 A top view of a representative diagram of different parts of a memory device.

[0015] Figures 6A to 10C This illustrates some embodiments of the formation described herein. Figures 2 to 5C Representative diagrams of different structural views during the manufacturing process of memory devices.

[0016] Figure 11 The embodiments described herein are shown as being configured to include in the formation Figures 6A to 10C The markings in a system that are part of a memory device.

[0017] Figure 12 A system comprising a lithography apparatus according to some embodiments described herein is illustrated, the lithography apparatus comprising Figure 11 The markings. Detailed Implementation

[0018] The technology described herein relates to a memory device, which, among other structures, particularly has a stepped structure and a support structure located at the stepped structure. The support structure has specific dimensions (e.g., width) and specific dimensional relationships (e.g., ratios) with other structures. These specific dimensions and dimensional relationships prevent potential collapse of some structures of the memory device during the process of forming the memory device. The technology described herein also relates to a marker that can be configured to be included in a system (e.g., a photolithography system) during a process of forming the support structure of the described memory device. The marker is designed to include a pattern such that specific dimensions of the support structure can be based on the dimensions of the pattern of the marker. The dimensions of the pattern of the marker are designed (e.g., determined) such that the support structure (whose dimensions are based on the dimensions of the pattern of the marker) prevents other structures of the memory device from collapsing during the process of forming the memory device. References are made below. Figures 1 to 12Further discussion will be given on the improvements and benefits of the techniques described in this article.

[0019] Figure 1 A device in the form of a memory device 100 according to some embodiments described herein is illustrated. The memory device 100 may include a memory array (or multiple memory arrays) 101 containing memory cells 102 arranged in blocks (memory cell blocks) (such as blocks 191 and 192). In the physical structure of the memory device 100, the memory cells 102 may be arranged vertically above a substrate (e.g., a semiconductor substrate) of the memory device 100 (e.g., stacked on top of each other). Figure 1 A memory device 100 having two blocks 191 and 192 is shown as an example. The memory device 100 may have more than two blocks.

[0020] like Figure 1 As shown, memory device 100 may include access lines (which may include word lines) 150 and data lines (which may include bit lines) 170. Access lines 150 may carry signals (e.g., word line signals) WL0 to WLm. Data lines 170 may carry signals (e.g., bit line signals) BL0 to BLn. Memory device 100 may use access lines 150 to selectively access memory cells 102 of blocks 191 and 192, and may use data lines 170 to selectively exchange information (e.g., data) with memory cells 102.

[0021] Memory device 100 may include an address register 107 to receive address information (e.g., address signals) ADDR on lines (e.g., address lines) 103. Memory device 100 may include row access circuitry 108 and column access circuitry 109 capable of decoding the address information from address register 107. Based on the decoded address information, memory device 100 can determine which memory cells 102 of which sub-blocks of blocks 191 and 192 will be accessed during memory operation. Memory device 100 may include a driver (driver circuitry) 140, which may be part of row access circuitry 108. Driver 140 may be operable (e.g., as a switch operation) to form (or not form) a conductive path (e.g., a current path) between a voltage-providing node and the corresponding access line 150 during operation of memory device 100.

[0022] The memory device 100 can perform read operations to read (e.g., sense) information (e.g., previously stored information) from memory cells 102 of blocks 191 and 192, or perform write (e.g., program) operations to store (e.g., program) information into memory cells 102 of blocks 191 and 192. The memory device 100 can use data lines 170 associated with signals BL0 to BLn to provide information to be stored in memory cells 102 or to obtain information read (e.g., sensed) from memory cells 102. The memory device 100 can also perform erase operations to erase some or all of the information from memory cells 102 of blocks 191 and 192.

[0023] Memory device 100 may include a control unit 118, which may be configured to control memory operations of memory device 100 based on control signals on line 104. Examples of control signals on line 104 include one or more clock signals and other signals (e.g., chip enable signal CE#, write enable signal WE#) to indicate which operation (e.g., read, write, or erase) memory device 100 may perform. Other devices external to memory device 100 (e.g., memory controller or processor) may control the values ​​of the control signals on line 104. Specific values ​​of combinations of signals on line 104 may generate commands (e.g., read, write, or erase commands) that cause memory device 100 to perform the corresponding memory operation (e.g., read, write, or erase).

[0024] Memory device 100 may include sensing and buffering circuitry 120, which may include components such as a sense amplifier and page buffer circuitry (e.g., a data latch). Sensing and buffering circuitry 120 may respond to signals BL_SEL0 to BL_SELn from column access circuitry 109. Sensing and buffering circuitry 120 may be configured (e.g., by sensing) to determine the value of information read from memory cells 102 of blocks 191 and 192 (e.g., during a read operation) and to provide the value of the information to line (e.g., a global data line) 175. Sensing and buffering circuitry 120 may also be configured to use signals on line 175 (e.g., voltage values) based on the value of signals on line 175 (e.g., during a write operation) to determine the value of information to be stored (e.g., programmed) in memory cells 102 of blocks 190 and 191 (e.g., during a write operation).

[0025] Memory device 100 may include input / output (I / O) circuitry 117 to exchange information between memory cells 102 in blocks 191 and 192 and lines (e.g., I / O lines) 105. Signals DQ0 to DQN on line 105 may represent information read from or stored in memory cells 102 in blocks 191 and 192. Line 105 may contain nodes within memory device 100 or pins (or solder balls) on a package in which memory device 100 may reside. Other devices external to memory device 100 (e.g., memory controllers or processors) may communicate with memory device 100 via lines 103, 104, and 105.

[0026] The memory device 100 can receive a power supply voltage, including a power supply voltage Vcc and a power supply voltage Vss. The power supply voltage Vss can operate at ground potential (e.g., having a value of approximately zero volts). The power supply voltage Vcc can include an external voltage supplied to the memory device 100 from an external power source such as a battery or an AC-DC converter circuit.

[0027] Each of the memory cells 102 can be programmed to store information representing a value of up to one bit (e.g., a single bit) or a value of multiple bits (e.g., two, three, four, or another number of bits). For example, each of the memory cells 102 can be programmed to store information representing the binary value "0" or "1" of a single bit. A single bit of each cell is sometimes referred to as a single-level cell. In another instance, each of the memory cells 102 can be configured to store information representing a value of multiple bits, such as one of the four possible values ​​"00", "01", "10", and "11" for two bits, one of the eight possible values ​​"000", "001", "010", "011", "100", "101", "110", and "111" for three bits, or one of another number of other values ​​of multiple bits. Cells with the ability to store multiple bits are sometimes referred to as multi-level cells (or polymorphic cells).

[0028] Memory device 100 may include a non-volatile memory device, and memory cell 102 may include a non-volatile memory cell such that memory cell 102 can retain information stored thereon when power (e.g., voltage Vcc, Vss, or both) is disconnected from memory device 100. For example, memory device 100 may be a flash memory device, such as NAND flash (e.g., 3D NAND) or NOR flash memory device, or another type of memory device, such as a variable resistance memory device (e.g., phase change memory device or resistive random access memory (RAM) device).

[0029] Those skilled in the art will recognize that the memory device 100 may include other components, some of which are not included in the above description. Figure 1 The examples are shown below to avoid confusion with the exemplary embodiments described herein. At least a portion of the memory device 100 may include the features described below. Figures 2 to 12 The structure of any of the described memory devices is similar to or equivalent to that of the memory device and performs operations similar to or equivalent to those of the memory device.

[0030] Figure 2 A schematic diagram of a device in the form of a memory device 200 having a memory cell array 201 and blocks (e.g., memory cell blocks) 291 and 292, according to some embodiments described herein, is shown. The memory device 200 may comprise a non-volatile (e.g., NAND flash memory device) or other type of memory device. The memory device 200 may correspond to memory device 100. For example, the memory array (or multiple memory arrays) 201 and blocks 291 and 292 may respectively correspond to... Figure 1 The memory array 101 and blocks 191 and 192 of the memory device 100.

[0031] like Figure 2 As shown, the memory device 200 may include memory cells 202 and data lines 2700 to 2700. N (2700 to 270) N Control gates 2500 to 250 in block 291 M and control gates 250'0 to 250' in block 292 M Data cable 2700 to 270 N It can correspond to Figure 1 A portion of the data line 170 of the memory device 100. Figure 2 In the middle, the number immediately following the other (e.g., 270) N The label "N" (index N) indicates the number of data lines in memory device 200. For example, if memory device 200 contains 16 data lines, then N is 15 (data lines 2700 to 270). 15 ).exist Figure 2 In the middle, the number immediately following the other (e.g., 250) M The designation "M" (index N) indicates the number of control gate memory devices 200. For example, if the memory device 200 contains 128 control gates, then M is 127 (control gates 2500 to 2500). 127 The memory device 200 may have the same number of control gates (e.g., M-1 control gates) in blocks of the memory device 200 (e.g., blocks 291 and 292).

[0032] exist Figure 2 In the middle, the data cable is 2700 to 270. N It may include bit lines (e.g., partial bit lines) (or may be a portion thereof) of the memory device 200. For example... Figure 2 As shown, the data line is 2700 to 270. N Signals (e.g., bit line signals) BL0 to BL can be carried separately. N In the physical structure of memory device 200, data lines 2700 to 270... N It can be structured as a conductive line and has a corresponding length extending in the Y direction.

[0033] like Figure 2 As shown, memory cells 202 can be organized into separate blocks (blocks of memory cells), such as blocks 291 and 292. Figure 2 A memory device 200 comprising two blocks 291 and 292 is shown as an example. However, the memory device 200 may contain multiple blocks. The blocks of the memory device 200 (e.g., blocks 291 and 292) may share data lines (e.g., data lines 2700 to 270). N (in signal form) information read from or stored in a selected memory cell of memory device 200 (e.g., a selected memory cell in block 291 or 292).

[0034] Control gate 2500 to 250 M It can be a part of a local word line, which can be a memory device 200 that can be connected to... Figure 1 A portion (or may be coupled to) a portion of an access line (e.g., a global word line) corresponding to an access line 150 of the memory device 100. Control gates 250'0 to 250' M It can be another portion of other local word lines, which may be part of the access lines (e.g., global word lines) of the memory device 200. Control gates 2500 to 250 M It can be used with control gate 250'0 to 250' M Electrical separation. Therefore, blocks 291 and 292 can be accessed separately (e.g., one at a time). For example, control gates 2500 to 250 can be used. M Block 291 can be accessed at one time, and control gates 250'0 to 250' can be used. M Access block 292 at another time.

[0035] Figure 2 The X, Y, and Z directions are shown as physical orientations (e.g., dimensions) relative to the structure of the memory device 200. For example, the Z direction can be perpendicular to the substrate of the memory device 200 (e.g., Figure 4A The orientation of the substrate 499 shown is (e.g., a direction vertical relative to the substrate). The Z direction is perpendicular to the X and Y directions (e.g., the Z direction is perpendicular to the XY plane of the memory device 200). In the physical structure of the memory device 200, control gates 2500 to 250... M It can be formed in the Z direction on different levels (e.g., layers) of the memory device 200. In this example, control gates 2500 to 2500 M A layer (e.g., a layer) can be formed (e.g., stacked) on another layer in the Z direction.

[0036] like Figure 2 As shown, memory cell 202 may be contained in a corresponding memory cell string 230 in each of the blocks (e.g., blocks 291 and 292) of memory device 200. Each of the memory cell strings 230 may have serially connected memory cells in the Z direction (e.g., M+1 serially connected memory cells). In the physical structure of memory device 200, memory cells may be arranged in different levels in the Z direction (e.g., Figure 2 In an example, M-1 different layers are formed (e.g., vertically stacked) of memory cells 202 in each of a string 230. The number of memory cells in each of the strings 230 may be equal to the number of control gates (e.g., control gates 2500 to 250) of the memory device 200. M The number of levels (e.g., layers).

[0037] like Figure 2 As shown, control gates 2500 to 250 M It can carry the corresponding signal WL0 to WL M As described above, the control gate 2500 to 250 M It may include access lines (e.g., word lines) (or may be a portion thereof) of the memory device 200. Control gates 2500 to 2500 M Each of these can be part of a structure (e.g., a hierarchy) of conductive material (e.g., a conductive material layer) located in the hierarchy of memory device 200. Memory device 200 can use signals WL0 to WL0 during operation (e.g., read, write, or erase operations). M This allows for selective control of access to memory cells 202 in block 291. For example, during a read operation, the memory device 200 can use signals WL0 to WL0. MThis controls access to memory cell 202 of block 291 to read (e.g., sense) information (e.g., previously stored information) from memory cell 202 of block 291. In another example, during a write operation, memory device 200 can use signals WL0 to WL M To control access to memory cell 202 of block 291 so as to store information in memory cell 202 of block 291.

[0038] like Figure 2 As shown, control gates 250'0 to 250' M It can carry the corresponding signal WL'0 to WL' M Control gate 250'0 to 250' M Each of these can be part of a structure (e.g., a layer) of conductive material (e.g., a conductive material layer) located in a single level of memory device 200. Control gates 250'0 to 250' M They can be located at control gates 2500 to 250 respectively. M Same level (in the Z direction). As described above, control gates 250'0 to 250' M (For example, a local word line) can be connected to control gates 2500 to 2500. M (For example, other local word lines) electrical separation.

[0039] The memory device 200 may use signals WL'0 to WL' during operation (e.g., read, write, or erase operations). M This controls access to memory cells 202 in block 292. For example, during a read operation, memory device 200 can use signals WL'0 to WL'0. M This controls access to memory cell 202 of block 292 to read (e.g., sense) information (e.g., previously stored information) from memory cell 202 of block 292. In another example, during a write operation, memory device 200 can use signals WL'0 to WL' M To control access to memory cell 202 of block 292 so as to store information in memory cell 202 of block 292.

[0040] like Figure 2As shown, memory cells in different memory cell strings within the same block can share the same control gate (e.g., can be controlled by it). For example, in block 291, memory cells 202 coupled to control gate 2500 can share control gate 2500 (can be controlled by it). In another example, memory cells 202 coupled to control gate 2501 can share control gate 2501 (can be controlled by it). In another example, in block 292, memory cells 202 coupled to control gate 250'0 can share control gate 250'0 (can be controlled by it). In another example, memory cells 202 coupled to control gate 250'1 can share control gate 250'1 (can be controlled by it).

[0041] Memory device 200 may include a source (e.g., source line, source plate, or source region) 298 that can carry a signal (e.g., a source line signal) SL. Source 298 may be structured as a conductive line or conductive plate (e.g., a conductive region) of memory device 200. Source 298 may be a common source line (e.g., a common source plate or common source region) of blocks 291 and 292. Source 298 may be coupled to a ground connection of memory device 200.

[0042] Memory device 200 may include select transistors (e.g., drain select transistors) 2610 to 261 i (2610-261 i ) and select gate (e.g., drain select gate) 2810 to 281 i Transistor 2610 can share the same select gate 2810. Transistor 261 i The same select gate 281 can be shared. i Select gates 2810 to 281. N Signals SGD0 to SGD can be carried separately. i .

[0043] Transistors 2610 to 261 i Signals SGD0 to SGD can be used separately. i Control (e.g., turning on or off). During memory operations (e.g., read or write operations) of memory device 200, transistors 2610 to 261... i It can be connected (e.g., by activating the corresponding signals SGD0 to SGD). i The memory cell string 230 of block 291 is coupled to the corresponding data lines 2700 to 270. N Transistors 2610 to 261 i It can be turned off (e.g., by disabling the corresponding signals SGD0 to SGD). iThe memory cell string 230 of block 291 is connected to the corresponding data lines 2700 to 2700. N Decoupling.

[0044] Memory device 200 may include transistors (e.g., source select transistors) 260, each of which may be coupled between a source 298 and a memory cell 202 in a respective memory cell string (one of memory cell strings 230) of block 291. Memory device 200 may include a select gate (e.g., source select gate) 280. Transistors 260 may share a select gate 280. Transistors 260 may be controlled (e.g., turned on or off) by the same signal (such as an SGS signal (e.g., a source select gate signal) provided on the select gate 280. During memory operations of memory device 200 (e.g., read or write operations), transistor 260 may be turned on (e.g., by activating the SGS signal) to couple the memory cell string of block 291 to the source 298. Transistor 260 may be turned off (e.g., by disabling the SGS signal) to decouple the memory cell string of block 291 from the source 298.

[0045] The memory device 200 may include similar select gates and select transistors in block 292. For example, in block 292, the memory device 200 may include select gates (e.g., drain select gates) 281'0 to 281'. i and transistors (e.g., drain-select transistors) 2610 to 261 i Transistor 2610 of block 291 can share the same select gate 281'0. Transistor 261 of block 292 i The same selection gate 281' can be shared. i Select gates 281'0 to 281' i Signals SGD0' to SGDi' can be carried separately.

[0046] Transistors 2610 to 261 in block 292 i They can be controlled (e.g., turned on or off) by signals SGD0' to SGDi' respectively. During memory operations (e.g., read or write operations) of memory device 200, transistors 2610 to 261 of block 292... i It can be switched on (e.g., by activating the corresponding signals SGD0' to SGDi') to couple the memory cell string of block 292 to data lines 2700 to 270. N Transistors 2610 to 261 in block 292 i The memory cells of block 292 can be switched off (e.g., by disabling the corresponding signals SGD0' to SGDi') to the corresponding group of data lines 2700 to 270. N Decoupling.

[0047] Memory device 200 may include transistors (e.g., source select transistors) 260, each of which may be coupled between source 298 and memory cells in a corresponding memory cell string of block 292. The transistors 260 of block 292 may share the same select gate (e.g., source select gate) 280' of memory device 200. The transistors 260 of block 292 may be controlled (e.g., turned on or off) by the same signal (such as an SGS' signal (e.g., a source select gate signal) provided on the select gate 280'. During memory operations of memory device 200 (e.g., read or write operations), the transistors 260 of block 292 may be turned on (e.g., by activating the SGS' signal) to couple the memory cell string of block 292 to source 298. The transistors 260 of block 292 may be turned off (e.g., by disabling the SGS' signal) to decouple the memory cell string of block 292 from source 298. Figure 2 Electrically separated select gates 280 and 280' are shown as an example. Alternatively, select gates 280 and 280' may be electrically coupled to each other.

[0048] Memory device 200 includes Figure 2 Other components are not shown to avoid obscuring the exemplary embodiments described herein. References below... Figures 2 to 12 Some structures of the memory device 200 are described. For simplicity, the accompanying drawings will not be repeated. Figures 1 to 12 ) Detailed description of the same elements in ).

[0049] Figure 3 A top view of the structure of a memory device 200 according to some embodiments described herein is shown, the memory device including a memory cell array 201, stepped regions 345 and 346, and dielectric structures 351A, 351B, 351C, 351D, and 351E between blocks 290, 291, 292, and 293. In the accompanying drawings (figures), Figure 2 And other accompanying drawings (e.g., Figures 3 to 12 Similar or identical elements of the memory device 200 are given the same labels. Their detailed descriptions and functions are repeated in the accompanying drawings. For simplicity, section lines (e.g., shaded lines) are omitted from some or all of the elements shown in the drawings described herein. Some elements of the memory device 200 may be omitted from specific drawings to avoid confusion with the views or descriptions of the elements (or elements) described in that specific drawing. Furthermore, the dimensions (e.g., physical structures) of the elements shown in the drawings described herein are not drawn to scale.

[0050] like Figure 3As shown, the blocks (memory cell blocks) 290, 291, 292, and 293 (290 to 293) of the memory device 200 can be positioned side-by-side in the X direction. Four blocks 290 to 293 are shown as an example. The memory device 200 may contain multiple blocks. Figure 3 Blocks 291 and 292 are referenced above. Figure 2 The images are shown and described schematically. Other blocks of the memory device 200 (e.g., blocks 290 and 293) are not shown in the images. Figure 2 As shown in the image.

[0051] The dielectric structures 351A, 351B, 351C, 351D, and 351E of the memory device may have a length extending in the Y direction between blocks 290 and 293. Each dielectric structure 351A, 351B, 351C, 351D, and 351E may include slits (e.g., trenches having depth in the Z direction) and dielectric material (or multiple dielectric materials) formed (e.g., filled) in the slits. The dielectric structures 351A, 351B, 351C, 351D, and 351E can electrically separate one block from another. For example, dielectric structure 351B can electrically separate block 291 from block 290, while dielectric structure 351C can electrically separate block 291 from block 292. The control gate and select gate of adjacent blocks can be electrically separated from each other by the dielectric structure between adjacent blocks. For example, control gates 2500 to 2500. M and select gates 280 and 2810 to 281 i ( Figure 2 The dielectric structure 351C can be used to connect the control gate 250'0 to 250'. M and select gates 280' and 281'0 to 281' i ( Figure 2 Electrical separation.

[0052] Memory device 200 may include data lines 2700 to 2700 coupled to corresponding data lines. N Pillars 330 in blocks 290, 291, 292, and 293. Memory cells 202 of the memory cell string can extend along the length of the corresponding pillar 330. Figure 4A The length positioning (as shown) can be formed vertically along the length (e.g., it can be formed vertically along the length).

[0053] like Figure 3 As shown, the data lines 2700 to 270 of the memory device 200 N (with signal BL0 to BL) N (Associated) It can be located above the memory cell array 201 and can have a length extending along the X direction. Data lines 2700 to 270 NIt can extend above (e.g., on top of) blocks 290 to 293 and across the blocks (in the X direction), and can be shared by blocks 290 to 293. Data lines 2700 to 270 N It can be coupled to the corresponding support 330 (the support is located in the Z direction between data lines 2700 and 270). N (Below).

[0054] The stepped regions 345 and 346 of the memory device 200 may be located on corresponding sides (in the Y direction) of the memory cell array 201. The stepped regions 345 and 346 may include conductive contacts to provide access to the select gate and control gate (e.g., in the corresponding blocks 290, 291, 292, and 293 of the memory device 200) for communication with these gates. Figure 2 Select gates 280, 2810 and 281 i and control gate 2500 to 250 M Electrical connections (e.g., providing signals to) are made to the stepped regions 345 and 346. Stepped regions 345 and 346 may contain similar structures. However, for simplicity and in the description herein, [the following is omitted as is]. Figure 3 Details of the stepped region 346 are omitted. In an alternative embodiment of the memory device 200 (e.g., an alternative structure), the stepped region 346 may be omitted from the memory device 200, such that only the stepped region 345 (rather than both stepped regions 345 and 346) is included in the memory device 200.

[0055] like Figure 3 As shown, in block 291, the memory device 200 may include support structures 344A to 344L and conductive contacts in corresponding portions 5A, 5B, and 5C of the memory device 200 (conductive contacts 3651 and 365 are only labeled). M and 365 SGDi For simplicity, Figure 3 No labels are provided for the other support structures and other conductive contacts of blocks 290 to 293. Figure 3 The memory devices 200, portions 5A, 5B, and 5C, are respectively located in... Figure 5A , 5B This is shown in more detail in 5C. Figure 3 In the middle, line 4A-4A shows Figure 4A The location of a portion (e.g., a cross-section) of the memory device 200 shown.

[0056] like Figure 3 As shown, memory device 200 may include conductive material 340 in block 291. SGS 3400, 3401, 340 M-1 340 M 340 SGD0 and 340SGDi They can be formed separately Figure 2 Select gate 280, control gate 2500 to 250 M And select gates 2800 and 280 i (The material that forms it). Conductive material 340 SGD0 and 340 SGDi They can be electrically separated from each other through gap 347 (which can be filled with one (or more) dielectric materials). For simplicity, Figure 3 Labels are not provided for the other conductive materials of the select gate and control gate forming blocks 290, 292 and 291.

[0057] Figure 4A It shows along Figure 3 Lines 4A-4A show a portion (e.g., a cross-section) of the memory device 200. Figure 4A As shown, the memory device 200 may include layers 462, 463, 464, 472, 474, and 482, which may be physical layers (e.g., partial layers) in the Z direction of the memory device 200. Conductive material 340 SGS 3400, 3401, 340 M-1 340 M 340 SGD0 and 340 SGDi Along the Z-direction, one layer (e.g., one layer) of layers 462, 463, 464, 472, 474, and 482 can be positioned (e.g., stacked) above another layer. Conductive material 340 SGD0 and 340 SGDi They can be located on the same layer (e.g., layer 482). Conductive material 340 SGS 3400, 3401, 340 M-1 340 M and 340 SGDi It can be called conductive material 340 SGS 3400, 3401, 340 M-1 340 M and 340 SGDi The hierarchy.

[0058] like Figure 4A As shown, conductive material 340 SGS 3400, 3401, 340 M-1 340 M and 340 SGDi It can be interleaved with dielectric material 341 in the Z direction. Conductive material 340 SGS 3400, 3401, 340 M-1 340 Mand 340 SGDi It may contain metals (e.g., tungsten or other metals), other conductive materials, or combinations of conductive materials. Dielectric material 341 may contain silicon dioxide.

[0059] and Figure 4A The corresponding conductive materials in Figure 4A The signals SGS, WL0, WL1, and WL are... M-1 WL M SGD0 and SGD i and Figure 2 The signals shown are the same. Conductive material 340 SGS It can form Figure 2 Select gate 280 (associated with signal SGS). Conductive materials 3400, 3401, 340. M-1 and 340 M It can form Figure 2 Control gate 2500 to 250 M (respectively related to signals WL0, WL1, WL) M-1 and WL M (Related). Conductive material 340 SDG0 and 340 SGDi (with signals SGD0 and SGD) i (Related) can be formed separately Figure 2 Select gates 2800 and 280 i .

[0060] like Figure 4A As shown, conductive material 3400 (which forms the control gate 2500 associated with signal WL0) can be relative to other control gates 2501 to 250 of the memory device 200. M (with signal WL) M-1 and WL M Other conductive materials 3401 and 340 (related to) M-1 and 340 M The closest (in the Z direction) substrate is 499.

[0061] Figure 4A An example of a memory device 200 is shown, the memory device comprising a conductive material 340 forming a select gate (e.g., a source select gate associated with a signal SGS). SGS One layer. However, the memory device 200 may include multiple conductive material layers (e.g., conductive material 340) located below the layer of conductive material 3401 (in the Z direction) (e.g., below layer 464). SGS Multiple levels) to form multiple source-select gates of memory device 200.

[0062] Figure 4A An example of a memory device 200 is shown, the memory device comprising a conductive material 340 forming a select gate (e.g., a drain select gate associated with a signal SGD0). SGD0 A level and forming a selection gate (e.g., with signal SGD) i The associated drain-selective gate) conductive material 340 SGDi One level. However, the memory device 200 can be in the conductive material 340. M Above the layer (e.g., above layer 474) (in the Z direction) are multiple conductive material layers (e.g., conductive material 340). SGD0 Multiple levels) to form multiple drain select gates similar to the select gate associated with the signal SGD0 of the memory device 200. Similarly, the memory device 200 can be made of conductive material 340 M Above the layer (e.g., above layer 474) (in the Z direction) are multiple conductive material layers (e.g., conductive material 340). SGDi (Multiple levels) to form a signal SGD similar to that of memory device 200 i Multiple drain select gates associated with select gates.

[0063] like Figure 4A As shown, the memory device 200 may include a step region 345 ( Figure 3 The stepped structures 415, 402, and 401 are used in the study. Conductive material 340 SGS The corresponding portions (e.g., end portions) of 3400 and 3401, and their corresponding edges (e.g., steps) at locations 340E1, 304E2, and 340E3, can collectively form a stepped structure 415. Conductive material 340 M-1 and 340 M The corresponding portions (e.g., end portions) and their corresponding edges (e.g., steps) at positions 340E4 and 304E5 can together form a stepped structure 402. Conductive material 340 SDG1 A portion (e.g., the end portion) and its edge (e.g., a step) at location 340E6 Figure 4B As shown, a stepped structure 401 can be formed. The description herein gives the number of instances of edges contained in a particular stepped structure (e.g., edges at positions 340E1 to 340E6). However, each stepped structure may contain more than one edge, and may contain edges with... Figure 4A The image shows several edges with different edges.

[0064] For the sake of simplicity, Figure 4AOther step structures between step structures 402 and 415 are omitted. The memory device 200 may contain up to 15 step structures. Alternatively, the memory device 200 may contain more than 15 step structures.

[0065] like Figure 4A As shown, the step structure 415 may be located closest to the substrate 499 in the Z direction relative to the positions of other step structures in the step structure (e.g., step structures 401 and 402, and the step structure between step structures 402 and 415 (not shown)).

[0066] exist Figure 4A In this context, a layer of conductive material (e.g., conductive material 3401) and an adjacent layer of dielectric material 341 (e.g., dielectric material 341 between conductive materials 3400 and 3401) can be referred to as a layer of the memory device 200. Figure 4A As shown, these layers can be stacked on top of each other in the Z direction above the substrate 499 (e.g., stacked). Figure 4A Examples are shown of a specific number of layers (and corresponding edges) for each step structure and a corresponding number of layers (e.g., three layers for step structure 415). However, each step structure of the memory device 200 can be composed of... Figure 4A The diagram shows several layers (and corresponding edges) of varying numbers. For simplicity, Figure 4A Several layers of the memory device 200 are shown. However, the memory device 200 may contain up to one hundred layers. Alternatively, the memory device 200 may contain more than one hundred layers.

[0067] Figure 3 Other blocks of the memory device 200 (e.g., blocks 290, 292, and 293) may also have their own ladder structures similar to the ladder structure of block 291. For simplicity, details of the ladder structures of the other blocks of the memory device 200 (e.g., blocks 290, 292, and 293) are omitted from the description herein.

[0068] like Figure 4A As shown, the dielectric material 341 may also include edges (not marked) adjacent to (e.g., aligned in the Z direction) the respective edges 340E1 to 340E5. Thus, the stepped structures 401, 402, and 415 may also be partially formed by portions and edges of the dielectric material 341.

[0069] The following description is for reference. Figure 4A , Figure 4B and Figure 4C . Figure 4B It shows Figure 4AMore details about a portion of the memory device 200. Figure 4C It shows Figure 4B A top view of a portion of the memory device 200.

[0070] like Figure 4A and Figure 4C As shown, conductive material 340 SGD0 and 340 SGDi They can be located at the same level (e.g., Figure 4A On level 482) and positioned side by side (in Figure 4C (in the X direction). For example Figure 4C As shown, conductive material 340 SGD0 and 340 SGDi (which respectively form select gates 2810 and 281) i They can be electrically separated from each other through gap 347.

[0071] like Figure 4A and Figure 4B As shown, the memory device 200 may include a substrate 499 and materials 496 and 497 located above (e.g., formed above) the substrate 499. The substrate 499 may include a semiconductor (e.g., silicon) substrate. The substrate 499 may also include circuitry 495 located below other components of the memory device 200 formed above the substrate 499. The circuitry 495 may include circuitry coupled to circuitry elements outside the substrate 499 (e.g., ...). Figure 4A Transistors Tr1 and Tr2 are shown. For example, circuit elements outside substrate 499 may include data lines 2700 to 270. N 365 conductive contacts SGS 3651, 365 M 365 M-1 ( Figure 4A ), 365 SGDi ( Figure 4B ) and 365 SGD0 ( Figure 4C The circuit 495 includes conductive path 491 and other conductive connections (not shown), as well as other circuit elements of the memory device 200. The circuit elements of circuit 495 (e.g., transistors Tr1 and Tr2) may be configured to perform part of the functions of the memory device 200. For example, transistors Tr1 and Tr2 may be part of decoder circuitry, driver circuitry, buffers, sense amplifiers, charge pumps, and other circuitry of the memory device 200.

[0072] like Figure 4AAs shown, the conductive path (e.g., conductive wiring) 491 may include a portion (segment) extending in the Z direction (e.g., vertically). The conductive path 491 may include (e.g., may be coupled to) conductive contacts (e.g., conductive contacts 365) of the memory device 200. SGS 3650, 3651, 365 M 365 M-1 ( Figure 4A ), 365 SGDi ( Figure 4B ) and 365 SGD0 ( Figure 4C Some (or all) of the following. For example... Figure 4A As shown, conductive path 491 can be coupled to circuit 495. For example, at least one of conductive paths 491 can be coupled to at least one transistor Tr1 and Tr2 of circuit 495.

[0073] Conductive path 491 can provide conductive contacts 365 SGS 3650, 3651, 365 M 365 M-1 ( Figure 4A ), 365 SGDi ( Figure 4B ) and 365 SGD0 ( Figure 4C Electrical connections between the memory device 200 and other components. For example, conductive path 491 can be coupled to conductive contact 365. SGS 3650, 3651, 365 M 365 M-1 ( Figure 4A ), 365 SGDi ( Figure 4B ) and 365 SGD0 ( Figure 4C The circuit elements of circuit 495 (e.g., word line driver and word line decoder, not shown) provide respectively from the circuit elements of circuit 495 (e.g., word line driver, word line decoder, and charge pump, not shown) to conductive contact 365. SGS 3650, 3651, 365 M 365 M-1 365 SGDi and 365 SGD0 Electrical connections (e.g., signals SGS, WL0, WL1, WL) M-1 WL M SGD0 and SGD i (in the form of).

[0074] like Figure 4A and Figure 4B As shown, conductive contact 365SGS 3650, 3651, 365 M 365 M-1 and 365 SGDi ( Figure 4A and Figure 4B The conductive contacts are hidden in the view. SGD0 The conductive contact 365 may have different lengths extending in the Z direction (e.g., extending vertically (e.g., outward) from the substrate 499). SGS 3650, 3651, 365 M 365 M-1 365 SGD0 and 365 SGDi Each of them can contact conductive material 340 SGS 3400, 3401, 340 M-1 340 M 340 SGD0 and 340 SGDi The corresponding conductive material (e.g., landed on it) is used to form electrical contacts with the corresponding conductive material. Therefore, conductive contacts 365 SGS 3650, 3651, 365 M 365 M-1 365 SGD0 and 365 SGDi It can be part of a conductive path (e.g., part of conductive path 491) to carry electrical signals to the selection gate (e.g., the source selection gate associated with signal SGS) and the control gate (e.g., associated with signal WL) respectively. M and WL M-1 Associated control gates) and other selection gates (e.g., those associated with signals SGD0 and SGD) i (Associated drain-select gate).

[0075] like Figure 4A As shown, conductive contact 365 SGS With conductive material 340 SGS Electrical contact, and with the remaining conductive materials (e.g., conductive materials 3400, 3401, 340...). M-1 340 M and 340 SGDi Electrical separation. Conductive contact 3650 is in electrical contact with conductive material 3400 and with the remaining conductive material (e.g., conductive material 340). SGS 3401, 340 M-1 340 M and 340 SGDiElectrical separation. Therefore, the conductive contacts (e.g., conductive contact 3650) can only interact with the conductive material of the memory device 200 (e.g., conductive material 340). SGS 3400, 3401, 340 M-1 340 M and 340 SGDi One of the conductive materials in the material is in electrical contact.

[0076] Materials 496 and 497 Figure 4A and Figure 4B ) is the source (e.g., source line, source plate, or source region) 298 of the memory device 200. Figure 2 Material 496 may contain polycrystalline silicon. Material 497 may be tungsten oxide.

[0077] Support structures 344A to 344L can be formed to provide structural support to a portion of the memory device 200 (e.g., stepped region 345) during a specific process of forming the memory device 200, as referenced. Figures 8A to 10C (More detailed description).

[0078] like Figure 4A As shown, support structures 344A, 344C, 344E, 344H, and 344J can have the same length extending in the Z direction (e.g., extending vertically (e.g., outwardly) from the substrate 499). Support structures 344B, 344D, 344F, 344G, 344I, and 344K ( Figure 4A and Figure 4B (Hidden in view) can also have with Figure 4A The support structures 344A, 344C, 344E, 344H, and 344J shown are of the same length. Support structures 344A to 344L can pass through conductive material 340. SGS 3400, 3401, 340 M-1 340 M and 340 SGDi The corresponding parts and dielectric material 341. Support structures 344A to 344L and conductive material 340. SGS 3400, 3401, 340 M-1 340 M 340 SGD0 and 340 SGDi Electrical separation. Each of the support structures 344A to 344L can contact the material 497 (e.g., land on it).

[0079] Figure 5A , Figure 5B and Figure 5C Several embodiments according to the description herein are shown respectively. Figure 3Top views of portions 5A, 5B, and 5C of the memory device 200. (See attached image.) Figure 5A , Figure 5B and Figure 5C As shown, conductive contact 365 SGS 3650, 3651, 365 M 365 M-1 365 SGD0 and 365 SGDi They can be grouped together (e.g., formed in) corresponding stepped structures 415, 402, and 401. For example, this group of conductive contacts 365 SGS 3650 and 3651 can be located at the stepped structure 415 and can have a width (e.g., diameter) W3 in the X direction. This set of conductive contacts 365... M and 365 M-1 It can be located at the stepped structure 402 and can have a width (e.g., diameter) W6 in the X direction. This set of conductive contacts 365 SGD0 and 365 SGDi It can be located at the stepped structure 401 and can have a width (e.g., diameter) W10 in the X direction.

[0080] Conductive contacts within the same group (located on the same step) can have the same width. For example, conductive contact 365 SGS Contacts 3650 and 3651 (located at step structure 415) can have the same width W3. Conductive contact 365 M and 365 M-1 (Located at step structure 402) can have the same width W6. Conductive contact 365 SGD0 and 365 SGDi (Located at step structure 401) can have the same width W10.

[0081] Conductive contacts in different groups (located at different steps) can have different widths (different dimensions (e.g., dimensions in nanometers)). Therefore, widths W3, W6, and W10 can be different from each other. As an example, width W3 can be greater than width W6, and width W6 can be greater than width W10. Each of widths W3, W7, and W10 can be smaller than each of widths W1, W2, W4, W5, W7, and W8 of the corresponding support structures 344A to 344L.

[0082] like Figure 5A , Figure 5B and Figure 5C As shown, support structures 344A to 344L can be positioned in groups (e.g., can be formed) at corresponding stepped structures 415, 402, and 401. Figure 5AAs shown, the set of support structures 344A to 344F can be located at the stepped structure 415 and at the corresponding conductive contact 365. SGS The support structures 344A to 344F may have corresponding widths (e.g., diameters) W1 and W2 in the X direction. The widths W1 and W2 may be the same (e.g., having the same nanometer size).

[0083] like Figure 5B As shown, the support structures 344G to 344J can be located at the stepped structure 402 and at the corresponding conductive contact 365. M-1 and 365 M Nearby. Support structures 344G to 344J may have corresponding widths (e.g., diameters) W4 and W5 in the X direction. Widths W4 and W5 may be the same (e.g., having nanometer dimensions).

[0084] like Figure 5C As shown, the support structures 344K and 344L can be located at the stepped structure 401 and at the corresponding conductive contact 365. SGD0 and 365 SGDi Nearby. Support structures 344K and 344L may have corresponding widths (e.g., diameters) W7 and W8 in the X direction. Widths W7 and W8 may be the same (e.g., having the same nanometer size).

[0085] Support structures in different groups (located at different step structures) can have different widths (e.g., different dimensions in nanometers). For example, widths W1, W4, and W7 (or widths W2, W5, and W8) can be different from each other. Width W1 can be smaller than width W4, and width W4 can be smaller than width W7. For example, width W1 can be 360 ​​nm (nanometers) and can have a range from 345 nm to 375 nm. Therefore, width W1 can be at least 345 nm and can have a dimension up to 375 nm. In another example, width W4 can be 414 nm and can have a range from 399 nm to 429 nm. In another example, width W7 can be 420 nm and can have a range from 405 nm to 435 nm.

[0086] Figure 5A , Figure 5B and Figure 5C Distances D1 to D9 are shown. Each of distances D1 to D9 can be the shortest distance between the edges of two adjacent elements (two adjacent structures) of the memory device 200.

[0087] The distance D1 can be measured between the edge (e.g., sidewall) 351B_E1 of the dielectric structure 351B and the edge (unmarked) or portion (unmarked) of the nearest edge 351B_E1 of the support structure 344A (relative to other parts of the support structure 344A). Figure 5A Similarly, each of the support structures 344C and 344E can be located at a distance D1 from the edge 351B_E1. The dielectric structure 351B comprises edges 351B_E1 and 351B_E2 opposite to each other in the X direction. The edge 351B_E1 of the dielectric structure 351B can be a conductive material 340. SGS The portion at the location where 3400 and 3401 contact (intersect) with the dielectric material of dielectric structure 351B (e.g., the interface in the Y direction). For example... Figure 5A , 5B As shown in Figure 5C, the edge 351B_E1 of the dielectric structure 351B can be located in the conductive material 340. SGS 3400, 3401, 340 M-1 and 340 M and conductive material 340 SGD0 Near the side wall (unmarked) (where 3400, 3401, 340) M-1 340 M Form the corresponding control gate 2500 to 250 M The edge 351C_E1 of the dielectric structure 351C can be located in the conductive material 340. SGS 3400, 3401, 340 M-1 and 340 M Other sidewalls (unmarked) and conductive material 340 SGDi Near the side wall.

[0088] The distance D2 can be measured between the edge (e.g., sidewall) 351C_E1 of the dielectric structure 351C and the edge or portion (unmarked) of the nearest edge 351C_E1 of the support structure 344B (relative to other parts of the support structure 344B). Figure 5A Similarly, each of the support structures 344D and 344F can be located at a distance D2 from the edge 351C_E1. The dielectric structure 351B comprises edges 351C_E2 and 351C_E1 opposite each other in the X direction. The edge 351B_C2 of the dielectric structure 351C can be a conductive material 340. SGS The portions at the locations where 3400 and 3401 contact (intersect) with the dielectric material of dielectric structure 351C (e.g., the interface in the Y direction).

[0089] The distance D3 can be measured between the adjacent edges (unmarked) of support structures 344A and 344B. Figure 5A Distance D3 can be the closest distance (in the X direction) between the corresponding edges of support structures 344A and 344B. Similarly, support structures 344C and 344D can be separated from each other by distance D3. Support structures 344E and 344F are separated from each other by distance D3.

[0090] The distance D4 can be measured between the edge 351B_E1 of the dielectric structure 351A and the edge or portion (unmarked) of the nearest edge 351B_E1 of the support structure 344G (relative to other parts of the support structure 344G). Figure 5B Similarly, the support structure 344I can be located at a distance D4 from the edge 351B_E1.

[0091] The distance D5 can be measured between the edge 351C_E1 of the dielectric structure 351C and the edge or portion (unmarked) of the nearest edge 351C_E1 of the support structure 344H (relative to other parts of the support structure 344H). Figure 5B Similarly, the support structure 344J can be located at a distance D5 from the edge 351C_E1.

[0092] The distance D6 can be measured between the adjacent edges (unmarked) of support structures 344G and 344H. Figure 5B The distance D6 can be the closest distance (in the X direction) between support structures 344G and 344H. Similarly, support structures 344I and 344J are separated by a distance D6.

[0093] The distance D7 can be measured between the edge 351B_E1 of dielectric structure 351A and the edge or portion (unmarked) of the nearest edge 351B_E1 of support structure 344K (relative to other parts of support structure 344K). Figure 5C ).

[0094] The distance D8 can be measured between the edge 351C_E1 of the dielectric structure 351C and the edge or portion (unmarked) of the nearest edge 351C_E1 of the support structure 344L (relative to other parts of the support structure 344L). Figure 5C ).

[0095] The distance D9 can be measured between the adjacent edges (unmarked) of the support structures 344K and 344L. Figure 5C The distance D9 can be the shortest distance (in the X direction) between support structures 344K and 344L.

[0096] Distances D1, D4, and D7 (at step structures 415, 402, and 401, respectively) can be different from each other. Distance D7 can be smaller than distance D4, and distance D4 can be smaller than distance D1. For example, distance D1 can be 203 nm and can have a range from 190 nm to 215 nm. Therefore, distance D1 can be less than 215 nm. In another example, distance D4 can be 176 nm and has a range from 163 nm to 189 nm. In another example, distance D7 can be 173 nm and can have a range from 160 nm to 186 nm.

[0097] The distances between components at different step structures can vary. For example, distances D3, D6, and D9 (at step structures 415, 402, and 401, respectively) can differ from one another. Distance D9 can be less than distance D6, and distance D6 can be less than distance D3. As an example, distances D3, D6, and D9 can be 214 nm, 160 nm, and 154 nm, respectively. In another example, distance D3 can have a range from 202 nm to 227 nm. Therefore, distance D3 can be less than 214 nm (and greater than or equal to 202 nm).

[0098] exist Figure 5A , Figure 5B and Figure 5C In this context, the ratio (e.g., dimensional relationship) of the width of a particular support structure to the distance from the edge of the particular support structure to the edge of the corresponding dielectric structure is expressed as W1 / D1, W4 / D4, and W7 / D7. For example, based on the dimensions of the example above, the ratio W1 / D1 = 1.77 (where W1 = 360 and D1 = 203). The ratio W1 / D1 can have a range (e.g., an approximate range) from W1 / D1 = 1.6 (where W1 = 345 and D1 = 215) to W1 / D1 = 2.0 (where W1 = 375 and D1 = 190).

[0099] During the process of forming memory device 200 (see below) Figures 6A to 10C (Description) Some structures at specific locations of the memory device 200 may collapse (e.g., due to static friction). Such collapse can be prevented by structuring some elements of the memory device 200 (e.g., support structures 344A to 344L) to have specific dimensions (e.g., critical dimensions) (such as specific dimensions of widths W1 to W10 and distances D1 to D9 (e.g., in nanometers)) and the width-to-distance ratio, as referenced above. Figure 5A , Figure 5B and Figure 5C As described. Preventing these collapses can lead to improved yield, reliability, or both of the memory device 200.

[0100] The following text can be used as a reference. Figures 6A to 10C The described process is used to form the support structures 344A to 344L (see above). Figures 3 to 5C (Described). The portions forming the support structures 344A to 344L may be included in the reference below. Figures 6A to 10C Markings (e.g., masks) are used during the described process. These markings may include references below. Figure 11 The 1100 caliber is described.

[0101] Figures 6A to 10C The following diagram illustrates some embodiments of the formation described herein. Figures 2 to 5C Different structural views of the memory device 200 during the manufacturing process. Figure 6A A side view (e.g., cross-sectional view) of the device 200 in the X direction is shown after dielectric material (dielectric material layer) 640 and dielectric material (dielectric material layer) 641 are alternately formed on the substrate 499 (e.g., materials are formed successively on the substrate 499 in an alternating manner).

[0102] like Figure 6A As shown, the conductive material 340 layer (e.g., a single layer) may have a thickness T1. The dielectric material 641 layer (e.g., a single layer) may have a thickness T2. Thickness T1 may be 32 nm and may have a range from 30 nm to 35 nm. Thickness T2 may be 25 nm and may have a range from 22 nm to 27 nm.

[0103] Dielectric material 640 may contain silicon nitride. Dielectric material 641 may contain silicon dioxide. For example... Figure 6A As shown, dielectric materials 640 and 641 can be formed such that dielectric material 640 can be interleaved with dielectric material 641 in the Z direction at layers 462, 464, 466, 472, 474, and 482, respectively. For simplicity, Figure 6A Some dielectric materials 640 and 641 between layers 466 and 472 have been omitted.

[0104] Figure 6B It shows Figure 6A A top view (e.g., XY plan view) of the memory device 200. Figure 6B The location of stepped area 345 is also shown, including stepped structures 401, 402, and 415. Figure 4A ) can be used in subsequent processes (e.g., with Figure 7 In the associated process, it is formed in the corresponding position in the stepped region 345. Figure 6B In the middle, line 6C-6C shows Figure 6C The location of a portion (e.g., a cross-section) of the memory device 200 shown.

[0105] like Figure 6C As shown, the interleaving of dielectric materials 640 and 641 along the YZ direction can be similar to the interleaving of dielectric materials 640 and 641 along the XZ direction (e.g.) Figure 6A (As shown) Same.

[0106] Figure 7 The diagram shows the formation of stepped structures 401, 402, and 415 (in the YZ direction). Figure 6C The memory device 200. Forming the stepped structures 401, 402 and 415 may include removing a portion of dielectric materials 640 and 641 to obtain the remainder of dielectric materials 640 and 641, which have corresponding edges (e.g., vertical edges) at positions 340E1 to 340E6, at the corresponding levels in layers 462, 464, 466, 472 and 482.

[0107] Figure 8A A side view (in the XZ direction, similar to) of the memory device 200 after the formation of the support structure 844 (of block 292) and the support structure 344B (of block 291) and the slit (e.g., trench) 851C is shown. Figure 6A (Side view).

[0108] Forming support structures 344B and 844 may involve removing portions of dielectric materials 640 and 641 to form openings (e.g., holes) at the locations where support structures 344B and 844 will be formed, and then forming materials 801 and 802 within the openings. Material 801 may comprise a combination of materials (e.g., different layers). Lines 8C-8C illustrate this. Figure 8C A portion (e.g., cross-section) of the support structure 344B is shown in detail.

[0109] Forming a slit 851C ( Figure 8A This may involve removing a portion of dielectric materials 640 and 641 to form an opening at the location of slit 851C, such that slit 851C may include edges (e.g., sidewalls) 851' and 851'". Edges 851' and 851' may correspond to edges 351C_E1 and 351C_E2 of FIG. 5, respectively. Figure 8A As shown, each of edges 851' and 851" may include corresponding sidewalls (not marked) of dielectric materials 640 and 641 at the location of slit 851C (e.g., which may be formed therefrom). Slit 851C may be formed after the support structures 344B and 844 are formed.

[0110] For the sake of simplicity, Figure 8AOnly two support structures, 344B and 844, are shown in the diagram. Other support structures (e.g., support structures 344A and 344C to 344L) may be formed in a similar manner to support structures 344B and 844, and may be formed simultaneously with support structures 344B and 844 (e.g., in the same process step).

[0111] Figure 8B The memory device 200 is shown after the formation of the support structures (only support structures 334A, 344B, 344K, 344L, and 844 are labeled) and the corresponding blocks 290, 291, 292, and 293 of the memory device 200. Slits 851B, 851C, and 851D can respectively correspond to... Figure 3 The corresponding slits of dielectric structures 351B, 351C, and 351D. Markings (e.g., Figure 11 Marker 1100 can be used in the process of forming support structures 344A to 344L (and other support structures) of block 291. Other marks (similar to mark 1100) can be used in the process of forming support structures in other blocks of the memory device (e.g., blocks 290, 292, and 293). The support structures of blocks 290, 291, 292, and 293 can be formed simultaneously (e.g., simultaneously using the same process steps).

[0112] like Figure 8C As shown, the material 801 of the support structure 344B may comprise a combination of materials 801a, 810b, 801c, and 801d, which can be formed one material after another (e.g., layer after layer). For example, material 801a may be formed first, material 801b may be formed after material 801a, material 801c may be formed after material 801b, and material 801d may be formed after material 801c. Material 802 may be formed after material 801 (e.g., after material 802d). Materials 801a, 810b, 801c, and 801d may comprise silicon dioxide, silicon nitride, titanium, and titanium nitride, respectively. Material 802 may comprise a metal (e.g., tungsten or other metals).

[0113] Support structure of memory device 200 Figure 8A The support structures 344B and 844, and other support structures not shown, can be formed simultaneously (e.g., in the same process step). However, as referenced above... Figure 5A , Figure 5B and Figure 5CAs described, the support structures at different stepped structures (e.g., stepped structures 401, 402, and 415) can have different widths (e.g., different diameters). Support structures that can form the memory device 200 ( Figure 8A Support structures 344B and 844 (and other support structures not shown) are used to provide structural support to portions of the memory device 200 (e.g., stepped regions 345) during a specific process of forming the memory device 200. Figure 9A When the dielectric material 640 is removed during the process of manufacturing the associated memory device 200, the support structure of the memory device 200 ( Figure 8A The support structures 344B and 844 (and other support structures not shown) can provide structural support to the memory device 200.

[0114] Figure 9A It is shown that from position 910 ( Figure 9A )Removal (e.g., depletion) of dielectric material 640 ( Figure 8A The memory device 200 is then formed. Support structures 344B and 844 can provide structural support to prevent damage during the process of forming the memory device 200 (e.g., in conjunction with...). Figure 9A During the process associated with the removal of material 640, higher-level dielectric material 641 falls onto lower-level dielectric material 641.

[0115] Figure 9B A memory device 200 is illustrated in an example configuration, which includes partial collapse of the dielectric material 641 at the location of the slit 851C. (As shown) Figure 9B As shown, adjacent portions of dielectric material 641 may collapse, allowing adjacent portions of dielectric material 641 to touch (contact) each other.

[0116] At some values ​​of thickness T1 and T2, the dielectric material 641 at certain locations of the memory device 200 (e.g., at the stepped structure 415) may collapse (e.g., due to static friction). This static friction may be caused by the adhesion of adjacent dielectric materials 641 to each other (e.g., when experiencing capillary forces caused by surface tension), resulting in some dielectric materials 641 becoming like... Figure 9B The example shown depicts a collapse. This collapse can lead to the formation of conductive material (e.g., conductive material 340) at the collapse site during subsequent processes. SGS 3400 and 3401) are short-circuited to each other (e.g., electrically coupled). This short circuit may degrade or destroy the function of the memory device 200. To prevent this collapse and improve the structure and reliability of the memory device 200, some elements of the memory device 200 may be formed with specific dimensions (e.g., critical dimensions in nanometers). For example, as referenced above Figure 5A , Figure 5B and Figure 5C As described, the width (e.g., widths W1 to W10), distance (e.g., distances D1 to D9), and width-to-distance ratio of the memory device 200 can be configured to have specific dimensions (e.g., critical dimensions in nanometers) to prevent the dielectric material 641 from collapsing at locations where such collapse is likely to occur (e.g., at the stepped structure 415). Figure 9A An example of dielectric material 641 without this collapse is shown.

[0117] Figure 10A This is shown after the formation of conductive material (e.g., conductive material layer) 340 and dielectric structure 351C. Figure 9A Memory device 200. For example... Figure 10A As shown, the conductive material 340 layer (e.g., a single layer) can have a thickness T1'. The thickness T1' can be different from that of the dielectric material 640 ( Figure 8A The thickness T1 of each layer is the same. For example, the thickness T1' can be 32nm and can have a range from 30nm to 35nm.

[0118] One or more materials can be filled into position 910. Figure 9A The conductive material 340 is formed by means of a process called a process. In one example, the conductive material 340 may comprise a single conductive material, such as a single metal (e.g., tungsten). In another example, the conductive material 340 may comprise multiple materials (which may be formed one material after another). One of the multiple materials may comprise a conductive material (e.g., a metal such as tungsten). For example, the conductive material 340 may comprise different layers of alumina (AlO), titanium nitride (TiNi), and tungsten (W). The conductive material 340 may correspond to... Figure 4A The conductive material 340 shown SGS 3400, 3401, 340 M-1 340 M 340 SGD0 and 340 SGDi .and Figure 10A The signals SGS, WL0, WL1, and WL associated with the corresponding conductive material 340 in the middle are: M-1 WL M SGD0 and SGD i and Figure 4A The signals shown are the same. Dielectric material 641 can correspond to... Figure 4A Dielectric material 341.

[0119] In Figure 10A In the associated process, it can be achieved by using slit 815B ( Figure 9AMaterials 1010 and 1015 are filled (e.g., deposited) in the positions to form a dielectric structure 351C. Material 1010 may contain a dielectric material (e.g., silicon dioxide). Material 1015 may contain polycrystalline silicon, or alternatively, a dielectric material (e.g., silicon dioxide or silicon nitride). Figure 10A As shown, material 1010 can be formed (e.g., positioned) at the location of dielectric structure 351C adjacent to the sidewalls (e.g., vertical sidewalls) of the corresponding materials 340 and 641.

[0120] Figure 10B It shows Figure 10A A top view (in the XY direction) of a portion of the memory device 200 at the dielectric structure 351C. (See attached image.) Figure 10A and Figure 10B As shown, material 1010 is formed on both sides of dielectric structure 351C (e.g., on opposite sidewalls in the X direction, not labeled). Material 1015 may be formed between portions of material 1010 (e.g., sidewall portions). Materials 1010 and 1015 may be formed along the length of dielectric structure 351C (in the Y direction).

[0121] Figure 10C The diagram shows support structures 344B, 344D, 344F, 344H, 344J, and 344L (in conjunction with...). Figure 8A (formed in related processes) Figure 10A A side view (e.g., cross-section) of the memory device 200. Figure 10C Other supporting structures are hidden in the view (e.g., in relation to...). Figure 8A Support structures 344B, 344D, 344F, 344G, 344I, and 344K are formed in the associated processes. After forming the support structures of the memory device 200 (e.g., support structures 344E to 344L), conductive contacts 365 can be formed in subsequent processes of the memory device 200. SGS 3651, 365 M 365 M-1 365 SGD0 and 365 SGDi ( Figure 5A , Figure 5B and Figure 5C For the sake of simplicity and to avoid obscuring the embodiments described herein, the subsequent processes for completing the memory device 200 are not described herein.

[0122] Figure 11 A tracing (e.g., a mask) 1100 is shown according to some embodiments described herein. The tracing 1100 can be configured for forming Figures 2 to 10CIn part of the process of memory device 200. For example, marker 1100 may be configured in block 291 (forming memory device 200) Figure 8B The support structure (e.g., support structures 344A to 344L) is included in the system (e.g., during the process) during manufacturing. Figure 12 In the system 1200).

[0123] like Figure 11 As shown, the marker 1100 may include edges (e.g., sides) 1111 and 1112 extending along the Y direction, and patterns (e.g., square features) 1144A to 1144L between edges 1111 and 1112. Pattern 1144A may include sides 1121 and 1122. Sides 1121 and 1122 may have the same size (e.g., a size in nm). Figure 11 As shown, pattern 1144A may be located near edge 1111. Side 1121 may be parallel to edge 1111. Side 1122 is connected to side 1121 at an angle (e.g., 90 degrees) and may be perpendicular to edge 1111.

[0124] Pattern 1144B may include sides 1131 and 1132. Sides 1131 and 1132 may have the same dimensions (e.g., dimensions in nm). Figure 11 As shown, pattern 1144B can be located near edge 1112. Side 1131 can be parallel to edge 1112. Side 1132 is connected to side 1131 at an angle (e.g., 90 degrees) and can be perpendicular to edge 1112.

[0125] Other patterns of the marking 1100 (e.g., patterns 1144C to 1144L) may also include sides similar to those of patterns 1144A and 1144B. This can be implemented in the memory device 200. Figure 5A , Figure 5B and Figure 5C During the process of forming support structures (e.g., support structures 344A to 344L) at the positions of the stepped structures 401, 402 and 415, patterns are used at the corresponding portions 1101, 1102 and 1115 of the marking line 1100.

[0126] Figure 11 The positions of some structures of the memory device 200 relative to patterns (e.g., patterns 1144A to 1144L) are also shown (in dashed lines). For example, positions 351B' and 351C' may correspond to the positions of dielectric structures 351B and 351C, respectively. Figure 5A , Figure 5B and Figure 5C Position 365' can correspond to the corresponding conductive contact 365. SGS3650, 3651, 365 M 365 M-1 365 SGDi and 365 SGD0 Location ( Figure 5A , Figure 5B and Figure 5C ).

[0127] like Figure 11 As shown, patterns 1144A to 1144L may contain corresponding widths W1', W2', W4', W5', W7', and W8'. The distances between patterns 1144A to 1144L, and between patterns 1144A to 1144L and their corresponding edges 1111 and 1112, are represented by distances D1' to D9'.

[0128] Patterns 1144A to 1144L can be used in the process of forming the support structures 344A to 344L of the memory device 200, respectively. Figure 5A , Figure 5B and Figure 5C Therefore, widths W1, W2, W4, W5, W7, and W8 ( Figure 5A , Figure 5B and Figure 5C The dimensions (in nm) can be based on the 1100 gauge. Figure 11 The dimensions (in nm) of the widths W1', W2', W4', W5', W7', and W8' of the array. For example, the widths W1', W2', W4', W5', W7', and W8' ( Figure 11 The dimensions of ) can be determined (e.g., selected) as being respectively related to widths W1, W2, W4, W5, W7, and W8. Figure 5A , Figure 5B and Figure 5C The dimensions are the same (or substantially the same).

[0129] Distance from D1 to D9 ( Figure 5A , Figure 5B and Figure 5C The dimensions (in nm) of the distances from D1' to D9' can be based on the dimensions of the distances from D1' to D9', respectively. For example, the dimensions (in nm) of the widths W1', W2', W4', W5', W7', and W8' can be determined (e.g., selected) to be based on the distances from D1' to D9', respectively. Figure 5A , Figure 5B and Figure 5C The widths W1, W2, W4, W5, W7, and W8 are the same (or substantially the same).

[0130] In gradation 1100, the ratios of widths W1', W4', and W7' to distances D1', D4', and D7' (e.g., W1' / D1', W4' / D4', and W7' / D7') can be the same as the ratios of widths W1, W4, and W7 to distances D1, D4, and D7 (e.g., W1 / D1, W4 / D4, and W7 / D7).

[0131] Using 1100 in the process of forming the support structure of memory device 200 (e.g., support structures 344A to 344L) allows the support structure of memory device 200 to have the features described above. Figure 5A , Figure 5B and Figure 5C The described specific dimensions (in nm). (See above for reference.) Figures 3 to 10C The benefits and improvements of the support structure (e.g., support structures 344A to 344L) for memory devices 200 having such specific dimensions (in nm) are described.

[0132] Figure 12 A system 1200 comprising a lithography apparatus (e.g., a stepper) 1201 and a marker 1100 is illustrated according to some embodiments described herein. The system 1200 can be used as part of a process for forming a memory device 200. For example, the lithography apparatus 1201 can be used to guide a light source (not shown) through the marker 1100. A projection lens (not shown) of the lithography apparatus 1201 can then receive the light source (after the light source has passed through the marker 1100) and generate a light beam 1205 based on the light source. The projection lens can be located in the support structures 344A to 344L of the memory device 200 (in... Figure 5A , Figure 5B and Figure 5C During the formation process (as detailed in the diagram), a beam 1205 is projected onto a wafer 1202, and the support structure may be part of the wafer 1202. The dimensions (in nm) of the support structures 344A to 344L may be based on the dimensions of the pattern of the marker 1100 (e.g., patterns 1144A to 1144L). (See above reference) Figures 3 to 11 The benefits and improvements of the support structures 344A to 344L (e.g., formed by using the markings 1100 in system 1200) are described.

[0133] The above references Figures 1 to 12The described embodiments include an apparatus and a method of forming the apparatus. One of the apparatuses includes a substrate; layers stacked one on top of the substrate, the layers including respective memory cells and control gates for the memory cells, the control gates including a control gate closest to the substrate and other control gates, the control gates including corresponding portions forming a stepped structure; conductive contacts contacting the control gates at locations of the stepped structure, the conductive contacts having different lengths extending vertically from the substrate, the conductive contacts including a conductive contact contacting a first control gate; a dielectric structure adjacent to the sidewalls of the control gates of the layers; and a support structure adjacent to the conductive contacts and electrically isolated from the control gates and the conductive contacts, the support structure having a length extending vertically from the substrate and extending through at least a portion of the control gates, the support structure including a support structure closest to the conductive contacts and other support structures, the support structure being located at a distance from the edge of the dielectric structure, wherein the ratio of the width of the support structure to the distance is in the range of 1.6 to 2.0. Other embodiments including additional devices and methods are described.

[0134] In the detailed description and claims, the term "on" and "on another" as used with respect to two or more elements (e.g., materials) indicate that there is at least some contact between the elements (e.g., between materials). The term "above" indicates that the elements (e.g., materials) are adjacent but may have one or more additional intervening elements (e.g., materials) such that contact is possible but not required. Neither "on" nor "above" implies any directionality as used herein unless stated otherwise.

[0135] In the detailed description and claims, the list of items connected by the term "at least one of..." can refer to any combination of the listed items. For example, if items A and B are listed, the phrase "at least one of A and B" means only A; only B; or A and B. In another instance, if items A, B, and C are listed, the phrase "at least one of A, B, and C" means only A; only B; only C; A and B (excluding C); A and C (excluding B); B and C (excluding A); or all A, B, and C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0136] In the detailed embodiments and claims, the list of items connected by the term "one of..." can refer to only one of the listed items. For example, if items A and B are listed, the phrase "one of A and B" means only A (excluding B) or only B (excluding A). In another instance, if items A, B, and C are listed, the phrase "one of A, B, and C" means only A; only B; or only C. Item A may contain a single element or multiple elements. Item B may contain a single element or multiple elements. Item C may contain a single element or multiple elements.

[0137] The foregoing description and accompanying drawings illustrate some embodiments of the subject matter of the invention to enable those skilled in the art to practice these embodiments. Other embodiments may include structural variations, logical variations, electrical variations, process variations, and other changes. The examples merely represent possible variations. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the foregoing description.

Claims

1. A memory device comprising: Substrate; The layers are stacked one on top of the other above the substrate. Each layer includes a corresponding memory cell and a plurality of control gates for the memory cell. The plurality of control gates includes a first control gate closest to the substrate and other control gates. The plurality of control gates includes corresponding portions that together form a stepped structure. A conductive contact is provided, wherein the conductive contact is in contact with the plurality of control gates at a position of the stepped structure, the conductive contact having different lengths extending vertically from the substrate, and the conductive contact including a conductive contact in contact with the first control gate; A dielectric structure adjacent to the sidewalls of the plurality of control gates of the layer; as well as A plurality of support structures are adjacent to the conductive contacts and electrically isolated from the plurality of control gates and the conductive contacts. The plurality of support structures have a length that extends vertically from the substrate and through at least a portion of the plurality of control gates. The plurality of support structures includes a first support structure that is closest to the conductive contacts and is not among the other support structures. The first support structure is located at a distance from the edge of the dielectric structure. The ratio of the width of the first support structure to the distance is in the range of 1.6 to 2.

0.

2. The memory device according to claim 1, wherein, The first support structure has a width ranging from 345 nanometers to 375 nanometers.

3. The memory device according to claim 1, wherein, The distance ranges from 190 nanometers to 203 nanometers.

4. The memory device according to claim 1, wherein, Each of the plurality of control gates has a thickness ranging from 30 nanometers to 35 nanometers.

5. The memory device of claim 4, further comprising dielectric material layers interleaved with the plurality of control gates, wherein the thickness of each of the dielectric material layers is in the range of 22 nanometers to 27 nanometers.

6. The memory device according to claim 1, wherein, The sidewalls of the plurality of control gates are first sidewalls, the dielectric structure is a first dielectric structure, the distance is a first distance, and the memory device further includes: A second dielectric structure is located on a second sidewall opposite to the first sidewall of the plurality of control gates; and The plurality of support structures includes a second support structure adjacent to the first support structure and the conductive contact. The second support structure is located at a second distance from the edge of the second dielectric structure, wherein the ratio of the width of the second support structure to the second distance is in the range of 1.6 to 2.

0.

7. A memory device comprising: Substrate; The layers are stacked one on top of the other above the substrate. Each layer includes a corresponding memory cell and a plurality of control gates for the memory cell. The plurality of control gates includes a first control gate closest to the substrate and other control gates. The plurality of control gates includes corresponding portions that together form a stepped structure. A conductive contact is provided, wherein the conductive contact is in contact with the plurality of control gates at a position of the stepped structure, the conductive contact having different lengths extending vertically from the substrate, and the conductive contact including a conductive contact in contact with the first control gate; as well as Multiple support structures are provided, the multiple support structures being adjacent to the conductive contact and electrically isolated from the multiple control gates and the conductive contact, the multiple support structures having a length that extends vertically from the substrate and extends through at least a portion of the multiple control gates, the multiple support structures including a first support structure closest to the conductive contact and other support structures, wherein the width of the first support structure is at least 345 nanometers.

8. The memory device according to claim 7, wherein, The width of the first support structure ranges from 345 nanometers to 375 nanometers.

9. The memory device according to claim 7, wherein, The lengths of the multiple support structures are the same.

10. The memory device of claim 7, wherein the width of the second support structure of the plurality of support structures is different from the width of the first support structure.

11. The memory device according to claim 7, wherein, Each of the plurality of control gates has a thickness ranging from 30 nanometers to 35 nanometers.

12. A memory device comprising: Substrate; The layers are stacked one on top of the other above the substrate. Each layer includes a corresponding memory cell and a plurality of control gates for the memory cell. The plurality of control gates includes a first control gate closest to the substrate and other control gates. The plurality of control gates includes corresponding portions that together form a stepped structure. A conductive contact is provided, wherein the conductive contact is in contact with the plurality of control gates at a position of the stepped structure, the conductive contact having different lengths extending vertically from the substrate, and the conductive contact including a conductive contact in contact with the first control gate; Multiple support structures are adjacent to the conductive contact and electrically isolated from the multiple control gates and the conductive contact. The multiple support structures have a length that extends vertically from the substrate and through at least a portion of the multiple control gates. The multiple support structures include a first support structure that is closest to the conductive contact and other support structures. as well as A dielectric structure adjacent to the sidewalls of the plurality of control gates, wherein the distance between the edge of the dielectric structure and the edge of the first support structure is less than 215 nanometers.

13. The memory device according to claim 12, wherein, The distance is greater than 190 nanometers.

14. The memory device according to claim 12, wherein, The first support structure has a width ranging from 345 nanometers to 375 nanometers.

15. The memory device of claim 12, wherein the first support structure has a first width, and the second support structure of the plurality of support structures has a second width greater than the first width.

16. The memory device according to claim 12, wherein, Each of the plurality of control gates has a thickness ranging from 30 nanometers to 35 nanometers.

17. The memory device according to claim 12, wherein, The sidewalls of the plurality of control gates are first sidewalls, the dielectric structure is a first dielectric structure, and the memory device further includes: A second dielectric structure is located on a second sidewall opposite to the first sidewall of the plurality of control gates; and The plurality of support structures include a second support structure adjacent to the first support structure and the conductive contact, wherein the distance between the edge of the second dielectric structure and the edge of the second support structure is less than 215 nanometers.

18. The memory device of claim 17, wherein, The edge of the first support structure is a first edge, the first support structure includes a second edge that is closest to the second support structure, and the distance between the second edge of the first dielectric structure and the edge of the second dielectric structure is less than 214 nanometers.

19. A method of forming a memory device, comprising: A stepped structure is formed above the substrate of the memory device, the stepped structure comprising a first stepped structure and a second stepped structure, wherein the first stepped structure is closest to the substrate relative to the second stepped structure. Conductive contacts are formed to contact the corresponding conductive material layers of the stepped structure. The conductive contacts have different lengths extending vertically from the substrate. The conductive contacts include conductive contacts that contact the conductive material layers in the conductive material layers. as well as Multiple support structures are formed, the multiple support structures being adjacent to the conductive contact and electrically isolated from the conductive material layer and the conductive contact, the multiple support structures having a length that extends vertically from the substrate and through at least a portion of the conductive material layer, the multiple support structures including a first support structure closest to the conductive contact and other support structures, wherein the width of the first support structure is at least 345 nanometers.

20. The method of claim 19, further comprising: A dielectric structure is formed adjacent to the sidewall of the conductive material layer, the dielectric structure comprising a slit and a dielectric material filling the slit, wherein the distance between the edge of the dielectric structure and the edge of the first support structure is less than 215 nanometers.

21. The method of claim 19, further comprising: A dielectric structure is formed adjacent to the sidewall of the conductive material layer, the dielectric structure comprising a slit and a dielectric material filling the slit, wherein the first support structure is located at a certain distance from the edge of the dielectric structure, and wherein the ratio of the width of the first support structure to the distance is in the range of 1.6 to 2.0.

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