Non-volatile memory devices and methods of operating the same

Abstract

The present application relates to a memory device and an operating method thereof, the memory device having a plurality of global word lines and a plurality of main gate switches, comprising: a cell array, the cell array including a plurality of memory blocks; and a row decoder, the row decoder including a plurality of groups of word line drivers corresponding to the plurality of memory blocks respectively, each group of word line drivers including a plurality of word line drivers, and a part of the plurality of word line drivers belonging to different groups sharing a part of the plurality of global word lines with each other.

Description

TECHNICAL FIELD

[0001] The present application relates to a non-volatile memory device and an operating method thereof, and more particularly, to a non-volatile memory device using a global word line and an operating method thereof. BACKGROUND

[0002] Non-volatile memory devices are widely used to store data in computer systems, and generally include a memory array having a large number of memory cells arranged in rows and columns. In such non-volatile memories, in order to program data in the memory cells in an initialized state and then change the data, a specified number of memory cells including selected memory cells can be reinitialized by an electrical erase operation, and then the selected memory cells can be reprogrammed with changed contents.

[0003] Generally, a unit of memory cells performing an electrical erase is called a block, and a unit of memory cells performing data recording or more specifically, programming is called a cell string. Here, the "cell string" refers to a group of memory cells connected to one word line, and one block includes a plurality of (e.g., 64 or 128) cell strings. In order to perform programming, reading, and erasing operations in a non-volatile memory device, a suitable bias voltage is applied to a selected word line for each operation. In the prior art, a global word line (GWL) can be used, specifically, a global word line is generated as a sample set of word lines provided in one block, a voltage for each operation is first applied to the global word line, and then transferred to the word lines in each block.

[0004] Figure 1 is a schematic diagram representing a conventional global word line distribution.

[0005] As shown in Figure 1 , a memory device includes a global word line GWL, an odd row decoder, an even row decoder, and a cell array. If the number of cell strings in each memory block included in the cell array is n, the number of global word lines GWL is also n (denoted as n GWLs in Figure 1 ). Voltages applied to the n global word lines GWL are transferred to each block through decoders (the even row decoder and the odd row decoder).

[0006] However, as the process technology shrinks, the number of cell strings increases, or the density of a single chip becomes larger. In these cases, the load of the metal line used for the global word line and the load at the connection and gate of the word line driver transistor can become larger. This results in a larger charge pump size.

[0007] In order to reduce such a load, a master gate switch is generally introduced in the conventional global word line distribution.

[0008] Figure 2 is a diagram showing a global word line distribution having a main gate switch. As shown in Figure 2 , let the number of global word lines be n, which is denoted as n GWLs in the figure. The n global word lines GWL are divided into two groups each of n global word lines by 2n main gate switches. Here, in order to distinguish the global word lines connected to the output terminals of the main gate switches from the global word lines connected to the input terminals of the main gate switches, the global word lines connected to the output terminals of the main gate switches are denoted as local global word lines, and are denoted as n local GWLs in Figure 2 . Then, the two groups each of n local global word lines are connected to each block through decoders (even row decoder and odd row decoder), respectively. By introducing 2n main gate switches, it is possible to turn off the global word lines related to the even row memory blocks when driving the odd row memory blocks, or to turn off the global word lines related to the odd row memory blocks when driving the even row memory blocks, thereby it is possible to reduce the core area capacitance load by about 50%.

[0009] However, in the case of adopting the structure shown in Figure 2 , since 2n main gate switches are introduced, it is necessary to increase the additional wiring area. Especially in the case of using a pump type high voltage switch, the wiring area for the 2n main gate switches will become very large.

[0010] Figure 3 is a diagram showing the architecture of a row decoder when using the global word line distribution shown in Figure 2 . As shown in FIG. 3, a cell array is provided to include a plurality of memory blocks BLK0, BLK1, BLK2, BLK3, ···, and each of the memory blocks includes a plurality of cell strings. The memory blocks are connected to a row decoder, and the row decoder includes a plurality of groups of a plurality of word line drivers corresponding to each of the memory blocks. The word line drivers corresponding to each of the memory blocks correspond one-to-one to the cell strings included therein, and thus the number of the word line drivers corresponding to each of the memory blocks is the same as the number of the cell strings included therein.

[0011] In the example shown in Figure 3 , for example, BLK0, BLK1, BLK2, BLK3 correspond to <0> to <n-1>The total of n word line drivers need a set of n local global word lines respectively. Among them, the even row memory blocks such as BLK0, BLK2, etc. are controlled by the left set of n local global word lines, and the odd row memory blocks such as BLK1, BLK3, etc. are controlled by the right set of n local global word lines.

[0012] In Figure 3 In the example shown, only four memory blocks BLK0, BLK1, BLK2, BLK3 and the corresponding word line drivers are shown. As shown by the ellipsis in Figure 3 More memory blocks are also included in the memory device.

[0013] However, with the continuous development of process technology, in some processes, the height of the cell array and the height of the decoder do not match. This occurs because the peripheral rules are fixed, but the rules of the cell array continue to shrink. Specifically, in order to ensure the normal operation of the product, the size rules of the devices other than the memory cells, i.e. the peripheral rules, are usually fixed and do not decrease with the optimization of the process. For example, the minimum length of PMOS is 380 nm regardless of the 19 nm process, the 24 nm process, or the 38 nm process. However, the size of the memory cells is continuously optimized and shrinks with the process.

[0014] Therefore, in this special case, it is inevitable to use multiple sets of global word lines.

[0015] Figure 4 is a schematic diagram showing the architecture of the row decoder in the special case. That is, Figure 4 The architecture of the row decoder when the height of the cell array and the height of the decoder do not match is shown.

[0016] The following describes the Figure 4 The special case shown in

[0017] The same point as shown in Figure 3 The same point as shown in Figure 4 The cell array shown in also includes a plurality of memory blocks BLK0, BLK1, BLK2, BLK3, etc., and the number of cell strings in each memory block is n, which corresponds to <0> to <n-1>n word line drivers in total.

[0018] But Figure 4 The difference between the structure shown in Figure 3 and the structure shown in

[0019] Specifically, in the example of the general case shown in Figure 3 , n word line drivers corresponding to memory block BLK0 are arranged in a row, the height of which corresponds to the height of two memory blocks, and n word line drivers corresponding to memory block BLK2 are arranged in a row, the height of which also corresponds to the height of two memory blocks.

[0020] In contrast, in the example of the special case shown in Figure 4 , with the continuous development of process technology, n word line drivers corresponding to memory block BLK0 are arranged in two rows, and n word line drivers corresponding to memory block BLK2 are also arranged in two rows, the total height of which corresponds to the height of four memory blocks.

[0021] If the addresses of the n word line drivers are simply set without consideration as shown in Figure 4 , two groups of n local global word lines (denoted as n local GWLs) are needed on the left and right sides of the cell array. For ease of illustration, the two groups of n local global word lines are denoted as Group A and Group B, respectively. In addition, in Figure 4 , the main gate switch is omitted, and only the local global word lines connected to the output end of the main gate switch are shown.

[0022] Specifically, for the left side of the cell array (even row decoders), if memory block BLK0 is to be driven, n local global word lines of Group A need to be used; if memory block BLK2 is to be driven, n local global word lines of Group B need to be used.

[0023] Similarly, for the right side of the cell array (odd row decoders), if memory block BLK1 is to be driven, n local global word lines of Group A need to be used; if memory block BLK3 is to be driven, n local global word lines of Group B need to be used.

[0024] In addition, the number of main gate switches corresponds to the number of local global word lines one-to-one, although not shown, in the structure of FIG. 4, two groups of n main gate switches are needed on the left and right sides of the cell array, a total of 2n main gate switches.

[0025] That is, compared with the architecture shown in Figure 3 , in the architecture shown in Figure 4 , one more times of global word lines need to be used and one more times of main gate switches need to be used for control.

[0026] Next, the control logic of the main gate switches to be used under the architecture shown in Figure 4

[0027] Figure 5 is a control logic diagram of the main gate switches to be used under the architecture shown in Figure 4 As can be seen from the above, under the architecture shown in Figure 4 Figure 3 Under the architecture shown in Figure 5 In the example of

[0028] The IN terminal of each main gate switch inputs the n global word line (denoted as GWL <n-1:0>), in the case that an enable signal En_GWL_Group_A or En_GWL_Group_B is input at the EN terminal, indicates the n global word line selected from group A or group B, respectively, thereby causing the n local global word line (GWL_Group_A <n-1:0>) or n local global word lines (GWL_Group_B <n-1:0>Action.

[0029] By Figure 4 to Figure 5 It is known that in this special case, the number of main gate switches used is doubled, and the number of global word lines is also increased accordingly, resulting in increased interconnection complexity and wiring difficulty. In particular, as the size of the cell string in each memory block increases (32, 64, 128, ···), the complexity will eventually increase exponentially. SUMMARY

[0030] To solve the above problems, the present application provides a non-volatile memory device using global word lines and an operating method thereof, by adjusting the positions of the word line drivers in the row decoder to share part of the global word lines, thereby reducing the number of global word lines and main gate switches, greatly reducing the complexity of wiring and making wiring easier.

[0031] The first aspect of the present application relates to a memory device having a plurality of global word lines and a plurality of main gate switches, characterized by comprising:

[0032] a cell array including a plurality of memory blocks; and

[0033] a row decoder including a plurality of groups of word line drivers corresponding to the plurality of memory blocks, respectively,

[0034] each group of word line drivers of the plurality of groups of word line drivers including a plurality of word line drivers,

[0035] a part of the plurality of word line drivers belonging to different groups share a part of the plurality of global word lines, i.e., shared global word lines.

[0036] In the memory device of the second aspect of the present application, in the first aspect of the present application, among the plurality of groups of word line drivers, the remaining part of the plurality of word line drivers belonging to different groups independently use the remaining part of the plurality of global word lines, i.e., independent global word lines.

[0037] In the memory device of the third aspect of the present application, in the first aspect or the second aspect of the present application, the cell array includes at least a first memory block, a second memory block,

[0038] the plurality of groups of word line drivers includes at least a first group of word line drivers, a second group of word line drivers,

[0039] the first memory block corresponds to the first group of word line drivers, and the second memory block corresponds to the second group of word line drivers,

[0040] The address arrangement of the plurality of word line drivers in the first group of word line drivers matches the address arrangement of the plurality of word line drivers in the second group of word line drivers.

[0041] In the memory device of the fourth aspect of the present application,

[0042] A portion of the first group of word line drivers uses the independent global word line for the first group of word line drivers, a portion of the second group of word line drivers uses the independent global word line for the second group of word line drivers, and the remaining portion of the first group of word line drivers and the remaining portion of the second group of word line drivers use the shared global word line.

[0043] In the memory device of the fifth aspect of the present application, in the first aspect or the second aspect of the present application, the memory block includes a plurality of cell strings, and the total number of the plurality of global word lines is less than the number of the cell strings.

[0044] In the memory device of the sixth aspect of the present application, in the first aspect or the second aspect of the present application, the memory block includes a plurality of cell strings, and the total number of the plurality of main gate switches is less than the number of the cell strings.

[0045] In the memory device of the seventh aspect of the present application, in the third aspect of the present application, when either the first memory block or the second memory block is enabled, the shared global word line shared by the first memory block and the second memory block is always on.

[0046] The eighth aspect of the present application relates to a method for operating a memory device, the method for operating a memory device comprising:

[0047] a cell array including a plurality of memory blocks; and

[0048] a row decoder including a plurality of groups of word line drivers corresponding to the plurality of memory blocks, respectively,

[0049] The method for operating the memory device is characterized in that,

[0050] in a case where each of the plurality of groups of word line drivers includes a plurality of word line drivers,

[0051] a portion of the plurality of word line drivers belonging to different groups share a portion of the plurality of global word lines, i.e., shared global word lines.

[0052] In the operation method of the memory device according to the ninth aspect of the present application, in the eighth aspect of the present application, the remaining portions of the plurality of word line drivers belonging to different groups are independently used with the remaining portions of the global word lines, i.e., independent global word lines.

[0053] In the operation method of the memory device according to the tenth aspect of the present application, in the eighth aspect of the present application, the cell array includes at least a first memory block and a second memory block, and the shared global word line shared by the first memory block and the second memory block is always on when either the first memory block or the second memory block is enabled. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a schematic diagram showing a conventional global word line architecture.

[0055] Figure 2 is a schematic diagram showing a global word line architecture with a master gate.

[0056] Figure 3 is a schematic diagram showing a row decoder architecture when using Figure 2 the global word line shown in

[0057] Figure 4 is a schematic diagram showing a row decoder architecture in a special case.

[0058] Figure 5 is a control logic diagram showing a master gate used under the architecture shown in Figure 4

[0059] Figure 6 is a schematic diagram showing a row decoder architecture in the memory device according to the first embodiment of the present application.

[0060] Figure 7 is a control logic diagram showing a master gate used under the architecture according to the first embodiment of the present application. DETAILED DESCRIPTION

[0061] The present application will now be described in greater detail by reference to specific embodiments thereof. The flow diagrams and block diagrams in the drawings show the architectural, functional and operational aspects of systems, methods according to embodiments of the present application. The drawings are for purposes of illustrating the preferred embodiments and are not intended to limit the present application. Further, in the drawings, the same reference numerals are used for the same components.

[0062] ​Furthermore, the various advantages and benefits of the present invention will become clear to those skilled in the art upon reading the detailed description of the specific embodiments described below. However, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. The following embodiments are provided to enable a more thorough understanding of the invention. Unless otherwise stated, the technical or scientific terms used in this invention should be understood in their ordinary sense by those skilled in the art.

[0063] Implementation Method 1

[0064] The memory device described in Implementation 1 uses multiple global word lines and multiple master gate switches.

[0065] Figure 6 This is a schematic diagram illustrating the row decoder architecture in the memory device according to Embodiment 1 of the present invention. Figure 6 The diagram only shows the architecture of the even-row decoders located on the left side of the cell array; the odd-row decoders on the right side use the same architecture. Furthermore, Figure 6 The main gate switch used in this architecture is omitted, but the main gate switch used is the same as that in existing technologies, corresponding one-to-one with each local global word line.

[0066] like Figure 6 As shown, the memory device involved in Embodiment 1 includes a cell array 101 and a row decoder 102. The cell array 101 includes multiple memory blocks BLK0, BLK1, BLK2, BLK3, etc. The number of memory blocks is not limited to four and can be more than four. The number of cell strings in each memory block is set to n, so the number of word line drivers corresponding to each memory block is also n.

[0067] With the above Figure 4 Similar to the special case shown, the row decoder 102 includes multiple sets of word line drivers corresponding to multiple memory blocks. The n word line drivers corresponding to memory block BLK0 are arranged in two rows, and the n word line drivers corresponding to memory block BLK2 are also arranged in two rows. The total height of both corresponds to the height of the four memory blocks.

[0068] Specifically, corresponding to memory block BLK0 <0> to <n-1>A word line driver is arranged in the first and second rows, corresponding to <0> to <7> of the memory block BLK2 <n-1>The word line drivers arranged in the first row and the second row.

[0069] In this embodiment 1, there are three sets of local global word lines used by the row decoder 102, denoted as GWL_A, GWL_B, and GWL_CM, respectively.

[0070] The partial word line drivers arranged in the first row corresponding to the memory block BLK0 use the local global word lines GWL_A and GWL_CM, and the remaining word line drivers arranged in the second row corresponding to the memory block BLK0 use the local global word line GWL_CM.

[0071] In Figure 6 In the example shown, in the word line drivers corresponding to the memory block BLK0, the <0> to <x-1>one word line driver uses a local global word line GWL_A, <x>To <y>One word line driver uses the local global word line GWL CM, arranged in the second row of <y+1> to <n-1>The individual word line driver uses the local global word line GWL_CM.

[0072] Similarly, the word line drivers in the second row corresponding to memory block BLK2 use the local global word line GWL_CM, and the remaining word line drivers in the third row corresponding to memory block BLK2 use the local global word lines GWL_CM and GWL_B.

[0073] exist Figure 6 In the example shown, in the word line driver corresponding to memory block BLK2, the third row is arranged... <0> to <x-1>One word line driver uses the local global word line GWL_B, <y+1> to <n-1>One word line driver uses the local global word line GWL CM, arranged in the second row of <x>To <y>One word line driver uses local global word line GWL_CM.

[0074] If the number of three groups of global word lines GWL_A, GWL_B and GWL_CM are counted, then (GWL_A+GWL_B+GWL_CM)=2x+n-x=n+x<2n. The specific values of x and y can be flexibly set according to actual process requirements.

[0075] That is, by arranging the addresses of the plurality of word line drivers included in the plurality of groups of word line drivers corresponding to the plurality of memory blocks, so that part of the plurality of word line drivers belonging to different groups share part of the plurality of global word lines with each other, and then the number of global word lines used in total is greatly reduced. In the case of greatly reducing the number of global word lines used in total, the number of main gate switches used is also greatly reduced accordingly.

[0076] Figure 7 is a control logic diagram of the main gate switch used under the architecture involved in Embodiment 1 of the present application.

[0077] In the example of Figure 7 , the control logic diagrams of the main gate switches used under the architecture shown in Figure 6 are shown. The main gate switch HVSW_A is a switch for selecting the global word line GWL_A, the main gate switch HVSW_B is a switch for selecting the global word line GWL_B, and the main gate switch HVSW_CM is a switch for selecting the global word line GWL_CM.

[0078] The IN terminal of each main gate switch HVSW_A and HVSW_B inputs the global word line (denoted as GWL <x-1:0>), in the case of inputting an enable signal EN_GWL_A or EN_GWL_B at the EN terminal, indicates that the global word line GWL_A or GWL_B is selected, respectively, so that the global word line GWL_A (GWL_A <x-1:0>) or global word line GWL_B (GWL_B <x-1:0>) Action.

[0079] The IN terminal of the common portion main door switch HVSW CM inputs a global word line (denoted as GWL <n-1:x>), in the case that an enable signal EN_GWL_CM is input to the EN terminal, indicates that the global word line GWL_CM is selected, so that the global word line GWL_CM (GWL_CM <n-1:x>Action.

[0080] By using the above architecture, the number of global word lines used is greatly reduced, and accordingly, the number and area of total main gate switches used are greatly reduced. Thus, the layout is easier, and the parasitic capacitance between interconnection lines is reduced, and the size of the pump used is smaller.

[0081] If each memory block contains 64 cell strings, according to the architecture of Embodiment 1, the total number of global word lines and main gate switches used is about 65% of the architecture shown in Figure 4 Figure 4 This means that in the case where the height of the memory cell and the height of the decoder do not match, if the architecture of Embodiment 1 of the present application is adopted, the total number of global word lines and main gate switches used can be reduced by about 35%.

[0082] Embodiment 2

[0083] In Embodiment 2, the operation method of the memory device using the architecture of Embodiment 1 described above is described. In the following description, reference is made to Figure 6 and Figure 7 The operation method of the memory device is described in detail.

[0084] In the operation method of the memory device shown in Embodiment 2, the portion of the global word line that is common, GWL_CM, is always on, and only one of the global word lines used, for example, GLW_A and GWL_B, is on according to the address of the memory block.

[0085] Specifically, if the memory block BLK0 is enabled, the following settings are made:

[0086] EN_GWL_A = 1;

[0087] EN_GWL_B = 0;

[0088] EN_GWL_CM = 1.

[0089] At this time, the global word lines GWL_CM and GWL_A are used.

[0090] If the memory block BLK2 is enabled, the following settings are made:

[0091] EN_GWL_A = 0

[0092] EN_GWL_B = 1

[0093] EN_GWL_CM = 1

[0094] At this time, the global word lines GWL_CM and GWL_B are used.​

[0095] If none of the memory blocks on the left side are enabled (even memory blocks on the left side) and one of the memory blocks on the right side (odd memory blocks on the right side not shown) is enabled (e.g., memory block BLK1 or BLK3, etc.), the following settings are made: Figure 6 Figure 6 EN_GWL_A = 0

[0096] EN_GWL_B = 0

[0097] EN_GWL_CM = 0

[0098] The above only shows the settings made when the right side, i.e., even memory blocks, are enabled or not enabled. For the case when the right side, i.e., odd memory blocks not shown, are enabled or not enabled, the corresponding settings are made with reference to the above settings.

[0099] The above only shows the settings made when the right side, i.e., even memory blocks, are enabled or not enabled. For the case when the right side, i.e., odd memory blocks not shown, are enabled or not enabled, the corresponding settings are made with reference to the above settings. Figure 6 Figure 6 The above only shows the settings made when the right side, i.e., even memory blocks, are enabled or not enabled. For the case when the right side, i.e., odd memory blocks not shown, are enabled or not enabled, the corresponding settings are made with reference to the above settings.

[0100] By operating the memory device in the above manner, the load on the metal lines used for the global word lines and the connections and gates of the word line driver transistors can be greatly reduced, and the size of the charge pump can be greatly reduced.

[0101] Reference Signs List

[0102] 101 cell array

[0103] 102 row decoder​​ < / y> < / x> < / y> < / x> ​​

Claims

1. A memory device comprising multiple global word lines and multiple master gate switches, characterized in that, include: A cell array, wherein the cell array comprises multiple memory blocks; as well as A row decoder, comprising multiple sets of word line drivers corresponding to the plurality of memory blocks respectively. Each of the multiple sets of word line drivers contains multiple word line drivers. A subset of the multiple word line drivers belonging to different groups may share a portion of multiple global word lines, and this shared portion of the multiple global word lines is designated as a shared global word line. The plurality of word line drivers include at least a first word line driver group and a second word line driver group, wherein the addresses of the plurality of word line drivers in the first word line driver group and the plurality of word line drivers in the second word line driver group are arranged to match each other.

2. The memory device as claimed in claim 1, characterized in that, In the multiple word line drivers, the remaining portions of the multiple word line drivers belonging to different groups independently use the remaining portions of the multiple global word lines, and the remaining portions of the multiple global word lines used independently are used as independent global word lines.

3. The memory device as claimed in claim 1 or 2, characterized in that, The cell array includes at least a first memory block and a second memory block. The first memory block corresponds to the first word line driver group, and the second memory block corresponds to the second word line driver group.

4. The memory device as claimed in claim 2, characterized in that, A portion of the first word line driver group uses the independent global word line for the first word line driver group. A portion of the second word line driver group uses the independent global word line for the second word line driver group. The remainder of the first word line driver group and the remainder of the second word line driver group use the shared global word line.

5. The memory device as claimed in claim 1 or 2, characterized in that, The memory block contains multiple cell strings. The total number of the global word lines is less than the number of the unit strings.

6. The memory device as claimed in claim 1 or 2, characterized in that, The memory block contains multiple cell strings. The total number of the multiple main door switches is less than the number of the unit strings.

7. The memory device as claimed in claim 3, characterized in that, When either the first memory block or the second memory block is enabled, the shared global word line shared by the first memory block and the second memory block is always enabled.

8. A method of operating a memory device, comprising: A cell array, wherein the cell array comprises multiple memory blocks; as well as A row decoder, comprising multiple sets of word line drivers corresponding to the plurality of memory blocks respectively. The method of operating the memory device is characterized in that... In the case where each of the multiple sets of word line drivers contains multiple word line drivers. A subset of the multiple word line drivers belonging to different groups may share a portion of multiple global word lines, and this shared portion of the multiple global word lines is designated as a shared global word line. The plurality of word line drivers include at least a first word line driver group and a second word line driver group, wherein the addresses of the plurality of word line drivers in the first word line driver group and the plurality of word line drivers in the second word line driver group are arranged to match each other.

9. The method of operating the memory device as claimed in claim 8, characterized in that, The remaining portions of the multiple word line drivers belonging to different groups are used independently of each other, and the remaining portions of the multiple global word lines used independently are treated as independent global word lines.

10. The method of operating the memory device as claimed in claim 8, characterized in that, The cell array includes at least a first memory block and a second memory block. When either the first memory block or the second memory block is enabled, the shared global word line shared by the first memory block and the second memory block is always enabled.

Images