A ferroelectric field effect transistor based on a two-dimensional material heterojunction and a manufacturing method thereof

Abstract

A manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction. This method utilizes the combined action of a two-dimensional ferroelectric material and deionized water. By applying a gate voltage, the two-dimensional ferroelectric material and deionized water jointly generate polarization, enhancing the polarization effect. The combined action acts on the conductive channel, and the electron doping concentration of the channel is regulated through different polarization directions, thereby changing the resistance value of the channel layer. This enables the ferroelectric field effect transistor to achieve two states of 'on' and 'off', corresponding to the low-resistance state and high-resistance state of the device. Due to the addition of deionized water, the polarization effect is greatly enhanced, and the resistivity of the device is significantly improved.

Description

Technical Field

[0001] The present invention belongs to the field of electronic memory, and specifically relates to a ferroelectric field effect transistor based on a two-dimensional material heterojunction and a manufacturing method thereof. Background Art

[0002] Because ferroelectric materials have unique spontaneous polarization properties, and the direction of polarization can be changed by changing the external electric field, such as Figure 7 As shown in the figure, In2Se3 has two polarization directions and has good non-volatile properties. Ferroelectric field effect transistors are new devices with great potential in the field of non-volatile memory. However, due to the size effect of ferroelectric materials and the constraints of polarization size, the regulation performance needs to be improved.

[0003] Since the discovery of 2D graphene, 2D layered materials have become an attractive platform for exploring the extraordinary properties of low-dimensional materials and physics. Their various electronic and optoelectronic properties and atomically thin flatness make them important candidates for next-generation devices. Not just satisfied with single-structure 2D materials, the exploration of 2D van der Waals (vdW) heterostructures is a key element for the success of advanced electronics and optoelectronics.

[0004] At present, the transfer method of two-dimensional material heterojunction in the production process of ferroelectric field effect transistors is mostly pure dry transfer. This transfer method needs to ensure that the thin film produced by mechanical peeling is not exposed to water as much as possible, and to ensure that the film is clean and free of impurities. However, the contrast between PDMS and the sample is relatively low, and some thin layer samples are difficult to be detected. The sample thickness is difficult to reach the two-dimensional limit, so there is a large limitation on the room for improving device performance. Summary of the invention

[0005] Traditionally, when preparing a two-dimensional material heterojunction, people always pursue a clean interface, believing that a clean interface can always improve the performance of the device. The content of the present invention is the discovery of a new preparation method, in which the performance of the device is greatly improved when the interface of the heterojunction contains deionized water.

[0006] The present invention utilizes the joint action of ferroelectric material and deionized water, and by applying gate voltage, the ferroelectric material and deionized water are polarized together, so that the polarization effect is enhanced, and they act together on the conductive channel, and the electron doping concentration of the channel is regulated by different polarization directions, thereby changing the resistance of the channel layer, so that the ferroelectric field effect transistor can realize two states of "on" and "off", corresponding to the low resistance state and high resistance state of the device. Due to the addition of deionized water, the polarization effect is greatly enhanced, and the resistivity of the device is also greatly improved.

[0007] In order to achieve the above object, the technical solution of the present invention is:

[0008] A manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction, comprising the following steps:

[0009] Step S1: Fabricate a two-dimensional graphene sheet on a clean substrate by mechanical exfoliation;

[0010] Step S2: Fabricate a two-dimensional In2Se3 sheet on a clean substrate by mechanical exfoliation;

[0011] Step S3: Use a polymer polyvinyl alcohol (PVA) film to pick up the two-dimensional graphene sheet; Press the PVA and the two-dimensional graphene sheet together on the marked substrate; Then soak in deionized water for a period of time to remove the PVA while only retaining the two-dimensional graphene sheet and the entire graphene sheet is soaked in deionized water to form a two-dimensional graphene sheet / substrate composite layer;

[0012] Step S4: Use the PVA film to pick up the two-dimensional In2Se3 sheet, press the PVA and the two-dimensional In2Se3 sheet together on the two-dimensional graphene sheet / substrate composite layer processed in Step S3, and then soak in deionized water to remove the PVA to form a graphene and In2Se3 heterojunction. The interface of the obtained heterojunction is soaked in deionized water instead of a clean and dry interface in the traditional sense to form a heterojunction / substrate composite layer.

[0013] Step S5: Fabricate a patterned metal electrode on the heterojunction / substrate composite layer formed in Step S4.

[0014] Further, in order to improve the film pressing effect, the polymer polyvinyl alcohol (PVA) film is attached to a glass slide coated with polydimethylsiloxane (PDMS);

[0015] The substrate is preferably a silicon wafer, specifically composed of a SiO2 oxide layer and a Si layer, hereinafter referred to as SiO2 / Si.

[0016] Further, the total thickness of the silicon wafer is 500 ± 15 μm, and the thickness of the SiO2 oxide layer is 285 nm.

[0017] Further, the PVA film is a solution obtained by stirring polymer polyvinyl alcohol powder and deionized water on a magnetic stirrer, and a small amount is taken on a glass slide and heated into a film.

[0018] Further, in Steps S3 and S4, the step of soaking in deionized water to remove the PVA is specifically: Soak the sample in deionized water for about 1.5 h until the PVA is completely dissolved;

[0019] Further, the structure of the two-dimensional material In2Se3 is as Figure 7As shown, the structure of the two-dimensional material graphene is as Figure 8 shown.

[0020] Advantageous effects:

[0021] First, the device manufacturing method disclosed in the present invention breaks the traditional operation requirements and methods for the dryness and cleanliness of the heterojunction interface in the preparation process of two-dimensional material heterojunctions. During the manufacturing process, the device can be manufactured without drying the heterojunction material, greatly reducing the difficulty of the entire manufacturing process and the manufacturing cost. By first peeling the sample on a silicon wafer to find a thin layer and then performing wet transfer, and going through two transfers during the preparation of the heterojunction, the success rate is improved. At the same time, the deionized water impurity removal function during the mechanical peeling process is cleverly utilized to generate a co-polarization effect with the ferroelectric material, increasing the polarization effect. The manufactured device has a higher resistivity compared to the device with a dry heterojunction interface. Description of the drawings

[0022] Figure 1 Schematic diagram of the structure of the devices described in Example 1 and Comparative Example 1;

[0023] Figure 2a Schematic diagram of the process of step S3.1 in the manufacture of the device according to Example 1 of the present invention;

[0024] Figure 2b Schematic diagram of the process of step S3.2 in the manufacture of the device according to Example 1 of the present invention;

[0025] Figure 2c Schematic diagram of the process of step S3.3 in the manufacture of the device according to Example 1 of the present invention;

[0026] Figure 2d Schematic diagram of the process of step S3.4 in the manufacture of the device according to Example 1 of the present invention;

[0027] Figure 2e Schematic diagram of the process of step S3.5 in the manufacture of the device according to Example 1 of the present invention;

[0028] Figure 2f Schematic diagram of the structure after the completion of step S3.5 in the manufacture of the device according to Example 1 of the present invention;

[0029] Figure 3 Photo of the device manufactured in Example 1 of the present invention under an optical microscope;

[0030] Figure 4 I-V curve of the intrinsic graphene in the present invention;

[0031] Figure 5 Gate voltage regulation curve of the device manufactured in Example 1 of the present invention;

[0032] Figure 6Gate voltage regulation curve of the device fabricated in Comparative Example 1 of the present invention;

[0033] Figure 7 Schematic diagrams of two atomic structures of In2Se3 with upward and downward polarization according to the present invention;

[0034] Figure 8 Atomic structure of two-dimensional graphene according to the present invention.

[0035] Among them, 1 - silicon wafer substrate, 2 - PDMS, 3 - PVA film, 4 - labeled silicon wafer substrate, 5 - glass slide, 6 - graphene flake, 7 - In2Se3 flake, 8 - experimental dish filled with deionized water, 9 - graphene / In2Se3 heterojunction. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. For those conditions not specified in the embodiments, they shall be carried out according to conventional conditions or the conditions recommended by the manufacturer. For the reagents or instruments not specified for the manufacturer, they are all conventional products that can be purchased commercially.

[0037] Embodiment 1

[0038] Step S1: Preliminary preparation work.

[0039] Prepare a clean SiO2 / Si (silicon wafer) with a total silicon wafer thickness of 500 ± 15 μm and an oxide layer thickness of 285 nm; place the cut SiO2 / Si (silicon wafer) substrate in acetone, ethanol, and deionized water in sequence, and clean it in an ultrasonic cleaner for 2 minutes with an ultrasonic power of 99 W, and dry it with a nitrogen gun. Acetone is used to wash off grease debris and other contaminants on the silicon wafer, ethanol is used to remove residual acetone, and deionized water is used to remove residual ethanol.

[0040] Prepare graphene bulk and In2Se3 bulk. In2Se3 is a-In2Se3 with a 2H structure.

[0041] Step S2: Prepare two-dimensional material thin layers.

[0042] Obtain graphene flakes 6 on the SiO2 / Si silicon wafer substrate 1 by tape mechanical exfoliation method, and obtain In2Se3 flakes 7 on the SiO2 / Si silicon wafer substrate 1 by tape mechanical exfoliation method;

[0043] Step S3: Prepare two-dimensional material heterojunctions on the two-dimensional material transfer platform

[0044] Step S3.1, as Figure 2a shown, use the PVA film 3 to pick up the graphene flakes 6;

[0045] Step S3.2, as Figure 2b shown, press the PVA film 3 and the graphene flakes 6 together onto the marked substrate 4;

[0046] Step S3.3, as Figure 2c shown, place it in the experimental dish 8 filled with deionized water, soak the pressed material in deionized water for 1.5 h until the PVA film 3 is completely dissolved, leaving the graphene flakes 6. This step is crucial, and at this time, the entire graphene flakes have been soaked in deionized water.

[0047] Step S3.4, adopt the same method as Figure 2a shown, use the PVA film 3 to pick up the In2Se3 flakes 7, and as Figure 2d shown, press the PVA film 3 and the In2Se3 flakes 7 together onto the graphene 6;

[0048] Step S3.5, as Figure 2e shown, then soak it in deionized water for 1.5 h until the PVA film 3 is completely dissolved, and as Figure 2f shown, the graphene / In2Se3 heterojunction 9 is prepared. The interface of the heterojunction 9 is soaked in deionized water, rather than a clean and dry interface in the traditional sense.

[0049] Step S4: Fabricate metal electrodes.

[0050] Adsorb the silicon wafer with the heterojunction on the spin coater, spin two layers of glue. First, use a disposable dropper to drop the methyl methacrylate (MMA) EL6 glue on the silicon wafer, set it to rotate on the spin coater at 4000 r / min for 45 s, and then bake it on the heating table. The temperature of the heating table is 120 °C and dry it for 2 min; then drop the polymethyl methacrylate (PMMA) A5 electron beam lithography glue. This time, the spin coating is set at two rates. First, set it to rotate at 4500 r / min for 30 s, then set it to rotate at 7000 r / min for 5 s, and then bake it on the heating table after finishing. Use the DrawBeam software to draw the top electrode design pattern, and then use the electron beam in the electron beam cavity of the electron-beam lithography (EBL) system. Reduce the vacuum in the cavity to below the order of 10 -6 Pa; after the exposure is completed, develop and fix it. The development time in acetone is 25 s, and the fixing time in isopropyl alcohol is 10 s.

[0051] Place the silicon wafer prepared in the previous step in the electron beam cavity of an electron-beam evaporation (EBE) system, and evacuate the cavity to a vacuum level below 10 -6 Pa. First, use EBE to evaporate metallic titanium (Ti) as an adhesion layer with an evaporation thickness of 10 nm, and then evaporate gold (Au) with an evaporation thickness of 30 nm. The evaporation rate of Ti is The evaporation rate of Au is The purpose of making the adhesion layer is that the adhesion between gold and the silicon wafer is insufficient and it is likely to fall off during subsequent operations. Immerse it in acetone for a peeling operation to obtain a sample with metal electrodes, that is, the target device is obtained.

[0052] Among them, the above-mentioned PVA film is a solution obtained by stirring 1 g of polymer polyvinyl alcohol powder and 12.5 ml of deionized water on a magnetic stirrer. Take a small amount and heat it into a film on a glass slide.

[0053] Comparative Example 1

[0054] The difference between Comparative Example 1 and Example 1 is only that: in steps S3 and S4, first pick up the In2Se3 film with PVA, then pick up graphene with the same piece of PVA to stack In2Se3 and graphene up and down, and then press them together on a marked substrate. Put the substrate into deionized water to soak and remove PVA. In this example, the heterojunction sample is picked up once, and the junction is dried without being soaked.

[0055] Figure 1 FIG. is a schematic structural diagram of the devices described in Example 1 and Comparative Example 1, where a, b, c, d, e are metal electrodes, where a, b are current terminals, c, d are voltage terminals, and e is a gate voltage terminal.

[0056] Figure 3 Shown is a photograph of the device fabricated in Example 1 under an optical microscope, and the scale bar is 5 microns.

[0057] Figure 4 The intrinsic resistance of graphene is approximately 1100 Ω.

[0058] Test process and results

[0059] To verify the effect, in the technical solution disclosed in the embodiments of the present application, the ferroelectric thin film transistor was also specifically tested, such as Figure 5 FIG. is the gate voltage regulation curve of the device in the present invention. The regulation process is specifically as follows: Apply a variable gate voltage to the metal electrode e: 0 - Vmax — Vmax - Vmax (Vmax is as Figure 5 ), and then apply a constant voltage to the cd voltage terminal, and obtain the change curve of the resistance measured at the ab current terminal; Figure 6For the device dried at the interface of the graphene / In2Se3 heterojunction fabricated in Comparative Example 1 using traditional methods, the gate voltage regulation curve was measured using the same testing method.

[0060] By comparing the two sets of data, as Figure 5 shown, under the combined action of In2Se3 and deionized water, the resistivity of the graphene conductive channel is much higher than that of the device with only the individual action of In2Se3 as Figure 6 shown, and Figure 5 as shown in the regulation, with the change of the polarization magnitude, the graphene realizes the transition from P-type to N-type.

[0061] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction, characterized in that, The manufacturing method includes: Step S1: Fabricate two-dimensional graphene flakes on a clean substrate using the mechanical exfoliation method; Step S2: Fabricate two-dimensional In2Se3 flakes on a clean substrate using the mechanical exfoliation method; Step S3: Use a polymer polyvinyl alcohol (PVA) film to pick up the two-dimensional graphene flakes; press the PVA and the two-dimensional graphene flakes together on the substrate at the marked position; then soak in deionized water for a period of time to remove the PVA while only retaining the two-dimensional graphene flakes and the entire graphene flake is soaked in deionized water to fabricate a two-dimensional graphene flake / substrate composite layer; Step S4: Use the PVA film to pick up the two-dimensional In2Se3 flakes, press the PVA and the two-dimensional In2Se3 flakes together on the two-dimensional graphene flake / substrate composite layer processed in Step S3, and then soak in deionized water to remove the PVA to fabricate a graphene and In2Se3 heterojunction; Step S5: Fabricate a patterned metal electrode on the heterojunction / substrate composite layer fabricated in Step S4.

2. The manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction according to claim 1, characterized in that The polymer polyvinyl alcohol (PVA) film is attached to a glass slide coated with polydimethylsiloxane (PDMS).

3. The manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction according to claim 1, characterized in that, The substrate is a silicon wafer.

4. The manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction according to claim 3, characterized in that, The substrate is composed of a SiO2 oxide layer and a Si layer.

5. The manufacturing method of a ferroelectric field-effect transistor based on a two-dimensional material heterojunction according to claim 3, wherein The total thickness of the silicon wafer is 500 ± 15 μm, and among them, the thickness of the SiO2 oxide layer is 285 nm.

6. The manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction according to claim 1, characterized in that, The PVA film is a film formed by heating a small amount of the solution obtained by stirring polymer polyvinyl alcohol powder and deionized water on a magnetic stirrer on a glass slide.

7. The manufacturing method of a ferroelectric field effect transistor based on a two-dimensional material heterojunction as described in claim 1, characterized in that, In Step S4, the step of soaking in deionized water to remove the PVA is specifically: soak the sample in deionized water for about 1.5 h until the PVA is completely dissolved.

8. A ferroelectric field effect transistor based on a two-dimensional material heterojunction fabricated by the manufacturing method according to any one of claims 1-7.

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