Epitaxial control method of slip lines under ultra-high temperature condition for BCD process

Abstract

The application discloses an epitaxial control method of slip lines under ultrahigh temperature for a BCD process, which comprises the following steps: (1) preparing a temperature control wafer; (2) heating a reaction cavity and performing HCL cleaning; (3) cooling to room temperature, and loading the temperature control wafer; (4) baking at a constant heating rate to 1150-1200 DEG C; (5) taking out the temperature control wafer for chemical treatment; (6) testing the resistivity of the temperature control wafer, obtaining the temperature of each region of the temperature control wafer, and performing temperature compensation; (7) cleaning a silicon wafer to be epitaxied, and repeating the operation of step (2), then placing the silicon wafer to be epitaxied into the reaction cavity; heating to a preset baking temperature at the heating rate in step (4) and simultaneously performing the temperature compensation in step (6), and baking; adjusting the temperature of the reaction cavity to a growth temperature, inputting SiHCl3 and H2, and doping, and epitaxially growing to a target thickness and a target resistivity. The application can effectively control the temperature distribution of the surface of the silicon wafer in the epitaxial process, and better control the generation of slip lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of silicon epitaxial control method, and in particular to an epitaxial control method of slip line under ultra-high temperature condition for BCD process. BACKGROUND

[0002] BCD (Bipolar CMOS DMOS) process is a process technology integrating bipolar transistor, CMOS and DMOS device. After a plurality of high temperature, implantation, lithography and other process procedures in the BCD process flow, a large number of endogenous stress and defects are generated on the surface, which may eventually lead to device leakage, breakdown and failure. By epitaxially growing a layer of single crystal silicon, not only the quality of the device surface can be effectively controlled to improve the device yield, but also the voltage resistance and other characteristics of the device can be improved, and the performance of the device can be comprehensively improved. At present, the normal pressure epitaxial process of integrated circuits adopts ultra-high temperature process to reduce the pattern distortion and drift in the epitaxial process, and most of the BCD process uses low-doped B silicon wafer (resistivity: 0.5-100Ω•cm) as the substrate. Such silicon wafer has low thermal conductivity, and due to the mechanical characteristics of Si-B crystal, a large amount of thermal stress cannot be released under the action of high temperature process. When the silicon wafer enters the high temperature epitaxial process again, dislocation slip movement occurs, especially the vertical climbing movement, thereby generating slip lines. The slip line has been an important control point and difficulty in the epitaxial process of BCD process. SUMMARY

[0003] The present application provides an epitaxial control method of slip line under ultra-high temperature condition for BCD process, which can effectively control the temperature distribution on the surface of the silicon wafer in the epitaxial process, thereby better controlling the generation of slip lines and further reducing the pattern distortion and drift.

[0004] Technical scheme: In order to solve the above problems, the present application adopts an epitaxial control method of slip line under ultra-high temperature condition for BCD process, which comprises the following steps:

[0005] (1) preparing temperature control wafer; using lightly doped B silicon wafer for dry oxygen oxidation, and implanting atomic P after oxidation to form temperature control wafer;

[0006] (2) after the reaction cavity of the epitaxial furnace is heated to 1160-1200℃, the reaction cavity is cleaned with HCl;

[0007] (3) after cleaning, the reaction cavity of the epitaxial furnace is cooled to room temperature, and the temperature control wafer is loaded;

[0008] (4) the reaction cavity is heated to a preset baking temperature at a constant heating rate, and constant temperature baking is carried out in H2 atmosphere;

[0009] (5) After baking, wait for the reaction chamber to cool naturally to room temperature, then remove the temperature control plate and perform chemical treatment to obtain a temperature control plate with the oxide layer removed;

[0010] (6) Perform resistivity tests on the temperature control sheet with the oxide layer removed to obtain the temperature distribution of each region of the temperature control sheet; calculate the temperature difference between the remaining regions of the temperature control sheet and the central region, and perform temperature compensation on the remaining regions of the temperature control sheet.

[0011] (7) After cleaning the silicon wafer to be epitaxially grown and repeating step (2), wait for the temperature of the reaction chamber to cool down to the preset temperature, and put the silicon wafer to be epitaxially grown into the reaction chamber. The reaction chamber is heated to the preset baking temperature at the heating rate in step (4) and the temperature compensation operation in step (6) is performed simultaneously. The silicon wafer is baked at a constant temperature in an H2 atmosphere. After the constant temperature baking is completed, the temperature of the reaction chamber is adjusted to the growth temperature, SiHCl3 and H2 are introduced and doped, and the silicon wafer is epitaxially grown to the target thickness and target resistivity.

[0012] Furthermore, before the dry oxidation in step (1), the lightly doped B silicon wafer is cleaned with a cleaning solution; the oxide layer thickness of the dry oxidation is 300-600 Å; the process of implanting P atoms includes: implantation energy of 60-100 keV, implantation concentration of 5-10E13 atoms / cm3, and implantation angle of 0-10°.

[0013] Furthermore, in step (4), the heating rate is 3-8℃ / s; the constant temperature baking time is 60-200s.

[0014] Furthermore, the preset baking temperature is 1150-1200℃.

[0015] Furthermore, the chemical treatment described in step (5) is as follows: the temperature control plate is soaked in HF solution with a concentration of 2-10% for 2-10 min.

[0016] Further, step (6) specifically involves: testing the resistivity of the five regions of the temperature control plate, namely the center, upper, lower, left, and right regions, respectively; calculating the resistivity difference between the four regions and the center region; and obtaining the temperature difference between the four regions and the center region respectively through the linear relationship between resistivity and temperature. Finally, adjusting the temperature of the four regions to the same temperature through temperature compensation.

[0017] Furthermore, in step (7), the growth temperature is 1150-1200℃, the H2 flow rate is 40-100slm, and the epitaxial growth rate is 2-5μm / min.

[0018] Furthermore, in step (7), the constant temperature baking time is 30-60s, and the doping is discharged while the constant temperature baking is being carried out. The discharge flow rate is controlled according to the target resistivity.

[0019] Furthermore, the preset temperature in step (7) is 700-850℃.

[0020] Furthermore, in step (7), the silicon wafer to be epitaxial is cleaned in two steps. The first step cleaning solution is a mixture of ammonia, hydrogen peroxide and deionized water, and the second step cleaning solution is a mixture of HF, hydrogen peroxide and deionized water.

[0021] Beneficial effects: Compared with the prior art, the significant advantage of this invention is that, compared with conventional temperature sensor control methods, this application can more clearly obtain the actual temperature of the silicon wafer surface during epitaxy, and can effectively control the temperature distribution of the silicon wafer surface during epitaxy, thereby better controlling the generation of slip lines and reducing pattern distortion and drift. Attached Figure Description

[0022] Figure 1 The flowchart shown is of the present invention;

[0023] Figure 2 The diagram shown is a schematic of the reaction chamber of an ASME2000 epitaxial device.

[0024] Figure 3 The diagram shows the distribution of slip lines on the surface of the silicon wafer after epitaxy.

[0025] Figure 4 The image shown is a comparison of the aligning figures before and after the extension. Detailed Implementation

[0026] The technical solution of the present invention will be further described below with reference to the accompanying drawings.

[0027] like Figure 2 As shown, the external equipment used in this embodiment is the ASM E2000 single-wafer epitaxial furnace manufactured by ASM Corporation of the United States. The main body of the reaction chamber is a high-purity graphite substrate 1 with a surface coated with high purity. Four sets of light bulbs are arranged directly below it, with a total of 17 light-emitting tubes arranged in upper and lower layers: 9 upper-layer heating tubes 2 and 8 lower-layer heating tubes 3. This allows for infrared heating of the center, front, back, left, and right areas of the reaction chamber. Thermocouples are also arranged directly below, at the front, rear, and sides of the high-purity graphite substrate 1, designated as central thermocouple 4, front thermocouple 5, rear thermocouple 6, and side thermocouple 7, to control the temperature of the reaction area. The main process carrier gas 8 in the reaction chamber is H2 purified to 99.9999%. A point light source 9 is also present in the reaction chamber. In this embodiment, all components within the reaction chamber, including the quartz bell jar and quartz support, need to be thoroughly cleaned to remove impurities and foreign matter adsorbed on their surfaces, ensuring purity.

[0028] like Figure 1As shown, this embodiment provides an epitaxial control method for a sliding line under ultra-high temperature conditions in BCD process based on the above-mentioned equipment, including the following steps:

[0029] Step 1: Prepare the temperature control plate;

[0030] An 8-inch boron-doped, non-back-sealed silicon wafer with a resistivity of 10 Ω•cm was selected. The wafer was cleaned successively with a mixture of ammonia, hydrogen peroxide, deionized water, and dilute HF. The cleaned wafer was then placed in a tube furnace for high-temperature oxidation, with the oxide layer thickness controlled to 400 Å by the oxidation time. After the oxidation was completed and the wafer was cooled to room temperature, ion implantation was performed under the following conditions: implanted P atoms, implantation energy of 80 keV, implantation concentration of 6E13 atoms / cm3, and implantation angle of 7°. After implantation, the required temperature-controlled wafer was formed.

[0031] Step 2: Preparation of the reaction chamber and graphite base;

[0032] The epitaxial equipment used is a single-wafer epitaxial furnace ASM E2000; after heating the reaction chamber in the epitaxial furnace to 1190℃, 20slm of HCl and 20slm of H2 are introduced for 20s, and then the H2 flow rate is increased to 60slm for 20s to remove the residual reactants in the chamber and ensure that the chamber environment is clean.

[0033] Step 3: Lower the temperature of the reaction chamber to room temperature, and then install the temperature control plate;

[0034] Step 4: Heat from room temperature to 1180℃ at a heating rate of 4℃ / s, and bake for 200s by introducing 60slm of H2.

[0035] Step 5: After the reaction chamber is cooled to room temperature after baking, remove the temperature control plate, soak it in 5% HF for 3 minutes, rinse it with deionized water, centrifuge and spin dry the surface to obtain the temperature control plate with the oxide layer removed.

[0036] Step 6: Using a 4D-280SI four-probe testing system, measure the resistivity of the temperature control plate used for oxide layer removal. Obtain the resistivity of five regions: center, top, bottom, left, and right. Calculate the corresponding temperature for each region using the linear relationship between temperature and resistivity. This allows you to determine the control temperatures of the central, front, rear, and side thermocouples within the reaction chamber. Calculate the resistivity difference between the top, bottom, left, and right regions and the center region. The temperature difference between the upper, lower, left, and right regions and the middle region was obtained by converting the linear relationship between resistivity and temperature. Specifically, the formula for converting resistivity to temperature linearly is as follows: ;in, Let T be the resistivity and T be the temperature. The temperature of the corresponding zones is adjusted by the machine's temperature compensation mechanism. Temperature compensation is performed on the four zones (upper, lower, left, and right) and the temperatures of the four zones are adjusted to be the same; that is, the temperature distribution compensation under the specified temperature is determined.

[0037] Step 7: Clean the silicon wafer to be epitaxial in two steps. The first step cleaning solution is a mixture of ammonia, hydrogen peroxide and deionized water. The second step cleaning solution is a mixture of HF, hydrogen peroxide and deionized water.

[0038] Step 8: Repeat the steps in step 2 to clean the cavity and base;

[0039] Step 9: After cleaning the reaction chamber, cool it to 800℃, load the cleaned silicon wafer to be epitaxially, and start heating at a rate of 4℃ / s with the temperature compensation from step six to 1180℃. Maintain constant temperature baking for 45s, while simultaneously removing the dopant. The flow rate of the removed dopant is controlled according to the target resistivity.

[0040] Step 10: After baking, adjust the temperature to the growth temperature. Simultaneously introduce 6g / min of SiHCl3, 60slm of H2, and dopant into the reaction chamber for epitaxial growth. Epitaxial growth is carried out to the target thickness and target resistivity, where the dopant is set according to the target resistivity.

[0041] Furthermore, the method provided by this invention has high versatility and efficiency, and can accommodate silicon wafer epitaxy of different sizes. It can be used not only for BCD process epitaxial growth control in monolithic flat-plate epitaxial furnaces, but also for depressurized BCD epitaxial control processes, and can accommodate different sizes.

[0042] The epitaxial silicon wafer manufactured using the control method described in this embodiment was tested. The fabricated silicon wafer had intact structure. Using SurfScan-SPI_TBI testing, the length of the in-wafer slip line after removing the 1.5mm edge was found to be 0. Figure 3 As shown, microscopic examination of the comparative images revealed no significant drift or distortion in the structures. Figure 4 As shown, Figure 4 (a) indicates before silicon wafer epitaxy, and (b) indicates after silicon wafer epitaxy. The surface of the epitaxial silicon wafer is free of defects such as fine bright spots, collapsed edges, and edge crystallization. The thickness uniformity of the surface epitaxial silicon wafer can be controlled within 1%, and the resistivity uniformity can be controlled within 2-3%, which fully meets the epitaxy requirements of BCD process.

Claims

1. A method for controlling slip lines in epitaxy under ultra-high temperature conditions for BCD processes, characterized in that, The method comprises the following steps: (1) preparing a temperature control wafer; using a lightly doped B wafer to perform dry oxygen oxidation, and then implanting atoms P to form the temperature control wafer; (2) after the reaction cavity of an epitaxial furnace is heated to 1160-1200 ℃, the reaction cavity is cleaned with HCl; (3) after the cleaning is completed, the reaction cavity of the epitaxial furnace is cooled to room temperature, and the temperature control wafer is loaded; (4) the reaction cavity is heated to a preset baking temperature at a constant heating rate, and constant temperature baking is performed in an H2 atmosphere; (5) after the baking is completed, the reaction cavity is naturally cooled to room temperature, and the temperature control wafer is taken out for chemical treatment to obtain a temperature control wafer with an oxide layer removed; (6) the temperature control wafer with the oxide layer removed is tested for resistivity to obtain the temperature distribution of each region of the temperature control wafer, the temperature difference between the remaining regions and the center region of the temperature control wafer is calculated, and the temperature of the remaining regions of the temperature control wafer is compensated; (7) after the silicon wafer to be epitaxied is cleaned and the operation of step (2) is repeated, the silicon wafer to be epitaxied is placed in the reaction cavity when the temperature of the reaction cavity is cooled to a preset temperature; the reaction cavity is heated to a preset baking temperature at the heating rate in step (4) and the temperature compensation operation in step (6) is performed synchronously, constant temperature baking is performed in an H2 atmosphere, the preset baking temperature is 700-850 ℃, and the constant temperature baking time is 30-60 s; after the constant temperature baking is completed, the temperature of the reaction cavity is adjusted to a growth temperature, SiHCl3 and H2 are introduced, and doping is performed, and epitaxial growth is performed to a target thickness and a target resistivity; the growth temperature is 1150-1200 ℃, the H2 flow rate is 40-100 slm, and the epitaxial growth rate is 2-5 μm / min.

2. The method of claim 1, wherein the method is performed at a temperature of 1,300°C or higher. The lightly doped B wafer is cleaned with a cleaning solution before dry oxygen oxidation in step (1); The thickness of the oxide layer obtained by dry oxygen oxidation is 300-600 A; the atom P implantation process comprises an implantation energy of 60-100 KeV, an implantation concentration of 5-10E13 atoms / cm3, and an implantation angle of 0-10°.

3. The method of claim 1, wherein the method is performed at an ultra-high temperature of about 1,100°C to about 1,300°C. The heating rate in step (4) is 3-8 ℃ / s; and the constant temperature baking time is 60-200 s.

4. The method of claim 1, wherein the BCD process is performed at a temperature of 1,300°C to 1,400°C. The preset baking temperature is 1150-1200 ℃.

5. The method of claim 1, wherein the BCD process is performed at a temperature of 1,300°C to 1,400°C. The chemical treatment in step (5) is that the temperature control wafer is soaked in HF with a solution concentration of 2-10% for 2-10 min.

6. The method of claim 1, wherein the method is performed at an ultra-high temperature of about 1,100°C to about 1,300°C. Step (6) specifically comprises: the resistivity of the center, upper, lower, left and right five regions of the temperature control wafer is tested respectively, the resistivity difference between the upper, lower, left and right four regions and the center region is calculated, the temperature difference between the upper, lower, left and right four regions and the center region is obtained through the linear relationship between resistivity and temperature, and the temperature of the upper, lower, left and right four regions is adjusted to the same temperature through temperature compensation.

7. The method of claim 1, wherein the method is performed at an ultra-high temperature of about 1,100°C to about 1,300°C. In step (7), doping and exclusion are performed simultaneously during constant temperature baking, and the exclusion flow rate is determined according to the target resistivity.

8. The method of claim 1, wherein the method is performed at an ultra-high temperature of about 1,100°C to about 1,300°C. In step (7), the silicon wafer to be epitaxied is cleaned in two steps, the first cleaning solution is a mixture of ammonia, hydrogen peroxide and deionized water, and the second cleaning solution is a mixture of HF, hydrogen peroxide and deionized water.

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