Three-dimensional transistor with improved channel mobility

Abstract

The invention relates to a three-dimensional transistor with improved channel mobility, providing a semiconductor structure comprising at least a first and a second three-dimensional transistor, wherein the first transistor and the second transistor are electrically connected in parallel to each other, and wherein each transistor comprises a source and a drain, wherein the source and / or the drain of the first transistor is / are at least partially separated from the source and / or the drain of the second transistor, respectively. The invention further relates to a process for forming such a semiconductor structure.

Description

[0001] This invention is a divisional application of Chinese patent application No. 201410541490.6, entitled "Three-dimensional transistor with improved channel mobility", filed on October 14, 2014. Technical Field

[0002] This invention generally relates to highly complex integrated circuits, including transistors with three-dimensional channel architectures such as FinFETs, capable of improving the electrical characteristics of transistors, and methods for manufacturing the same. Background Technology

[0003] Manufacturing advanced integrated circuits such as CPUs (Central Processing Units), storage devices, and application-specific integrated circuits (ASICs) requires forming a large number of circuit elements on a given chip area according to a specific circuit layout. Field-effect transistors (FETs) represent an important type of circuit element that fundamentally determines the performance of the integrated circuit. Generally, various process technologies are currently implemented. Among them, for many types of complex circuits, including FETs, MOS technology is one of the most promising methods due to its superior characteristics in terms of operating speed and / or power consumption and / or cost efficiency. During the fabrication of complex integrated circuits using technologies such as MOS, millions of transistors, such as N-channel and / or P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. FETs, whether N-channel or P-channel, typically include a PN junction formed through an interface between a highly doped region called the source / drain region and a weakly doped or undoped region, such as the channel region, located adjacent to the highly doped region. In an FET, the channel conductivity, i.e., the ability to drive the current through the conductive channel, is controlled by a gate electrode formed adjacent to the channel and separated from it by a thin insulating layer. After a suitable control voltage is applied to the gate electrode to form a conductive channel, the channel conductivity depends in particular on the dopant concentration, carrier mobility, and the distance between the source and drain (for planar transistor architectures), which is also called the channel length.

[0004] Based on mature materials and further consideration of reducing device size, the industry has proposed new transistor configurations that employ a "three-dimensional" architecture to achieve the desired channel width while maintaining excellent controllability of the current flowing through the channel. To this end, the industry has proposed FinFETs, in which thin wafers or fins made of silicon are formed in a thin active layer of SOI (silicon-on-insulator) or a standard silicon substrate. Gate dielectric and gate electrode materials are disposed on the sidewalls and (if desired) on the top surface to achieve a multi-gate transistor with complete channel depletion.

[0005] In some conventional methods of forming FinFETs, fins are formed in the shape of elongated devices, followed by the deposition of gate electrode material, possibly incorporating arbitrary spacers. The ends of the fins can then be "merged" by epitaxially growing source or drain material. In particular, several FinFETs can be connected in parallel in this way to increase the overall drive current. Typically, to achieve such parallel connections, each FinFET uses the same source and / or drain regions.

[0006] However, this negatively impacts the electrical performance of FinFET transistors. Among the various problems, the approach of having all FinFETs share a common source and drain increases the parasitic capacitance between the source and gate, as well as between the drain and gate, and limits the types and amounts of stress available on each FinFET.

[0007] In view of the above situation, this disclosure relates to semiconductor devices and manufacturing techniques, in which FinFETs or generally three-dimensional transistors can be formed and potentially connected in parallel with each other, while avoiding or at least reducing the effects of one or more of the above problems. Summary of the Invention

[0008] The following is a brief summary of the invention to provide a basic understanding of some embodiments thereof. This summary is not an exhaustive overview of the invention. It is not intended to identify key or essential elements of the invention or to define its scope. Its sole purpose is to provide some simplified concepts as a prelude to the more detailed discussion that follows.

[0009] Generally, the present invention provides a manufacturing technique and a semiconductor device in which a finned field-effect transistor device or a generally three-dimensional transistor can be formed by forming a common drain and / or source region for multiple devices and subsequently etching the drain and / or source region to remove at least a portion of the drain and / or source region located between field-effect transistor fins or channels. Alternatively, a mask can be used to form the drain and / or source region to obtain the same geometry, i.e., the material of the drain and / or source region located between the field-effect transistor fins is less than the material of the drain and / or source region located on the fins themselves. Since this removal, or the absence of the drain and / or source region material, is present during deposition, this is beneficial for reducing the surface area of ​​the drain and / or source region facing the gate, thereby reducing the parasitic capacitance between the drain and the gate and / or the source region and the gate. In addition, by limiting the amount of drain and / or source region material between channels, structural stress caused by the presence of drain and / or source region material can be differentially controlled for cases where drain and / or source region material exists between fins. Furthermore, since the material in the drain region and / or source region is at least partially absent, more gaps are available between the fins, allowing for the deposition of different materials and thus enabling further control over the stress on the fins.

[0010] One example method disclosed herein relates to a semiconductor structure comprising at least a first and a second three-dimensional transistor, the first transistor and the second transistor being electrically connected in parallel to each other and sharing a common gate, and each transistor comprising a source and a drain, the source and / or drain of the first transistor being at least partially spaced from the source and / or drain of the second transistor.

[0011] Another example method disclosed herein relates to a process for forming a semiconductor structure comprising at least a first and a second three-dimensional transistor, the first transistor being electrically connected in parallel with the second transistor and sharing a common gate. The process includes forming a single source region and / or a single drain region as the drain and / or source of the first and second transistors, respectively, and removing material from the single source region and / or the single drain region such that the source and / or drain of the first transistor is at least partially separated from the source and / or drain of the second transistor.

[0012] Another example method disclosed herein relates to a process for forming a semiconductor structure comprising at least a first and a second three-dimensional transistor, the first transistor being electrically connected in parallel with the second transistor and sharing a common gate, the process comprising forming separate sources and / or separate drains for each of the first and second transistors.

[0013] Another example method disclosed herein relates to a process for forming a semiconductor structure including at least a first and a second three-dimensional transistor, the first transistor and the second transistor being electrically connected in parallel and sharing a common gate, the process including forming the source and / or drain of each of the first and second transistors, wherein the source and drain of the first transistor are respectively connected to the source and drain of the second transistor through source and drain regions, respectively, the width of the source and drain regions along the channel direction of the transistors being smaller than the width of the source and / or the drain.

[0014] As a result of the above methods, the regions of the source and / or drain facing the gate can be reduced, or the regions can be moved further away from the gate, thereby limiting the parasitic capacitance between the source and gate and / or the drain and gate. Furthermore, by removing at least a portion of the material in the source and / or drain regions and replacing it with another material, the stress on the channels and / or the source and / or drain of these transistors can be better controlled. Attached Figure Description

[0015] This disclosure can be understood in conjunction with the accompanying drawings and the following description, in which similar reference numerals represent similar elements, wherein:

[0016] Figure 1a A top view schematic diagram of a semiconductor structure according to an example embodiment is shown;

[0017] Figure 1b The display is based on the example embodiment along Figure 1a A cross-sectional view of section A-A';

[0018] Figure 1c The display is based on the example embodiment along Figure 1a A schematic cross-sectional view of section B-B';

[0019] Figure 1d The display is based on the example embodiment along Figure 1a A cross-sectional view of section C-C';

[0020] Figure 2a The example embodiment shows another manufacturing stage. Figure 1a A top-view schematic diagram of a semiconductor structure;

[0021] Figure 2b The display is based on the example embodiment along Figure 2a A cross-sectional view of section A-A';

[0022] Figure 2c The display is based on the example embodiment along Figure 2a A schematic cross-sectional view of section B-B';

[0023] Figure 2d The display is based on the example embodiment along Figure 2a A cross-sectional view of section C-C';

[0024] Figure 3a The example embodiment shows another manufacturing stage. Figure 1a A top-view schematic diagram of a semiconductor structure;

[0025] Figure 3b The display is based on the example embodiment along Figure 3a A cross-sectional view of section A-A';

[0026] Figure 3c The display is based on the example embodiment along Figure 3a A schematic cross-sectional view of section B-B';

[0027] Figure 3d The display is based on the example embodiment along Figure 3a A cross-sectional view of section C-C';

[0028] Figure 4a The example embodiment shows another manufacturing stage. Figure 1a A top-view schematic diagram of a semiconductor structure;

[0029] Figure 4b The display is based on the example embodiment along Figure 4a A cross-sectional view of section A-A';

[0030] Figure 4c The display is based on the example embodiment along Figure 4a A schematic cross-sectional view of section B-B';

[0031] Figure 4d The display is based on the example embodiment along Figure 4a A cross-sectional view of section C-C';

[0032] Figure 5a The example embodiment shows another manufacturing stage. Figure 1a A top-view schematic diagram of a semiconductor structure;

[0033] Figure 5b The display is based on the example embodiment along Figure 5a A cross-sectional view of section A-A';

[0034] Figure 5c The display is based on the example embodiment along Figure 5a A schematic cross-sectional view of section B-B';

[0035] Figure 5d The display is based on the example embodiment along Figure 5a A cross-sectional view of section C-C';

[0036] Figure 6aThe example embodiment shows another manufacturing stage. Figure 1a A top-view schematic diagram of a semiconductor structure;

[0037] Figure 6b The display is based on the example embodiment along Figure 6a A cross-sectional view of section A-A';

[0038] Figure 6c The display is based on the example embodiment along Figure 6a A schematic cross-sectional view of section B-B';

[0039] Figure 6d The display is based on the example embodiment along Figure 6a A cross-sectional view of section C-C';

[0040] Figure 7a A top view schematic diagram of a semiconductor structure according to an example embodiment is shown; and

[0041] Figure 7b This shows a top view schematic diagram of a semiconductor structure according to an example embodiment.

[0042] While the subject matter of the invention disclosed herein allows for various modifications and alternatives, specific embodiments of the subject matter are shown by way of example in the accompanying drawings and are described in detail herein. However, it should be understood that the description of specific embodiments herein is not intended to limit the invention to the specific forms disclosed, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined in the claims. Detailed Implementation

[0043] Various exemplary embodiments of the present invention are described below. For clarity, not all features in actual implementations are described in this specification. It should be understood that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to meet the developer's specific objectives, such as compliance with system-related and business-related constraints that vary from implementation to implementation. Furthermore, it should be understood that such development efforts may be complex and time-consuming, but they remain a conventional procedure performed by those skilled in the art using this specification.

[0044] The invention will now be described with reference to the accompanying drawings. The various structures, systems, and devices illustrated in the drawings are for illustrative purposes only and to avoid obscuring the invention from details known to those skilled in the art. However, the invention still includes these drawings to illustrate and explain examples of the invention. The meanings of the words and phrases used herein should be understood and interpreted in accordance with the understanding of those skilled in the art. The coherent use of terms or phrases herein is not intended to imply any particular definition, i.e., a definition different from the commonly used meaning understood by those skilled in the art. If a term or phrase is intended to have a specific meaning, i.e., a meaning different from that understood by those skilled in the art, such a specific definition will be explicitly stated in the specification by providing a direct and clear definition of the term or phrase.

[0045] The following embodiments are provided to enable those skilled in the art to use the invention. It should be understood that other embodiments will be apparent based on this disclosure, and changes to the system, structure, process, or machinery may be made without departing from the scope of this disclosure. In the following description, specific reference numerals are given in detail to provide a thorough understanding of this disclosure. However, it will be apparent that this disclosure can be practiced without these specific details. To avoid obscuring this disclosure, some known circuits, system configurations, structural configurations, and process steps are not disclosed in detail.

[0046] Generally, this disclosure considers manufacturing technologies and semiconductor devices in which a non-planar transistor configuration (also known as a three-dimensional transistor or more specifically, FinFET) can be configured based on a process strategy in which an initial fin formed from a semiconductor-based material such as silicon can be used.

[0047] Figure 1a This is a top view schematic diagram of the semiconductor structure 100. Figure 1b , 1c And 1d shows cross-sectional schematic diagrams of the semiconductor structure 100 along lines A-A', B-B' and C-C' respectively.

[0048] As shown in the accompanying figures, the semiconductor structure 100 includes a substrate 101 in which fins 102a to 102c are disposed. At least a portion of the fins 102a to 102c serve as channels for corresponding FinFETs, as will be described in detail later. The fins 102a to 102c can be formed by etching material from the substrate 101 to expose the fins 102a to 102c, or by depositing material on the substrate 101 to construct the fins 102a to 102c. Alternatively, they can be formed by a sidewall image transfer method. In all cases, the final structure is as follows: Figures 1a to 1dAs shown. The substrate 101 may include or be composed of silicon or any other semiconductor material such as germanium (Ge), silicon / germanium (SiGe), or a layered semiconductor structure such as silicon-on-insulator (SOI), or a semiconductor alloy such as a III-V alloy. The fins 102a to 102c may be formed of the same semiconductor material as the substrate 101, particularly when the fins 102a to 102c are formed by removing material from the substrate 101, and when the fins 102a to 102c are formed by depositing material on the substrate 101, for example, when using silicon epitaxial growth on a silicon substrate. Alternatively, the fins 102a to 102c may be formed of different semiconductor materials. In both cases, the fins 102a to 102c may be doped differently relative to the substrate 101.

[0049] like Figure 1b As shown, fins 102a to 102c extend along the perpendicular Y direction. Preferably, fins 102a to 102c have a height T1 in the range of 60 to 90 nanometers, more preferably, the value of height T1 is 70 nanometers. Furthermore, each fin 102a to 102c has a width W1 along the X direction. Preferably, the width W1 is in the range of 20 to 40 nanometers, more preferably, the value of width W1 is 25 nanometers. Finally, as... Figure 1c As shown, fin 102b and fins 102a and 102c ( Figure 1c (Not shown in the figure) The fins 102a and 102c are arranged with a length L1 along the Z direction. Preferably, the length L1 is in the range of 50 to 80 nanometers, and more preferably, the length L1 is 60 nanometers. In addition, the fins 102a and 102c are arranged with a mutual distance W2 along the X direction in the range of 20 to 40 nanometers, preferably 35 nanometers.

[0050] Each fin 102a to 102c can withstand a maximum current, which is limited by the materials and dimensions used. Some applications may require current levels higher than that that a single FinFET can withstand. In these cases, fins 102a to 102c can be connected in parallel by forming a common source region and / or a common drain region for at least two of them, thereby increasing the total current flowing between the common source region and / or common drain region. The formation of such common source region and / or drain region will be described below, with particular reference to... Figures 4a to 4d .

[0051] Figures 2a to 2d This schematic diagram shows a semiconductor structure 200, which is formed after further manufacturing steps are performed on the semiconductor structure 100. In particular, Figures 2a to 2d respectively indicating and Figures 1a to 1d The same semiconductor structure from the same perspective.

[0052] like Figures 2a to 2dAs shown, semiconductor structure 200 is obtained by depositing an insulating layer 103 onto semiconductor structure 100. Preferably, in some embodiments, the insulating layer 103 may have a deposition thickness of 100 nanometers along the Y direction. Subsequently, the insulating layer 103 may be thinned by a chemical mechanical polishing (CMP) step so that its height corresponds substantially to the top surface of fins 102a to 102c. Finally, the insulating layer 103 may be anisotropically etched to retain an insulating material layer with a preferred thickness T2 of 50 nanometers at the bottom of fins 102a to 102c. In other words, in some embodiments, the height of the insulating layer 103 is less than the height of fins 102a to 102c.

[0053] Although the above process steps are provided to illustrate an example embodiment of forming the insulating layer 103, those skilled in the art will understand that the insulating layer 103 can be formed in the fins 102a to 102c by alternative process steps. For example, by using appropriate masking and deposition steps, the insulating layer 103 can be deposited only in the gaps between the fins 102a to 102c to achieve the desired thickness in a single deposition step without using any chemical mechanical polishing and / or etching.

[0054] Figures 3a to 3d This diagram shows a semiconductor structure 300, which is formed after further manufacturing steps are performed on the semiconductor structure 200. In particular, Figures 3a to 3d respectively indicating and Figures 1a to 1d The same semiconductor structure from the same perspective.

[0055] like Figure 3a As shown, a dummy gate 104 is formed on semiconductor structure 200, thereby forming semiconductor structure 300. Although referred to herein as a dummy gate, the present invention is not limited thereto, as a gate will replace the dummy gate in subsequent processes (not shown). In particular, in some embodiments, gate 104 may be the final gate rather than a dummy gate. Thus, in describing the present invention, the terms "dummy gate 104" and "gate 104" are used interchangeably.

[0056] In particular, the dummy gate 104 can be formed, for example, from polysilicon. Preferably, the width of the dummy gate 104 along the Z direction, corresponding to the channel length of the FinFET, is in the range of 20 to 30 nanometers, and more preferably, this width is 26 nanometers. In other words, portions of the fins 102a to 102c located below the dummy gate 104 correspond to the channel of the corresponding FinFET. Figures 3b to 3dAs shown, the dummy gate 104 is separated from each fin 102a to 102c by a gate dielectric 105. The gate dielectric 105 is typically an oxide, such as silicon oxide, and preferably has a thickness of 2 to 3 nanometers. The gate dielectric 105 can be obtained, for example, by chemical vapor deposition or any other technique capable of forming a thin layer on the fins 102a to 102c. The dummy gate 104 is obtained by depositing the material to form the dummy gate 104, followed by a subsequent planarization step of chemical mechanical polishing.

[0057] Although not shown in the accompanying drawings, a nitride layer may be formed on top of the dummy gate 104 and / or on portions of the fins where source / drain electrodes are not required and / or on the insulating layer. The purpose of such a nitride layer is to facilitate the subsequent growth of source / drain regions 108 and 109. Figures 4a to 4d During this period, it acts as a spacer wall. In this regard, those skilled in the art will understand that such a spacer layer does not necessarily have to be made of nitride, but can be any material that allows for the subsequent localized formation of source and drain electrodes.

[0058] Figures 4a to 4d A schematic diagram showing semiconductor structure 400 is displayed. Semiconductor structure 400 is formed after further manufacturing steps are performed on semiconductor structure 300. Specifically, Figures 4a to 4d respectively indicating and Figures 1a to 1d The same semiconductor structure from the same perspective.

[0059] More specifically, in the semiconductor structure 400, source / drain regions 108 and 109 are formed at both ends of each fin 102a to 102c. The positioning of the source / drain regions 108 and 109 can be precisely controlled by using the aforementioned nitride layer or any equivalent mask layer. In particular, the shapes of the source / drain regions 108 and 109 are similar to those described above. Figures 3a to 3d The negative image of the nitride layer or mask layer, which is described but not illustrated.

[0060] In some embodiments, the fin ends in regions 108 and 109 (i.e., regions not covered by a mask layer or a nitride layer (SiN)) are merged by epitaxial growth of silicon to form source region 108 and drain region 109. Due to the nitride layer or mask layer, the proximity of source / drain regions 108 and 109 to the dummy gate 104 can be precisely controlled. In one example fabrication method, gate 104 is completely covered by nitride, and only the regions where source / drain regions 108 and 109 will be formed are exposed by photolithography and subsequent corresponding etching steps to grow selective silicon in these regions. Although it is stated herein that source / drain regions 108 and 109 are formed by epitaxial growth of silicon, the invention is not limited thereto; instead, other materials, such as SiGe or III-V alloys, and / or other deposition methods, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), can be used. Next, if necessary, the source / drain regions 108 and 109 can be doped, for example, boron for P-type field-effect transistors and phosphorus (P) / arsenic (As) for N-type field-effect transistors. The distance W3 between the source / drain regions 108 and 109 and the gate 104 along the Z direction can be set in the range of 10 to 30 nanometers, preferably 20 nanometers. In addition, the width W4 of the source / drain regions 108 and 109 along the Z direction is in the range of 20 to 40 nanometers, preferably 30 nanometers.

[0061] After the source and drain regions 108 and 109 are formed, the fins 102a to 102c are electrically connected in parallel. Corresponding source and drain contacts (not shown) can be formed on the source and drain regions 108 and 109 to access them. However, this architecture results in a relatively large area for the source and drain regions 108 and 109 facing the gate 104 in the XY plane. This leads to high parasitic capacitance between the source region 108 and the gate 104, and between the drain region 109 and the gate 104. Furthermore, the material of the source and drain regions 108 and 109 may exhibit biaxial stress due to the growth techniques used for these regions. This may limit the amount of current flowing through the fins 102a to 102c and / or the source and drain regions 108 and 109.

[0062] Figures 5a to 5d A schematic diagram of semiconductor structure 500 is shown, which corresponds to semiconductor structure 400 having a cover mask 107. In particular, Figures 5a to 5d respectively indicating and Figures 1a to 1d The same semiconductor structure from the same perspective.

[0063] More specifically, in Figure 5aIn this configuration, mask 107 vertically covers semiconductor structure 500. Here, to reduce the number of masks and thus manufacturing costs, mask 107 can correspond to the mask (not shown) used to form fins 102a to 102c. Here, the removal process can be successfully performed even if mask 107 has a positioning tolerance of 5 to 10 nanometers relative to its original position when forming fins 102a to 102c. However, any mask capable of removing at least a portion of the material of source / drain regions 108 and 109 in at least a portion of the region R1 that separates fins 102a to 102c can be used. Due to the use of mask 107, the material used in the source / drain regions 108 and 109 in the region R1 between fins 102a to 102c can be selectively removed. At this stage, the area between the gate 104 and the source / drain regions 108 and 109 is still protected by the silicon nitride used in the aforementioned manufacturing steps, or more generally, by the mask layer of the gap wall, so as to selectively remove the material of the source / drain regions 108 and 109 in the portion between fins 102a and 102c without affecting the rest of the structure.

[0064] Figures 6a to 6d A schematic diagram of semiconductor structure 600 is shown, which corresponds to semiconductor structure 400 after an etching process based on mask 107 is performed. In particular, Figures 6a to 6d respectively indicating and Figures 1a to 1d The same semiconductor structure from the same perspective.

[0065] By removing material from the source / drain regions 108 and 109 in region R1 between fins 102a and 102c, as shown in the figure, Figures 6a to 6d The semiconductor structure 600 is shown. In particular, as... Figure 6a As shown, the region R1 between the fins 102a to 102c aligned with the source / drain regions 108 and 109 along the X direction does not contain material that connects the source / drain regions 108 and 109 to each other. Instead, for each fin 102a to 102c, the source / drain regions 108 and 109 are independently separated, resulting in the formation of independent sources 108a to 108c and independent drains 109a to 109c.

[0066] It should be noted that in this embodiment, the mask 107 shown covers the entire source / drain region 108 and 109 along the Z direction. However, the present invention is not limited thereto. In particular, the source / drain material between the fins 102a and 102c can be completely removed, such as... Figures 6a to 6d As shown, each fin has an independent source electrode 108a to 108c and a drain electrode 109a to 109c. These independent source and drain electrodes can then be electrically connected through their respective contacts and by the appropriate use of vias and connecting wires.

[0067] Alternatively, only a portion of the source / drain region material between fins 102a and 102c can be removed, especially the portion closest to the dummy gate 104 along the Z direction, such as... Figure 7b The semiconductor structure 800 is shown here. Here, compared to the source / drain electrodes 108g to 108i and 109g to 109i on the fins 102a to 102c, the material of the source / drain regions 108 and 109, which are farther from the dummy gate 104 along the Z direction, can be retained. In particular, the remaining material of the source / drain regions 108 and 109 can begin at a distance W5 along the Z direction, where W5 is in the range of 20 to 30 nanometers, preferably 25 nanometers. Due to this latter method, the remaining material of the source / drain regions 108 and 109 between the fins 102a to 102c ensures the connection between the source / drain electrodes 108g to 108i and 109g to 109i of the fins 102a to 102c.

[0068] Alternatively, only a portion of the source / drain region material between fins 102a and 102c can be removed, especially the portion along the Z direction away from the dummy gate 104, such as... Figure 7a The semiconductor structure 700 is shown here. Here, compared to the source / drain electrodes 108d to 108f and 109d to 109f on the fins 102a to 102c, the material of the source / drain regions 108 and 109, which are equally close to the dummy gate 104 along the Z direction, can be retained. Due to this method, the remaining material in the source / drain regions 108 and 109 between the fins 102a to 102c ensures the connection between the source / drain electrodes 108g to 108i and 109g to 109i of the fins 102a to 102c.

[0069] For example, the embodiments shown in semiconductor structures 700 and 800 can be used to increase the mechanical strength of fins 102a to 102c.

[0070] In semiconductor structures 700 and 800, the width W6 of the remaining source / drain region material along the Z direction can be in the range of 10 to 20 nanometers, preferably 15 nanometers.

[0071] Thus, due to the aforementioned process, a semiconductor structure comprising at least first and second three-dimensional transistors can be obtained. The first transistor and the second transistor are electrically connected in parallel and share a common gate 104. In this semiconductor structure, each transistor includes a source and a drain. The source and / or drain of the first transistor are at least partially separated from the sources 108a to 108i and / or drains 109a to 109i of the second transistor, respectively. More specifically, each of the first and second transistors includes a channel, and along a direction parallel to the channel of the first transistor and / or the channel of the second transistor, the source and / or drain of the first transistor are at least partially separated from the source and / or drain of the second transistor, respectively. Furthermore, in the portion of the source and / or drain closest to the gate 104, the sources 108a to 108c, 108g to 108i and / or drains 109a to 109c, 109g to 109i of the first transistor are at least partially separated from the sources 108a to 108c, 108g to 108i and / or drains 109a to 109c, 109g to 109i of the second transistor, respectively. Alternatively, in the portion of the source and / or drain furthest from the gate 104, the sources 108d to 108f and / or drains 109a to 109f of the first transistor are at least partially separated from the sources 108d to 108f and / or drains 109a to 109f of the second transistor, respectively. Alternatively, the sources 108a to 108c and / or drains 109a to 109c of the first transistor are completely separated from the sources 108a to 108c and / or drains 109a to 109c of the second transistor, respectively. In this last case, each transistor also includes a channel, and the source and / or drain of the first transistor has a width W1 corresponding to the width of the channel of the first transistor, and / or the source and / or drain of the second transistor has a width W1 corresponding to the width of the channel of the second transistor. Here, the expression "partially separated" means that the two elements are not completely connected along their facing sides, but only a portion of their facing sides is used for connection to the other element.

[0072] More generally, the present invention can be implemented by completely removing the material in region R1, as shown in semiconductor structure 600, or by removing only a portion of its material, as shown in semiconductor structures 700 and 800. Those skilled in the art will understand that semiconductor structures 700 and 800 are merely two extreme cases with the same configuration in which some material in source / drain regions 108 and 109 remains in region R1, and other configurations between these two cases can be implemented.

[0073] Thus, semiconductor structures 600 to 800 differ from semiconductor structure 400 due to the removal of at least a portion of the source / drain region material between fins 102a and 102c (i.e., in region R1). In particular, in semiconductor structures 600 and 800, the capacitance between the dummy gate 104 and the source / drain regions 108 and 109 can be reduced by removing such material near the dummy gate 104. In fact, comparing semiconductor structures 600 and 800 with semiconductor structure 400 reveals that the regions of the source / drain electrodes 108a to 108c and 109a to 109c in the XY plane of semiconductor structure 600 are substantially smaller than the equivalent regions of semiconductor structure 400. Even in the case of semiconductor structure 800, where only a portion of the material forming the source / drain regions 108 and 109 is removed between fins 102a and 102c, although the source / drain regions 108 and 109 of semiconductor structure 800 and semiconductor structure 400 have the same area in the XY plane, the average distance between such regions of semiconductor structure 800 and the gate 104 is greater than that of semiconductor structure 400. That is, when only a portion of the material of source / drain regions 108 and 109 is removed, or when all such material is removed, the capacitance between source / drain regions 108 and 109 and the dummy gate 104 is reduced, thus improving the electrical characteristics of the parallel-connected FinFET.

[0074] Furthermore, by removing the material between fins 102a and 102c, the biaxial stress generated by the epitaxial growth of the material in the source / drain regions 108 and 109, such as silicon / germanium, can be converted into uniaxial stress. In some cases, in fact, uniaxial stress in FinFETs achieves better mobility improvement compared to biaxial stress. Thus, semiconductor structures 600, 700, and 800 exhibit better electrical characteristics than semiconductor structure 400, in which the material between fins 102a and 102c generates biaxial stress on the fins, while this is absent or reduced in semiconductor structures 600, 700, and 800.

[0075] Furthermore, the gaps formed between the independent source / drain electrodes 108a to 108c and 109a to 109c of adjacent fins 102a to 102c in semiconductor structure 600 by completely removing the source / drain material, and the gaps formed between the source / drain electrodes 108d to 108i and 109d to 109i of adjacent fins 102a to 102c in semiconductor structures 700 and 800 by partially removing the source / drain material, can subsequently be filled with different materials, such as stress-coating films, such as silicon nitride (Si3N4), silicon oxide (SiO2), etc., thereby improving mobility and drive current. In other words, due to the use of another material, desired stresses can be further configured on the fins 102a to 102c and / or the source / drain electrodes 108a to 108i and 109a to 109i to improve the corresponding electrical characteristics of the FinFET based on the fins 102a to 102c. In semiconductor structure 400, such further configuration of source and drain stress is not possible. In semiconductor structure 400, the gap R1 between the source and drain regions 108 and 109 of fins 102a to 102c is completely filled with the same source and drain region material.

[0076] Although not illustrated, those skilled in the art will understand that some process steps not shown in the figures, such as RTA (rapid thermal annealing) for activation and diffusion, and / or silicide formation, and / or the removal of the dummy gate and replacement with a high-k / metal gate, and / or contact formation and back-end processes in conventional FinFET processes, are not illustrated for clarity.

[0077] In an alternative embodiment of the invention, instead of removing the material from the source / drain regions 108 and 109 between fins 102a and 102c, such material can be deposited only in the regions indicated by reference numerals 108a to 108i and 109a to 109i in the semiconductor structures 600 to 800. In other words, instead of performing the deposition of the source / drain regions 108 and 109 and performing subsequent patterning by, for example, photolithography and etching, the source / drain electrodes 108a to 108i and 109a to 109i can be deposited locally and directly. This method can be achieved, for example, by using a mask 700 for locally depositing the material of the source / drain regions 108 and 109, except for the aforementioned nitride layer or, more generally, a mask layer that covers the dummy gate 104 and acts as a spacer along the Z direction to define the distance between the source 108 and the dummy gate 104 and the drain 109 and the dummy gate 104. In other words, such localization of source and drain electrodes 108a to 108c and 109a to 109c can be achieved by using Figures 4a to 4d The deposition step shown in the figure is achieved using the mask 107.

[0078] Moreover, although three fins 102a to 102c are shown in the accompanying drawings, those skilled in the art will understand that any number of fins, more than two, can be used to implement the present invention.

[0079] Since those skilled in the art can readily modify and implement the invention in different but equivalent ways with the aid of the teachings herein, the specific embodiments described above are merely exemplary. For example, the process steps described above may be performed in a different order. Moreover, the invention is not limited to the details of the architecture or design shown herein, but rather to the claims. Therefore, it is evident that modifications or alterations can be made to the specific embodiments disclosed above, and all such modifications fall within the scope and spirit of the invention. Accordingly, the claims define the scope of protection of the invention.

Claims

1. A semiconductor structure, comprising: Multiple fins, including semiconductor material, are spaced apart; A gate dielectric is located on the top and sidewalls of the plurality of fins and between the plurality of fins; A common gate is located above the gate dielectric and extends across each of the plurality of fins; A continuously merged semiconductor material region is located on each of the plurality of fins and above the gate dielectric, wherein the continuously merged semiconductor material region is laterally spaced from the common gate and extends and is in solid contact between the plurality of fins. The continuously merged semiconductor material region has a first sidewall surface facing the common gate and a second sidewall surface opposite to the first sidewall surface and facing away from the common gate. The first sidewall surface of the continuously merged semiconductor material region, a first portion of the opposing sidewall surfaces of adjacent pairs of the plurality of fins, and a first portion of the upper surface of the gate dielectric at least partially define a first gap between the continuously merged semiconductor material region and the common gate. Furthermore, the second sidewall surface of the continuously merged semiconductor material region, a second portion of the opposing sidewall surfaces of adjacent pairs of the plurality of fins, and a second portion of the upper surface of the gate dielectric at least partially define a second gap on the side of the continuously merged semiconductor material region opposite to the first gap. The stress-covering membrane is located only in the first gap between the opposing sidewall surfaces of the adjacent pairs of the plurality of fins.

2. The semiconductor structure as described in claim 1, wherein, The stress-covering film is in direct contact with at least the first sidewall surface of the continuously merged semiconductor material region, the opposing sidewall surfaces of the adjacent pairs of the plurality of fins, and the upper surface of the gate dielectric.

3. The semiconductor structure as described in claim 1, wherein, The stress-coating film comprises either silicon nitride or silicon oxide.

4. The semiconductor structure as described in claim 1, wherein, This continuously merged semiconductor material region includes epitaxial silicon / germanium alloys.

5. The semiconductor structure as described in claim 1, wherein, The gate dielectric covers the lower sidewall surface of each of the plurality of fins.

6. The semiconductor structure as claimed in claim 1, wherein, The continuously merged semiconductor material region is a first continuously merged semiconductor material region located on the source region side of the common gate, and the semiconductor structure also includes a second continuously merged semiconductor material region located on the drain region side of the common gate.

7. The semiconductor structure as claimed in claim 6, wherein, The second continuously merged semiconductor material region is located on each of the plurality of fins and above the gate dielectric, wherein the second continuously merged semiconductor material region is laterally spaced from the common gate and extends and is in solid contact between the plurality of fins, and the second continuously merged semiconductor material region has a third sidewall surface facing the common gate and a fourth sidewall surface opposite to the third sidewall surface and facing away from the common gate.

8. The semiconductor structure as claimed in claim 7, wherein, The stress covering film is a first stress covering film, and the semiconductor structure also includes a second stress covering film located in a third gap, the third gap being defined at least in part by the third sidewall surface of the second continuously merged semiconductor material region, the opposing sidewall surfaces of the adjacent pairs of the plurality of fins, and the upper surface of the gate dielectric.

9. The semiconductor structure as claimed in claim 1, wherein, The common gate is an alternative gate structure that includes a high-k dielectric material and a metal gate electrode.

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