Display panel

Abstract

The present application discloses a display panel. By arranging the second data line in the display area between the first data line and the third data line, and making the distance between the first data line and the second data line smaller than the distance between the third data line and the second data line, and arranging the first pad on the side of the second data line and the third data line close to the first data line, when the second pad is located between the first pad and the third pad in the direction perpendicular to the display area and pointing to the bonding area, the first pad is electrically connected to the first data line, the second pad is electrically connected to the third data line, and the third pad is electrically connected to the second data line, so as to facilitate the parasitic capacitance between the first data line and the second data line and the parasitic capacitance between the second data line and the third data line to tend to be consistent.

Description

Technical Field

[0001] This application relates to the field of display technologies, and in particular, to a display panel. Background Art

[0002] Currently, when multiple data lines with unequal intervals are arranged in the display area of a display panel, the parasitic capacitance between two adjacent data lines is different from that between two relatively distant data lines. The inconsistency of the parasitic capacitance will affect the display effect of the display panel.

[0003] Therefore, it is necessary to propose a technical solution to solve the problem that the inconsistent parasitic capacitance between data lines affects the display effect. Summary of the Invention

[0004] The purpose of this application is to provide a display panel to solve the problem that the inconsistent parasitic capacitance between multiple data lines affects the display effect.

[0005] To achieve the above purpose, the technical solution is as follows:

[0006] A display panel, which has a display area and a bonding area, and includes:

[0007] A first data line, extending from the display area to the bonding area and electrically connected to the first column of sub-pixels in the display area;

[0008] A second data line, extending from the display area to the bonding area, located on one side of the first data line, and electrically connected to the second column of sub-pixels in the display area, where the second column of sub-pixels is located on one side of the first column of sub-pixels; and

[0009] A third data line, extending from the display area to the bonding area, electrically connected to the third column of sub-pixels in the display area, and the second column of sub-pixels is located between the first column of sub-pixels and the third column of sub-pixels. In the display area, the second data line is located between the first data line and the third data line, and the distance between the first data line and the second data line is less than the distance between the third data line and the second data line;

[0010] A first pad, disposed in the bonding area and located on the side of the second data line and the third data line close to the first data line, and the first pad is electrically connected to the first data line;

[0011] A second pad, disposed in the bonding area and electrically connected to the third data line;

[0012] A third pad is disposed in the bonding area and is electrically connected to the second data line. The second pad is located between the first pad and the third pad in a direction perpendicular to the display area and pointing to the bonding area; and

[0013] A source driver chip is connected to the first pad, the second pad, and the third pad.

[0014] Advantageous effects: The present application discloses a display panel. By arranging the second data line between the first data line and the third data line in the display area, and the distance between the first data line and the second data line is less than the distance between the third data line and the second data line, and the first pad is located on the side of the second data line and the third data line close to the first data line, and the second pad is located between the first pad and the third pad in a direction perpendicular to the display area and pointing to the bonding area, the first pad is electrically connected to the first data line, the second pad is electrically connected to the third data line, and the third pad is electrically connected to the second data line, which is beneficial to increasing the distance between the first data line and the second data line and decreasing the distance between the second data line and the third data line in the area between the display area and the bonding area, and further beneficial to making the parasitic capacitance between the first data line and the second data line and the parasitic capacitance between the second data line and the third data line tend to be consistent. Description of the Drawings

[0015] Figure 1 is a schematic diagram of the display panel according to the embodiment of the present application;

[0016] Figure 2 is Figure 1 a partial plan schematic diagram of the shown display panel;

[0017] Figure 3 is Figure 1 a schematic diagram of the pixel circuit of the sub-pixel of the shown display panel;

[0018] Figure 4 is Figure 2 a schematic diagram of the connection between the pixel circuit of the sub-pixel and the data line of the shown display panel;

[0019] Figure 5 is Figure 1 a cross-sectional schematic diagram of the shown display panel;

[0020] Figures 6A - 6J is Figure 3 a schematic diagram of the film layer stack structure of the pixel circuit of one sub-pixel and multiple signal lines connected to the pixel circuit of the shown display panel. Detailed Embodiments

[0021] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application.

[0022] Please refer to Figure 1 , the present application provides a display device 50, and the display device 50 can be any one of a liquid crystal display device, an organic light emitting diode display device, a micro light emitting diode display device, and a submillimeter light emitting diode display device. Specifically, the display device 50 is an organic light emitting diode display device.

[0023] The display device 50 includes a display panel 10, a source driver chip 20, a gate driving circuit 30, and a light emission control driving circuit 40.

[0024] The display panel 10 has a display area 10a, a fan-shaped area 10b, and a bonding area 10c. In the second direction, the fan-shaped area 10b is located between the display area 10a and the bonding area 10c, and the second direction is the direction from the display area 10a to the bonding area 10c.

[0025] The display panel 10 includes a plurality of sub-pixels 101, a plurality of data lines 102, a first scan signal line 1031, a second scan signal line 1032, a third scan signal line 1033, a light emission control signal line 1034, a first power supply voltage line 104, a second power supply voltage line 105, a first initialization voltage line 1061, a second initialization voltage line 1062, and a plurality of pads.

[0026] The plurality of sub-pixels 101 are arranged in an array in the row direction (the first direction) and the column direction (the second direction) in the display area 10a of the display panel 10. The plurality of sub-pixels 101 include red sub-pixels, blue sub-pixels, and green sub-pixels, and the red sub-pixels, blue sub-pixels, and green sub-pixels are arranged in a Pentile RGB layout.

[0027] Among them, the plurality of pixels 101 include a first red sub-pixel R1, a first green sub-pixel G1, a first blue sub-pixel B1, a second green sub-pixel G2, a second red sub-pixel R2, a third green sub-pixel G3, a second blue sub-pixel B2, and a fourth green sub-pixel G4 that are arranged in the same row and sequentially arranged in the first direction. The first direction is perpendicular to the second direction. The first red sub-pixel R1, the first green sub-pixel G1, the first blue sub-pixel B1, and the second green sub-pixel G2 serve as a repeating unit, and the second red sub-pixel R2, the third green sub-pixel G3, the second blue sub-pixel B2, and the fourth green sub-pixel G4 serve as a repeating unit. The plurality of repeating units are repeatedly arranged in the row direction.

[0028] It is understandable that the red sub-pixels, blue sub-pixels, and green sub-pixels can be arranged in a standard RGB layout, and the multiple sub-pixels 101 can also include white sub-pixels.

[0029] The first scan signal line 1031, the second scan signal line 1032, the third scan signal line 1033, the light emission control signal line 1034, the first initialization voltage line 1061, and the second initialization voltage line 1062 are all disposed in the display area 10a and extend along the first direction. One first scan signal line 1031, one second scan signal line 1032, one third scan signal line 1033, one light emission control signal line 1034, one first initialization voltage line 1061, and one second initialization voltage line 1062 pass through one row of sub-pixels 101 in the row direction.

[0030] The gate driving circuit 30 is electrically connected to the first scan signal line 1031, the second scan signal line 1032, and the third scan signal line 1033. The gate driving circuit 30 outputs a first scan signal Pscan(n) to the first scan signal line 1031, the gate driving circuit 30 outputs a second scan signal Nscan(n) to the second scan signal line 1032, and the gate driving circuit 30 outputs a third scan signal Nscan(n + 1) to the third scan signal line 1033.

[0031] The light emission control driving circuit 40 is connected to the light emission control signal line 1034, and the light emission control driving circuit 40 outputs a light emission control signal EM to the light emission control signal line 1034.

[0032] The first initialization voltage line 1061 and the second initialization voltage line 1062 can obtain corresponding signals from an external voltage source. The first initialization voltage line 1061 is used to transmit a first initialization voltage Vi1. The second initialization voltage line 1062 is used to transmit a second initialization voltage Vi2.

[0033] Multiple first power voltage lines 104 are disposed in the display area 10a and extend in the second direction. One first power voltage line 104 is disposed between two adjacent data lines 102. The second power voltage line 105 is located in the display area 10a and is disposed along the edge of the display area 10a.

[0034] The first power voltage line 104 and the second power voltage line 105 can obtain corresponding signals from an external voltage source. The first power voltage line 104 is used to transmit a first power voltage VDD, and the first power voltage VDD is a predetermined high-level voltage; the second power voltage line 105 is used to transmit a second power voltage VSS, and the second power voltage VSS is a predetermined low-level voltage.

[0035] A plurality of pads are arranged side by side in a first direction in the bonding area 10c. The source driver chip 20 is bonded to the plurality of pads, and the plurality of pads are electrically connected to a plurality of data lines 102 one-to-one. The source driver chip 20 outputs a data signal DATA to the plurality of data lines 102 through the plurality of pads.

[0036] Among them, the plurality of pads include a first pad 1071, a second pad 1072, a third pad 1073, and a fourth pad 1074. The second pad 1072 is located between the first pad 1071 and the third pad 1073, and the fourth pad 1074 is located on the side of the third pad 1073 away from the second pad 1072.

[0037] Please refer to Figure 2 , the plurality of data lines 102 extend from the display area 10a through the fan-shaped area 10b in a second direction to be electrically connected to the plurality of pads in the bonding area 10c, and the plurality of data lines 102 are insulated from each other. Among them, the plurality of data lines 102 include a first data line 1021, a second data line 1022, a third data line 1023, and a fourth data line 1024. The second data line 1022 and the third data line 1023 are located between the first data line 1021 and the fourth data line 1024, and the first pad 1071 is located on the side of the second data line 1022 and the third data line 1023 close to the first data line 1021.

[0038] In the display area 10a, the second data line 1022 is located between the first data line 1021 and the third data line 1023, the fourth data line 1024 is located on the side of the second data line 1022 and the third data line 1023 away from the first data line 1021, and the distance between the fourth data line 1024 and the third data line 1023 is equal to the distance between the first data line 1021 and the second data line 1022.

[0039] In the display area 10a, the first data line 1021 is electrically connected to the first column of sub-pixels in the display area 10a, the second data line 1022 is electrically connected to the second column of sub-pixels in the display area 10a, the third data line 1023 is electrically connected to the third column of sub-pixels in the display area 10a, the fourth data line 1024 is electrically connected to the fourth column of sub-pixels in the display area 10a. The second column of sub-pixels is located between the first column of sub-pixels and the third column of sub-pixels, and the fourth column of sub-pixels is located on the side of the third column of sub-pixels away from the second column of sub-pixels. Among them, the first column of sub-pixels includes a first red sub-pixel R1, the second column of sub-pixels includes a first green sub-pixel G1, the third column of sub-pixels includes a first blue sub-pixel B1, and the fourth column of sub-pixels includes a second green sub-pixel G2.

[0040] Please refer to Figure 3, each sub-pixel 101 includes a pixel circuit 1011, and each pixel circuit 1011 includes an organic light-emitting diode OLED, a plurality of transistors T1 to T7, and capacitors C1 to C2. A pixel circuit 1011 receives a data signal DATA, a first scan signal Pscan, a second scan signal Nscan(n), a third scan signal Nscan(n + 1), a light emission control signal EM, a first power supply voltage VDD, a second power supply voltage VSS, a first initialization voltage Vi1, and a second initialization voltage Vi2.

[0041] The organic light-emitting diode OLED includes an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The cathode of the organic light-emitting diode OLED is connected to the second power supply voltage VSS.

[0042] The first capacitor C1 includes a first electrode plate and a second electrode plate. The first electrode plate of the first capacitor C1 is connected to the gate of the first transistor T1, the first pole of the third transistor T3, and the first pole of the fourth transistor T4, and the second electrode plate of the first capacitor C1 is connected to the first power supply voltage VDD.

[0043] The second capacitor C2 includes a third electrode plate and a fourth electrode plate. The third electrode plate of the second capacitor C2 is connected to the gate of the first transistor T1, the first pole of the third transistor T3, and the first pole of the fourth transistor T4, and the fourth electrode plate of the second capacitor C2 is connected to the first scan signal Pscan.

[0044] Each of the plurality of transistors T1 to T7 includes a gate, a first pole, and a second pole. The first pole of the plurality of transistors T1 to T7 is one of the source or the drain, and the second pole of the plurality of transistors T1 to T7 is the other of the source and the drain.

[0045] The plurality of transistors T1 to T7 are all thin-film transistors. Each of the transistors T1 to T7 can be either a PMOS transistor or an NMOS transistor, and the active layer of each of the transistors T1 to T7 is either polysilicon or metal oxide.

[0046] Specifically, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all PMOS transistors. The active layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all located in the first semiconductor layer, and the first semiconductor layer is a low-temperature polysilicon active layer. The third transistor T3 and the fourth transistor T4 are both NMOS transistors, and the active layers of the third transistor T3 and the fourth transistor T4 are both located in the second semiconductor layer, and the second semiconductor layer is a metal oxide active layer.

[0047] It should be noted that the characteristics of PMOS transistors and NMOS transistors are different from each other. The third transistor T3 and the fourth transistor T4 are formed of NMOS transistors having relatively good turn-off characteristics, so that leakage of the drive current can be reduced during the light emission period of the organic light emitting diode OLED.

[0048] The gate of the first transistor T1 is connected to the first electrode plate of the first capacitor C1, the third electrode plate of the second capacitor C2, the first pole of the third transistor T3, and the first pole of the fourth transistor T4. The first pole of the first transistor T1 is connected to the first power supply voltage VDD through the fifth transistor T5, and the first pole of the first transistor T1 is connected to the data signal DATA through the second transistor T2. The second pole of the first transistor T1 is connected to the anode of the organic light emitting diode OLED through the sixth transistor T6. The first transistor T1 receives the data signal DATA according to the switching operation of the second transistor T2 and supplies a drive current to the organic light emitting diode OLED.

[0049] The gate of the second transistor T2 receives the first scan signal Pscan. The first pole of the second transistor T2 receives the data signal DATA. The second pole of the second transistor T2 is connected to the first pole of the first transistor T1, and the second pole of the second transistor T2 is connected to the first power supply voltage VDD through the fifth transistor T5. The second transistor T2 is turned on in response to the first scan signal Pscan to perform a switching operation of transmitting the data signal DATA to the first pole of the first transistor T1.

[0050] The gate of the third transistor T3 receives the second scan signal Nscan(n). The first pole of the third transistor T3 is connected to the first pole of the fourth transistor T4 and the gate of the first transistor T1, and the second pole of the third transistor T3 is connected to the second pole of the first transistor T1 and the first pole of the sixth transistor T6. The third transistor T3 is turned on in response to the second scan signal Nscan(n) to connect the gate and the second pole of the first transistor T1, and thus the first transistor T1 is diode-connected. A voltage difference is generated between the gate electrode and the second electrode of the first transistor T1 by the threshold voltage of the first transistor T1, and a data signal DATA having a compensated threshold voltage is supplied to the gate electrode of the first transistor T1, thereby compensating for the threshold voltage deviation of the first transistor T1.

[0051] The gate of the fourth transistor T4 is connected to the third scan signal Nscan(n + 1). The first pole of the fourth transistor T4 is connected to the gate of the first transistor T1, the first electrode plate of the first capacitor C1, the third electrode plate of the second capacitor C2, and the first pole of the third transistor T3. The second pole of the fourth transistor T4 is connected to the first initialization voltage Vi1. The fourth transistor T4 is turned on in response to the third scan signal Nscan(n + 1) to output the first initialization voltage Vi1 to the gate of the first transistor T1, so as to perform the operation of initializing the voltage of the gate of the first transistor T1.

[0052] The gate of the fifth transistor T5 is connected to the emission control signal EM. The first pole of the fifth transistor T5 is connected to the first power supply voltage VDD. The second pole of the fifth transistor T5 is connected to the first pole of the first transistor T1 and the second pole of the second transistor T2.

[0053] The gate of the sixth transistor T6 is connected to the emission control signal EM. The first pole of the sixth transistor T6 is connected to the second pole of the first transistor T1 and the second pole of the third transistor T3. The second pole of the sixth transistor T6 is connected to the anode of the organic light-emitting diode OLED and the first pole of the seventh transistor T7.

[0054] The gate of the seventh transistor T7 is connected to the first scan signal Pscan. The first pole of the seventh transistor T7 is connected to the anode of the organic light-emitting diode OLED and the second pole of the sixth transistor T6. The second pole of the seventh transistor T7 is connected to the second initialization voltage Vi2. The seventh transistor T7 is turned on in response to the first scan signal Pscan to transmit the first scan signal Pscan to the anode of the organic light-emitting diode OLED, realizing the initialization of the anode of the organic light-emitting diode OLED.

[0055] Please refer to Figure 4 , the first red sub-pixel R1 includes a first pixel circuit 1012, and the first pixel circuit 1012 is electrically connected to the first data line 1021; the first green sub-pixel G1 includes a second pixel circuit 1013, and the second pixel circuit 1013 is electrically connected to the second data line 1022; the first blue sub-pixel B1 includes a third pixel circuit 1014, and the third pixel circuit 1014 is electrically connected to the third data line 1023; the second green sub-pixel G2 includes a fourth pixel circuit 1015, and the fourth pixel circuit 1015 is electrically connected to the fourth data line 1024.

[0056] Among them, in the display area 10a, at least part of the first pixel circuit 1012 is located on the side of the first data line 1021 away from the second data line 1022, at least part of the second pixel circuit 1013 and at least part of the third pixel circuit 1014 are located between the second data line 1022 and the third data line 1023, and at least part of the fourth pixel circuit 1015 is located on the side of the fourth data line 1024 away from the third data line 1023.

[0057] Specifically, the first pixel circuit 1012 is divided into a first part and a second part. The area occupied by the second part of the first pixel circuit 1012 is larger than the area occupied by the first part of the first pixel circuit 1012. The first part of the first pixel circuit 1012 overlaps with the first data line 1021, and the second part of the first pixel circuit 1012 is located on the side of the first data line 1021 away from the second data line 1022. Therefore, the first pixel circuit 1012 is mainly located on the side of the first data line 1021 away from the second data line 1022.

[0058] The second pixel circuit 1013 is also divided into a first part and a second part. The area occupied by the second part of the second pixel circuit 1013 is larger than the area occupied by the first part of the second pixel circuit 1013. The first part of the first pixel circuit 1012 is the same as the first part of the second pixel circuit 1013, and the second part of the second pixel circuit 1013 is the same as the second part of the first pixel circuit 1012. The first part of the second pixel circuit 1013 overlaps with the second data line 1022, and the second part of the second pixel circuit 1013 is located on the side of the second data line 1022 away from the first data line 1021. The first pixel circuit 1012 and the second pixel circuit 1013 are symmetrically arranged with respect to the center line between the first data line 1021 and the second data line 1022.

[0059] The third pixel circuit 1014 is also divided into a first part and a second part. The first part of the third pixel circuit 1014 is the same as the first part of the second pixel circuit 1013, and the second part of the third pixel circuit 1014 is the same as the second part of the second pixel circuit 1013. The area occupied by the second part of the third pixel circuit 1014 is larger than the area occupied by the first part of the third pixel circuit 1014. The first part of the third pixel circuit 1014 is arranged overlapping with the third data line 1023. The second part of the third pixel circuit 1014 is arranged adjacent to the second part of the second pixel circuit 1013, and both are arranged between the second data line 1022 and the third data line 1023. The second pixel circuit 1013 and the third pixel circuit 1014 are symmetrically arranged about the center line between the second data line 1022 and the third data line 1023. The second pixel circuit 1013 and the third pixel circuit 1014 share a first power supply voltage line 104, and the first power supply voltage line 104 shared by the second pixel circuit 1013 and the third pixel circuit 1014 is located between the second data line 1022 and the third data line 1023.

[0060] The fourth pixel circuit 1015 is also divided into a first part and a second part. The area occupied by the second part of the fourth pixel circuit 1015 is larger than the area occupied by the first part of the fourth pixel circuit 1015. The first part of the fourth pixel circuit 1015 is the same as the first part of the third pixel circuit 1014, and the second part of the fourth pixel circuit 1015 is the same as the second part of the third pixel circuit 1014. The first part of the fourth pixel circuit 1015 is arranged overlapping with the fourth data line 1024. The second part of the fourth pixel circuit 1015 is located on the side of the fourth data line 1024 away from the third data line 1023. The fourth pixel circuit 1015 and the third pixel circuit 1014 are symmetrically arranged about the center line between the third data line 1023 and the fourth data line 1024.

[0061] Since each pixel circuit 1011 includes P-type transistors and N-type transistors and two different types of scanning signals need to be input into the P-type transistors and N-type transistors, the wiring in each pixel circuit is complex. By setting the adjacent pixel circuits to be mirror-symmetric, the space required for arranging multiple pixel circuits is reduced.

[0062] It can be understood that all parts of a second pixel circuit 1013 and all parts of a third pixel circuit 1014 can also be located between the second data line 1022 and the third data line 1023, all parts of a first pixel circuit 1012 are located on the side of the first data line 1021 away from the second data line 1022, and all parts of a fourth pixel circuit 1015 are located on the side of the fourth data line 1024 away from the third data line 1023.

[0063] Since, for exampleFigure 4 The layout of the pixel circuit and the data lines shown results in the distance between the first data line 1021 and the second data line 1022 in the display area being smaller than the distance between the third data line 1023 and the second data line 1022, and the distance between the fourth data line 1024 and the third data line 1023 being smaller than the distance between the third data line 1023 and the second data line 1022.

[0064] The distance between the first data line 1021 and the second data line 1022 is different from the distance between the third data line 1023 and the second data line 1022, and the distance between the third data line 1023 and the second data line 1022 is different from the distance between the fourth data line 1024 and the third data line 1023. This causes the parasitic capacitance between the first data line 1021 and the second data line 1022 to be different from the parasitic capacitance between the third data line 1023 and the second data line 1022, and the parasitic capacitance between the third data line 1023 and the second data line 1022 is also different from the parasitic capacitance between the fourth data line 1024 and the third data line 1023. That is, the parasitic capacitances between adjacent data lines are inconsistent, and the inconsistent parasitic capacitances will affect the display effect of the display panel.

[0065] To address the problem of inconsistent parasitic capacitances between adjacent data lines, in this application, the first pad 1071 is electrically connected to the first data line 1021, the second pad 1072 is electrically connected to the third data line 1023, the third pad 1073 is electrically connected to the second data line 1022, and the fourth pad 1074 is electrically connected to the fourth data line 1024, so as to facilitate the distance between the first data line 1021 and the second data line 1022 in the area between the display area 10a and the bonding area 10c being greater than the distance between the second data line 1022 and the third data line 1023, and the distance between the fourth data line 1024 and the third data line 1023 being greater than the distance between the third data line 1023 and the second data line 1022. Furthermore, this makes the parasitic capacitances between the first data line 1021 and the second data line 1022, between the second data line 1022 and the third data line 1023, and between the third data line 1023 and the fourth data line 1024 tend to be consistent, thereby ensuring the display effect of the display panel.

[0066] Specifically, as Figure 2As shown, in the area between the fan-shaped area 10b and the display area 10a, the third data line 1023 intersects with the second data line 1022, and in the fan-shaped area 10b, the third data line 1023 is located between the second data line 1022 and the first data line 1021, so that the second pad 1072 is electrically connected to the third data line 1023, and the third pad 1073 is electrically connected to the second data line 1022. Furthermore, in the fan-shaped area 10b, the distance between the first data line 1021 and the second data line 1022 is greater than the distance between the second data line 1022 and the third data line 1023, and the distance between the third data line 1023 and the fourth data line 1024 is greater than the distance between the third data line 1023 and the second data line 1022.

[0067] In the fan-shaped area 10b, the distance between the first data line 1021 and the third data line 1023, the distance between the third data line 1023 and the second data line 1022, and the distance between the second data line 1022 and the fourth data line 1024 are equal to each other.

[0068] In the area between the display area 10a and the fan-shaped area 10b, one of the second data line 1022 and the third data line 1023 includes a first trace segment 10231 and a second trace segment 10232. The second trace segment 10232 is located on a different metal layer from the first trace segment 10231 and is electrically connected. The other of the second data line 1022 and the third data line 1023 includes a third trace segment 10221. The third trace segment 10221 is located on a different metal layer from the second trace segment 10232, and the third trace segment 10221 is electrically insulated from and intersects with the second trace segment 10232. In the thickness direction of the display panel 10, the second trace segment 10232 and the third trace segment 10221 are respectively located on opposite sides of the first trace segment 10231, so as to minimize the parasitic capacitance formed by the front intersection between the second trace segment 10232 and the third trace segment 10221 and avoid the problem of uneven display caused by too large parasitic capacitance generated by the front intersection.

[0069] Specifically, the second data line 1022 includes the third trace segment 10221. The third trace segment 10221 extends in a direction away from the first data line 1021, and the third trace segment 10221 is parallel to the first direction; the third data line 1023 includes a first trace segment 10231 and a second trace segment 10232 that are located on different metal layers and are electrically connected. The third trace segment 10221 and the second trace segment 10232 are respectively located on opposite sides of the first trace segment 10231. The first trace segment 10231 extends in a direction close to the first data line 1021, the first trace segment 10231 is parallel to the first direction, and the second trace segment 10232 is parallel to the second direction.

[0070] It can be understood that the second data line 1022 may also include a first trace segment 10231 and a second trace segment 10232 located in different metal layers and electrically connected, while the third data line 1023 includes a third trace segment 10221.

[0071] The display panel 10 further includes a substrate 11, and the third trace segment 10221 is located between the first trace segment 10231 and the substrate 11.

[0072] In the thickness direction of the display panel 10, the first data line 1021 and the second data line 1022 in the fan-shaped area 10b are located in the same layer and made of the same material, and the third data line 1023 and the fourth data line 1024 in the fan-shaped area 10b are located in the same layer and made of the same material, which is beneficial to routing using different metal layers in the fan-shaped area 10b and reducing the risk of short circuit between the data lines in the fan-shaped area.

[0073] In the display area 10a, the first data line 1021, the second data line 1022, the third data line 1023, and the fourth data line 1024 are all arranged in the same layer and made of the same material to simplify the manufacturing process.

[0074] In the thickness direction of the display panel 10, the first data line 1021, the second data line 1022, the third data line 1023, and the fourth data line 1024 located in the display area 10a are on the side of the second trace segment 10232 away from the substrate 11.

[0075] As Figure 5 shown, the display panel 10 includes a substrate 11, a buffer layer 12, a first semiconductor layer 13, a first insulating layer 14, a first conductive layer 15, a second insulating layer 16, a second conductive layer 17, a third insulating layer 18, a second semiconductor layer 19, a fourth insulating layer 21, a third conductive layer 22, a fifth insulating layer 23, a fourth conductive layer 24, a first planarization layer 25, a fifth conductive layer 26, a second planarization layer 27, a first electrode layer 28, a pixel definition layer 29, an organic light-emitting layer 31, and a second electrode layer 32 stacked in sequence.

[0076] Among them, the buffer layer 12, the first insulating layer 14, the second insulating layer 16, the third insulating layer 18, the fourth insulating layer 21, and the fifth insulating layer 23 all have inorganic film layers, and the first planarization layer 25 and the second planarization layer 27 are both organic film layers with a thickness of 1 micron - 3 microns.

[0077] The first data line 1021, the second data line 1022, the third data line 1023, and the fourth data line 1024 located in the display area 10a are all located in the fifth conductive layer 26. The first data line 1021 and the second data line 1022 in the fan-shaped area 10b, and the third segment 10221 of the second data line 1022 located between the fan-shaped area 10b and the display area 10a are all located in the first conductive layer 15. The third data line 1023 and the fourth data line 1024 in the fan-shaped area 10b, and the first segment 10231 of the third data line 1023 located between the fan-shaped area 10b and the display area 10a are located in the second conductive layer 17. The second segment 10232 of the third data line 1023 located between the fan-shaped area 10b and the display area 10a is located in the fourth conductive layer 24.

[0078] The following description is combined with Figure 5 the specific film stack structure of the display panel shown Figure 4 the planar layout of the second pixel circuit 1013 and the signal lines electrically connected to the second pixel circuit 1013 in the figure. According to the principle of mirror symmetry, the planar layouts of the third pixel circuit 1014, the first pixel circuit 1012, and the fourth pixel circuit 1015 can be obtained.

[0079] The first semiconductor layer 13 is the active layer for forming the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. The preparation material of the first semiconductor layer 13 is low-temperature polycrystalline silicon.

[0080] As Figure 6A shown, the first semiconductor layer 13 includes a first vertical portion 131, a second vertical portion 132, a third vertical portion 133, a fourth vertical portion 134, a first horizontal extension portion 135, and a second horizontal extension portion 136. The first vertical portion 131, the second vertical portion 132, the third vertical portion 133, and the fourth vertical portion 134 extend substantially in the column direction, and the first horizontal extension portion 135 and the second horizontal extension portion 136 extend substantially in the row direction.

[0081] The first horizontal extension portion 135 is connected between the first vertical portion 131 and the second vertical portion 132. The second vertical portion 132 connects the first horizontal extension portion 135 and the second horizontal extension portion 136. The third vertical portion 133 is connected to the side of the second horizontal extension portion 136 away from the second vertical portion 132. The fourth vertical portion 134 is separated from the first vertical portion 131, the second vertical portion 132, the third vertical portion 133, the first horizontal extension portion 135, and the second horizontal extension portion 136. The first vertical portion 131 and the second vertical portion 132 are located at the opposite edges of the pixel circuit, and the fourth vertical portion 134 is adjacent to the first vertical portion 131.

[0082] The first horizontal extension portion 135 includes the channel of the first transistor T1. The first vertical portion 131 includes the channels of the second transistor T2 and the fifth transistor T5. The second vertical portion 132 includes the channel of the sixth transistor T6. The fourth vertical portion 134 includes the channel of the seventh transistor T7.

[0083] As Figure 6B shown, the first conductive layer 15 includes a first scan signal line 1031, a gate 151 of the first transistor T1, and a light emission control signal line 1034. Both the first scan signal line 1031 and the light emission control signal line 1034 extend in the row direction. The gate 151 of the first transistor T1 is located between the first scan signal line 1031 and the light emission control signal line 1034.

[0084] The first scan signal line 1031 includes the gates of the second transistor T2 and the seventh transistor T7. The light emission control signal line 1034 includes the gates of the fifth transistor T5 and the sixth transistor T6.

[0085] The gate 151 of the first transistor T1 overlaps with the first horizontal extension portion 135. The first scan signal line 1031 intersects with the first vertical portion 131 and the fourth vertical portion 134. The light emission control signal line 1034 intersects with the first vertical portion 131 and the second vertical portion 132.

[0086] As Figure 6C shown, the second conductive layer 17 includes a first initialization voltage line 1061, a third lower scan signal line 171, a second lower scan signal line 172, and a second electrode plate 173. The first initialization voltage line 1061, the third lower scan signal line 171, and the second lower scan signal line 172 all extend in the row direction, and the third lower scan signal line 171 is located between the first initialization voltage line 1061 and the second lower scan signal line 172. The second electrode plate 173 is located on the side of the second lower scan signal line 172 away from the third lower scan signal line 171.

[0087] The third lower scan signal line 171 includes the lower gate of the fourth transistor T4. The second lower scan signal line 172 includes the lower gate of the third transistor T3.

[0088] The first initialization voltage line 1061, the third lower scan signal line 171 intersect with the fourth vertical portion 134. The second lower scan signal line 172 intersects with the first vertical portion 131.

[0089] The second electrode plate 173 overlaps with the gate 151 of the first transistor T1. The gate 151 of the first transistor T1 is the first electrode plate of the first capacitor C1. The middle position of the second electrode plate 173 includes an opening 173a.

[0090] As Figure 6DAs shown, the second semiconductor layer 19 is the active layer for forming the third transistor T3 and the fourth transistor T4. The material for preparing the second semiconductor layer 19 is a metal oxide, and the metal oxide includes indium gallium zinc oxide.

[0091] The second semiconductor layer 19 includes a fifth vertical portion 191 that extends in the column direction. The fifth vertical portion 191 includes the channels of the third transistor T3 and the fourth transistor T4.

[0092] The fifth vertical portion 191 intersects with the third lower scan signal line 171 and the second lower scan signal line 172. The fifth vertical portion 191 intersects with the first scan signal line 1031, and the overlapping part of the fifth vertical portion 191 and the first scan signal line 1031 is the third electrode plate of the second capacitor C2, and the overlapping part of the first scan signal line 1031 and the fifth vertical portion 191 is the fourth electrode plate of the second capacitor C2.

[0093] As Figure 6E shown, the third conductive layer 22 includes a third upper scan signal line 221 and a second upper scan signal line 222, and both the third upper scan signal line 221 and the second upper scan signal line 222 extend in the row direction.

[0094] The third upper scan signal line 221 is arranged corresponding to the third lower scan signal line 171, and the third upper scan signal line 221 overlaps with the third lower scan signal line 171. The third upper scan signal line 221 is electrically connected to the corresponding third lower scan signal line 171 and they jointly form the third scan signal line 1033.

[0095] The second upper scan signal line 222 is arranged corresponding to the second lower scan signal line 172, and the second upper scan signal line 222 overlaps with the second lower scan signal line 172. The second upper scan signal line 222 is electrically connected to the corresponding second lower scan signal line 172 and they jointly form the second scan signal line 1032.

[0096] The third upper scan signal line 221 includes the upper gate of the fourth transistor T4, and the second upper scan signal line 222 includes the upper gate of the third transistor T3.

[0097] Both the third upper scan signal line 221 and the second upper scan signal line 222 intersect with the fifth vertical portion 191.

[0098] As Figure 6F shown, the display panel 10 includes first contact holes VIA1 to eighth contact holes VIA8, and the first contact holes VIA1 to eighth contact holes VIA8 are used to connect the fourth conductive layer 24 to at least one of the first semiconductor layer 13, the first conductive layer 15, and the second conductive layer 17.

[0099] The first contact hole VIA1 exposes a portion of the first vertical portion 131. The first pole of the second transistor T2 and the first lead 241 of the fourth conductive layer 24 below are electrically connected through the first contact hole VIA1. The first contact hole VIA1 penetrates through the first insulating layer 14 to the fifth insulating layer 23.

[0100] The second contact hole VIA2 exposes a portion of the fourth vertical portion 134. The second pole of the seventh transistor T7 and the second initialization voltage line 1062 of the fourth conductive layer 24 below are electrically connected through the second contact hole VIA2. The second contact hole VIA2 penetrates through the first insulating layer 14 to the fifth insulating layer 23.

[0101] The third contact hole VIA3 is provided corresponding to the opening 173a. The gate 151 of the first transistor T1 and the second lead 242 in the fourth conductive layer 24 below are electrically connected through the third contact hole VIA3 and the opening 173a. The third contact hole VIA3 penetrates through the first insulating layer 14 to the fifth insulating layer 23.

[0102] The fourth contact hole VI4 exposes a portion of the second electrode plate 173. The second electrode plate 173 and the third lead 243 in the fourth conductive layer 24 below are electrically connected through the fourth contact hole VI4. The third lead 243 transmits the first power supply voltage VDD so that the second electrode plate 173 is connected to the first power supply voltage VDD. The fourth contact hole VI4 penetrates through the third insulating layer 18 to the fifth insulating layer 23.

[0103] The fifth contact hole VI5 exposes a portion of the first horizontal extension portion 135. The second pole of the first transistor T1 and the fourth lead 244 in the fourth conductive layer 24 below are electrically connected through the fifth contact hole VI5. The fifth contact hole VI5 penetrates through the first insulating layer 14 to the fifth insulating layer 23.

[0104] The sixth contact hole VI6 exposes a portion of the first initialization voltage line 1061. The first initialization voltage line 1061 and the fifth lead 245 in the fourth conductive layer 24 below are electrically connected through the sixth contact hole VI6 to transmit the first initialization voltage VI1 transmitted by the first initialization voltage line 1061 to the fifth lead 245. The sixth contact hole VI6 penetrates through the second insulating layer 16 to the fifth insulating layer 23.

[0105] The seventh contact hole VI7 exposes a portion of the first vertical portion 131. The first pole of the fifth transistor T5 and the third lead 243 in the fourth conductive layer 24 below are electrically connected through the seventh contact hole VI7 so that the first pole of the fifth transistor T5 is connected to the first power supply voltage VDD. The seventh contact hole VI6 penetrates through the first insulating layer 14 to the fifth insulating layer 23.

[0106] The eighth contact hole VI8 exposes a portion of the second horizontal extension 136. The second pole of the sixth transistor T6 is electrically connected to the sixth lead 246 in the fourth conductive layer 24 below through the eighth contact hole VI8.

[0107] As Figure 6G shown, the display panel 10 includes ninth to eleventh contact holes VIA9 - VIA11 for overlapping the fourth conductive layer 24 and the second semiconductor layer 19.

[0108] The ninth contact hole VIA9 exposes the fifth vertical portion 191. The second pole of the fourth transistor T4 is electrically connected to the second initialization voltage line 1062 in the fourth conductive layer 24 below through the ninth contact hole VIA9.

[0109] The tenth contact hole VIA10 exposes the fifth vertical portion 191. The second lead 242 in the fourth conductive layer 24 below is electrically connected to the first pole of the fourth transistor T4 and the first pole of the third transistor T3 through the tenth contact hole VIA10, so that the second lead 242 bridges the gate 151 of the first transistor T1 and the first poles of the fourth transistor T4 and the third transistor T3.

[0110] The eleventh contact hole VIA11 exposes the fifth vertical portion 191. The fourth lead 244 in the fourth conductive layer 24 below is electrically connected through the eleventh contact hole VIA11, so that the fourth lead 244 bridges the second pole of the first transistor T1 and the second pole of the third transistor T3.

[0111] As Figure 6H shown, the fourth conductive layer 24 includes first to sixth leads 241 - 246 and a second initialization voltage line 1062.

[0112] The second initialization voltage line 1062 extends in the row direction and intersects the fourth vertical portion 134, the first vertical portion 131, and the fifth vertical portion 191.

[0113] The first lead 241 overlaps with the first vertical portion 131. The second lead 242 is inclined, one end of the second lead 242 overlaps with the fifth vertical portion 191, the other end of the second lead 242 overlaps with the gate of the first transistor T1, and one end of the second lead 242 is opposite to the other end. The third lead 243 is in an L - shaped block and overlaps with the second electrode plate 173 and the first vertical portion 131. The fourth lead 244 overlaps with the fifth vertical portion 191 and the first horizontal extension 135. The fifth lead 245 overlaps with the first initialization voltage line 1061. The sixth lead 246 overlaps with the second horizontal extension 136.

[0114] AsFigure 6I As shown, the first planarization layer 25 includes the twelfth contact hole VIA12 to the fourteenth contact hole VIA14. The twelfth contact hole VIA12 to the fourteenth contact hole VIA14 are used to connect the fourth conductive layer 24 and the fifth conductive layer 26.

[0115] The twelfth contact hole VIA12 is overlapped with the first lead 241. The twelfth contact hole VIA12 is used to electrically connect the first lead 241 and the data line 102 of the fifth conductive layer 26 below, so that the first pole of the second transistor T2 is electrically connected to the data line 102.

[0116] The thirteenth contact hole VIA13 is overlapped with the sixth lead 246. The thirteenth contact hole VIA13 is used to electrically connect the sixth lead 246 and the seventh lead 261 of the fifth conductive layer 26 below, so that the seventh lead 261 is electrically connected to the second pole of the sixth transistor T6.

[0117] The fourteenth contact hole VIA14 is overlapped with the third lead 243. The fourteenth contact hole VIA14 is used to electrically connect the third lead 243 and the first power supply voltage line 104 of the fifth conductive layer 26 below, so that the third lead 243 inputs the first power supply voltage VDD.

[0118] As Figure 6J shown, the fifth conductive layer 26 includes the first power supply voltage line 104, the data line 102, and the seventh lead 261. Both the first power supply voltage line 104 and the data line 102 extend in the column direction.

[0119] The data line 102 is overlapped with the first vertical portion 131. The first power supply voltage line 104 is overlapped with the fifth vertical portion 191, the third lead 243, etc. The seventh lead 261 is overlapped with the sixth lead 246.

[0120] The description of the above embodiments is only used to help understand the technical solution and its core idea of the present application; those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that, The display panel has a display area and a bonding area, and the display panel includes: A first data line extending from the display area to the bonding area and electrically connected to the first column of sub-pixels in the display area; A second data line extending from the display area to the bonding area, located on one side of the first data line, and electrically connected to the second column of sub-pixels in the display area, where the second column of sub-pixels is located on one side of the first column of sub-pixels; and A third data line extending from the display area to the bonding area, electrically connected to the third column of sub-pixels in the display area, and the second column of sub-pixels is located between the first column of sub-pixels and the third column of sub-pixels. In the display area, the second data line is located between the first data line and the third data line, and the distance between the first data line and the second data line is less than the distance between the third data line and the second data line; A first pad provided in the bonding area and located on the side of the second data line and the third data line close to the first data line, and the first pad is electrically connected to the first data line; A second pad provided in the bonding area and electrically connected to the third data line; A third pad provided in the bonding area and electrically connected to the second data line. In the direction perpendicular to the display area pointing to the bonding area, the second pad is located between the first pad and the third pad; and A source driver chip, and the source driver chip is connected to the first pad, the second pad, and the third pad.

2. The display panel according to claim 1, wherein The display panel further has a fan-shaped area located between the display area and the bonding area; In the area between the fan-shaped area and the display area, the third data line intersects with the second data line; In the fan-shaped area, the third data line is located between the second data line and the first data line.

3. The display panel according to claim 2, wherein In the area between the display area and the fan-shaped area, one of the second data line and the third data line includes a first trace segment and a second trace segment. The second trace segment and the first trace segment are located in different metal layers and are electrically connected. The other of the second data line and the third data line includes a third trace segment. The third trace segment and the second trace segment are located in different metal layers, and the third trace segment is electrically insulated from and intersects with the second trace segment; Wherein, in the thickness direction of the display panel, the second trace segment and the third trace segment are respectively located on opposite sides of the first trace segment.

4. The display panel according to claim 3, wherein, The display panel further includes a substrate, and the third trace segment is located between the first trace segment and the substrate.

5. The display panel according to claim 4, wherein, The display panel further includes: A fourth data line extends from the display area to the bonding area. The fourth data line is electrically connected to the sub-pixels in the fourth column of the display area. The sub-pixels in the fourth column are located on the side of the sub-pixels in the third column away from the sub-pixels in the second column. The fourth data line is located on the side of the second data line and the third data line away from the first data line. In the display area, the distance between the fourth data line and the third data line is less than the distance between the third data line and the second data line; and A fourth pad is disposed in the bonding area, on the side of the third pad away from the second pad. The fourth pad is electrically connected to the fourth data line and is connected to the source driver chip.

6. The display panel according to claim 5, wherein In the thickness direction of the display panel, in the fan-shaped area, the first data line and the second data line are on the same layer and are made of the same material; In the thickness direction of the display panel, in the fan-shaped area, the third data line and the fourth data line are on the same layer and are made of the same material.

7. The display panel according to claim 5, characterized in that, In the display area, the first data line, the second data line, the third data line, and the fourth data line are all on the same layer and are made of the same material.

8. The display panel according to claim 7, wherein In the thickness direction of the display panel, the first data line, the second data line, the third data line, and the fourth data line in the display area are on the side of the second trace segment away from the substrate.

9. The display panel according to claim 2, characterized in that, In the fan-shaped area, the distance between the first data line and the third data line is equal to the distance between the third data line and the second data line.

10. The display panel according to claim 1, wherein The display panel further includes: A first pixel circuit located in the display area and electrically connected to the first data line; A second pixel circuit located in the display area and electrically connected to the second data line; and A third pixel circuit located in the display area and electrically connected to the third data line; Wherein, in the display area, at least part of the first pixel circuit is located on the side of the first data line away from the second data line, and at least part of the second pixel circuit and at least part of the third pixel circuit are located between the second data line and the third data line.

11. The display panel according to claim 10, wherein In the display area, the first pixel circuit and the second pixel circuit are symmetrically arranged with respect to the center line between the first data line and the second data line, and the second pixel circuit and the third pixel circuit are symmetrically arranged with respect to the center line between the second data line and the third data line.

12. The display panel according to claim 10 or 11, characterized in that, The second pixel circuit and the third pixel circuit share a power signal line, and the power signal line shared by the second pixel circuit and the third pixel circuit is located between the second data line and the third data line.

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