Three-dimensional memory and methods of making the same

Abstract

Embodiments of the present application provide a three-dimensional memory and a manufacturing method thereof. The three-dimensional memory comprises at least one storage surface, wherein the storage surface is provided with a stack structure, a plurality of first gate line slit structures penetrating through the stack structure, and a plurality of isolation structures penetrating through the stack structure. The plurality of first gate line slit structures extend along a first direction to divide the storage surface into a plurality of storage blocks. The isolation structures are located at the edge of the storage surface and extend along a second direction to contact the plurality of first gate line slit structures. The first direction intersects the second direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a three-dimensional memory and its fabrication method. Background Technology

[0002] Three-dimensional memory, such as 3D NAND flash memory, has been increasingly widely used in electronic products due to its advantages of low power consumption and high integration density. During the manufacturing process of 3D memory, the presence of stress can cause warping deformation of the wafer used to form the memory; and as the thickness of the 3D memory increases, the warping of the wafer also becomes greater, thus affecting the performance and yield of the 3D memory. Summary of the Invention

[0003] To address one or more existing technical problems, embodiments of the present invention propose a three-dimensional memory and a method for manufacturing the same.

[0004] An embodiment of the present invention provides a three-dimensional memory, comprising: at least one storage surface; wherein the storage surface is provided with a stacked structure, multiple first gate line slit structures penetrating the stacked structure, and multiple isolation structures penetrating the stacked structure; wherein,

[0005] The multiple first gate line slit structures extend along a first direction to divide the memory surface into multiple memory blocks;

[0006] The isolation structure is located at the edge of the storage surface and extends along the second direction to contact the plurality of first gate line slit structures, wherein the first direction intersects the second direction.

[0007] In the above scheme, at least one of the straight lines containing the first gate line slit structure extends beyond the straight line containing the corresponding isolation structure along the first direction;

[0008] And / or,

[0009] At least one of the isolation structures lies on a straight line that extends beyond the straight line of the corresponding first gate line slit structure along a second direction.

[0010] In the above scheme, the stacking structure includes a step area, a first dummy area and a second dummy area located on opposite sides of the step area, a first core storage area located between the step area and the first dummy area, and a second core storage area located between the step area and the second dummy area; wherein, the plurality of isolation structures are respectively disposed in the first dummy area and the second dummy area.

[0011] In the above scheme, multiple storage channel holes are provided in the first core storage area and the second core storage area; multiple virtual channel holes are provided in the first virtual area and the second virtual area.

[0012] In the above scheme, the storage surface is further provided with multiple second gate line slit structures that penetrate the stacked structure;

[0013] The second gate line slit structure extends along the first direction and includes a plurality of spaced sub-gate line slit structures.

[0014] In the above scheme, each of the isolation structures is in contact with the plurality of second gate line slit structures.

[0015] In the above scheme, each storage block is provided with M rows of storage channel holes; M is a positive integer greater than 1.

[0016] In the above scheme, the stacking structure includes at least a first sub-stacking structure and a second sub-stacking structure located on the first sub-stacking structure;

[0017] The first sub-stack structure is provided with a first sub-channel hole;

[0018] The second sub-stacking structure is provided with a second sub-channel hole;

[0019] The first sub-channel hole and the second sub-channel hole are connected in a third direction; the third direction is parallel to the stacking direction of the stacked structure.

[0020] In the above scheme, the isolation structure is integrally formed with the first gate line slit structure.

[0021] This invention also provides a method for manufacturing a three-dimensional memory, the three-dimensional memory including at least one storage surface, the method for forming the storage surface including:

[0022] Forming a stacked structure;

[0023] Multiple first gate line slit structures penetrating the stacked structure and multiple isolation structures penetrating the stacked structure are formed; wherein...

[0024] The multiple first gate line slit structures extend along a first direction to divide the memory surface into multiple memory blocks;

[0025] The isolation structure is located at the edge of the storage surface and extends along the second direction to contact the plurality of first gate line slit structures, wherein the first direction intersects the second direction.

[0026] In the above scheme, the first gate line slit structure is integrally formed with the isolation structure.

[0027] In the above scheme, forming a stacked structure includes:

[0028] A first sub-stack structure is formed on the substrate;

[0029] A second sub-stack structure is formed on the first sub-stack structure; the first sub-stack structure and the second sub-stack structure form the stack structure.

[0030] The method further includes: forming a first sub-channel hole in the first sub-stacking structure before forming the second sub-stacking structure;

[0031] After the second sub-stack structure is formed, a second sub-channel hole is formed in the second sub-stack structure; the first sub-channel hole and the second sub-channel hole are connected in a third direction; the third direction is parallel to the stacking direction of the stack structure.

[0032] In the above scheme, the method further includes: forming a sacrificial layer in the first sub-channel hole before forming the second sub-stack structure.

[0033] In the above scheme, the formation of multiple first gate line slit structures penetrating the stacked structure and multiple isolation structures penetrating the stacked structure includes:

[0034] Forming a first trench and a second trench that penetrate the stacked structure;

[0035] An insulating layer is formed covering the sidewalls and bottom of the first trench and the second trench;

[0036] Semiconductor material is filled into the insulating layer to form the first gate line slit structure and the isolation structure, respectively.

[0037] This invention provides a three-dimensional memory and its fabrication method. The three-dimensional memory includes: at least one memory surface; a stacked structure disposed in the memory surface; multiple first gate line slits penetrating the stacked structure and multiple isolation structures penetrating the stacked structure; wherein the multiple first gate line slits extend along a first direction, dividing the memory surface into multiple memory blocks; the isolation structures are located at the edge of the memory surface and extend along a second direction, contacting the multiple first gate line slits, the first direction intersecting the second direction. In this invention, by forming multiple intersecting first gate line slits and multiple isolation structures in the memory surface, multiple closed memory blocks are formed after the multiple isolation structures contact the multiple first gate line slits, thereby avoiding short circuits between adjacent memory blocks in the same memory surface; thus achieving electrical isolation between multiple memory blocks in the same memory surface; and improving the reliability and yield of the three-dimensional memory. Attached Figure Description

[0038] Figure 1a This is a top view of a three-dimensional memory provided in an embodiment of the present invention;

[0039] Figure 1b As described in the embodiments of the present invention Figure 1a A schematic diagram of the cross-sectional structure of the AA' position in the XOZ plane;

[0040] Figure 1c As described in the embodiments of the present invention Figure 1a A schematic diagram of the cross-sectional structure of the BB' position in the YOZ plane;

[0041] Figure 2 This is a schematic diagram of the structure of a three-dimensional memory provided in an embodiment of the present invention;

[0042] Figure 3a A top view of another three-dimensional memory structure provided in an embodiment of the present invention;

[0043] Figure 3b This is a top view schematic diagram of a first gate line slit structure and isolation structure provided in an embodiment of the present invention;

[0044] Figure 3c As described in the embodiments of the present invention Figure 3a A schematic diagram of the cross-sectional structure of the CC' position in the XOZ plane;

[0045] Figures 4a-4d A top view schematic diagram of four types of first gate line slit structures in contact with isolation structures provided in embodiments of the present invention;

[0046] Figure 5 This is a schematic diagram of a first gate line slit structure and a second gate line slit structure provided in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram illustrating the positional relationship between the storage surface and the isolation structure in a three-dimensional memory, provided by an embodiment of the present invention.

[0048] Figure 7 This is a schematic diagram of the structure of a memory material layer in a memory channel hole provided in an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram illustrating the relationship between a first sub-stack structure and a second sub-stack structure provided in an embodiment of the present invention;

[0050] Figures 9a-9h This is a cross-sectional schematic diagram illustrating the implementation process of a three-dimensional memory fabrication method provided in an embodiment of the present invention. Detailed Implementation

[0051] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid obscuring the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0053] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0054] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And when a second element, component, area, layer, or portion is discussed, it does not imply that the first element, component, area, layer, or portion necessarily exists in this invention. In addition, terms like "first," "second," etc., can be used to distinguish similar objects, rather than to describe a specific order or sequence.

[0055] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0056] To fully understand this invention, detailed steps and structures will be presented in the following description to illustrate the technical solution of this invention. Preferred embodiments of the invention are described in detail below; however, in addition to these detailed descriptions, the invention may have other embodiments.

[0057] In this article, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added to the substrate can be patterned, or it can remain unpatterned.

[0058] The term "layer" in this document can refer to a portion of material comprising a region of a certain thickness. A layer may extend over the entire underlying or overlying structure, or it may have a smaller extent than the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that continuous structure.

[0059] The three-dimensional memory in the embodiments of the present invention includes, but is not limited to, 3D NAND type memory.

[0060] In some embodiments of the present invention, the three-dimensional memory may include peripheral circuitry and a memory cell array; wherein, the peripheral circuitry may include any suitable digital, analog, and / or mixed-signal circuitry configured to facilitate various operations such as read, write, and erase operations of the memory. For example, the peripheral circuitry may include control logic (e.g., control circuitry or controller), a data buffer, a decoder (also called a decoder), a driver, and read / write circuitry. When the control logic receives read / write operation commands and address data, under the action of the control logic, the decoder can apply the corresponding voltage obtained from the driver to the corresponding bit line and word line based on the decoded address to realize data read / write and interact with the outside world through the data buffer.

[0061] The memory cell array may include multiple memory dies; each memory die may include multiple memory plans; each memory plan may include multiple memory blocks; each memory block may include multiple memory pages; each memory page may include multiple memory cells; each memory cell may be programmed to store one or more bits of data.

[0062] In other specific embodiments, the storage cell array may include multiple storage strings; each storage string may include multiple storage cells stacked vertically. Specifically,

[0063] The memory cell array of a three-dimensional memory may specifically include: a semiconductor substrate and a stacked structure located on the semiconductor substrate, the stacked structure including a plurality of gate layers and insulating layers spaced apart; a plurality of memory channel holes (CH, Channel Hole) and a plurality of dummy channel holes (DCH, Dummy Channel Hole) penetrating the gate layers and insulating layers; wherein, a memory material layer (i.e., ONOP structure) is disposed in both the memory channel holes and the dummy channel holes. Here, the position where the memory material layer in each memory channel hole intersects with each gate layer corresponds to a memory cell.

[0064] In related technologies, during the manufacturing process of 3D memory, the presence of stress (such as thermal stress) can cause the wafers used to form multiple 3D memory to warp and deform. As the number of stacked structure layers increases, the warpage of the wafer also becomes larger and larger. When the warpage of the wafer exceeds the upper limit or capacity of the machine, it can cause the wafer to get stuck or slide in the machine, reducing the reliability of the wafer and thus affecting the electrical performance and reliability of the 3D memory.

[0065] In some embodiments of the present invention, in order to control wafer warpage, a stacked structure similar to the core memory region (e.g., a nitride-oxide stack, NO Stack) can be formed in the dummy regions of the scribe lanes between multiple memory surfaces in the wafer. This reduces the warpage stress caused by the structural differences between the dummy regions of the scribe lanes and the core memory region, thereby reducing wafer warpage and improving wafer reliability.

[0066] However, in the back-gate process, the core memory region is divided into multiple memory blocks by multiple gate line slit structures. When the gate layer of multiple memory blocks is replaced through multiple gate line slits, the nitride layer in the region near the gate line slit structure in the dummy area of ​​the dicing channel may be replaced with the gate layer. This causes multiple adjacent memory blocks to conduct through the gate layer in the dummy area of ​​the dicing channel, which in turn causes a short circuit between multiple memory blocks, affecting the reliability of the 3D memory.

[0067] Specifically, such as Figure 1a , Figure 1b , Figure 1c As shown, Figure 1a This is a schematic diagram of a three-dimensional memory structure provided in some embodiments of the present invention; here, a stacked structure is provided in the storage surface 10; the stacked structure may include a core storage region 101, a dummy slit region 102, and multiple gate line slit structures 103 (GLS); wherein, the core storage region 101 is provided with multiple storage channel vias 1011; the dummy slit region 102 is provided with multiple dummy channel vias 1021; the gate line slit structure 103 penetrates the stacked structure and extends along a first direction.

[0068] Here, the first direction is parallel to the surface of the stacked structure; for example... Figure 1a The X direction is shown in the diagram. Here, the surface of the stacked structure can be understood as... Figure 1a The XOY plane is shown in the figure.

[0069] Figure 1b for Figure 1a A schematic diagram of the cross-sectional structure of the AA' position in the XOZ plane; Figure 1c for Figure 1a A schematic diagram of the cross-sectional structure of the BB' position in the YOZ plane.

[0070] It should be noted that the direction of AA' extension can be either the X or Y direction; the direction of BB' extension can be either the Y or X direction; in some embodiments of the present invention, when the direction of AA' extension is the X direction, the direction of BB' extension is the Y direction; and when the direction of AA' extension is the Y direction, the direction of BB' extension is the X direction. For ease of understanding, in the embodiments of the present invention, the example of AA' extension being in the X direction and BB' extension being in the Y direction will be used for explanation.

[0071] In some embodiments, the gate line slit structure 103 can be used to divide the core memory region 101 into multiple memory blocks; it can also be used in the back gate process to replace the nitride layer in the multiple memory blocks with the gate layer.

[0072] However, in the back-gate process, when the nitride layer, such as the silicon nitride (SiN) layer, of the core memory region 101 is replaced with a gate layer, such as tungsten (W), through the gate line slit structure 103, a portion of the nitride layer in the dummy region 102 of the diced channel, which is not separated by the gate line slit structure 103, may also be replaced with a gate layer. This allows multiple adjacent memory blocks to conduct to each other through the gate layer (the gate layer formed after the nitride replacement) in the dummy region 102 of the diced channel; consequently, a short circuit may occur between multiple memory blocks, such as... Figure 1aThe arrow shown indicates a decrease in the reliability of the 3D memory.

[0073] It should be noted that, Figure 1a , Figure 1b and Figure 1c A schematic diagram of the cross-sectional structure after the back gate process is applied to the storage surface.

[0074] To address one or more of the above-mentioned problems, embodiments of the present invention provide a three-dimensional memory; Figure 2 This is a schematic diagram of a three-dimensional memory provided in an embodiment of the present invention. The three-dimensional memory 20 includes:

[0075] At least one storage surface 201; a stacked structure 2011 is disposed in the storage surface; multiple first gate line slit structures 2012 penetrating the stacked structure and multiple isolation structures 2013 penetrating the stacked structure; wherein...

[0076] The multiple first gate line slit structures 2012 extend along the first direction to divide the storage surface 201 into multiple storage blocks 2014;

[0077] The isolation structure 2013 is located at the edge of the storage surface and extends along the second direction to contact the plurality of first gate line slit structures 2012, wherein the first direction intersects the second direction.

[0078] It should be noted that the first direction can be either the X or Y direction; the second direction can be either the Y or X direction; it should also be noted that when the first direction is the X direction, the second direction is the Y direction; and when the first direction is the Y direction, the second direction is the X direction. For ease of understanding, this embodiment uses the example of the first direction being the X direction and the second direction being the Y direction for explanation. However, it should be noted that the limitations on directions in this embodiment are only for illustrative purposes and are not intended to limit the scope of the invention.

[0079] Here, the first plane can be understood as a plane parallel to the XOY plane formed by the intersection of the X and Y directions.

[0080] In some embodiments of the present invention, the three-dimensional memory 20 may include multiple storage surfaces 201; each storage surface may adopt a three-dimensional stacked structure, giving the three-dimensional memory advantages such as high storage density and high-efficiency storage cell performance. Figure 3a , 3b As shown in 3c, the storage surface 201 may include a substrate 200 and a stacked structure 2011 located on the substrate 200 (see reference). Figure 3c The stacked structure 2011 may include a core storage area 2011a and a slicing virtual area 2011b (see reference). Figure 3bThe core storage area 2011a contains multiple storage channel holes 301; the dummy channel area 2011b contains multiple dummy channel holes 302 (see reference). Figure 3a ).

[0081] Here, for reference Figure 3a The storage surface 201 may also include a first gate line slit structure 2012 and an isolation structure 2013 that penetrate the stacked structure 2011; wherein, multiple first gate line slit structures 2012 extend along the X-axis direction to divide the storage surface 201 into multiple storage blocks 2014; and the multiple first gate line slit structures 2012 are parallel to each other.

[0082] Here, for reference Figure 3b Each storage block 2014 includes a portion of the core storage area 2011a and a portion of the slicing track virtual area 2011b. In some embodiments of the present invention, reference is made to... Figure 3a The storage surface 201 also includes multiple opposing isolation structures 2013; these isolation structures 2013 are parallel to each other; each isolation structure 2013 is located in a dummy area 2011b of the storage surface 201 and extends along the Y-axis. It should be noted that each dummy area of ​​the storage surface may include multiple isolation structures 2013, wherein at least one isolation structure 2013 contacts the first gate line slit structure 2012, forming a closed storage block 2014 between the first gate line slit structure 2012 and the isolation structure 2013.

[0083] In this way, even if the nitride layer in the dummy area 2011b of the cut channel is replaced with the gate layer, multiple adjacent memory blocks 2014 can still be electrically isolated through the isolation structure 2013, thus avoiding short circuits between multiple memory blocks in a memory plane; improving the reliability and yield of the three-dimensional memory.

[0084] In some embodiments of the present invention, the isolation structure 2013 may be a gate line slit structure that penetrates the stacked structure and extends along the second direction.

[0085] In some embodiments, reference Figure 3a Each of the storage blocks 2014 is provided with M rows of storage channel holes; M is a positive integer greater than 1.

[0086] In some embodiments of the present invention, the number of rows of storage channel holes provided in each storage block can be selected by those skilled in the art according to actual needs, such as 9 rows, 12 rows, 16 rows, etc.

[0087] Understandably, each storage plane can contain multiple storage blocks. Figure 3aOnly two storage blocks 2014 are shown as examples, namely storage block 1 (2014-1) and storage block 2 (2014-2).

[0088] Here, the isolation structure 2013 is disposed in the dummy region 2011b of the memory surface. In some specific embodiments, depending on the expansion position of the gate layer during the replacement process, the isolation structure 2013 can be disposed in the region of the dummy region 2011b close to the core memory region 2011a; it can also be disposed in the region of the dummy region 2011b far from the core memory region 2011a; or it can be disposed in the middle region of the dummy region 2011b.

[0089] For ease of description, we will take the area near the core storage area 2011a in the dummy area 2011b of the cut track, where the isolation structure 2013 is located, as an example.

[0090] here, Figure 3c It shows Figure 3b A schematic diagram of the cross-sectional structure of the CC' position in the XOZ plane.

[0091] It should be noted that, Figure 3b and 3c The diagram only shows the case where the isolation structure 2013 is located on one side of the storage surface; it is understood that in some embodiments of the present invention, reference is made to... Figure 3a In order to achieve complete isolation between the dummy area of ​​the slicing track and the core storage area, the isolation structure 2013 can also be set on the opposite side of the storage surface.

[0092] In some embodiments, the plurality of isolation structures 2013 disposed on opposite sides of the storage surface 201 may be parallel to each other or intersect on their extension lines.

[0093] In the actual manufacturing process, in order to simplify the process flow and save manufacturing costs, multiple isolation structures 2013 are set in parallel; that is, the multiple isolation structures 2013 are parallel to each other.

[0094] In this embodiment of the invention, for the purpose of clearly describing the invention, multiple parallel isolation structures 2013 are used as an example. However, it should be noted that the following embodiments are only used to illustrate the invention and are not intended to limit the scope of the invention.

[0095] In some embodiments of the present invention, multiple first gate line slit structures 2012 are in contact with at least two isolation structures 2013, so that each adjacent pair of first gate line slit structures 2012 and the contacted multiple isolation structures 2013 form a closed multiple memory blocks 2014.

[0096] Here, the first plane is perpendicular to the stacking direction of the stacked structure 2011. Alternatively, it can be understood that the first plane is parallel to the surface of the stacked structure 2011.

[0097] For example, such as Figure 3a As shown, multiple first gate line slit structures 2012 are in contact with two isolation structures 2013 to form closed memory blocks 1 (2014-1) and 2 (2014-2).

[0098] It should be noted that in some embodiments, the shapes of storage block 1 and storage block 2 may be the same or different; here, we will take the example of multiple storage blocks being the same.

[0099] In other words, each pair of adjacent first gate line slit structures 2012 contacts multiple isolation structures 2013 to form multiple closed memory blocks; each memory block is isolated from its adjacent memory blocks.

[0100] In this way, during the use of the 3D memory, each memory block is isolated from its adjacent memory blocks, avoiding electrical connections between adjacent memory blocks on the same memory plane, thereby improving the yield and reliability of the 3D memory.

[0101] In some embodiments of the present invention, the first direction intersects with the second direction; to facilitate a clear understanding of the intent of the present invention, the example of the first direction being perpendicular to the second direction will be used for explanation.

[0102] For example, such as Figure 4a As shown, the first gate line slit structure 2012 extends along the X direction, and the isolation structure 2013 extends along the Y direction.

[0103] In some embodiments, at least one of the straight lines containing the first gate line slit structure extends beyond the straight line containing the corresponding isolation structure along a first direction;

[0104] And / or,

[0105] At least one of the isolation structures lies on a straight line that extends beyond the straight line containing the corresponding first gate line slit structure along a second direction.

[0106] In some embodiments of the present invention, the first gate line slit structure and the isolation structure may be arranged in an intersecting manner. Specifically, after multiple first gate line slit structures intersect with the isolation structure, the multiple first gate line slit structures may extend beyond the isolation structure along the first direction, or they may not extend beyond the isolation structure; alternatively, some of the multiple first gate line slit structures may extend beyond the isolation structure.

[0107] Similarly, after the isolation structure intersects with the first gate line slit structure, the isolation structure may extend beyond the first gate line slit structure along the second direction, or it may not extend beyond the first gate line slit structure.

[0108] For example, such as Figure 4a As shown, after the first gate line slit structure 2012 intersects with the isolation structure 2013, multiple first gate line slit structures 2012 extend beyond the isolation structure 2013 along the X-axis direction.

[0109] It should be noted that, in the embodiments of the present invention, reference is made to... Figure 4a Multiple first gate line slit structures 2012 extend beyond the isolation structure 2013 along the X-axis, which can increase the process window when the first gate line slit structures 2012 and the isolation structure 2013 come into contact during the fabrication process of the 3D memory, thereby improving the reliability of the 3D memory. On the other hand, it can also increase the probability of the memory block being enclosed.

[0110] For example, such as Figure 4b As shown, after the first gate line slit structure 2012 intersects with the isolation structure 2013, the two first gate line slit structures 2012 located at the opposite edges of the storage surface do not extend beyond the isolation structure 2013 along the X-axis direction, while the remaining multiple first gate line slit structures 2012 in the middle of the storage surface all extend beyond the isolation structure 2013 along the X-axis direction.

[0111] For example, such as Figure 4c As shown, after the first gate line slit structure 2012 intersects with the isolation structure 2013, the two isolation structures 2013 located on the other two sides of the storage surface do not extend beyond the first gate line slit structure 2012 along the Y direction.

[0112] For example, such as Figure 4d As shown, after the first gate line slit structure 2012 intersects with the isolation structure 2013, the two first gate line slit structures 2012 located on opposite sides of the storage surface do not extend beyond the isolation structure 2013 in the X direction, the remaining multiple first gate line slit structures 2012 in the middle of the storage surface all extend beyond the isolation structure 2013 in the X direction, and the two isolation structures 2013 located on the other two sides of the storage surface do not extend beyond the first gate line slit structure 2012 in the Y-axis direction.

[0113] It should be noted that the embodiments of the present invention only show a schematic diagram of the contact between part of the first gate line slit structure 2012 and the isolation structure 2013, but are not limited thereto.

[0114] It should be noted that in the above embodiments, the first gate line slit structure and the isolation structure can form a closed memory block after they intersect, so that each memory block is isolated from its adjacent memory blocks; thus avoiding electrical connection between adjacent memory blocks in the same memory plane; thereby improving the yield and reliability of the three-dimensional memory.

[0115] In some embodiments, such as Figure 5 As shown, the storage surface is also provided with a plurality of second gate line slit structures 2015 that penetrate the stacked structure;

[0116] The second gate line slit structure 2015 extends along the first direction and includes a plurality of spaced-apart sub-gate line slit structures. Here, each of the isolation structures is in contact with the plurality of second gate line slit structures.

[0117] In some embodiments of the present invention, during the manufacturing process of the three-dimensional memory, in order to prevent the stacked structure from tilting or collapsing, a second gate line slit structure 2015 is provided between two adjacent first gate line slit structures 2012. For example... Figure 5 As shown, in some embodiments of the present invention, the multiple spaced sub-gate line slit structures in the second gate line slit structure 2015 are not continuous, forming an "H"-shaped structure (H-cut). In the process of manufacturing three-dimensional memory, the unisolated stacked structure is used to connect the stacked structures on both sides of the sub-gate line slit structure. In other words, the unisolated stacked structure can prevent the stacked structure from tilting or collapsing, thus meeting the structural stability requirements of multi-layer three-dimensional memory.

[0118] In some embodiments of the present invention, a top select gate cut (TSG-CUT) extending along a first direction is further provided in the memory block; the top select gate cut is used to divide the memory block 2014 into multiple finger memory regions. Figure 5 (Not shown in the image). In some embodiments of the present invention, the TSG-CUT can be formed in an "H"-shaped structure, so that the two can be combined to divide the memory block into memory areas, thus saving process costs.

[0119] In some embodiments of the present invention, the second gate line slit structure may further include a conductive material for leading out the array common source. In this case, the multiple spaced sub-gate line slit structures need to be connected to each other via a connecting bridge structure to achieve the connection of several sub-common sources.

[0120] In some embodiments of the present invention, reference is made to Figure 5In the stacked structure region between the first gate line slit structure 2012 and the second gate line slit structure 2015, multiple rows of memory channel holes can also be set according to actual needs, such as 9 rows, 12 rows, 16 rows, etc.

[0121] It should be noted that in some embodiments of the present invention, multiple rows of storage channel holes may be set in each storage area according to actual needs.

[0122] In some embodiments, the stacked structure includes a step area, a first dummy area and a second dummy area located on opposite sides of the step area, a first core storage area located between the step area and the first dummy area, and a second core storage area located between the step area and the second dummy area; wherein the plurality of isolation structures are respectively disposed in the first dummy area and the second dummy area.

[0123] In some embodiments of the present invention, a memory chip may include multiple memory surfaces; each memory surface is provided with a stacked structure; the stacked structure may include a core memory region, a dummy reticle region, and a step region; the core memory region includes a first core memory region and a second core memory region; the dummy reticle region includes a first dummy region and a second dummy region. The first dummy region is located on one side of the first core memory region; a step region is provided on the other side of the first core memory region; the other side of the step region is connected to the second core memory region; and a second dummy region is provided on the other side of the second core memory region.

[0124] For example, such as Figure 6 As shown, the memory chip includes four memory planes, such as memory plane 1 (Plane1), memory plane 2 (Plane2), memory plane 3 (Plane3), and memory plane 4 (Plane4); each memory plane is provided with a first dummy area 2011b-1, a first core memory area 2011a-1, a step area 2011c, a second core memory area 2011a-2, and a second dummy area 2011b-2 arranged in sequence.

[0125] Here, the core storage area 2011a includes the first core storage area 2011a-1 and the second core storage area 2011a-2; the slicing dummy area includes the first dummy area 2011b-1 and the second dummy area 2011b-2.

[0126] In some embodiments of the present invention, reference is made to Figure 6 The isolation structure 2013 is set in two relative sub-dummy areas of each storage surface, namely in the first dummy area 2011b-1 and the second dummy area 2011b-2.

[0127] To better understand the specific location of the isolation structure 2013, in Figure 6The image also shows the first dummy region 2011b-1 and the second dummy region 2011b-2 at the edge of storage surface 2. Figure 6 The enlarged view of the corresponding structure of the isolation structure 2013 (shown as a dashed box around the edge of Plane2).

[0128] In some embodiments, such as Figure 6 As shown, multiple storage channel holes 301 are provided in both the first core storage area 2011a-1 and the second core storage area 2011a-2; multiple virtual channel holes 302 are provided in both the first virtual area 2011b-1 and the second virtual area 2011b-2.

[0129] In some embodiments of the present invention, a memory material layer (i.e., an ONOP structure) is formed in both the memory channel via 301 and the dummy channel via 302. Here, the distribution of the thin film in the ONOP structure is as follows: Figure 7 As shown. From Figure 7 As can be seen, the ONOP structure includes four thin films, specifically a barrier dielectric layer, a charge trapping layer, a tunneling dielectric layer, and a channel layer that are sequentially stacked along the radial direction of the storage channel.

[0130] In some embodiments, such as Figure 8 As shown, the stacking structure 2011 includes at least a first sub-stacking structure 2011-1 and a second sub-stacking structure 2011-2 located on the first sub-stacking structure.

[0131] It should be noted that, in the stacking structure 2011, the first sub-stack structure 2011-1 may be located above the second sub-stack structure 2011-2; or the second sub-stack structure 2011-2 may be located above the first sub-stack structure 2011-1. Here, we will take the example of the first sub-stack structure 2011-1 being located above the second sub-stack structure 2011-2 for explanation.

[0132] In some embodiments, the first sub-stack structure 2011-1 is provided with a first sub-channel hole;

[0133] The second sub-stacking structure 2011-2 is provided with a second sub-channel hole;

[0134] The first sub-channel hole and the second sub-channel hole are connected in a third direction; the third direction is parallel to the stacking direction of the stacked structure 2011.

[0135] Here, the first sub-channel hole may include a first sub-storage channel hole 3011 and a first sub-dummy channel hole 3021; ​​the second sub-channel hole may include a second sub-storage channel hole 3012 and a second sub-dummy channel hole 3022.

[0136] The first sub-storage channel hole 3011 and the second sub-storage channel hole 3012 are connected in the third direction;

[0137] The first sub-dummy channel hole 3021 and the second sub-dummy channel hole 3022 are connected in the third direction.

[0138] It should be noted that the third direction can be the Z direction.

[0139] This invention also provides a method for manufacturing a three-dimensional memory, the three-dimensional memory including at least one storage surface, the method for forming the storage surface including the following steps:

[0140] Forming a stacked structure;

[0141] Multiple first gate line slit structures penetrating the stacked structure and multiple isolation structures penetrating the stacked structure are formed; wherein...

[0142] The multiple first gate line slit structures extend along a first direction to divide the memory surface into multiple memory blocks;

[0143] The isolation structure is located at the edge of the storage surface and extends along a second direction to contact the plurality of first gate line slit structures. The first direction intersects the second direction.

[0144] Figures 9a-9h This is an example of a cross-sectional view illustrating the fabrication process of a three-dimensional memory according to an embodiment of the present invention. It should be understood that the operations shown in the above-described method steps for forming the storage surface are not exclusive, and other operations may be performed before, after, or between any of the operations shown. The following is in conjunction with... Figures 9a-9h Methods for forming semiconductor structures according to various embodiments of the present invention are described.

[0145] It should be noted that, Figures 9a-9h All are based on Figure 3a The example given is a cross-sectional view of the CC' position in the XOZ plane.

[0146] In some embodiments of the present invention, in the above-described method steps for forming a storage surface, a stacked structure 2011, a first gate line slit structure, and an isolation structure 2013 are formed.

[0147] In some embodiments, forming the stacked structure 2011 includes:

[0148] Forming the first sub-stacked structure on the substrate 2011-1;

[0149] A second sub-stack structure 2011-2 is formed on the first sub-stack structure 2011-1; the first sub-stack structure 2011-1 and the second sub-stack structure 2011-2 form the stack structure 2011;

[0150] The method further includes: forming a first sub-storage channel hole 3011 and a first sub-dummy channel hole 3021 in the first sub-stack structure 2011-1 before forming the second sub-stack structure 2011-2;

[0151] After forming the second sub-stack structure 2011-2, a second sub-memory channel via 3012 and a second sub-dummy channel via 3022 are formed in the second sub-stack structure; the first sub-memory channel via 3011 and the second sub-memory channel via 3012 are connected in the third direction; the first sub-dummy channel via 3021 and the second sub-dummy channel via 3022 are connected in the third direction.

[0152] The third direction is parallel to the stacking direction of the stacked structure.

[0153] It should be noted that the stacked structure 2011 includes a core memory region 2011a and a dummy scribe line region 2011b; to facilitate understanding of the positional relationship between the core memory region 2011a and the dummy scribe line region 2011b and structures such as the first gate line slit structure 2012 and the isolation structure 2013, etc., in Figures 9a-9h The relative positions of the core storage area 2011a and the slicing dummy area 2011b with the stack structure 2011 are shown in the figure.

[0154] In some embodiments of the present invention, such as Figure 9a , Figure 9b , Figure 9c , Figure 9d As shown, a substrate 200 is provided before forming the stacked structure 2011; Reference Figure 9a A first sub-stack structure 2011-1 is formed on substrate 200.

[0155] Here, the substrate 200 may include a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

[0156] Here, the first sub-stack structure 2011-1 includes a plurality of sacrificial layers 901 and insulating layers 902 (e.g., oxide layers) stacked at intervals. The material of the sacrificial layer 901 may be a nitride, such as silicon nitride, but is not limited thereto. The material of the insulating layer 902 may be an oxide, such as silicon dioxide, but is not limited thereto.

[0157] In some embodiments of the present invention, the sacrificial layer 901 and the insulating layer 902 can be formed by deposition processes, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition (ALD). In some embodiments, the deposition process further includes plasma-enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), etc.

[0158] like Figure 9b As shown, a first sub-storage channel hole 3011 and a first sub-dummy channel hole 3021 are formed in the first sub-stack structure 2011-1.

[0159] In some embodiments, the method further includes forming a sacrificial layer in the first sub-channel hole before forming the second sub-stack structure 2011-2.

[0160] Here, a sacrificial layer is formed in the first sub-storage channel hole 3011 and the first sub-dummy channel hole 3021; ​​the sacrificial layer is used to provide support.

[0161] It should be noted that the material of the sacrificial layer located in the first sub-storage channel hole 3011 and the first sub-dummy channel hole 3021 may include nitrides, but is not limited thereto.

[0162] In some alternative embodiments, the material used for the sacrificial layers formed in the first sub-storage via 3011 and the first sub-dummy via 3021 is different from the material used for the sacrificial layer 901 forming the stacked structure.

[0163] like Figure 9c As shown, a second sub-stack structure 2011-2 is formed on the first sub-stack structure 2011-1.

[0164] Here, the second sub-stack structure 2011-2 includes several sacrificial layers 901 and insulating layers 902 stacked at intervals. The materials of the sacrificial layers 901 and insulating layers 902 have been described previously and will not be repeated here.

[0165] Understandably, compared to using a metal gate layer, etching a nitride sacrificial layer is easier and more controllable when using a nitride sacrificial layer 901.

[0166] like Figure 9d , Figure 9e As shown, a second sub-storage channel hole 3012 and a second sub-dummy channel hole 3022 are formed in the second sub-stack structure 2011-2.

[0167] Here, the first sub-storage channel hole 3011 and the second sub-storage channel hole 3012 are connected in the third direction to form a storage channel hole 301; the first sub-dummy channel hole 3021 and the second sub-dummy channel hole 3022 are connected in the third direction to form a dummy channel hole 302.

[0168] In some embodiments of the present invention, the sacrificial layer located in the first sub-memory channel via 3011 and the first sub-dummy channel via 3021 can be removed by an etching process.

[0169] like Figure 9e As shown, a memory material layer (i.e., ONOP structure) is formed in the memory channel hole 301 and the dummy channel hole 302. The ONOP structure has been described before and will not be repeated here.

[0170] In some embodiments of the present invention, the methods for forming the memory material layer include, but are not limited to, CVD, PVD, or ALD.

[0171] Next, as Figure 9f , Figure 9g , Figure 9h As shown, a first gate line slit structure 2012 forms multiple through-stacking structures. Figure 9f , Figure 9g , Figure 9h (not shown in the image) and isolation structure 2013.

[0172] In some embodiments, forming multiple first gate line slit structures penetrating the stacked structure and multiple isolation structures penetrating the stacked structure includes:

[0173] Forming a first trench through the stacked structure ( Figure 9f , Figure 9g , Figure 9h (not shown in the middle) and the second trench 2013-1;

[0174] An insulating layer 2013-2 is formed covering the sidewalls and bottom of the first trench and the second trench 2013-1;

[0175] Semiconductor material 2013-3 is filled into the insulating layer 2013-2 to form the first gate line slit structure and the isolation structure 2013, respectively.

[0176] In some embodiments of the present invention, the first trench and the second trench 2013-1 can be formed by an etching process, but are not limited thereto.

[0177] Methods for forming insulating layers 2013-2 include, but are not limited to, CVD, PVD, or ALD.

[0178] Methods for filling semiconductor materials 2013-3 include, but are not limited to, CVD, PVD or ALD.

[0179] Here, the filling structures within the plurality of first gate line slit structures 2012 and isolation structures 2013 are insulated from the stacked structure 2011 and from the substrate 200.

[0180] In some embodiments of the present invention, the insulating layer 2013-2 is made of an insulating material, such as silicon dioxide, but is not limited thereto. The semiconductor material 2013-3 can be polycrystalline silicon, but is not limited thereto.

[0181] In some embodiments, the first gate line slit 2012 is integrally formed with the isolation structure 2013.

[0182] It should be noted that, here, the isolation structure 2013 can be a gate line slit structure extending along the second direction and penetrating the stacked structure 2011. That is to say, the first gate line slit structure and the isolation structure can be formed simultaneously in the same process without adding any additional process steps, i.e., without adding any additional cost.

[0183] It should be noted that before forming the insulating layer 2013-2 covering the surfaces of the first trench and the second trench 2013-1, the sacrificial layer in the stacked structure can be removed through the first trench and the second trench and replaced with the gate layer 202.

[0184] Here, the material of the gate layer 202 may include, but is not limited to, tungsten metal.

[0185] In some embodiments of the present invention, the methods for forming the gate layer include, but are not limited to, CVD, PVD, or ALD.

[0186] Based on this, in the implementation of the present invention, by forming multiple first gate line slit structures and multiple isolation structures that penetrate the stacked structure and intersect each other in the storage surface, multiple isolation structures form multiple closed storage blocks after contacting the multiple first gate slit structures, thereby avoiding short circuits between multiple adjacent storage blocks in the same storage surface; thus achieving electrical isolation between multiple storage blocks in the same storage surface; and improving the reliability and yield of the three-dimensional memory.

[0187] Furthermore, the technical solutions described in the embodiments of the present invention can be combined arbitrarily without conflict.

[0188] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention.

Claims

1. A three-dimensional memory, characterized in that, include: At least one storage surface; the storage surface is provided with a stacked structure, multiple first gate line slit structures penetrating the stacked structure, multiple second gate line slit structures penetrating the stacked structure, and multiple isolation structures penetrating the stacked structure; wherein... The multiple first gate line slit structures extend along a first direction to divide the memory surface into multiple memory blocks; The isolation structure is located at the edge of the storage surface and extends along the second direction to contact the plurality of first gate line slit structures; the second gate line slit structure is located between two adjacent first gate line slit structures and extends along the first direction, and the second gate line slit structure includes a plurality of spaced sub-gate line slit structures; the first direction intersects the second direction.

2. The three-dimensional memory according to claim 1, characterized in that, At least one of the straight lines containing the first gate line slit structure extends beyond the straight line containing the corresponding isolation structure along the first direction; And / or, At least one of the isolation structures lies on a straight line that extends beyond the straight line of the corresponding first gate line slit structure along a second direction.

3. The three-dimensional memory according to claim 1, characterized in that, The stacked structure includes a step area, a first dummy area and a second dummy area located on opposite sides of the step area, a first core storage area located between the step area and the first dummy area, and a second core storage area located between the step area and the second dummy area; wherein the plurality of isolation structures are respectively disposed in the first dummy area and the second dummy area.

4. The three-dimensional memory according to claim 3, characterized in that, The first core storage area and the second core storage area are provided with multiple storage channel holes; the first dummy area and the second dummy area are provided with multiple dummy channel holes.

5. The three-dimensional memory according to claim 1, characterized in that, Each of the isolation structures is in contact with the plurality of second gate line slit structures.

6. The three-dimensional memory according to claim 1, characterized in that, Each of the storage blocks is provided with M rows of storage channel holes; where M is a positive integer greater than 1.

7. The three-dimensional memory according to claim 1, characterized in that, The stacking structure includes at least a first sub-stacking structure and a second sub-stacking structure located on the first sub-stacking structure; The first sub-stack structure is provided with a first sub-channel hole; The second sub-stacking structure is provided with a second sub-channel hole; The first sub-channel hole and the second sub-channel hole are connected in a third direction; the third direction is parallel to the stacking direction of the stacked structure.

8. The three-dimensional memory according to claim 1, characterized in that, The isolation structure is integrally formed with the first gate line slit structure.

9. A method for manufacturing a three-dimensional memory, characterized in that, The three-dimensional memory includes at least one storage surface, and the method for forming the storage surface includes: Forming a stacked structure; Multiple first gate line slit structures, multiple second gate line slit structures, and multiple isolation structures are formed that penetrate the stacked structure; wherein... The plurality of first gate line slit structures extend along a first direction to divide the storage surface into a plurality of storage blocks; the isolation structure is located at the edge of the storage surface and extends along a second direction to contact the plurality of first gate line slit structures; the second gate line slit structure is located between two adjacent first gate line slit structures and extends along the first direction, and the second gate line slit structure includes a plurality of spaced sub-gate line slit structures; the first direction and the second direction intersect.

10. The method for manufacturing a three-dimensional memory according to claim 9, characterized in that, The first gate line slit structure is integrally formed with the isolation structure.

11. The method for manufacturing a three-dimensional memory according to claim 9, characterized in that, The formation of the stacked structure includes: A first sub-stack structure is formed on the substrate; A second sub-stack structure is formed on the first sub-stack structure; the first sub-stack structure and the second sub-stack structure form the stack structure. The method further includes: forming a first sub-channel hole in the first sub-stacking structure before forming the second sub-stacking structure; After the second sub-stack structure is formed, a second sub-channel hole is formed in the second sub-stack structure; the first sub-channel hole and the second sub-channel hole are connected in a third direction; the third direction is parallel to the stacking direction of the stack structure.

12. The method for manufacturing a three-dimensional memory according to claim 11, characterized in that, The method further includes forming a sacrificial layer in the first sub-channel hole before forming the second sub-stack structure.

13. The method for manufacturing a three-dimensional memory according to claim 9, characterized in that, Forming the first gate line slit structure and the isolation structure includes: A first trench and a second trench are formed that penetrate the stacked structure; the first trench extends along the first direction, and the second trench extends along the second direction; the first trench and the second trench are connected. An insulating layer is formed covering the sidewalls and bottom of the first trench and the second trench; Semiconductor material is filled into the insulating layer to form the first gate line slit structure and the isolation structure, respectively.

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