A reverse voltage protection circuit and bus transceiver

Abstract

The application provides a reverse voltage protection circuit and a bus transceiver, and the reverse voltage protection circuit comprises a comparator, the input port and the output port of the circuit are connected with the input end of the comparator, the comparator is used for comparing the voltage of the input port and the output port, and outputs a comparison signal; a trigger circuit receives the comparison signal, turns on / off a MOS tube connected between the input port and the output port according to the comparison signal; and the MOS tube is used for preventing abnormal voltage of the output port from flowing back to the input port. By using the above circuit, the trigger circuit can be turned on or turned off by comparing the voltage of the input port and the output port, the MOS tube is controlled in the off state by the trigger circuit, the abnormal voltage is prevented from flowing back to the input port, the function of the high-voltage diode is replaced by the reverse voltage protection circuit, the use of the high-voltage diode is reduced, and the manufacturing difficulty and the manufacturing cost of the chip are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of bus technology, in particular to a reverse voltage protection circuit applied to a field bus and a bus transceiver. BACKGROUND

[0002] When field buses such as CAN bus, RS485 and RS422 are applied, the bus interface may appear common-mode voltage. The protocol stipulates that the common-mode voltage range of CAN bus is -2V to +7V, the common-mode voltage range of RS485 bus is -7V to +12V, and the common-mode voltage range of RS422 bus is ±7V. However, the common-mode voltage range of these products in actual application may reach ±15V or ±30V or even higher. Therefore, the bus transceiver needs a reverse voltage protection circuit to meet the requirement of bus terminal pin to withstand the bus common-mode voltage.

[0003] The driving circuit of a common RS-485 / 422 bus transceiver and CAN bus transceiver, when OUT or CANH appears positive high voltage, high-voltage diode D1 prevents the "backflow" path formed by the bus pin OUT to the power supply pin VCC; when OUT or CANL appears negative high voltage, high-voltage diode D2 prevents the "backflow" path formed by the ground pin GND to the bus pin OUT.

[0004] In the current technology, high-voltage diodes D1 and D2 need to have the characteristics of high reverse voltage resistance, but the process implementation is difficult. Therefore, a circuit is needed to replace the high-voltage diode to achieve high reverse voltage resistance and prevent abnormal voltage from flowing back to VCC or GND. SUMMARY

[0005] In view of the above problems of the prior art, the purpose of the present application is to provide a reverse voltage protection circuit and a bus transceiver to solve the problem that the chip flow process is difficult when using high-voltage diodes for reverse voltage protection in the prior art.

[0006] In order to solve the above technical problems, the specific technical solutions of the present application are as follows: on the one hand, the present application provides a reverse voltage protection circuit, comprising:

[0007] a comparator, the input port and the output port of the circuit are connected to the input end of the comparator, and the comparator is used to compare the voltages of the input port and the output port and output a comparison signal;

[0008] a trigger circuit, which receives the comparison signal and turns on / off a MOS tube connected between the input port and the output port according to the comparison signal;

[0009] The MOS tube is used to prevent abnormal voltage of the output port from flowing back to the input port.

[0010] As an embodiment herein, when the input port is power VCC, the trigger circuit comprises a fifth NMOS, a fourth PMOS, a first inverter, a sixth NMOS and a second PMOS, and the output port is a zeroth PMOS;

[0011] The gate of the fifth NMOS is connected with the output of the comparator, and the source of the fifth NMOS is connected with GND;

[0012] The gate of the fourth PMOS is connected with the gate of the fifth NMOS, the drain of the fourth PMOS is connected with the drain of the fifth NMOS, and the source of the fourth PMOS is connected with the power VCC;

[0013] The input of the first inverter is connected with the output of the comparator;

[0014] The gate of the sixth NMOS is connected with the output of the inverter, and the source of the sixth NMOS is connected with the GND;

[0015] The gate of the second PMOS is connected with the connection point of the drain of the fifth NMOS and the drain of the fourth PMOS, the drain of the second PMOS is connected with the drain of the sixth NMOS, and the source of the second PMOS is connected with the source of the zeroth PMOS.

[0016] As an embodiment herein, when the input port is GND, the trigger circuit comprises a fifth PMOS, a fourth NMOS, a second inverter, a sixth PMOS and a second NMOS, and the output port is a zeroth NMOS;

[0017] The gate of the fifth PMOS is connected with the output of the comparator, and the source of the fifth PMOS is connected with power VCC;

[0018] The gate of the fourth NMOS is connected with the gate of the fifth PMOS, the drain of the fourth NMOS is connected with the drain of the fifth PMOS, and the source of the fourth NMOS is connected with the GND;

[0019] The input of the second inverter is connected with the output of the comparator;

[0020] The gate of the sixth PMOS is connected with the output of the inverter, and the source of the sixth PMOS is connected with the power VCC;

[0021] The gate of the second NMOS is connected to the connection point of the drain of the fifth PMOS and the drain of the fourth NMOS, the drain of the second NMOS is connected to the drain of the sixth PMOS, and the source of the second NMOS is connected to the source of the zeroth NMOS.

[0022] As an embodiment herein, when the input port comprises a power supply VCC and GND, the circuit comprises two comparators, two trigger circuits, a first MOS, a second MOS, a zeroth PMOS and a zeroth NMOS, wherein:

[0023] A first comparator, the input of the first comparator is connected to the power supply VCC and the drain of the zeroth PMOS, and the first comparator is used to compare the voltage of the power supply VCC and the drain of the zeroth PMOS and output a first comparison signal;

[0024] A first trigger circuit, which receives the first comparison signal and turns on / off the first MOS connected between the power supply VCC and an output port according to the first comparison signal;

[0025] The first MOS is used to prevent abnormal voltage at the drain of the zeroth PMOS from flowing back to the power supply VCC;

[0026] A second comparator, the input of the second comparator is connected to the GND and the drain of the zeroth NMOS, and the second comparator is used to compare the voltage of the GND and the drain of the zeroth NMOS and output a second comparison signal;

[0027] A second trigger circuit, which receives the second comparison signal and turns on / off the second MOS connected between the GND and an output port according to the second comparison signal;

[0028] The second MOS is used to prevent abnormal voltage at the drain of the zeroth NMOS from flowing back to the GND.

[0029] As an embodiment herein, the first trigger circuit comprises a fifth NMOS, a fourth PMOS, a first inverter, a sixth NMOS and a second PMOS;

[0030] The gate of the fifth NMOS is connected to the output of the comparator, and the source of the fifth NMOS is connected to the GND;

[0031] The gate of the fourth PMOS is connected to the gate of the fifth NMOS, the drain of the fourth PMOS is connected to the drain of the fifth NMOS, and the source of the fourth PMOS is connected to the power supply VCC;

[0032] an input terminal of the first inverter is connected with an output terminal of the comparator;

[0033] a gate of the sixth NMOS is connected with an output terminal of the inverter, and a source of the sixth NMOS is connected with the GND;

[0034] a gate of the second PMOS is connected with a connection point of a drain of the fifth NMOS and a drain of the fourth PMOS, a drain of the second PMOS is connected with a drain of the sixth NMOS, and a source of the second PMOS is connected with a source of the zeroth PMOS;

[0035] the second trigger circuit comprises a fifth PMOS, a fourth NMOS, a second inverter, a sixth PMOS and a second NMOS;

[0036] a gate of the fifth PMOS is connected with an output terminal of the comparator, and a source of the fifth PMOS is connected with the power supply VCC;

[0037] a gate of the fourth NMOS is connected with a gate of the fifth PMOS, a drain of the fourth NMOS is connected with a drain of the fifth PMOS, and a source of the fourth NMOS is connected with the GND;

[0038] an input terminal of the second inverter is connected with an output terminal of the comparator;

[0039] a gate of the sixth PMOS is connected with an output terminal of the inverter, and a source of the sixth PMOS is connected with the power supply VCC;

[0040] a gate of the second NMOS is connected with a connection point of a drain of the fifth PMOS and a drain of the fourth NMOS, a drain of the second NMOS is connected with a drain of the sixth PMOS, and a source of the second NMOS is connected with a source of the zeroth NMOS.

[0041] as an embodiment herein, a first gate oxide protection circuit is further coupled between the output port and the trigger circuit, the first gate oxide protection circuit comprises a first resistor, an eighth PMOS, a third PMOS and a first diode;

[0042] one end of the first resistor is connected with a drain of the fifth NMOS, and the other end is connected with a source of the eighth PMOS;

[0043] a gate of the eighth PMOS is connected with a source of the eighth PMOS, and a drain of the eighth PMOS is connected with a drain of the fourth PMOS;

[0044] The gate of the third PMOS tube is connected with the source, the source of the third PMOS tube is connected with the source of the eighth PMOS tube, and the drain of the third PMOS tube is connected with the anode of the first diode;

[0045] The cathode of the first diode is connected with the source of the second PMOS tube.

[0046] As an embodiment herein, a second gate oxide protection circuit is further coupled between the output port and the trigger circuit, and the second gate oxide protection circuit comprises a second resistor, a seventh PMOS tube, a third NMOS tube and a second diode;

[0047] One end of the second resistor is connected with the drain of the fifth PMOS tube, and the other end is connected with the drain of the seventh PMOS tube;

[0048] The gate of the seventh PMOS tube is connected with the source, the source of the seventh PMOS tube is connected with the drain of the fourth NMOS tube;

[0049] The gate of the third NMOS tube is connected with the source, the source of the third NMOS tube is connected with the drain of the seventh PMOS tube, and the drain of the third NMOS tube is connected with the cathode of the second diode;

[0050] The anode of the second diode is connected with the source of the second NMOS tube.

[0051] As an embodiment herein, a first gate oxide protection circuit is further coupled between the output port and the trigger circuit, and the first gate oxide protection circuit comprises a first resistor, an eighth PMOS tube, a third PMOS tube and a first diode;

[0052] One end of the first resistor is connected with the drain of the fifth NMOS tube, and the other end is connected with the source of the eighth PMOS tube;

[0053] The gate of the eighth PMOS tube is connected with the source, the drain of the eighth PMOS tube is connected with the drain of the fourth PMOS tube;

[0054] The gate of the third PMOS tube is connected with the source, the source of the third PMOS tube is connected with the source of the eighth PMOS tube, and the drain of the third PMOS tube is connected with the anode of the first diode;

[0055] The cathode of the first diode is connected with the source of the second PMOS tube.

[0056] The output port and the trigger circuit are further coupled with a second gate oxide protection circuit, and the second gate oxide protection circuit comprises a second resistor, a seventh PMOS tube, a third NMOS tube and a second diode.

[0057] One end of the second resistor is connected with the drain of the fifth PMOS tube, and the other end is connected with the drain of the seventh PMOS tube.

[0058] The gate of the seventh PMOS tube is connected with the source, the source of the seventh PMOS tube is connected with the drain of the fourth NMOS tube.

[0059] The gate of the third NMOS tube is connected with the source, the source of the third NMOS tube is connected with the drain of the seventh PMOS tube, and the drain of the third NMOS tube is connected with the cathode of the second diode.

[0060] The anode of the second diode is connected with the source of the second NMOS tube.

[0061] As an embodiment herein, the output port comprises the zeroth PMOS tube and the zeroth NMOS tube.

[0062] When the output port outputs one-way signal, the gate of the zeroth PMOS tube is connected with the first control signal, the source of the zeroth PMOS tube is connected with the source of the second PMOS tube, the gate of the zeroth NMOS tube is connected with the second control signal, the source of the zeroth NMOS tube is connected with the source of the second NMOS tube, the drain of the zeroth PMOS tube is connected with the drain of the zeroth NMOS tube, and one-way signal is outputted.

[0063] When the output port outputs two-way signal, the gate of the zeroth PMOS tube is connected with the first control signal, the source of the zeroth PMOS tube is connected with the source of the second PMOS tube, the gate of the zeroth NMOS tube is connected with the second control signal, the source of the zeroth NMOS tube is connected with the source of the second NMOS tube, the drain of the zeroth PMOS tube outputs one-way signal, and the drain of the zeroth NMOS tube outputs one-way signal.

[0064] The application further provides a bus transceiver provided with the reverse voltage protection circuit.

[0065] The above technical solution can compare the voltage of the input port and the output port to turn on or turn off the trigger circuit, and the MOS tube is controlled in the off state by the trigger circuit to prevent abnormal voltage from flowing into the input port, the function of the high-voltage diode is replaced by the reverse voltage protection circuit, the use of the high-voltage diode can be reduced, and the manufacturing difficulty and cost of the chip are reduced.

[0066] To make the above and other purposes, features and advantages of the present text more apparent and easy to understand, the following preferred embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present text, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0068] Figure 1 A reverse voltage protection circuit schematic diagram of an embodiment of the present text is shown;

[0069] Figure 2 A power supply VCC input port circuit schematic diagram of an embodiment of the present text is shown;

[0070] Figure 3 A first gate oxide protection circuit schematic diagram of an embodiment of the present text is shown;

[0071] Figure 4 A GND input port circuit schematic diagram of an embodiment of the present text is shown;

[0072] Figure 5 A second gate oxide protection circuit schematic diagram of an embodiment of the present text is shown;

[0073] Figure 6 A preferred reverse voltage protection circuit of an embodiment of the present text is shown;

[0074] Figure 7 A trigger circuit schematic diagram of a preferred reverse voltage protection circuit of an embodiment of the present text is shown;

[0075] Figure 8 A double gate oxide protection circuit schematic diagram of an embodiment of the present text is shown;

[0076] Figure 9 A schematic diagram of a one-way signal reverse protection circuit with gate oxide protection circuit of an embodiment of the present text is shown;

[0077] Figure 10 A schematic diagram of a one-way signal reverse protection circuit without gate oxide protection circuit of an embodiment of the present text is shown;

[0078] Figure 11 A schematic diagram of a two-way signal reverse protection circuit with gate oxide protection circuit of an embodiment of the present text is shown;

[0079] Figure 12This diagram illustrates a two-channel reverse protection circuit without gate oxide protection, as described in the embodiments of this paper. Explanation of symbols in the accompanying drawings:

[0080] 1. First resistor;

[0081] 2. Second resistor;

[0082] 101. Comparator;

[0083] 1011, First comparator;

[0084] 1012, Second comparator;

[0085] 102. Trigger circuit;

[0086] 103. MOSFET;

[0087] 10. Zeroth PMOS transistor;

[0088] 11. First inverter;

[0089] 12. Second PMOS transistor;

[0090] 13. Third PMOS transistor;

[0091] 14. Fourth PMOS transistor;

[0092] 15. Fifth NMOS transistor;

[0093] 16. The sixth NMOS transistor;

[0094] 18. The eighth PMOS transistor;

[0095] 19. First diode;

[0096] 20. Zeroth NMOS transistor;

[0097] 21. Second inverter;

[0098] 22. Second NMOS transistor;

[0099] 23. Third NMOS transistor;

[0100] 24. Fourth NMOS transistor;

[0101] 25. Fifth PMOS transistor;

[0102] 26. The sixth PMOS transistor;

[0103] 27. The seventh PMOS transistor;

[0104] 29. Second diode;

[0105] 602. First trigger circuit;

[0106] 603, First MOSFET;

[0107] 605. Second trigger circuit;

[0108] 606, Second MOSFET. Detailed Implementation

[0109] The technical solutions in the embodiments described below will be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments described herein, and not all of the embodiments. Based on the embodiments described herein, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this document.

[0110] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings herein are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0111] like Figure 1 The schematic diagram shown is of a reverse voltage protection circuit, including:

[0112] Comparator 101, the input port and output port of the circuit are connected to the input terminal of the comparator, the comparator is used to compare the voltage of the input port and the output port and output a comparison signal.

[0113] Trigger circuit 102 receives the comparison signal and turns on / off MOS transistor 103 connected between the input port and the output port according to the comparison signal.

[0114] The MOSFET 103 is used to prevent abnormal voltage from the output port from flowing back to the input port.

[0115] In this paper, the output port can be either a zeroth PMOS or a zeroth NMOS, depending on the type of the input port.

[0116] In the embodiment, the comparator 101 is used to compare the voltage of the input port and the output port, when the abnormal voltage appears in the output port, that is, the voltage of the output port is greater than or equal to the voltage of the input port, the comparison signal can be sent, the mutual coupling of the electronic devices is realized through the triggering circuit 102, and the MOS tube 103 is cut off. When the MOS tube 103 is cut off, the abnormal voltage can be prevented from flowing back to the input port through the output port.

[0117] It should be noted that generally, the one-way conduction of the high-voltage diode is used to prevent the abnormal voltage from flowing back to the input port. However, when the high-voltage diode is used to realize this function, because the on-resistance of the high-voltage diode is large, in the normal case, that is, when the voltage is transmitted from the input port to the output port, the high-voltage diode is inevitably needed to pass through, and then a part of the voltage is taken away by the high-voltage diode. According to experimental data, when the voltage of the input port is 5V, the high-voltage diode takes away about 0.7V of the voltage, and finally, the output port outputs 4.3V of the voltage. Obviously, the energy transmission efficiency is too low to meet the requirements of the precise microelectronic process.

[0118] And when the reverse voltage protection circuit in the present application is used, that is, when the MOS tube 103 is in the cut-off state, the abnormal voltage can be prevented from flowing back, and when the MOS tube 103 is in the on state, the MOS tube 103 works in the linear region, which can greatly reduce the on-voltage drop. According to the research, when 5V of the voltage is input to the input port, the MOS tube takes away at most 0.3V of the voltage, that is, the output port outputs at least 4.7V of the voltage, which can meet the requirements of the precise microelectronic process.

[0119] It should be noted that the type of the comparator is not limited in the present application. As a preferred mode, the forward comparator is used in the embodiment of the present application, but the forward comparator can be replaced by the reverse comparator, the proportional operation amplifier, the voltage follower, and the like according to the needs of the person skilled in the art, which will not be described herein.

[0120] It should be noted that in the circuit, there are the power supply VCC input and the GND input, and the voltage output by the output port also has two kinds, one is the forward voltage, and the other is the reverse voltage. When the power supply VCC is input, the output port outputs the forward voltage, and when the GND is input, the output port outputs the reverse voltage. Therefore, in the present application, the reverse circuit needs to be discussed in different cases, which will be discussed in detail below.

[0121] It should be noted that when the circuit on one side is discussed, the person skilled in the art can use the conventional means to prevent the abnormal voltage of the circuit on the other side from flowing back, for example, when the input port is the power supply VCC, the circuit on the other side can use, for example, the high-voltage diode to prevent the reverse voltage from flowing back. The present application does not limit this, which can reduce the chip flow difficulty by half.

[0122] As Figure 2 shown in the power supply VCC input port circuit schematic diagram, as an embodiment herein, when the input port is the power supply VCC, the trigger circuit 102 comprises: a fifth NMOS tube 15, a fourth PMOS tube 14, a first inverter 11, a sixth NMOS tube 16 and a second PMOS tube 12, and the output port is the zeroth PMOS tube 10.

[0123] The gate of the fifth NMOS tube 15 is connected with the output end of the first comparator 1011, and the source of the fifth NMOS tube 15 is connected with GND.

[0124] The gate of the fourth PMOS tube 14 is connected with the gate of the fifth NMOS tube 15, the drain of the fourth PMOS tube 14 is connected with the drain of the fifth NMOS tube 15, and the source of the fourth PMOS tube 14 is connected with the power supply VCC.

[0125] The input end of the first inverter 11 is connected with the output end of the first comparator 1011.

[0126] The gate of the sixth NMOS tube 16 is connected with the output end of the first inverter 11, and the source of the sixth NMOS tube 16 is connected with the GND.

[0127] The gate of the second PMOS tube 12 is connected with the connection point of the drain of the fifth NMOS tube 15 and the drain of the fourth PMOS tube 14, the drain of the second PMOS tube 12 is connected with the drain of the sixth NMOS tube 16, and the source of the second PMOS tube 12 is connected with the source of the zeroth PMOS tube 10.

[0128] It should be noted that the NMOS high level is turned on, and the PMOS low level is turned on.

[0129] It should be noted that in the case of the input port being connected with the power supply VCC, the MOS tube is the first PMOS tube 103, and the output port is the zeroth PMOS tube 10.

[0130] When the abnormal voltage appears at the drain of the zeroth PMOS transistor 10, the voltage at the drain of the zeroth PMOS transistor 10 is greater than the voltage at the input port, at this time, since the drain of the zeroth PMOS transistor 10 is connected to the positive output terminal of the first comparator 1011 and the input port is connected to the negative output terminal of the first comparator 1011, the first comparator 1011 outputs a high level, at this time, the fifth NMOS transistor 15 is turned on, the fourth PMOS transistor 14 is turned off, the first inverter 11 inverts the high level to a low level, and then the sixth NMOS transistor 16 is turned off, since the fifth NMOS transistor 15 is turned on, the fifth NMOS transistor 15 connects the gate of the second PMOS transistor 12 to GND, GND is equivalent to a low level, so the second PMOS transistor 12 is turned on, at this time, after the second PMOS transistor 12 is turned on, the MOS transistor 103 is connected between the gate and the source of the MOS transistor 103, and the MOS transistor 103 is turned off, preventing the abnormal voltage at the drain of the zeroth PMOS transistor 10 from flowing back to the input port.

[0131] When the abnormal voltage does not appear at the drain of the zeroth PMOS transistor 10, the voltage at the drain of the zeroth PMOS transistor 10 is less than the voltage at the input port, at this time, since the drain of the zeroth PMOS transistor 10 is connected to the positive output terminal of the first inverter 11 and the input port is connected to the negative output terminal of the first inverter 11, the first inverter 11 outputs a low level, at this time, the fifth NMOS transistor 15 is turned off, the fourth PMOS transistor 14 is turned on, at this time, the power supply VCC of the input port is equivalent to a high level, then the gate of the second PMOS transistor 12 is connected to the high level, the second PMOS transistor 12 is turned off, the first inverter 11 inverts the low level to a high level, and then the sixth NMOS transistor 16 is turned on, since the sixth NMOS transistor 16 is turned on, the gate of the MOS transistor 103 is connected to GND, GND is equivalent to a low level, so the MOS transistor 103 is turned on, at this time, after the MOS transistor 103 is turned on, the power supply VCC of the drain of the zeroth PMOS transistor 10 can be transmitted to the output port.

[0132] Therefore, through the above circuit, when the voltage at the output port is greater than the voltage at the input port, the abnormal voltage can be prevented from flowing back to the input port, and the power supply of the input port can be prevented from being broken down, thereby avoiding irreparable loss.

[0133] The first gate oxide protection circuit is arranged at the power supply VCC side. When the drain of the zeroth PMOS transistor 10 has an abnormal voltage greater than the input port, only the MOS transistor 103 is used to cut off the abnormal voltage, and the high-voltage PN junction of the drain and the substrate of the MOS transistor 103 is used to prevent the abnormal voltage from flowing back. Therefore, in order to prevent the second PMOS transistor 12 from being broken down by the abnormal voltage, a protection measure needs to be arranged at the gate of the second PMOS transistor 12. The third PMOS transistor 13, the first diode 19, and the first resistor 1 jointly protect the second PMOS transistor 12. The eighth PMOS transistor 18 protects the drain of the fourth PMOS transistor 14 from being broken down by the abnormal voltage flowing back. In this way, the abnormal voltage flowing back can be more safely prevented, and the components can be prevented from being damaged.

[0134] As shown in the first gate oxide protection circuit schematic diagram, Figure 3 As an embodiment, a first gate oxide protection circuit is further coupled between the output port and the trigger circuit. The first gate oxide protection circuit comprises a first resistor 1, an eighth PMOS transistor 18, a third PMOS transistor 13, and a first diode 19.

[0135] One end of the first resistor 1 is connected to the drain of the fifth NMOS transistor 15, and the other end is connected to the source of the eighth PMOS transistor 18.

[0136] The gate and the source of the eighth PMOS transistor 18 are connected, and the drain of the eighth PMOS transistor 18 is connected to the drain of the fourth PMOS transistor 14.

[0137] The gate and the source of the third PMOS transistor 13 are connected, the source of the third PMOS transistor 13 is connected to the source of the eighth PMOS transistor 18, and the drain of the third PMOS transistor 13 is connected to the anode of the first diode 19.

[0138] The cathode of the first diode 19 is connected to the source of the second PMOS transistor 12.

[0139] It should be understood that the source, gate, and substrate of the eighth PMOS transistor 18 and the third PMOS transistor 13 in the circuit are short-circuited to form an equivalent high-voltage diode. Therefore, the eighth PMOS transistor 18 and the third PMOS transistor 13 can also be replaced by a suitable high-voltage diode.

[0140] As shown in the GND input port circuit schematic diagram, Figure 4 As an embodiment, when the input port is GND, the trigger circuit comprises a fifth PMOS transistor 25, a fourth NMOS transistor 24, a second inverter 21, a sixth PMOS transistor 26, and a second NMOS transistor 22. The output port is a zeroth NMOS transistor 20.

[0141] The gate of the fifth PMOS tube 25 is connected with the output end of the second comparator 1012, and the source of the fifth PMOS tube 25 is connected with the power supply VCC;

[0142] The gate of the fourth NMOS tube 24 is connected with the gate of the fifth PMOS tube 25, the drain of the fourth NMOS tube 24 is connected with the drain of the fifth PMOS tube 25, and the source of the fourth NMOS tube 24 is connected with the GND;

[0143] The input end of the second inverter 21 is connected with the output end of the second comparator 1012;

[0144] The gate of the sixth PMOS tube 26 is connected with the output end of the second inverter 21, and the source of the sixth PMOS tube 26 is connected with the power supply VCC;

[0145] The gate of the second NMOS tube 22 is connected with the connection point of the drain of the fifth PMOS tube 25 and the drain of the fourth NMOS tube 24, the drain of the second NMOS tube 22 is connected with the drain of the sixth PMOS tube 26, and the source of the second NMOS tube 22 is connected with the source of the zeroth NMOS tube 20.

[0146] It should be noted that the NMOS high level is turned on, and the PMOS low level is turned on.

[0147] It should be noted that the MOS tube on the side of the input port GND is an NMOS tube.

[0148] When the abnormal voltage appears at the drain of the zeroth NMOS tube 20, the voltage at the drain of the zeroth NMOS tube 20 is lower than the voltage of the input port, at this time, since the drain of the zeroth NMOS tube 20 is connected with the positive output end of the second comparator 1012, and the input port is connected with the negative output end of the second comparator 1012, the output of the second comparator 1012 is low level, at this time, the fifth PMOS tube 25 is turned on, the fourth NMOS tube 24 is cut off, the second inverter 21 inverses the low level to high level, and then the sixth PMOS tube 26 is cut off, since the fifth PMOS tube 25 is turned on, the fifth PMOS tube 25 connects the gate of the second NMOS tube 22 with VCC, and VCC is equivalent to high level, so the second NMOS tube 22 is turned on, at this time, after the second NMOS tube 22 is turned on, it is equivalent to connecting the gate and the source of the MOS tube 103 through a wire, and the MOS tube 103 is cut off, thereby preventing the abnormal voltage of the output port from "absorbing" current from the input port.

[0149] When there is no abnormal voltage at the drain of the zeroth NMOS transistor 20, the voltage at the drain of the zeroth NMOS transistor 20 is greater than the voltage at the output port, at this time, since the drain of the zeroth NMOS transistor 20 is connected to the positive output end of the second comparator 1012, and the input port is connected to the negative output end of the second comparator 1012, the second comparator 1012 outputs a high level, at this time, the fifth PMOS transistor 25 is cut off, the fourth NMOS transistor 24 is turned on, the sixth PMOS transistor 26 is turned on after the high level is inverted to a low level by the second inverter 21, since the fourth NMOS transistor 24 is turned on, the fourth NMOS transistor 24 connects the gate of the second NMOS transistor 22 to GND, GND is equivalent to a low level, so the second NMOS transistor 22 is cut off, at the same time, the gate of the MOS transistor 103 is pulled to VCC through the turned-on sixth PMOS transistor, the MOS transistor 103 is turned on, at this time, the MOS transistor 103 works in a linear region, and the conduction voltage drop is very low.

[0150] Therefore, through the above circuit, it can be realized that when the voltage at the output port is less than the voltage at the input port, the output port is prevented from "absorbing" current from GND.

[0151] The second gate oxide protection circuit is arranged on the GND side, when the output port has an abnormal voltage less than the input port, at this time, only the MOS transistor can cut off the abnormal voltage, and the high-voltage PN junction of the drain and the buffer of the MOS transistor 103 prevents the output port from absorbing current from the input port GND, therefore, in order to prevent the second NMOS transistor 22 from being broken down by the abnormal voltage, a protection measure needs to be arranged at the gate of the second NMOS transistor 22, wherein the third NMOS transistor 23, the second diode 29 and the second resistor 2 jointly protect the second NMOS transistor 22, the seventh PMOS transistor 27 protects the drain of the fourth NMOS transistor 24 from being broken down by the abnormal voltage, in this way, the abnormal voltage can be more safely prevented from absorbing current from the input port, and the components can be prevented from being damaged.

[0152] Specifically, as shown in the second gate oxide protection circuit diagram, Figure 5 as an embodiment of the present application, the second gate oxide protection circuit comprises: a second resistor 2, a seventh PMOS transistor 27, a third NMOS transistor 23 and a second diode 29;

[0153] One end of the second resistor 2 is connected to the drain of the fifth PMOS transistor 25, and the other end is connected to the drain of the seventh PMOS transistor 27;

[0154] The gate of the seventh PMOS transistor 27 is connected to the source, and the source of the seventh PMOS transistor 27 is connected to the drain of the fourth NMOS transistor 24;

[0155] The gate of the third NMOS tube 23 is connected with the source, the source of the third NMOS tube 23 is connected with the drain of the seventh PMOS tube 27, and the drain of the third NMOS tube 23 is connected with the cathode of the second diode 29.

[0156] The anode of the second diode 29 is connected with the source of the second NMOS tube 22.

[0157] As Figure 6 A preferred reverse voltage protection circuit is shown in the figure, on both sides of the output port power supply VCC and GND, all using the reverse voltage protection circuit in this paper, including two comparators, two trigger circuits, a first MOS tube 603, a second MOS tube 606, a zeroth PMOS tube 10 and a zeroth NMOS tube 20, wherein:

[0158] A first comparator 1011, the power supply VCC and the drain of the zeroth PMOS tube 10 are connected to the input of the first comparator 1011, and the first comparator 1011 is used to compare the voltage of the power supply VCC and the drain of the zeroth PMOS tube 10, and output a first comparison signal;

[0159] A first trigger circuit 602 receives the first comparison signal, and according to the first comparison signal, the first MOS tube 603 connected between the power supply VCC and the output port is turned on / off;

[0160] The first MOS tube 603 is used to prevent abnormal voltage at the drain of the zeroth PMOS tube 10 from flowing back to the power supply VCC;

[0161] A second comparator 1012, the GND and the drain of the zeroth NMOS tube 20 are connected to the input of the second comparator 1012, and the second comparator 1012 is used to compare the voltage of the GND and the drain of the zeroth NMOS tube 20, and output a second comparison signal;

[0162] A second trigger circuit 605 receives the second comparison signal, and according to the second comparison signal, the second MOS tube 606 connected between the GND and the output port is turned on / off;

[0163] The second MOS tube 606 is used to prevent abnormal voltage at the drain of the zeroth NMOS tube 20 from flowing back to the GND.

[0164] It should be noted that, Figure 6The circuit can be applied to the field bus application scenario, for example, the first trigger circuit 602 side can output a high and low level, the second trigger circuit 605 can also output a high and low level, and through the two high and low levels, the signal control of the field bus can be realized.

[0165] In Figure 6 , the power supply VCC is used as an input port side, and the first trigger circuit is used to turn on or turn off the MOS tube to prevent the reverse flow of abnormal voltage of the output port. In GND as an input port side, the second trigger circuit is used to turn on or turn off the MOS tube to prevent the reverse flow of abnormal voltage of the output port.

[0166] Through the circuit on both sides, the use of high-voltage diodes can be avoided, thereby widening the process selection range. And compared with high-voltage diodes, the circuit has lower conduction voltage drop, thereby ensuring better output voltage characteristics.

[0167] As Figure 7 shown is a preferred trigger circuit schematic diagram of a reverse voltage protection circuit, which is an embodiment of the present application, the first trigger circuit comprises: a fifth NMOS tube 15, a fourth PMOS tube 14, a first inverter 11, a sixth NMOS tube 16 and a second PMOS tube 12.

[0168] The gate of the fifth NMOS tube 15 is connected with the output of the first comparator 1011, and the source of the fifth NMOS tube 15 is connected with GND.

[0169] The gate of the fourth PMOS tube 14 is connected with the gate of the fifth NMOS tube 15, the drain of the fourth PMOS tube 14 is connected with the drain of the fifth NMOS tube 15, and the source of the fourth PMOS tube 14 is connected with the power supply VCC.

[0170] The input of the first inverter 11 is connected with the output of the first comparator 1011.

[0171] The gate of the sixth NMOS tube 16 is connected with the output of the first inverter 11, and the source of the sixth NMOS tube 16 is connected with the GND.

[0172] The gate of the second PMOS tube 12 is connected with the connection point of the drain of the fifth NMOS tube 15 and the drain of the fourth PMOS tube 14, the drain of the second PMOS tube 12 is connected with the drain of the sixth NMOS tube 16, and the source of the second PMOS tube 12 is connected with the zeroth PMOS tube 10.

[0173] The second trigger circuit comprises a fifth PMOS tube 25, a fourth NMOS tube 24, a second inverter 21, a sixth PMOS tube 26 and a second NMOS tube 22.

[0174] The gate of the fifth PMOS tube 25 is connected with the output terminal of the first comparator 1011, and the source of the fifth PMOS tube 25 is connected with the power supply VCC.

[0175] The gate of the fourth NMOS tube 24 is connected with the gate of the fifth PMOS tube 25, the drain of the fourth NMOS tube 24 is connected with the drain of the fifth PMOS tube 25, and the source of the fourth NMOS tube 24 is connected with the GND.

[0176] The input terminal of the second inverter 21 is connected with the output terminal of the second comparator 1012.

[0177] The gate of the sixth PMOS tube 26 is connected with the output terminal of the second inverter 21, and the source of the sixth PMOS tube 26 is connected with the power supply VCC.

[0178] The gate of the second NMOS tube 22 is connected with the connection point of the drain of the fifth PMOS tube 25 and the drain of the fourth NMOS tube 24, the drain of the second NMOS tube 22 is connected with the drain of the sixth PMOS tube 26, and the source of the second NMOS tube 22 is connected with the zeroth NMOS tube 20.

[0179] It should be noted that the NMOS high level is turned on, and the PMOS low level is turned on.

[0180] It should be noted that the MOS tube for conducting or cutting off the reverse voltage protection circuit on the side of the input port of the power supply VCC is the first MOS tube 603, and the device for conducting or cutting off the reverse voltage protection circuit on the side of the input port of the GND is the second MOS tube 606.

[0181] The first gate oxide protection circuit is arranged on the side of the power supply VCC, when the output port appears an abnormal voltage greater than the input port, at this time, only the MOS tube is cut off to the abnormal voltage, the high-voltage PN junction of the drain of the first MOS tube 603 prevents the reverse flow of the abnormal voltage, therefore, in order to prevent the second PMOS tube 12 from being broken down by the abnormal voltage, a protection measure needs to be arranged at the gate of the second PMOS tube 12, wherein the third PMOS tube 13, the first diode 19 and the first resistor 1 jointly protect the second PMOS tube 12, and the eighth PMOS tube 18 protects the drain of the fourth PMOS tube 14 from being broken down by the reverse flow of the abnormal voltage, in this way, the reverse flow of the abnormal voltage can be more safely prevented, and the damage to the components can be avoided.

[0182] The second gate oxide protection circuit is arranged on the GND side. When the output port has an abnormal voltage less than the input port, only the second MOS tube 606 can cut off the abnormal voltage. The high-voltage PN junction of the drain and the substrate of the second MOS tube 606 prevents the negative high voltage of the output port from absorbing current from the input port GND. Therefore, in order to prevent the second NMOS tube 22 from being broken down by the abnormal voltage, a protection measure needs to be arranged on the gate of the second NMOS tube 22. The third NMOS tube 23, the second diode 29, and the second resistor 2 jointly protect the second NMOS tube 22. The seventh PMOS tube 27 protects the drain of the fourth NMOS tube 24 from being broken down by the abnormal voltage. In this way, the abnormal voltage can be more safely prevented from absorbing current from the input port, and the components can be prevented from being damaged.

[0183] It should be noted that the first gate oxide protection circuit is arranged on the power supply VCC side, and the second gate oxide protection circuit is arranged on the GND side.

[0184] Specifically, as shown in the double gate oxide protection circuit schematic diagram, Figure 8 as an embodiment of the present application, the output port and the trigger circuit are further coupled with a first gate oxide protection circuit. The first gate oxide protection circuit comprises a first resistor 1, an eighth PMOS tube 18, a third PMOS tube 13, and a first diode 19.

[0185] One end of the first resistor 1 is connected with the drain of the fifth NMOS tube 15, and the other end is connected with the source of the eighth PMOS tube 18.

[0186] The gate and the source of the eighth PMOS tube 18 are connected, and the drain of the eighth PMOS tube 18 is connected with the drain of the fourth PMOS tube 14.

[0187] The gate and the source of the third PMOS tube 13 are connected, the source of the third PMOS tube 13 is connected with the source of the eighth PMOS tube 18, and the drain of the third PMOS tube 13 is connected with the anode of the first diode 19.

[0188] The cathode of the first diode 19 is connected with the source of the second PMOS tube 12.

[0189] The output port and the trigger circuit are further coupled with a second gate oxide protection circuit. The second gate oxide protection circuit comprises a second resistor 2, a seventh PMOS tube 27, a third NMOS tube 23, and a second diode 29.

[0190] One end of the second resistor 2 is connected with the drain of the fifth PMOS tube 25, and the other end is connected with the drain of the seventh PMOS tube 27.

[0191] The gate of the seventh PMOS transistor 27 is connected to the source, and the source of the seventh PMOS transistor 27 is connected to the drain of the fourth NMOS transistor 24.

[0192] The gate of the third NMOS transistor 23 is connected to the source, the source of the third NMOS transistor 23 is connected to the drain of the seventh PMOS transistor 27, and the drain of the third NMOS transistor 23 is connected to the cathode of the second diode 29.

[0193] The anode of the second diode 29 is connected to the source of the second NMOS transistor 22.

[0194] It should be understood that the source, gate, and substrate of the eighth PMOS transistor 18 and the third PMOS transistor 13 in the circuit are shorted to form a high-voltage diode, which can also be replaced by a suitable high-voltage diode. Similarly, the source, gate, and substrate of the third NMOS transistor 23 and the seventh PMOS transistor 27 in the circuit are shorted to form a high-voltage diode, which can also be replaced by a suitable high-voltage diode.

[0195] As an example of this article, it can be applied to fieldbuses such as CAN bus, RS485 bus and RS422 bus. In the CAN bus, there are two control signals and two output signals from the output port. In the RS485 and RS422 buses, there are two control signals and one output signal. Therefore, it is necessary to discuss the cases where the output port outputs one or two signals.

[0196] The output port includes a zeroth PMOS transistor 10 and a zeroth NMOS transistor 20;

[0197] like Figure 9 The diagram shows a signal reverse protection circuit with gate oxide protection. When the output port outputs a signal, the gate of the zeroth PMOS transistor 10 is connected to the first control signal, the source of the zeroth PMOS transistor 10 is connected to the source of the second PMOS transistor 12, the gate of the zeroth NMOS transistor 20 is connected to the second control signal, the source of the zeroth NMOS transistor 20 is connected to the source of the second NMOS transistor 22, and the drain of the zeroth PMOS transistor 10 is connected to the drain of the zeroth NMOS transistor 20, thus outputting a signal.

[0198] It should be noted that, Figure 9 The circuit shown can be applied to RS-485 and RS-422 buses. The output port of this circuit outputs only one signal. There can be a bus control signal on the power supply VCC side and another bus control signal on the GND side. The signal output of the output port is realized through the bus control signal.

[0199] likeFigure 10 The diagram shown illustrates a single-signal reverse protection circuit without a gate oxide protection circuit. Figure 10 If the chip uses a thick gate oxide process, the first gate oxide protection circuit can be removed on the VCC side and the second gate oxide protection circuit can be removed on the GND side.

[0200] It should be noted that, Figure 10 The circuit shown can be applied to RS-485 and RS-422 buses. The output port of this circuit outputs only one signal. There can be a bus control signal on the power supply VCC side and another bus control signal on the GND side. The signal output of the output port is realized through the bus control signal.

[0201] like Figure 11 The diagram shows a two-way signal reverse protection circuit with gate oxide protection. When the output port outputs two signals, the gate of the zeroth PMOS transistor 10 is connected to the first control signal, the source of the zeroth PMOS transistor 10 is connected to the source of the second PMOS transistor 12, the gate of the zeroth NMOS transistor 20 is connected to the second control signal, the source of the zeroth NMOS transistor 20 is connected to the source of the second NMOS transistor 22, the drain of the zeroth PMOS transistor 10 outputs one signal, and the drain of the zeroth NMOS transistor 20 outputs one signal.

[0202] It should be noted that, Figure 11 The circuit shown can be applied to the CAN bus. The output port of this circuit can output two signals. One bus control signal can be provided on the power supply VCC side, corresponding to the CAN-H output signal or the H-IO output signal. Another bus control signal can be provided on the GND side, corresponding to the CAN-L output signal or the L-IO output signal. Through the two bus control signals, the two signal outputs of different output ports can be realized.

[0203] like Figure 12 The diagram shown illustrates a two-channel reverse protection circuit without gate oxide protection. Figure 12 If the chip uses a thick gate oxide process, the first gate oxide protection circuit can be removed on the VCC side and the second gate oxide protection circuit can be removed on the GND side.

[0204] It should be noted that, Figure 12 The circuit shown can be applied to the CAN bus. The output port of this circuit can output two signals. One bus control signal can be provided on the power supply VCC side, corresponding to the CAN-H output signal or the H-IO output signal. Another bus control signal can be provided on the GND side, corresponding to the CAN-L output signal or the L-IO output signal. Through the two bus control signals, the two signal outputs of different output ports can be realized.

[0205] The embodiments of the present application also provide an isolated bus transceiver with the reverse voltage protection circuit. It should be noted that the isolated bus transceiver is also integrated with a DC-DC conversion device, a signal isolation transmission device and a bus transceiving device. The isolated bus transceiver can be a chip or an integrated circuit, which is not limited herein.

[0206] Similarly, the reverse voltage protection circuit herein can be applied to the application scenario of the field bus, and can also be applied to the scenario of protecting the input power supply except for the field bus. Those skilled in the art can adjust the parameters of the MOS tube, the trigger circuit and the gate oxide protection circuit according to actual needs to realize power supply protection in different scenarios.

[0207] It should also be noted that, for example, when the gate oxide protection circuit is needed when the chip process is used to integrate the isolated bus transceiver herein, a thin gate oxide process can be used to manufacture the chip, and when the gate oxide protection circuit is not needed, a thick gate oxide process can be used to manufacture the chip.

[0208] In the several embodiments provided herein, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. In actual implementation, another division mode can be used, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can also be electrical, mechanical or other forms of connection.

[0209] It should also be understood that, in the embodiments of the present application, the term "and / or" is only used to describe the association relationship of the associated objects, and means that there can be three relationships. For example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone. In addition, the character " / " in the present application generally means that the front and rear associated objects have an "or" relationship.

[0210] The principles and implementation modes of the present application are described by using specific embodiments. The above description of the embodiments is only used to help understand the method and its core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation mode and application range can be changed. In summary, the content of the present application should not be understood as a limitation.

Claims

1. A reverse voltage protection circuit, characterized in that, When the circuit's input port is the power supply VCC, it includes: The input and output ports of the circuit are connected to the input terminal of the comparator. The comparator is used to compare the voltages at the input and output ports and output a comparison signal. A trigger circuit receives the comparison signal and turns on / off the MOS transistor connected between the input port and the output port according to the comparison signal. The MOSFET is used to prevent abnormal voltage from the output port from flowing back to the input port; The trigger circuit includes: a fifth NMOS transistor, a fourth PMOS transistor, a first inverter, a sixth NMOS transistor, and a second PMOS transistor, and the output port is the zeroth PMOS transistor; The gate of the fifth NMOS transistor is connected to the output terminal of the comparator, and the source of the fifth NMOS transistor is connected to GND. The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply VCC. The input terminal of the first inverter is connected to the output terminal of the comparator; The gate of the sixth NMOS transistor is connected to the output terminal of the inverter, and the source of the sixth NMOS transistor is connected to GND. The gate of the second PMOS transistor is connected to the junction of the drain of the fifth NMOS transistor and the drain of the fourth PMOS transistor. The drain of the second PMOS transistor is connected to the drain of the sixth NMOS transistor. The source of the second PMOS transistor is connected to the source of the zeroth PMOS transistor.

2. The reverse voltage protection circuit according to claim 1, characterized in that, A first gate oxide protection circuit is also coupled between the output port and the trigger circuit. The first gate oxide protection circuit includes: a first resistor, an eighth PMOS transistor, a third PMOS transistor, and a first diode. One end of the first resistor is connected to the drain of the fifth NMOS transistor, and the other end is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the source, and the drain of the eighth PMOS transistor is connected to the drain of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to its source, the source of the third PMOS transistor is connected to the source of the eighth PMOS transistor, and the drain of the third PMOS transistor is connected to the anode of the first diode. The cathode of the first diode is connected to the source of the second PMOS transistor.

3. A reverse voltage protection circuit, characterized in that, When the circuit's input port is GND, it includes: The input and output ports of the circuit are connected to the input terminal of the comparator. The comparator is used to compare the voltages at the input and output ports and output a comparison signal. A trigger circuit receives the comparison signal and turns on / off the MOS transistor connected between the input port and the output port according to the comparison signal. The MOSFET is used to prevent abnormal voltage from the output port from flowing back to the input port; The trigger circuit includes: a fifth PMOS transistor, a fourth NMOS transistor, a second inverter, a sixth PMOS transistor, and a second NMOS transistor, and the output port is the zeroth NMOS transistor; The gate of the fifth PMOS transistor is connected to the output terminal of the comparator, and the source of the fifth PMOS transistor is connected to the power supply VCC. The gate of the fourth NMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the fourth NMOS transistor is connected to GND. The input terminal of the second inverter is connected to the output terminal of the comparator; The gate of the sixth PMOS transistor is connected to the output terminal of the inverter, and the source of the sixth PMOS transistor is connected to the power supply VCC. The gate of the second NMOS transistor is connected to the junction of the drain of the fifth PMOS transistor and the drain of the fourth NMOS transistor, the drain of the second NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the second NMOS transistor is connected to the source of the zeroth NMOS transistor.

4. The reverse voltage protection circuit according to claim 3, characterized in that, A second gate oxide protection circuit is also coupled between the output port and the trigger circuit. The second gate oxide protection circuit includes: a second resistor, a seventh PMOS transistor, a third NMOS transistor, and a second diode. One end of the second resistor is connected to the drain of the fifth PMOS transistor, and the other end is connected to the drain of the seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the source, and the source of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to its source, the source of the third NMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the third NMOS transistor is connected to the cathode of the second diode. The anode of the second diode is connected to the source of the second NMOS transistor.

5. A reverse voltage protection circuit, characterized in that, When the circuit's input ports include power supply VCC and GND, it includes two comparators, two trigger circuits, a first MOSFET, a second MOSFET, a zeroth PMOS transistor, and a zeroth NMOS transistor, wherein: The first comparator is connected to the input terminal of the circuit's power supply VCC and the drain of the zeroth PMOS transistor. The first comparator is used to compare the voltage of the power supply VCC and the drain of the zeroth PMOS transistor and output a first comparison signal. A first trigger circuit receives the first comparison signal and turns on / off the first MOS transistor connected between the power supply VCC and the output port according to the first comparison signal. The first MOS transistor is used to prevent abnormal voltage at the drain of the zeroth PMOS transistor from flowing back to the power supply VCC; The second comparator connects GND and the drain of the zeroth NMOS transistor to its input. The second comparator compares the voltages of GND and the drain of the zeroth NMOS transistor and outputs a second comparison signal. The second trigger circuit receives the second comparison signal and turns on / off the second MOS transistor connected between GND and the output port according to the second comparison signal. The second MOS transistor is used to prevent abnormal voltage at the drain of the zeroth NMOS transistor from flowing back to GND; The first trigger circuit includes: a fifth NMOS transistor, a fourth PMOS transistor, a first inverter, a sixth NMOS transistor, and a second PMOS transistor; The gate of the fifth NMOS transistor is connected to the output terminal of the comparator, and the source of the fifth NMOS transistor is connected to GND. The gate of the fourth PMOS transistor is connected to the gate of the fifth NMOS transistor, the drain of the fourth PMOS transistor is connected to the drain of the fifth NMOS transistor, and the source of the fourth PMOS transistor is connected to the power supply VCC. The input terminal of the first inverter is connected to the output terminal of the comparator; The gate of the sixth NMOS transistor is connected to the output terminal of the inverter, and the source of the sixth NMOS transistor is connected to GND. The gate of the second PMOS transistor is connected to the junction of the drain of the fifth NMOS transistor and the drain of the fourth PMOS transistor, the drain of the second PMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the second PMOS transistor is connected to the source of the zeroth PMOS transistor. The second trigger circuit includes: a fifth PMOS transistor, a fourth NMOS transistor, a second inverter, a sixth PMOS transistor, and a second NMOS transistor; The gate of the fifth PMOS transistor is connected to the output terminal of the comparator, and the source of the fifth PMOS transistor is connected to the power supply VCC. The gate of the fourth NMOS transistor is connected to the gate of the fifth PMOS transistor, the drain of the fourth NMOS transistor is connected to the drain of the fifth PMOS transistor, and the source of the fourth NMOS transistor is connected to GND. The input terminal of the second inverter is connected to the output terminal of the comparator; The gate of the sixth PMOS transistor is connected to the output terminal of the inverter, and the source of the sixth PMOS transistor is connected to the power supply VCC. The gate of the second NMOS transistor is connected to the junction of the drain of the fifth PMOS transistor and the drain of the fourth NMOS transistor, the drain of the second NMOS transistor is connected to the drain of the sixth PMOS transistor, and the source of the second NMOS transistor is connected to the source of the zeroth NMOS transistor.

6. The reverse voltage protection circuit according to claim 5, characterized in that, A first gate oxide protection circuit is also coupled between the output port and the trigger circuit. The first gate oxide protection circuit includes: a first resistor, an eighth PMOS transistor, a third PMOS transistor, and a first diode. One end of the first resistor is connected to the drain of the fifth NMOS transistor, and the other end is connected to the source of the eighth PMOS transistor. The gate of the eighth PMOS transistor is connected to the source, and the drain of the eighth PMOS transistor is connected to the drain of the fourth PMOS transistor. The gate of the third PMOS transistor is connected to its source, the source of the third PMOS transistor is connected to the source of the eighth PMOS transistor, and the drain of the third PMOS transistor is connected to the anode of the first diode. The cathode of the first diode is connected to the source of the second PMOS transistor; A second gate oxide protection circuit is also coupled between the output port and the trigger circuit. The second gate oxide protection circuit includes: a second resistor, a seventh PMOS transistor, a third NMOS transistor, and a second diode. One end of the second resistor is connected to the drain of the fifth PMOS transistor, and the other end is connected to the drain of the seventh PMOS transistor. The gate of the seventh PMOS transistor is connected to the source, and the source of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor. The gate of the third NMOS transistor is connected to its source, the source of the third NMOS transistor is connected to the drain of the seventh PMOS transistor, and the drain of the third NMOS transistor is connected to the cathode of the second diode. The anode of the second diode is connected to the source of the second NMOS transistor.

7. The reverse voltage protection circuit according to claim 5, characterized in that, The output port includes the zeroth PMOS transistor and the zeroth NMOS transistor; When the output port outputs one signal, the gate of the zeroth PMOS transistor is connected to the first control signal, the source of the zeroth PMOS transistor is connected to the source of the second PMOS transistor, the gate of the zeroth NMOS transistor is connected to the second control signal, the source of the zeroth NMOS transistor is connected to the source of the second NMOS transistor, the drain of the zeroth PMOS transistor is connected to the drain of the zeroth NMOS transistor, and one signal is output. When the output port outputs two signals, the gate of the zeroth PMOS transistor is connected to the first control signal, the source of the zeroth PMOS transistor is connected to the source of the second PMOS transistor, the gate of the zeroth NMOS transistor is connected to the second control signal, the source of the zeroth NMOS transistor is connected to the source of the second NMOS transistor, the drain of the zeroth PMOS transistor outputs one signal, and the drain of the zeroth NMOS transistor outputs one signal.

8. A bus transceiver, characterized in that, The bus transceiver is provided with a reverse voltage protection circuit as described in any one of claims 1-7.

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