An adaptive pulse width de-noising folding circuit

Abstract

The application provides an adaptive pulse width noise folding circuit, which comprises a frequency discriminator, a charge pump, a pulse width current source, a loop filter, a voltage controlled oscillator, an auxiliary controller, a pulse width generator, a multi-mode frequency divider and a sum-difference modulator. The pulse width generator is adapted to follow the change of the output frequency of the voltage controlled oscillator, and when the output frequency changes, the offset time of the frequency discriminator is changed correspondingly, so that the nonlinear region of the frequency discriminator / charge pump is avoided, the noise folding is avoided, and the reference spur performance is not deteriorated. The introduction of the technology will bring greater power consumption and area. In order to reduce the power consumption and the area, the inverter delay unit of the pulse width generator is copied by the equal ratio replication technology in the application, the delay time is unchanged, and the power consumption and the area of the delay unit are reduced by equal ratio.

Description

TECHNICAL FIELD

[0001] The application is a self-adaptive pulse width de-noise folding circuit, belonging to the technical field of integrated circuits. BACKGROUND

[0002] In modern various types of system on chip, usually adopt the fractional-N phase-locked loop with good output frequency accuracy as frequency generating circuit, provide the required local oscillator signal or clock signal of system; on the other hand, in the selection of oscillator structure, ring oscillator (RO) gradually becomes mainstream, because it has extremely wide frequency range and multi-phase output. In the fractional-N phase-locked loop based on sum-difference modulator (SDM), due to the inevitable mismatch between charge pump (CP) charging and discharging current, the nonlinearity of the circuit causes the out-of-band high frequency noise to be folded into the band, which deteriorates the in-band noise performance.

[0003] When the loop is locked, due to the inevitable nonlinearity, the transmission curve of the frequency discriminator / charge pump (PFD / CP) appears nonlinear near the zero point, and some traditional methods have been proposed to solve this problem. For example Figure 2 A fixed static current is added to the CP load end When the loop is locked, a fixed phase difference is formed, avoiding the influence of PFD / CP nonlinearity. Based on the same principle, for example Figure 3 A delay is added in the PFD circuit The DN signal is generated later than the UP signal Turn off The current source, so in the circuit, more than Size of current is extracted, to increase the effect of static current. Due to the large ripple on the control voltage Vc, the system reference spur is seriously deteriorated, and for this problem, for example Figure 4 A duty cycle fixed offset current is added to the CP load end From the timing diagram, if the pulse width signal used to select the offset current has the appropriate phase, the ripple Will be reduced, and the reference spur performance will not be deteriorated. But for the traditional pulse width current linearization technology, the pulse width is fixed, when the output frequency range is large, it cannot maintain good reference spur performance while better suppressing noise folding, therefore it is of great significance to invent a pulse width adaptive output frequency scheme. SUMMARY

[0004] In view of the deficiencies existing in the prior art, the application provides a self-adaptive pulse width de-noise folding circuit, which increases an adaptive pulse width generator to solve the problems in the above background art.

[0005] In order to achieve the above object, the application is realized by the following technical scheme: an adaptive pulse width de-noise folding circuit, comprising an auxiliary controller, a pulse width generator, a pulse width current source, a loop filter, a voltage controlled oscillator, a multi-mode frequency divider, a sum-difference modulator, a frequency discriminator and a charge pump, the auxiliary controller is connected with the pulse width generator, the pulse width signal B generated by the pulse width generator is connected and controls the pulse width current source, effectively avoiding the non-linear region of the frequency discriminator / charge pump and not deteriorating the reference spur, the pulse width current source is connected with the charge pump and the loop filter at the same point, the loop filter is connected with the pulse width generator and the voltage controlled oscillator at the same point, the voltage controlled oscillator is connected with the multi-mode frequency divider, the multi-mode frequency divider is connected with the sum-difference modulator and the frequency discriminator at the same point, the frequency discriminator is connected with the charge pump, the pulse width generator is composed of a buffer U6, an inverter U7 and an AND gate U8, the input of the buffer U6 is connected with a reference source signal REF and a control signal Vc, the output of the buffer U6 is connected with the input of the inverter U7, the output of the inverter U7 is connected with one input of the AND gate U8, the reference source signal REF is connected with the other input of the AND gate U8, and the output of the AND gate U8 outputs a pulse width signal B, when the auxiliary controller detects that the loop is locked, the pulse width generator starts to work, the pulse width of the pulse width signal B output by the pulse width generator, and the output frequency of the voltage controlled oscillator are adaptively followed.

[0006] Further, the voltage controlled oscillator is composed of an inverter U1, an inverter U2, an inverter U3, an inverter U4 and an inverter U5, the output of the inverter U1 is connected with the input of the inverter U2, the output of the inverter U2 is connected with the input of the inverter U3, the output of the inverter U3 is connected with the input of the inverter U4, the output of the inverter U4 is connected with the input of the inverter U5, the output Vout of the inverter U5 is connected with the input of the inverter U1, and the inverters U1, U2, U3, U4 and U5 are all composed of M1 and M2, wherein the sizes of the single transistors M1 and M2 are equal, and the numbers of the single transistors M1 and M2 are not equal, M1 is composed of 8 parallel transistors, and M2 is composed of 24 parallel transistors, that is, the total width of M2 is 3 times of the total width of M1, and the total lengths of M1 and M2 are equal, the source end of M2 is connected with a control voltage Vc, and the output frequency is changed by changing Vc.

[0007] Further, the delay time of the buffer is 2 times of the period of the voltage controlled oscillator, the buffer U6 is composed of 25 cascaded inverters U9 to U28, the input end of the inverter U9 is connected with a reference source signal REF, the control ends of the inverters U9 to U28 are connected with a control signal Vc, the delay time of the buffer is changed, and the inverter U28 is connected with an output signal A.

[0008] Further, the inverters U9 to U28 are consistent with the structure of the inverters U1 to U5, M1 and M2 adopt the equal ratio replication technology, the parallel quantity is reduced by 8 times in proportion, the width is reduced by 8 times in proportion, the delay is unchanged, the power consumption is reduced by 8 times, the area is reduced by 8 times, the transistors M3 and M4 are obtained, and the inverters U9 to U28 are all composed of the transistors M3 and M4.

[0009] The application has the advantages that the application is a self-adaptive pulse width denoising folding circuit, an adaptive pulse width denoising folding circuit is provided, a pulse width adaptive circuit is adopted, the offset time of a phase discriminator is changed simultaneously when the frequency of an output signal changes, so that the appropriate pulse width is ensured, and the working frequency range of a phase-locked loop is increased. Since the number of inverter delay units is large, the power consumption and the area are greatly increased, in order to reduce the power consumption and the area, the application adopts the equal ratio replication technology for the inverter delay units of the buffer, the delay time is unchanged, and the power consumption and the area of the buffer are reduced in proportion. In actual use, the application is more suitable for the low-power and small-size field. BRIEF DESCRIPTION OF DRAWINGS

[0010] Other characteristics, objects and advantages of the application will become more apparent from the following detailed description of non-restrictive embodiments, made with reference to the attached drawings:

[0011] Figure 1 The structure diagram of the self-adaptive pulse width denoising folding circuit provided by the application;

[0012] Figure 2 The schematic diagram of the existing direct current offset linearization compensation technology;

[0013] Figure 3 The schematic diagram of the existing increase delay linearization compensation technology;

[0014] Figure 4 The schematic diagram of the existing pulse width offset linearization compensation technology;

[0015] Figure 5 The circuit principle diagram of the voltage-controlled oscillator in the application;

[0016] Figure 6 The input signal simulation eye diagram of the phase discriminator in the application;

[0017] Figure 7 The circuit principle diagram of the pulse width generator in the self-adaptive pulse width denoising folding circuit of the application;

[0018] Figure 8 The timing diagram of the pulse width generator;

[0019] Figure 9 The buffer circuit principle diagram in the pulse width generator circuit;

[0020] Figure 10 Figure 6 is a simulation comparison chart of the output pulse width of the 2Tvco and the actual output pulse width. DETAILED DESCRIPTION

[0021] In order to make the technical means, creative features, purposes and effects of the present application easy to understand, the technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments (the selection of the oscillator can be various, as long as the delay unit in the pulse width generator applies the same delay unit as the structure of the oscillator, and the equal ratio replication technology can also be adopted to reduce the area and power consumption of the pulse width generator, which are all within the protection scope of the present patent). Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the protection scope of the present application.

[0022] Noise folding: in a fractional-N PLL based on a sigma-delta modulator, the quantization noise shaped to high frequency offset by the sigma-delta modulator is folded back to low frequency offset due to the nonlinearity in the loop, i.e. the mismatch of charge-in and charge-out current in the charge pump, which worsens the in-band noise.

[0023] Reference spur: the non-ideal factors in the charge pump (such as the mismatch of charge-in and charge-out current) will introduce a periodic ripple in the oscillator control voltage signal with the same frequency as the reference clock, which results in a periodic spur in the output signal, and the frequency difference between the frequency at the spur and the carrier frequency is the frequency of the reference clock.

[0024] Referring to Figure 1 The present application provides a kind of adaptive pulse width noise folding circuit scheme: including auxiliary controller, pulse width generator, pulse width current source, loop filter, voltage controlled oscillator, multi-mode frequency divider, sigma-delta modulator, frequency discriminator and phase detector and charge pump, the auxiliary controller is connected with the pulse width generator, the pulse width signal B generated by the pulse width generator is connected and controls the pulse width current source, effectively avoids frequency discriminator / charge pump non-linear region and does not worsen reference spur, the pulse width current source is connected with the charge pump and the loop filter in same point, the loop filter is connected with the pulse width generator and the voltage controlled oscillator in one point, the voltage controlled oscillator is connected with the multi-mode frequency divider, the multi-mode frequency divider is connected with the sigma-delta modulator and the frequency discriminator and phase detector in same point, the frequency discriminator and phase detector are connected with the charge pump.

[0025] The voltage-controlled oscillator is composed of inverters U1, U2, U3, U4 and U5, the output of the inverter U1 is connected with the input of the inverter U2, the output of the inverter U2 is connected with the input of the inverter U3, the output of the inverter U3 is connected with the input of the inverter U4, the output of the inverter U4 is connected with the input of the inverter U5, the output Vout of the inverter U5 is connected with the input of the inverter U1, and the inverters U1, U2, U3, U4 and U5 are composed of M1 and M2, wherein M1 and M2 are single transistors with equal size and unequal number, M1 is 8 parallel transistors, and M2 is 24 parallel transistors, that is, the total width of M2 is 3 times of the total width of M1, and the total length is equal, the source end of the M2 transistor is connected with the control voltage Vc, and the output frequency size is changed by changing Vc.

[0026] The pulse width generator is composed of a buffer U6, an inverter U7 and an AND gate U8, the input of the buffer U6 is connected with a reference source signal REF and a control signal Vc, the output of the buffer U6 is connected with the input of the inverter U7, the output of the inverter U7 is connected with one input of the AND gate U8, the reference source signal REF is connected with the other input of the AND gate U8, and the output of the AND gate U8 outputs a pulse width signal B, the pulse width generator starts to work when the auxiliary controller detects loop locking, and the pulse width of the pulse width signal B output by the pulse width generator is adaptively followed to the output frequency of the voltage-controlled oscillator.

[0027] The delay time of the buffer is 2 times of the period of the voltage-controlled oscillator, the buffer U6 is composed of 25-stage inverters U9 to U28 connected in cascade, the input of the inverter U9 is connected with a reference source signal REF, the control ends of the inverters U9 to U28 are connected with a control signal Vc, the delay time of the buffer is changed, and the inverter U28 is connected with an output signal A.

[0028] The inverters U9 to U28 keep consistent with the structure of the inverters U1 to U5, M1 and M2 adopt equal-ratio replication technology, the parallel number is reduced by 8 times in proportion, that is, the width is reduced by 8 times in proportion, the delay time is unchanged, the power consumption is reduced by 8 times, the area is reduced by 8 times, transistors M3 and M4 are obtained, and the inverters U9 to U28 are composed of the transistors M3 and M4.

[0029] The working principle of the application is as follows:

[0030] The application provides a self-adaptive pulse width denoising folding circuit, Figure 1 When the auxiliary control module (ACM) detects loop locking, the pulse width generator (PG) starts to work, adaptively follows the output frequency of the voltage-controlled oscillator to generate a narrow pulse signal B to control the switch to be turned on or off, that is, the offset current The switch is turned on and turned off in sequence. The delay unit used in the pulse generator is consistent with the inverter delay unit of the voltage-controlled oscillator, and has the same delay time constant, so as to ensure that the pulse width generator output pulse width is adaptive to the frequency of the voltage-controlled oscillator output, and since

[0031]

[0032] In the formula is the oscillation period of the voltage-controlled oscillator, N is the number of delay units (i.e. the number of inverter stages) in the voltage-controlled oscillator, is the delay time of the inverter. Since the delay time of one period of the oscillator needs 2N inverters, resulting in excessive power consumption and area consumption of the pulse width generation module, it is of great significance to invent a low-power and small-area pulse buffer.

[0033] The ring oscillator used in the application is as shown in Figure 5 Based on the 5-stage ring oscillator of inverter U1, inverter U2, inverter U3, inverter U4 and inverter U5, the Barkhausen criterion is met, and the ring loop oscillates, is the output, is the control voltage, and the output waveform of each inverter is opposite in phase to the input waveform. The inverter delay unit is composed of M1 and M2, wherein M1 and M2 are equal in size and unequal in number, M1 is 8 identical transistors in parallel, and M2 is 24 identical transistors in parallel, that is, the total width of M2 is 3 times the total width of M1, and the total length is equal, because:

[0034] Oscillation frequency

[0035] Delay time ,

[0036] R is the equivalent impedance of the delay unit output node, is the equivalent impedance of M1, is the equivalent impedance of M2, is the equivalent capacitance of the delay unit output, and its size is:

[0037]

[0038] , , , , , and represent the input capacitance, output capacitance, gate oxide capacitance, M1 transistor width, M1 transistor length, M2 transistor width and M2 transistor length of the delay unit, respectively. From the above formula, we can get:

[0039]

[0040] Because

[0041] ,

[0042] 、 The process-related quantity and . Thus, the delay time

[0043]

[0044] Therefore, from the above formula, the delay time is irrelevant to the width of M1 and M2, and is closely related to the length of M1 and M2.

[0045] The present application uses a sum-difference modulator based on the MASH1-1-1 structure, the maximum variation range of the division ratio of which is 8 times the period of the output signal of the phase-locked loop (fREF). As Figure 6 , before the compensation circuit structure is added, when the loop is locked, the output signal is 2.4 GHz, and the rising edges of the feedback signal DIV are mostly distributed before and after the rising edge of the reference signal REF , so the working area of the frequency discriminator should be shifted , according to the formula

[0046]

[0047] When the shift time of the frequency discriminator is , that is, the pulse width is , so when the output frequency of the oscillator changes, the pulse width also changes adaptively.

[0048] Therefore, the present application proposes an adaptive pulse width generation circuit, the structure of the pulse width generation delay unit is consistent with that of the oscillator delay unit, when the output frequency changes, the pulse width changes adaptively, which suppresses noise folding while not deteriorating reference spur. Figure 7 As Figure 8 shown, the pulse width generator is composed of a buffer U6, an inverter U7 and an AND gate U8, Vc controls the delay time of the buffer, the reference source signal REF is the input signal of the buffer U6, the output signal A is obtained after the signal passes through the buffer U6, the signal A is inverted after passing through the inverter U7, and the narrow pulse signal B is obtained after the inverted signal and the reference signal REF pass through the AND gate U8, the timing diagram is as

[0049] ,

[0050] The N=5 of the application, namely the buffer is composed of 20-stage inverter chain composed of U9~U28, as shown in Figure 9 , because of the introduction of more delay unit, will lead to power consumption and area greatly increased, in the increasingly low power consumption and small size of the application is unacceptable, so the solution of power consumption and area is particularly important. Because the buffer and voltage controlled oscillator have the same inverter delay unit, when the oscillator is at the output frequency of 2.4GHz, the buffer power consumption reaches 0.5mW. Because the delay time , the power consumption of the delay unit is proportional to the width of M1, M2. Therefore, the application proposes a low power consumption, small area pulse width generation circuit, which uses the equal ratio replication technology for the inverter delay unit of the buffer, and the width of M1, M2 is reduced by 8 times, that is, m is reduced by 8 times, to obtain an inverter delay unit composed of M3, M4. When the output frequency reaches 2.4GHz, the power consumption is reduced to 0.065mW, and the buffer power consumption is reduced by about 8 times. When the output frequency changes from 0.75GHz to 3.2GHz, as shown in Figure 10 , the output and the actual output narrow pulse width are always close, meeting the design requirements. Therefore, the application can effectively reduce the power consumption introduced by the pulse width generation circuit while realizing the pulse width adaptive following of the voltage controlled oscillator frequency change, and can greatly reduce the area, can suppress noise folding without worsening reference spur, so it can be widely applied in low power consumption, small size anti-noise folding fractional phase-locked loop. The above shows and describes the basic principles and main features of the application and the advantages of the application. For those skilled in the art, it is obvious that the application is not limited to the details of the above exemplary embodiments, and the application can be realized in other specific forms without departing from the spirit or essential characteristics of the application. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting, and the scope of the application is defined by the appended claims rather than the above description, therefore all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the application. Any reference signs in the claims should not be considered as limiting the claims involved.

[0051] In addition, it should be understood that although the present application is described in the specification, each embodiment only contains one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be properly combined to form other embodiments which can be understood by those skilled in the art.

[0052] In addition, it should be understood that although the present application is described in the specification, each embodiment only contains one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can be properly combined to form other embodiments which can be understood by those skilled in the art.

Claims

1. An adaptive pulse width de-noise folding circuit, comprising an auxiliary controller, a pulse width generator, a pulse width current source, a loop filter, a voltage controlled oscillator, a multi-mode frequency divider, a sum-difference modulator, a frequency discriminator and a charge pump, the auxiliary controller is connected to the pulse width generator, the pulse width signal B generated by the pulse width generator is connected to and controls the pulse width current source, effectively avoiding the frequency discriminator / charge pump nonlinear region and not deteriorating the reference spur, the pulse width current source is connected to the charge pump and the loop filter at the same point, the loop filter is connected to the pulse width generator and the voltage controlled oscillator at the same point, the voltage controlled oscillator is connected to the multi-mode frequency divider, the multi-mode frequency divider is connected to the sum-difference modulator and the frequency discriminator at the same point, the frequency discriminator is connected to the charge pump, the pulse width generator is composed of a buffer U6, an inverter U7 and an AND gate U8, the input of the buffer U6 is connected to a reference source signal REF and a control signal Vc, the output of the buffer U6 is connected to the input of the inverter U7, the output of the inverter U7 is connected to one input of the AND gate U8, the reference source signal REF is connected to the other input of the AND gate U8, and the output of the AND gate U8 outputs the pulse width signal B, the auxiliary controller detects that the loop is locked, and the pulse width generator starts to work, the pulse width of the pulse width signal B output by the pulse width generator is adaptive to follow the output frequency of the voltage controlled oscillator.

2. A self-adapting pulse-width de-noising folding circuit according to claim 1, wherein, The voltage controlled oscillator is composed of inverters U1, U2, U3, U4 and U5, the output of the inverter U1 is connected to the input of the inverter U2, the output of the inverter U2 is connected to the input of the inverter U3, the output of the inverter U3 is connected to the input of the inverter U4, the output of the inverter U4 is connected to the input of the inverter U5, the output Vout of the inverter U5 is connected to the input of the inverter U1, and the inverters U1, U2, U3, U4 and U5 are all composed of M1 and M2, wherein the sizes of the individual transistors M1 and M2 are equal, and the number of M1 is 8 and the number of M2 is 24, that is, the total width of M2 is 3 times the total width of M1, and the total length is equal, the source end of the M2 transistor is connected to the control voltage Vc, and the output frequency size is changed by changing Vc.

3. A self-adapting pulse-width de-noising folding circuit according to claim 2, wherein, The delay time of the buffer is 2 times the period of the voltage controlled oscillator, the buffer U6 is composed of a 25-stage inverter cascade composed of inverters U9 to U28, the input end of the inverter U9 is connected to the reference source signal REF, and the control ends of the inverters U9 to U28 are connected to the control signal Vc, the delay time of the buffer is changed, and the inverter U28 is connected to the output signal A.

4. A self-adapting pulse-width de-noising folding circuit according to claim 3, wherein, The inverters U9 to U28 are consistent with the structure of the inverters U1 to U5, M1 and M2 adopt an equal ratio replication technology, the parallel quantity is reduced by 8 times in proportion, that is, the width is reduced by 8 times in proportion, the delay is unchanged, the power consumption is reduced by 8 times, the area is reduced by 8 times, and transistors M3 and M4 are obtained, and the inverters U9 to U28 are all composed of the transistors M3 and M4.

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