A phase-locked loop capable of fast locking

Abstract

The application discloses a phase-locked loop capable of realizing fast locking, comprising a waveform broadening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider; the application realizes greater gain by broadening the pulse width of UP or DN, and simultaneously, due to the proposed new locking mode, a new discrimination is added on the basis of the traditional size bandwidth: whether the phase error exceeds pi, the filter structure is different when the phase error exceeds pi, the loop stability does not need to be considered when the current is increased to realize greater bandwidth, so that greater current, higher upper limit and greater gain are realized on the basis of the original, simultaneously, due to the early entering of the phase tracking stage, the charging speed of the capacitor is accelerated, the establishment time is accelerated, in addition, the switching of the bandwidth and the switching of the resistance can realize the invariability of the damping coefficient, the loop stability is not affected, the robustness is better, and fast locking is realized under the condition of guaranteeing small bandwidth and good performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of phase-locked loop technology, and particularly relates to a phase-locked loop capable of realizing fast locking. BACKGROUND

[0002] Frequency synthesizers based on phase-locked loop (PLL) are important components in various applications, especially in communication systems, the frequency synthesizer needs to have good phase noise, jitter, spurious performance, at the same time, the locking time is also an important design requirement, the phase-locked loop capable of realizing fast locking is particularly important in the system needing to realize frequency hopping operation, the phase-locked loop is a second-order damping system, the stable time is determined by the time constant, which is inversely proportional to the loop bandwidth, when the loop bandwidth increases, the establishment time will decrease, but when the frequency is high and the frequency division is large, increasing the bandwidth will increase the in-band noise.

[0003] In the prior art, the locking process of the PLL is divided into two parts, one part is the frequency locking process, and the other part is the phase locking process, if the gain of the charge pump is increased in the frequency locking process, the gain of the charge pump is restored in the phase locking process, which can reduce the time of the frequency locking process without affecting the bandwidth, thereby reducing the locking time. Figure 1 As shown in the figure, the typical double-loop PFD / CP circuit structure mainly includes a coarse adjustment PFD / CP (frequency discriminator), a fine adjustment PFD / CP, a filter, a voltage-controlled oscillator (VCO) and a frequency divider, wherein the coarse adjustment PFD / CP is used in the frequency locking process, the phases of the reference signal and the frequency-divided signal are compared, and the phase difference is converted into current in proportion, the fine adjustment PFD / CP is used in the phase locking process, the phases of the reference signal and the frequency-divided signal are compared, and the phase difference is converted into current in proportion, the filter converts the current generated by the charge pump into the control voltage of the VCO, and filters the high-frequency components on the control voltage to reduce the ripple, the VCO generates a corresponding frequency signal according to the control voltage generated by the filter, and the frequency divider converts the high-frequency signal generated by the VCO into a low-frequency signal.

[0004] The main idea of ​​the typical dual-loop PFD / CP circuit structure described above is to use a coarse-tuned PFD / CP during frequency locking, increasing the gain of the charge pump to increase the bandwidth and accelerate the locking time. However, this PFD / CP has a large dead zone, and it will stop working when the phase error decreases to a certain value. At this time, the fine-tuned PFD / CP starts to work until the phase error decreases to zero. However, the circuit structure of this dual-loop PFD / CP is complex, with two PFD / CPs, requiring reasonable setting of the dead zone value, which is cumbersome to design. It also cannot guarantee the stability during the locking process and has poor robustness. It also needs to consider the changes in parameters such as phase margin and damping coefficient, resulting in a low upper limit, that is, the lock time that can be reduced is limited. Therefore, this invention proposes a phase-locked loop that can achieve fast locking to solve the problems existing in the prior art. Summary of the Invention

[0005] To address the aforementioned problems, the present invention aims to propose a phase-locked loop (PLL) capable of rapid locking, thereby solving the problems of complex structure, cumbersome design, poor robustness due to inability to guarantee stability during the locking process, and limited reduction in locking time in existing PLL technologies.

[0006] To achieve the objectives of this invention, the following technical solution is provided: a phase-locked loop (PLL) capable of fast locking, comprising a waveform broadening phase detector, a digital auxiliary phase detector, a charge pump, a filter, a VCO, and a frequency divider. The charge pump is a switchable charge pump, and the filter is a switchable filter. The waveform broadening phase detector and the digital auxiliary phase detector receive a reference signal and a frequency division signal from the frequency divider. The digital auxiliary phase detector generates a MODE signal to change the charge pump current and the filter to achieve bandwidth switching. The waveform broadening phase detector increases the charge pump gain by broadening the waveform of the UP signal or DN signal, and simultaneously generates an SW1 signal to send to the filter to achieve filter switching. The filter changes the locking process of the loop and causes the loop to enter the phase-locking process earlier, while ensuring that the damping coefficient remains unchanged when switching filters. The output of the filter is connected to the input of the VCO, and the output of the VCO is connected to the input of the frequency divider.

[0007] The further improvement lies in the fact that the waveform widening frequency and phase detector consists of four parts: a phase detection part, a leading and lagging part, a phase error determination part, and a waveform widening part.

[0008] A further improvement is that the phase detection section uses a three-state gate frequency phase detector to compare the rising edges of the VREF signal and the VDIV signal to generate corresponding QA and QB signals.

[0009] Further improvement lies in that the judgment of the leading and lagging part is used to judge whether VREF is leading or lagging, and QB is used to sample QA, if high, VREF signal is leading, if low, VDIV signal is leading, and the MODE signal is enabled, if high, it is opened, and if low, a low level is outputted.

[0010] Further improvement lies in that the judgment of whether the phase error exceeds pi part is used to judge whether VREF signal and VDIV signal exceed pi, and SW1 signal is outputted, QB is used to sample VREF signal, if high, it exceeds pi, otherwise, it does not exceed pi.

[0011] Further improvement lies in that the digital auxiliary phase discriminator is used to generate the MODE signal with switchable size bandwidth, specifically, a phase threshold tau is set, if the phase difference between VREF signal and VDIV signal exceeds tau, the MODE signal is high, otherwise, it is low.

[0012] Further improvement lies in that the charge pump adopts a source level switch operational amplifier charge pump, and current switching is realized through a proportional current mirror and a MODEB control signal, wherein the large current is 4 times of the small current, when the MODEB control signal is high, two current mirrors work simultaneously, and when the MODEB signal is low, only one current mirror works.

[0013] Further improvement lies in that the filter adopts a first-order / two-order filter, and MODEB is used as a control signal to switch the size of the filter resistance, when the loop bandwidth is switched from large to small, the damping coefficient remains unchanged, and SW1 signal is used to switch between the first-order filter and the two-order filter.

[0014] The phase-locked loop has the advantages that: the phase-locked loop structure is simple and clear, including a waveform expansion frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider, a larger gain is realized by expanding the pulse width of UP or DN, and a new locking mode is proposed, a new discrimination that whether the phase error exceeds pi is added on the basis of the traditional size bandwidth, the filter structures are different when the phase error exceeds pi or not, the loop stability is not considered when the current is increased to realize a larger bandwidth, so that a larger current and a higher upper limit are realized on the basis of the original, the gain is larger, the charging speed of the capacitor is accelerated and the establishment time is accelerated due to the early entering of the phase tracking stage, in addition, the resistance is switched at the same time of switching the bandwidth, the damping coefficient remains unchanged, the loop stability is not affected, the robustness is better, compared with the traditional circuit structure, the trade-off among the bandwidth, the phase noise and the locking time is broken, so that fast locking is realized under the condition of ensuring small bandwidth and good performance. BRIEF DESCRIPTION OF DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the accompanying drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the accompanying drawings in the following description only represent some of the embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative effort based on these accompanying drawings also belong to the protection scope of the present application.

[0016] Figure 1 is a circuit structure schematic diagram of a double-loop PFD / CP in the technical background of the present application;

[0017] Figure 2 is a phase-locked loop circuit structure schematic diagram in the embodiments of the present application;

[0018] Figure 3 is a waveform spreading frequency discriminator circuit principle schematic diagram in the embodiments of the present application;

[0019] Figure 4 is a waveform spreading frequency discriminator circuit output waveform schematic diagram in the embodiments of the present application;

[0020] Figure 5 is a digital auxiliary phase discriminator circuit principle schematic diagram in the embodiments of the present application;

[0021] Figure 6 is a digital auxiliary phase discriminator circuit output waveform schematic diagram in the embodiments of the present application;

[0022] Figure 7 is a switchable charge pump circuit structure schematic diagram in the embodiments of the present application;

[0023] Figure 8 is a switchable filter circuit structure schematic diagram in the embodiments of the present application;

[0024] Figure 9 is a lock-in time schematic diagram of a phase-locked loop capable of realizing fast locking in the embodiments of the present application;

[0025] Figure 10 is a lock-in time schematic diagram of a conventional phase-locked loop in the embodiments of the present application. DETAILED DESCRIPTION

[0026] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments only represent some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort also belong to the protection scope of the present application.

[0027] Referring toFigure 2 The embodiment provides a phase-locked loop capable of realizing fast locking, which comprises a waveform widening frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider, the charge pump is a switchable charge pump, the filter is a switchable filter, the waveform widening frequency discriminator and the digital auxiliary phase discriminator receive a reference signal and a frequency division signal from the frequency divider, the digital auxiliary phase discriminator generates a MODE signal to change the current size of the charge pump and the filter to realize bandwidth switching, the switching of the bandwidth and the switching of the resistance can realize that the damping coefficient remains unchanged, and the loop stability is not affected, the robustness is better, the waveform widening frequency discriminator increases the charge pump gain by widening the waveform of the UP signal or the DN signal, a greater gain is realized by widening the pulse width of the UP or the DN, a SW1 signal is generated and sent to the filter to realize filter switching, the filter changes the locking process of the loop and makes the loop enter the phase locking process in advance, and the damping coefficient is unchanged when the filter is switched, since the phase locking stage is entered in advance, the charging speed of the capacitor is accelerated, and the establishment time is accelerated, the output end of the filter is connected with the input end of the VCO, and the output end of the VCO is connected with the input end of the frequency divider, compared with a traditional circuit structure, the trade-off among the bandwidth, the phase noise and the locking time is broken, so that fast locking is realized under the condition of ensuring small bandwidth and good performance, the structure is simple and clear, the stability in the locking process can be ensured, and the robustness is higher.

[0028] Referring to Figure 3 The waveform widening frequency discriminator is composed of four parts, which are a phase discrimination part, a part for judging whether VREF is ahead or behind, a part for judging whether the phase error exceeds pi, and a waveform expansion part; the phase discrimination part uses a three-state gate frequency discriminator to compare the rising edges of the VREF signal and the VDIV signal to generate corresponding QA and QB signals; the part for judging whether VREF is ahead or behind is used for judging whether VREF is ahead or behind, and uses QB to sample QA, if it is high, VREF is ahead, and if it is low, VDIV is ahead, and is enabled according to the MODE signal, if the MODE signal is high, it is turned on, and if the MODE signal is low, a low level is output; the part for judging whether the phase error exceeds pi is used for judging whether the phase error between the VREF signal and the VDIV signal exceeds pi, and outputs a SW1 signal, and uses QB to sample the VREF signal, if the SW1 signal is high, the phase error exceeds pi, otherwise, the phase error does not exceed pi; the waveform expansion part, when SW1 is high and FORMER is high, VREF is ahead and the phase error exceeds pi, XOR operation is performed on VREF and VDIV, and then OR operation is performed on the QA signal, at this time, the QUP signal is always high, so that the purpose of waveform expansion is achieved, and the frequency locking process is accelerated, and when SW1 is low, it is indicated that the phase error does not exceed pi, the QUP signal is the QA signal, waveform expansion is not performed, and the phase locking process is not affected, and the waveform is as shown in Figure 4 .

[0029] In the traditional size bandwidth on the basis of the new judgment: phase error more than π, in the phase error more than π filter structure is different, in the increase of current to achieve greater bandwidth without considering the loop stability, so as to achieve greater current on the basis of the original, the upper limit is higher, the gain is greater.

[0030] As shown in Figure 5 , Figure 6 The digital auxiliary phase detector is used to generate the switch size bandwidth of the MODE signal, set a phase threshold τ, if the phase difference between VREF signal and VDIV signal exceeds τ, the MODE signal is high, otherwise is low, the specific implementation is: QUP and QDN do and operation, after the delay of τ, use RESET signal sampling output MODE signal.

[0031] As shown in Figure 7 The charge pump uses source level switch operational amplifier charge pump, current switching through a proportional current mirror and MODEB control signal, in which the large current is 4 times of the small current, when MODEB control signal is high, two current mirrors work at the same time, when MODEB signal is low, only one current mirror works.

[0032] The filter uses first order / second order filter, and uses MODEB as control signal to switch the size of filter resistance, when the loop bandwidth from large to small switching, the damping coefficient remains unchanged, at the same time, SW1 signal is used to switch between first order filter and second order filter, as shown in Figure 8 When SW is low, it means that the phase error between VREF and VDIV exceeds π, at this time, only the capacitor C1 exists, and it is charged quickly, Vcont increases rapidly, and the frequency rises rapidly. When SW is low, it means that the phase error between VREF and VDIV does not exceed π, at this time, the branch of R and C2 in series also begins to work, which pulls down the frequency to carry on the process of phase tracking. This process circulates several times until the voltage on C1 and C2 is equal.

[0033] This invention breaks away from the traditional PLL locking process and proposes a new locking method that further reduces the locking time based on bandwidth switching PLLs. Greater gain is achieved by widening the pulse width of UP or DN. Furthermore, due to the proposed new locking method, a new criterion is added to the original bandwidth: whether the phase error exceeds π. The filter structure differs depending on whether the phase error exceeds π. When increasing the current to achieve a larger bandwidth, loop stability does not need to be considered, thus achieving a larger current, a higher upper limit, and greater gain. Simultaneously, by entering the phase tracking stage earlier, the charging speed of capacitor C2 is accelerated, and the settling time is shortened. In addition, switching the resistor while switching the bandwidth can maintain a constant damping coefficient, without affecting loop stability, resulting in better robustness.

[0034] See Figure 9 , Figure 10 The simulation time of the phase-locked loop (PLL) that enables fast locking provided in this embodiment is compared with that of a traditional PLL. Figure 7 This embodiment provides the locking time for the phase-locked loop that enables fast locking. Figure 8 For the locking time of a traditional phase-locked loop, according to Figure 7 and Figure 8 The comparison shows that the phase-locked loop in this embodiment, which enables fast locking, reduces the locking time by two-thirds compared to the traditional PLL.

[0035] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A phase-locked loop capable of fast locking, characterized by: The application relates to a phase-locked loop (PLL) circuit, which comprises a waveform expansion frequency discriminator, a digital auxiliary phase discriminator, a charge pump, a filter, a VCO and a frequency divider, the charge pump is a switchable charge pump, the filter is a switchable filter, the waveform expansion frequency discriminator and the digital auxiliary phase discriminator receive a reference signal and a frequency-divided signal from the frequency divider, the digital auxiliary phase discriminator generates a MODE signal to change the current size of the charge pump and the filter to realize bandwidth switching, the waveform expansion frequency discriminator increases the charge pump gain by expanding the waveform of a UP signal or a DN signal, simultaneously generates a SW1 signal to send to the filter to realize filter switching, the filter changes the locking process of the loop and makes the loop enter the phase locking process in advance, while ensuring that the damping coefficient is unchanged when the filter is switched, the output end of the filter is connected with the input end of the VCO, the output end of the VCO is connected with the input end of the frequency divider, the waveform expansion frequency discriminator is composed of four parts, namely a phase discrimination part, a part for judging whether the phase error exceeds pi, a part for judging whether the phase error exceeds pi, and a waveform expansion part, the phase discrimination part uses a three-state gate frequency discriminator to compare the rising edges of a VREF signal and a VDIV signal and generates corresponding QA and QB signals, the part for judging whether the phase error exceeds pi is used for judging whether the VREF signal leads or lags, and uses QB to sample QA, if the VREF signal leads, the QB signal is high, if the VDIV signal leads, the QB signal is low, and the part for judging whether the phase error exceeds pi is used for judging whether the phase error between the VREF signal and the VDIV signal exceeds pi, simultaneously outputs a SW1 signal, and uses QB to sample the VREF signal, if the switch signal is high, the phase error exceeds pi, otherwise, the phase error does not exceed pi, the digital auxiliary phase discriminator is used for generating a MODE signal for switching the size of the bandwidth, and the MODE signal is high when the phase difference between the VREF signal and the VDIV signal exceeds a phase threshold tau, otherwise, the MODE signal is low.

2. The phase-locked loop capable of fast locking of claim 1, wherein: The charge pump adopts a source stage switch operational amplifier charge pump, and current switching is realized through a proportional current mirror and a MODEB control signal, wherein the large current is 4 times the small current, when the MODEB control signal is high, two current mirrors work simultaneously, and when the MODEB signal is low, only one current mirror works.

3. The phase-locked loop capable of fast locking of claim 1, wherein: The filter adopts a first-order / two-order filter, and adopts a MODEB as a control signal to switch the size of the filter resistance, when the loop bandwidth is switched from large to small, the damping coefficient remains unchanged, and a SW1 signal is used to switch between the first-order filter and the two-order filter.

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