Cache memory and method for distributing write operations

Abstract

The embodiments of the present application disclose a cache memory and a method for allocating write operations, which relate to the field of storage technology and can reduce the impact of cache performance degradation caused by the use of static strategies to control write allocation or non-allocation of writes to SW. The cache memory includes: a detector for detecting a target write operation stream from received write operations, the addresses of multiple write operations contained in the target write operation stream have regularity, and the target write operation stream refers to a write operation performed on a fully modified cache line; a register for storing information of at least one historical write operation stream, at least one historical write operation stream is used to indicate a write operation stream before the target write operation stream; an arbitrator for determining whether to allocate a cache line for the target write operation stream based on the information of the historical write operation stream. The embodiments of the present application are used to determine whether to allocate a cache line for a write operation stream.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a cache memory and a method for allocating write operations. Background Art

[0002] With the rapid development of processor design and process nodes, in order to reduce unnecessary main memory access by the processor, the cache needs to store recently used instructions or data, so that the vast majority of processor accesses are completed in the cache. When the data to be written by the processor to the cache in a write operation is not stored in the cache, it is considered a cache miss. In this case, there are two allocation strategies for write operations: write allocate and write no allocate. Write allocate writes the data to be written to the cache when a cache miss occurs; write no allocate writes the data to be written to the cache directly when a cache miss occurs, instead of writing the data to be written to the cache.

[0003] If the addresses of multiple write operations have regularity during the execution of a program by the processor, for example, the addresses of multiple write operations increase or decrease, then for the write operation stream (streaming write, SW) composed of these multiple write operations, whether to allocate a cache line for the SW to write the data of the SW into the cache, the current solutions are: Figure 1 The figure shows a structural diagram of a cache memory. When the SW detector detects that the addresses of multiple write operations have regularity, it predicts that the addresses of multiple subsequent write operations also have regularity. These multiple subsequent write operations are SWs. The SW detector then adds tags to these multiple subsequent write operations. When the register configuration switch detects a tagged SW, it determines whether to allocate a cache line to the SW based on a preset policy. This preset policy can be, for example, manually setting the register configuration switch on or off by the programmer. When the register configuration switch is on, a cache line can be allocated to the tagged SW. When the register configuration switch is off, no cache line is allocated to the tagged SW.

[0004] In other words, the current solution is to use a register to configure the switch preset strategy to control whether to allocate cache lines for multiple subsequent write operations according to the same preset strategy. However, there is only one such strategy, which is fixed and unchanging. Moreover, the data written to the cache by the SW is unpredictable due to its reusability and data volume. If the SW data is written to the cache, if the cache needs to release cache space, the frequently used data may be removed from the cache, resulting in a decrease in cache performance. Moreover, when the SW data is written to the cache using write allocation but is no longer used, it is easy to cause cache pollution, resulting in a decrease in cache performance. If the data written to the SW is not written to the cache using write non-allocation, if the SW data needs to be reused, it will cause cache misses, which will also cause a decrease in cache performance. Summary of the Invention

[0005] The embodiments of the present application provide a cache memory that can reduce the impact of cache performance degradation caused by adopting a static policy to control write allocation or write non-allocation for SW.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, a cache memory is provided, comprising: a detector for detecting a target write operation stream from received write operations, wherein the addresses of multiple consecutive write operations contained in the target write operation stream have regularity; a register for storing information of at least one historical write operation stream, wherein the at least one historical write operation stream is used to indicate a write operation stream before the target write operation stream; and an arbitrator for determining whether to allocate a cache line to the target write operation stream based on the information of the historical write operation stream.

[0008] This application records the information of the historical write operation stream in the register. When the target write operation stream is received, whether to perform write allocation on the target write operation stream can be determined based on the information of the historical write operation stream. Since the information of the historical write operation stream is constantly changing with the program or use case, different target write operation streams arrive at different time points, and their historical write operation stream information may also be different. Therefore, this method of determining whether to allocate cache for the target write operation stream based on the information of the historical write operation stream can determine whether to allocate cache lines for the target write operation stream based on the dynamically changing information of the historical write operation stream, or can determine whether to allocate cache lines for the target write operation stream based on the dynamically changing program characteristics, which can improve cache performance.

[0009] In one possible design, the detector is specifically configured to: when regularity is detected in the addresses of d consecutive write operations received, use a write operation stream consisting of m write operations starting from the d+1th write operation as a target write operation stream, where d and m are both positive integers greater than 1. In other words, when regularity is detected in the addresses of d consecutive write operations received, it is predicted that the addresses of a subsequent write operation stream consisting of m write operations received starting from the d+1th write operation also have regularity. Therefore, the write operation stream consisting of m write operations starting from the d+1th write operation can be used as the target write operation stream to determine whether to allocate a cache line to the target write operation stream.

[0010] In one possible design, information about at least one historical write operation stream includes an average length of the at least one historical write operation stream and reuse information of the at least one historical write operation stream; an arbiter is configured to determine whether to allocate a cache line to a target write operation stream based on the average length of the at least one historical write operation stream and the reuse information of the at least one historical write operation stream. The average length can be used to determine the length of the write operation stream during the most recent program execution, and further, the length of the write operation stream recently written to the cache can be determined based on the average length, thereby predicting the remaining cache space. Therefore, the average length of the at least one historical write operation stream can be used as an indicator for determining whether to allocate a cache line to the target write operation stream; the reuse information can be used to determine the reuse of cache lines allocated to the historical write operation stream during the most recent program execution, thereby determining the reuse of cache lines if allocated to the target write operation stream. Therefore, the reuse information of the at least one historical write operation stream can be used as an indicator for determining whether to allocate a cache line to the target write operation stream. The average length of the at least one historical write operation stream is the average value of the lengths of the at least one historical write operation stream; and the reuse information of the at least one historical write operation stream is the proportion of cache lines that are reused among the cache lines allocated to the at least one historical write operation stream.

[0011] In one possible design, the arbitrator includes a random probability generator and a calculator; the random probability generator is used to randomly generate a probability value; the calculator is used to determine whether to allocate a cache line to a target write operation stream based on an average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and the probability value.

[0012] In one possible design, the calculator is specifically used to: if the average length of at least one historical write operation stream is less than a length threshold, and the probability value is less than the reuse information of the historical write operation stream, determine to allocate a cache line for the target write operation stream. In the present application, although the probability value is randomly extracted, that is, when the target write operation stream arrives, whether the target write operation stream is write-allocated is randomly determined, but the reuse information controls the probability of the target write operation stream being allocated. When the reuse information is high, the probability that the randomly extracted probability value is less than the reuse information increases. In other words, when the average length of the historical write operation stream is low, the remaining space in the cache may be large; and when the reuse information is high, the higher the probability of allocating cache to the target write operation stream, if the target write operation stream is written to the cache, the higher the proportion of the target write operation stream being reused.

[0013] In one possible design, the calculator is specifically configured to: if the average length of at least one historical write operation stream is less than a length threshold and the probability value is greater than or equal to the reuse information of the historical write operation stream, determine not to allocate a cache line to the target write operation stream. Specifically, when the average length of the historical write operation stream is low, while the remaining space in the cache may be large, the probability value is greater than or equal to the reuse information of the historical write operation stream. Therefore, it is determined that the reuse rate of the historical write operation stream when allocated to the cache is low, and therefore, it can be determined not to allocate a cache line to the target write operation stream.

[0014] In one possible design, the calculator is specifically configured to: if the average length of at least one historical write operation stream is greater than a length threshold, determine not to allocate a cache line for the target write operation stream. Specifically, when the average length of at least one historical write operation stream is greater than the length threshold, it is considered that the average length of the historical write operation stream is relatively high. When the write operation stream is allocated to the cache, the remaining space in the cache may be small, and the length of the target write operation stream may also be relatively large. Therefore, it is determined that no cache line is allocated for the target write operation stream.

[0015] In one possible design, the cache memory further includes a clearer. The clearer is configured to instruct the register to clear at least one historical write operation flow when the detector fails to detect a write operation flow for a period exceeding a threshold. This is because a significant period of time without receiving a write operation flow may indicate a program change, necessitating the re-recording of historical write operation flow information for the next program.

[0016] In a possible design, the regularity of the addresses of the multiple write operations included in the target write operation stream means that the addresses of the multiple write operations increase or decrease.

[0017] In a second aspect, a method for allocating write operations is provided, comprising: detecting a target write operation stream from received write operations, wherein the addresses of multiple consecutive write operations contained in the target write operation stream exhibit regularity; and determining whether to allocate a cache line for the target write operation stream based on information from at least one historical write operation stream, wherein the at least one historical write operation stream indicates a write operation stream preceding the target write operation stream. The beneficial effects achieved by this write allocation processing method can be seen in the beneficial effects described above for the cache memory.

[0018] In one possible design, detecting a target write operation stream from received write operations includes: when it is detected that the addresses of d consecutive write operations in the received write operations are regular, using a write operation stream consisting of m write operations starting from the d+1th write operation as the target write operation stream, where d and m are both positive integers greater than 1.

[0019] In one possible design, the information of at least one historical write operation stream includes an average length of the at least one historical write operation stream and reuse information of the at least one historical write operation stream; and determining whether to allocate a cache line to a target write operation stream based on the information of the at least one historical write operation stream includes: determining whether to allocate a cache line to the target write operation stream based on the average length of the at least one historical write operation stream and the reuse information of the at least one historical write operation stream. The average length of the at least one historical write operation stream is an average value of the lengths of the at least one historical write operation stream; and the reuse information of the at least one historical write operation stream is a proportion of cache lines that are reused among the cache lines allocated to the at least one historical write operation stream.

[0020] In one possible design, determining whether to allocate a cache line to a target write operation stream based on an average length of at least one historical write operation stream and reuse information of at least one historical write operation stream includes: randomly generating a probability value; and determining whether to allocate a cache line to a target write operation stream based on an average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and the probability value.

[0021] In one possible design, determining whether to allocate a cache line to a target write operation stream based on an average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and a probability value includes: if the average length of at least one historical write operation stream is less than a length threshold, and the probability value is less than the reuse information of the historical write operation stream, determining to allocate a cache line to the target write operation stream.

[0022] In one possible design, determining whether to allocate a cache line to a target write operation stream based on an average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and a probability value includes: if the average length of at least one historical write operation stream is less than a length threshold, and the probability value is greater than or equal to the reuse information of the historical write operation stream, determining not to allocate a cache line to the target write operation stream.

[0023] In one possible design, determining whether to allocate a cache line for a target write operation stream based on an average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and a probability value includes: if the average length of at least one historical write operation stream is greater than a length threshold, determining not to allocate a cache line for the target write operation stream.

[0024] In one possible design, the method further includes: when the time during which no write operation flow is detected exceeds a time threshold, clearing information of at least one historical write operation flow.

[0025] In a possible design, the regularity of the addresses of the multiple write operations included in the target write operation stream means that the addresses of the multiple write operations increase or decrease.

[0026] In a third aspect, a processing device is provided, which includes the cache memory and a processor in the above-mentioned first aspect or any possible design of the first aspect.

[0027] In a fourth aspect, a chip is provided, which includes the cache memory of the first aspect or any possible design of the first aspect, or the chip includes the processing device provided by the third aspect.

[0028] In a fifth aspect, a device is provided, which includes the cache memory in the first aspect or any possible design of the first aspect, or the device includes the processing device provided by the third aspect, or the device includes the chip provided by the fourth aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the structure of a cache memory;

[0030] Figure 2 A schematic diagram of the structure of a processing device provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the structure of a cache memory provided in an embodiment of the present application;

[0032] Figure 4 A schematic diagram of the structure of a cache memory provided in an embodiment of the present application;

[0033] Figure 5 A schematic diagram of the structure of an arbitrator provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the structure of a cache memory provided in an embodiment of the present application;

[0035] Figure 7 A schematic structural diagram of a remover provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of the structure of a training device provided in an embodiment of the present application;

[0037] Figure 9 A flowchart of a method for allocating write operations provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] For ease of understanding, some examples of concepts related to the embodiments of this application are provided for reference as follows:

[0039] Cache: Cache design primarily leverages the principle of locality, meaning that programs don't access all code and data uniformly, but instead frequently reuse recently used data and instructions. Caching involves placing recently used instructions or data into the cache and removing infrequently used instructions or data from the cache, allowing the processor to complete most accesses within the cache. Cache is typically categorized as Level 1 (L1 cache), Level 2 (L2 cache), and Level 3 (L3 cache). The L3 cache is often referred to as the Last Level Cache (LLC).

[0040] Cache line: There are two concepts about cache line: data granularity and physical granularity. 1. Data granularity: cache line is the smallest unit for exchanging data between cache and memory, and can also be understood as the smallest cache unit in the cache. A cache line generally consists of three parts: a valid bit, a tag, and data. The valid bit is used to mark whether the data in the cache line is valid, and the tag is used to indicate the address of the memory corresponding to the cache line. 2. Physical granularity: refers to the smallest storage unit in the physical cache, which corresponds to the cache line of the above data granularity.

[0041] Fully modified cache line: A data granularity concept. For a cache line, if all data in the cache line will be modified (usually by the processor), then the cache line is called a fully modified cache line; otherwise, it is called a non-fully modified cache line. For example, for a 64-byte cache line, if all data in the 64-byte cache line will be modified, then the 64-byte cache line is a fully modified cache line. For fully modified cache lines, if a write-allocate strategy is adopted, the write data can be written to the cache without accessing main memory, saving main memory bandwidth.

[0042] Streaming write / store: This can also be called a sequential write operation stream. A write operation stream consists of multiple consecutive write operations. Each write operation indicates that all data in the cache line is modified, that is, the entire cache line is modified. If not all data in the cache line is modified, such as modifying part of the data in the cache line, it cannot be called a write operation.

[0043] The technical solutions in the embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships can exist, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0044] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this embodiment, unless otherwise specified, "plurality" means two or more.

[0045] In the embodiments of this application, the word "exemplary" is used to mean an example, illustration, or description. Any embodiment or design described in this application as "exemplary" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of the word "exemplary" is intended to present concepts in a concrete way.

[0046] In the embodiments of the present application, “of”, “corresponding”, “relevant” and “corresponding” may sometimes be used interchangeably. It should be noted that when the distinction between them is not emphasized, the meanings they intend to express are consistent.

[0047] An embodiment of the present application proposes a cache memory that can be applied to an application scenario in which adaptive write allocation processing is performed on a write operation stream, that is, a dynamic allocation strategy is adopted to improve cache performance.

[0048] like Figure 2As shown, an embodiment of the present application provides a processing device 20, the hardware structure of which may include multiple processors 21, dedicated caches 22 corresponding to the multiple processors 21, LLC 23 shared by the multiple processors 21, and a main memory 24. The processor 21 is used to run instructions in the main memory 24 and process data in the software. The dedicated cache 22 can be accessed by the corresponding processor, and the dedicated cache includes L1 cache and L2 cache, etc.; the LLC 23 can be accessed by multiple processors 21. The main memory 24 is one of the important components in computer-type devices. It is a bridge for communication with the processor 21. The execution of all programs in the processing device 20 is carried out in the main memory 24, which is used to temporarily store the calculation data in the processor 21 and the data exchanged with external memories such as hard disks.

[0049] The embodiment of the present application provides a cache memory, which updates the hardware structure in the cache in the processing device 20, for example, updates the hardware structure in the LLC, so that the cache memory can achieve: when a target write operation flow is detected, it can determine whether to allocate a cache line for the target write operation flow based on the information of the historical write operation flow. Since the information of the historical write operation flow changes with the change of the historical write operation flow, and the historical write operation flow changes with the change of the program, each time the target write operation flow arrives, it can be dynamically determined whether to allocate a cache line for the target write operation flow based on the information of the current historical write operation flow, so that whether to allocate a cache line for the target write operation flow changes with the information of the historical write operation flow, so that whether to write allocation conforms to the current program changes, improves cache performance, and reduces cache pollution.

[0050] The following describes the hardware modules involved in the embodiments of the present application, taking the cache memory included in the LLC 23 as an example. Although the embodiments of the present application are described using the cache memory included in the LLC 23 as an example, it is understandable that the cache memory may also be included in the L1 cache or the L2 cache, and this application does not limit this.

[0051] like Figure 3 As shown, the hardware modules included in the LLC 23 may include a detector 231 , a register 232 , and an arbitrator 233 . One end of the detector 231 is connected to one end of the register 232 , and the other end of the register 232 is connected to the arbitrator 233 .

[0052] a detector 231 configured to detect a target write operation stream from the write operations received from the processor 21, wherein the addresses of the multiple write operations included in the target write operation stream have regularity, and the target write operation stream refers to write operations performed on a fully modified cache line;

[0053] The regularity of the addresses of the multiple write operations may also be understood as the addresses of the multiple write operations satisfying a preset regularity.

[0054] Register 232, used to store information of at least one historical write operation stream, where the at least one historical write operation stream is used to indicate a write operation stream preceding the target write operation stream; the information of the historical write operation stream is used to indicate characteristic information when the processor performs read and write access to the historical write operation stream;

[0055] The arbiter 233 is configured to determine whether to allocate a cache line for the target write operation flow based on the information of the historical write operation flow, wherein the allocated cache line here refers to a physical cache line in the cache, that is, a storage unit in the cache.

[0056] The cache memory may also include a read / write controller for storage. When the arbiter 233 determines that a cache line is allocated for the target write operation stream, the arbiter 233 may send this result to the read / write controller, which then allocates a cache line based on the cache space. When the arbiter 233 determines that a cache line is not allocated for the target write operation stream, the data of the target write operation stream is directly sent to the main memory 24. When the main memory 24 receives the data sent by the cache memory, it writes the data to the main memory 24.

[0057] Therefore, the cache memory provided by this application records historical write operation stream information in registers, and this historical write operation stream information can change based on the historically executed programs. Because different target write operation streams arrive at different times, their historical write operation stream information may also vary. Therefore, the arbitrator can determine whether to allocate a cache line for the target write operation stream based on the current historical write operation stream information. This allows the determination of whether to allocate a cache line for the target write operation stream based on the dynamically changing historical write operation stream information, or in other words, the determination of whether to allocate a cache line for the target write operation stream based on the dynamically changing program characteristics, thereby improving cache performance.

[0058] The above hardware modules are further introduced below.

[0059] Detector 231: In some embodiments, the detector 231 can be used to: when it is detected that the addresses of d consecutive write operations in the received write operations are regular, a write operation stream consisting of m write operations starting from the d+1th write operation is used as the target write operation stream, where d and m are both positive integers greater than 1.

[0060] In some embodiments, if the detector 231 determines that the addresses of d consecutive write operations among the received write operations have regularity, tags are added to the subsequently received m write operations.

[0061] Specifically, if the detector 231 detects write operations with a certain address pattern based on the addresses corresponding to multiple write operations received by LLC 23, for example, when the address pattern presents an arithmetic progression (for example, the address of the write operation may be increasing or decreasing), the detector 231 predicts that there may be more write operations with a certain address pattern to be issued, and the detector 231 can add an SW label to the subsequent write operations received. In an embodiment of the present application, the write operation stream composed of the write operations with SW labels received subsequently is used as the target write operation stream. For example, when the detector 231 detects that the addresses of d consecutive write operations (S0, S1, ..., Sd-1) present a certain address pattern, the detector 231 can add an SW label to m write operations starting from Sd (including Sd), that is, add an SW label to Sd, Sd+1, ..., Sn, and nd=m, Sd, Sd+1, ..., Sn is the target write operation stream.

[0062] In some embodiments, the detector 231 may also be configured to send a first indication to the register 232 , where the first indication is configured to indicate that the detector 231 has detected a target write operation flow.

[0063] Register 232: Figure 4 As shown, the register 232 may maintain a SW table (SW table), in which at least one historical write operation flow information received before the target write operation flow is recorded.

[0064] In some embodiments, the information of at least one historical write operation stream includes the average length avg_L of at least one historical write operation stream and the reuse information P of at least one historical write operation stream; the register 232 can read the average length of at least one historical write operation stream and the reuse information of at least one historical write operation stream in the information of the historical write operation stream according to the received first indication, and output them to the arbitrator 233. The arbitrator 233 can be used to determine whether to allocate a cache line to the target write operation stream based on the average length of at least one historical write operation stream and the reuse information of at least one historical write operation stream.

[0065] In some embodiments, the average length of at least one historical write operation stream is the average of the lengths of at least one historical write operation stream; that is, the average length of at least one historical write operation stream can be understood as the ratio of the number of write operations with SW tags detected before the detector 231 detects the target write operation stream to the number of detected write operation streams;

[0066] The reuse information of the at least one historical write operation stream is a ratio of cache lines that are reused among cache lines allocated to the at least one historical write operation stream.

[0067] In some embodiments, when determining whether to allocate a cache line for a target write operation flow, arbiter 233 may determine whether to allocate a cache line for the target write operation flow based on whether avg_L and P in the SWtable meet conditions. The determination of whether to allocate a cache line for a target write operation flow will be discussed later in the description of arbiter 233. The following first describes the various entries in the SW table.

[0068] In addition to avg_L and P, the SW table may also include some entries used to assist the register 232 in calculating avg_L and P, as well as some other entries.

[0069] In one embodiment, the entries of the SW table may be as shown in Table 1:

[0070] Table 1

[0071]

[0072] 1) An indication (index) indicating the addressing of the SW sequence. The value of each index and the value of the corresponding table item is a table entry. In some embodiments, the composition of the index may include: an indication representing the central processing unit CPU (processor) that sends the SW, or an indication representing the source of the SW, recorded as scr[rs]; an indication representing the address range of the received SW, recorded as addr[ra]; an indication representing the value of the received SW, or representing the ZV attribute (zero value) of the value of the received SW, that is, whether the value of the write operation is 0. According to this composition, the index can be represented in binary, for example, the index occupies 13 bits, of which 2 bits represent scr[rs], 10 bits represent addr[ra], and 1 bit represents the ZV attribute. There can be multiple different indexes in the SWtable. Different indexes correspond to different program types. When a new target write operation stream arrives, the information in the table entry corresponding to the target write operation stream can be obtained based on the index query.

[0073] 2) Indication of whether the target write operation flow is being sent (SW). In other words, the SW table entry in the SW table indicates whether there is a target write operation flow that matches an index value in the index table entry and is tagged with SW and is being sent. When the detector 231 detects that the target write operation flow is being sent, if the target write operation flow matches an index value in the index table entry, it will trigger the value of SW corresponding to the index value in the SW table to show a rising edge. For example, the value of SW is set from 0 to 1, and when the reception of the target write operation flow is completed, the value of SW is a falling edge. For example, the value of SW is set from 1 to 0, and when the target write operation flow is in the process of being received, the value of SW can always be 1.

[0074] 3) The number of write operation flows received since the last clearing of historical write operation flow information (num). That is, num represents the number of write operation flows received since the last clearing of the values ​​of certain table entries in the SW table, including the number of write operation flows with regular addresses and the number of write operation flows with irregular addresses.

[0075] 4) The number of cache lines reused (reuse_p) among all allocated cache lines since the last time the historical write operation flow information was cleared. This means how many cache lines have been reused among the allocated cache lines. This reuse can be a write operation or a read operation on the cache line.

[0076] 5) The total number of cache lines allocated by all write-allocated write operation flows since the last time the historical write operation flow information was cleared (alloc_p), that is, the total number of cache lines written to the cache by all write-allocated write operation flows since the last time the historical write operation flow information was cleared.

[0077] 6) The number of SW-tagged write operations received since the last time the historical write operation stream was cleared (total_L). This statistic is independent of whether the SW-tagged write operations are allocated to the cache. Thus, avg_L = total_L / num.

[0078] 7) An indication of the number of cache lines allocated for the currently received target write operation stream (anum_L). This indication may be cleared when a new target write operation stream arrives, and may be incremented by one each time a cache line is allocated for the currently received target write operation stream.

[0079] 8) The maximum number of cache lines that can be allocated to the target write operation flow (amax_L), that is, the maximum number of cache lines that can be allocated to the cache for the target write operation flow.

[0080] 9) The first time interval (T) since the last receipt of the target write operation stream. T can also represent a fixed time interval count, that is, a target write operation stream is received every fixed time interval.

[0081] 10) The second time interval (th_T) for clearing at least one item in the information of the historical write operation stream.

[0082] 11) The length threshold th_L for determining whether to allocate a cache line for the target write operation stream. The length threshold th_L can include a first length threshold th1_L and a second length threshold th2_L, where th1_L < th2_L. th_L can be understood as the low length threshold for whether to allocate a cache line for the target write operation stream, and th2_L can be understood as the high length threshold for whether to allocate a cache line for the target write operation stream.

[0083] It should be noted that the above table entries can each have a separate value in each table entry, that is, for each index, there is a separate combination of table entries, or domain segment combinations. For example, the first time intervals corresponding to each index are different; or, the above table entries can also share a single value among all table entries, that is, corresponding to all indexes, they share the same domain segment value. In this case, the table entries do not distinguish the attributes in the index. For example, the values of th1_L or amax_L corresponding to each index are the same.

[0084] As the target write operation stream is received, the SW table also needs to be updated accordingly. This update action can occur when the detector 231 recognizes the target write operation stream, when the detector 231 recognizes the completion of the receipt of the target write operation stream, when the LLC finishes allocating a cache line for the target write operation stream, and during the process of the LLC allocating a cache line for the target write operation stream.

[0085] Exemplarily, when the detector 231 identifies a target write operation flow, the detector 231 may send a first indication that a target write operation flow with a regular address is being sent to the register 232, and notify the register 232 of the src[rs] representing the source of the target write operation flow, the addr[ra] representing the address range to be accessed, and the ZV attribute of the data to be written by the target write operation flow. When the register 232 determines that the src[rs] representing the source of the target write operation flow, the addr[ra] representing the address range to be accessed, and the ZV attribute of the value of the target write operation flow match the src[rs], addr[ra], and ZV attribute indicated by a first index, the register 41 updates the historical information in the table entry corresponding to the index. The updated table entry includes: updating the value of the table entry SW to the indication that the SW with a regular address is being sent, for example, setting the value of the table entry SW in the above-mentioned SW table from 0 to 1. For example, when detector 231 assigns an SW tag to the first write operation in the target write operation stream, register 232 receives the first indication from detector 231 and sets the value of table entry SW to 1. Furthermore, the value of num also needs to be incremented by 1. Each time detector 231 assigns an SW tag to a write operation in the target write operation stream, register 41 increments the value of total_L in the SW table by 1. Furthermore, register 41 can also read the values ​​of avg_L, th1_L, th1_L, amax_L, and P from the table entry corresponding to the first index and send them to arbiter 233. As can be appreciated, the value of T also changes accordingly.

[0086] When the detector 231 identifies that the write operation with the SW tag is received after the target write operation stream is received, the value of avg_L in the SW table also changes accordingly with the value of num and the value of total_L when the target write operation stream is received after the target write operation stream is received.

[0087] During the process of allocating cache lines for a target write operation stream, each time the LLC allocates a cache line to the target write operation stream, the SW table may update anum_L, an indicator of the number of cache lines allocated to the target write operation stream, thereby updating the value of anum_L in the SW table in real time. For example, upon receiving write operations from the target write operation stream, the initial value of anum_L is 0. When the LLC allocates the first cache line to the target write operation stream, the value of anum_L is 1. Thereafter, the value of anum_L increases by 1 each time a cache line is allocated to the target write operation stream.

[0088] When allocating cache lines for the target write stream is complete, the value of anum_L corresponding to the target write stream can be added to the current alloc_p, thus updating the value of alloc_p. After the data cache of the target write stream is completed, the reuse information P in the SW table needs to be updated in real time as the data written to the LLC by the target write stream is reused (including write operations or read operations).

[0089] Arbitrator 233: Figure 4 As shown, the arbitrator 233 may include a calculator 2331 and a random probability generator 2332;

[0090] A random probability generator 2332 is used to randomly generate a probability value P';

[0091] In some embodiments, the random probability generator may be used to determine the size of the randomly generated probability value and the reuse information P, and generate a second indication, the second indication being used to indicate whether the probability value is less than the reuse information P;

[0092] The calculator 2331 is configured to determine whether to allocate a cache line to the target write operation flow according to an average length avg_L of at least one historical write operation flow, reuse information P of at least one historical write operation flow, and a probability value P′.

[0093] In some embodiments, the calculator 2331 may generate a third indication based on an average length avg_L of at least one historical write operation stream and the second indication, where the third indication is used to indicate whether to allocate a cache line for the target write operation stream.

[0094] In some embodiments, the principle for the calculator 2331 to determine whether to allocate a cache line for the target write operation stream may be:

[0095] If the average length avg_L of at least one historical write operation flow is less than the length threshold th_T, and the probability value P' is less than the reuse information P of the historical write operation flow, then it is determined to allocate a cache line to the target write operation flow. That is, the second indication is used to indicate that the probability value is less than the reuse information P, and the third indication is used to indicate that a cache line is allocated to the target write operation flow;

[0096] If the average length avg_L of at least one historical write operation flow is less than the length threshold th_T, and the probability value P' is greater than or equal to the reuse information P of the historical write operation flow, it is determined not to allocate a cache line for the target write operation flow. That is, the second indication is used to indicate that the probability value P' is greater than or equal to the reuse information P, and the third indication is used to indicate that a cache line is not allocated for the target write operation flow;

[0097] If the average length avg_L of at least one historical write operation stream is greater than the length threshold th_T, it is determined not to allocate a cache line for the target write operation stream. That is, the third indication is used to indicate not allocating a cache line for the target write operation stream. Thus, as the program changes, the values of the entries in the SW table will also change accordingly, and the average length avg_L and the length threshold th_T will also change accordingly. Moreover, the probability value P' and the reuse information P will control the probability of allocating the target write operation stream, enabling whether the target write operation stream is write-allocated to change with the change of the program, which can solve the problem that a fixed write-allocation mechanism cannot adapt to the change of program behavior.

[0098] Specifically, in some embodiments, when a write operation stream is referred to as a sequence, the length of the sequence is divided into three length intervals: a short sequence interval, a long sequence interval, and a medium-length interval between the short sequence interval and the long sequence interval. The sizes of the intervals are: short sequence interval < medium-length interval < long sequence interval. As mentioned above, the length threshold th_L may include a first length threshold th1_L and a second length threshold th2_L, where th1_L < th2_L. Therefore, there are the following multiple cases for write-allocation:

[0099] If avg_L < th1_L, it can be considered that the length of the write operation stream from the last clearing of the information of the historical write operation stream to the write operation stream before receiving the target write operation stream is relatively small, or in other words, they all belong to the short sequence interval, and there may still be relatively more cache space remaining in the cache. However, the target write operation stream may also belong to the long sequence interval, and it is also possible that the remaining cache space in the cache is not enough to allocate a cache line for the target write operation stream. Therefore, in some embodiments, if avg_L < th1_L, it is possible to determine whether to allocate a cache line for the target write operation stream with a certain probability, that is, with P' and P; specifically, when the probability value P' randomly drawn by the random probability generator 2332 is less than P, it is determined to allocate a cache line for the target write operation stream, and when the P' is greater than or equal to P, it is determined not to allocate a cache line for the target write operation stream;

[0100] If th1_L ≤ avg_L < th2_L, it can be considered that the length of the write operation stream from the last clearing of the information of the historical write operation stream to the write operation stream before receiving the target write operation stream is all in the medium-length interval. Then, the target write operation stream is also very likely to belong to the medium-length interval or may also belong to the long sequence interval. At this time, the remaining cache space in the cache may also be not enough to allocate a cache line for the target write operation stream. In some embodiments, it is still possible to determine whether to allocate a cache line for the target write operation stream with P' and P. The implementation of whether to allocate can refer to the description in the above case of avg_L < th1_L;

[0101] If avg_L≥th2_L, it can be considered that the length of the write operation stream from the last time the historical information was cleared to before the target write operation stream was received is in the long sequence interval, then the probability of the target write operation stream being a long sequence is relatively high, so the remaining cache space in the cache may not be enough to allocate a cache line for the target write operation stream. At this time, the arbitrator 233 determines not to allocate a cache line for the target write operation stream.

[0102] In the embodiment of the present application, although the probability value is randomly extracted, that is, when the target write operation stream arrives, whether the target write operation stream is written and allocated is randomly determined, the reuse information controls the probability of the target write operation stream being allocated. When the reuse information in the historical information is low, it means that the previously received write operation stream has basically not been reused. Therefore, it is inferred that the target write operation stream at this time will most likely not be accessed again, that is, it tends not to be allocated to the cache. The present application is implemented by comparing the randomly extracted probability value and the reuse information. The smaller the reuse information, the greater the probability that the randomly extracted probability value is greater than or equal to the reuse information, and the lower the probability that the target write operation stream is allocated into the cache. Similarly, when the reuse information is high, the greater the probability that the randomly extracted probability value is less than the reuse information, the higher the probability that the target write operation stream is allocated into the cache. In other words, the reuse characteristics of a specific program (identified by index) are basically consistent within a certain period of time (due to the regular clearing of historical information) (locality principle). The present application can infer future reuse based on the historical reuse of this program. When the target write operation flow meets a certain index with high historical reuse, the target write operation flow will be allocated to the cache with a high probability, and the target write operation flow will also be used again with a high probability. Therefore, the embodiment of the present application can improve the cache hit rate for programs with high reuse information.

[0103] Based on the above principles, in some embodiments, the hardware circuit structure inside the arbiter 233 in the embodiment of the present application can be as follows: Figure 5 As shown. That is, the calculator 2331 in the arbiter 233 may include multiple numerical comparators and multiple logic gate devices. Figure 5 The calculator 2331 may include a numerical comparator A, a numerical comparator B, a numerical comparator C, a two-input AND gate D, a two-input AND gate E, a three-input AND gate F, a two-input OR gate G and a NOT gate H; the random probability generator 2332 in the arbitrator 233 may include a random probability generator I and a numerical comparator J.

[0104] For example, the arbiter 233 determines that the instruction to output the allocated cache line is a binary number "1".

[0105] When avg_L < th1_L, the numerical comparator A outputs "1"; when the probability value P' generated by the random probability generator I < the reuse information P, the numerical comparator J outputs "1"; at this time, the two-input AND gate D outputs binary "1"; the two-input OR gate G outputs "1", that is, the arbiter 233 outputs an indication to allocate a cache line.

[0106] When avg_L ≥ th1_L, the numerical comparator A outputs "0", and the NOT gate H outputs "1"; when avg_L < th2_L (th1_L ≤ avg_L < th2_L), the numerical comparator B also outputs "1", then the two-input AND gate E outputs "1"; if the probability value P' generated by the random probability generator I < the reuse information P, the numerical comparator J outputs "1"; if the number of cache lines anum_L allocated for the target write operation stream < the maximum number of cache lines amax_L, the numerical comparator C outputs "1", then the three-input AND gate F outputs "1", and the two-input OR gate G outputs "1", that is, the arbiter 233 outputs an indication to allocate a cache line.

[0107] It can be understood that if avg_L < th1_L does not hold and avg_L < th2_L does not hold either, the two-input AND gate D outputs "0", the three-input AND gate F also outputs "0", and the two-input OR gate G outputs "0", that is, the arbiter 233 outputs an indication not to allocate a cache line. This situation is equivalent to the situation where avg_L ≥ th2_L mentioned above.

[0108] In the embodiments of the present application, the clearing of historical information has been mentioned above. Therefore, as Figure 6 shown, the hardware module included in the LLC 23 may further include a sweeper 234 and a training unit 235.

[0109] The sweeper 234 is used to periodically clear / reset the historical information of some entries in the SW table, which can prevent the accumulation of the information of historical write operation streams from having a negative impact on the detection of changes in program behavior characteristics.

[0110] In some embodiments, the sweeper 234 is used to indicate the register 232 to clear the information of at least one historical write operation stream when the time when the detector 231 does not detect a write operation stream exceeds a time threshold.

[0111] In some embodiments, when the time when the detector 231 does not detect a write operation stream exceeds a time threshold, the sweeper 234 sends a fourth indication to the register 232, and the fourth indication is used to indicate clearing the information of at least one historical write operation stream (or the values of at least one entry).

[0112] That is, if the clearer 234 learns from the detector 231 that the detector 231 has not received the next write operation flow within the second time interval th_T (time threshold) from the time when the last write operation flow was received, then the clearer 234 can clear / reset the information of the historical write operation flow corresponding to certain indexes in the SW table.

[0113] In some embodiments, as Figure 7 As shown, the clearer 234 may be provided with a numerical comparator K. When the clearer 234 reads from the SW table in the register 232 that the first time interval T is greater than or equal to the second time interval th_T, indicating that the time interval since the last SW was received is greater than or equal to the time interval for clearing at least one item in the historical information, the clearer 234 may send a fourth instruction to the register 232 to clear the information of the historical write operation stream corresponding to certain indexes in the SW table. This is because receiving a write operation stream a considerable amount of time may indicate a program change, and the information in the SW table needs to be re-recorded for the next program.

[0114] The information of the cleared / reset historical write operation stream may include one or more of the above-mentioned num, reuse_p, alloc_p, P, total_L, avg_L, and anum_L.

[0115] Due to the clearing action for the SW table, the average length of the at least one historical write operation stream can also be understood as: the average length of the at least one historical write operation stream received since the last clearing of the historical write operation stream information;

[0116] The reuse information of at least one historical write operation stream may also be understood as: the proportion of cache lines that have been reused among cache lines allocated to the at least one historical write operation stream since the information of the historical write operation stream was last cleared.

[0117] The trainer 235 is used to train a threshold parameter used in the SW table for determining whether to allocate a cache line, and gradually converge the threshold parameter.

[0118] In some embodiments, the trainer 235 is configured to generate adjustment information based on a value of reuse information in the historical write operation stream information when the historical write operation stream information is most recently cleared, and a value of reuse information in the historical write operation stream information when the historical write operation stream information is most recently cleared.

[0119] The trainer 235 is further configured to send adjustment information to the register 232;

[0120] Register 232 is also used to update the information of the current historical write operation stream according to the adjustment information.

[0121] In some embodiments, the trainer 235 can generate adjustment information according to the first reuse information P_now in the information of the historical write operation stream when the information of the historical write operation stream was last cleared, and the second reuse information P_pre in the information of the historical write operation stream when the information of the historical write operation stream was cleared the previous time before the most recent clearing.

[0122] That is to say, the trainer 235 can adaptively adjust the threshold parameters in the SW table according to the reuse information each time the information of the historical write operation stream is cleared.

[0123] Among them, the adjusted table entries include one or more of the following items:

[0124] th1_L, th2_L, amax_L, and th_T.

[0125] In some embodiments, if P_now ≥ P_pre, and at least one value in the information of the historical write operation stream when the information of the historical write operation stream was last cleared is greater than or equal to at least one value in the information of the historical write operation stream when the information of the historical write operation stream was cleared the previous time, then add a preset value to at least one value in the information of the current historical write operation stream;

[0126] If P_now ≥ P_pre, and at least one value in the information of the historical write operation stream when the information of the historical write operation stream was last cleared is less than at least one value in the information of the historical write operation stream when the information of the historical write operation stream was cleared the previous time, then subtract a preset value from at least one value in the information of the current historical write operation stream;

[0127] If P_now < P_pre, and at least one value in the information of the historical write operation stream when the information of the historical write operation stream was last cleared is greater than or equal to at least one value in the information of the historical write operation stream when the information of the historical write operation stream was cleared the previous time, then subtract a preset value from at least one value in the information of the current historical write operation stream;

[0128] If P_now < P_pre, and at least one value in the information of the historical write operation stream when the information of the historical write operation stream was last cleared is less than at least one value in the information of the historical write operation stream when the information of the historical write operation stream was cleared the previous time, then add a preset value to at least one value in the information of the current historical write operation stream.

[0129] It should be noted that if multiple items in the information of the historical write operation stream need to be adjusted, the corresponding preset values for multiple items can be the same or different.

[0130] Exemplarily, if P_now ≥ P_pre, it indicates that the reuse ratio of the cache line has increased. Then it can be inferred that the adjustment direction of the information on the historical write operation stream in the previous time is feasible. At this time, if when clearing the information on the historical write operation stream recently, the value th_now of at least one item in the information on the historical write operation stream is greater than or equal to the value th_pre of at least one item in the information on the historical write operation stream when clearing the information on the historical write operation stream last time, then the value th_now of at least one item in the current information on the historical write operation stream can be continuously accumulated with a preset value dth to obtain the updated value th_next of the information on the historical write operation stream, that is, the threshold adjustment direction is: th_next = th_now + dth;

[0131] If P_now ≥ P_pre, it indicates that the reuse ratio of the cache line has increased. Then it can be inferred that the adjustment direction of the information on the historical write operation stream in the previous time is feasible. At this time, if when clearing the information on the historical write operation stream recently, the value th_now of at least one item in the information on the historical write operation stream is less than the value th_pre of at least one item in the information on the historical write operation stream when clearing the information on the historical write operation stream last time, then the value th_now of at least one item in the current information on the historical write operation stream can be subtracted by the preset value dth to obtain the updated value th_next of the information on the historical write operation stream, that is, the threshold adjustment direction is: th_next = th_now - dth;

[0132] If P_now < P_pre, it indicates that the reuse ratio of the cache line has decreased. Then it can be inferred that the adjustment direction of the information on the historical write operation stream in the previous time is not feasible. At this time, if when clearing the information on the historical write operation stream recently, the value th_now of at least one item in the information on the historical write operation stream is greater than or equal to the value th_pre of at least one item in the information on the historical write operation stream when clearing the information on the historical write operation stream last time, then the value th_now of at least one item in the current information on the historical write operation stream can be subtracted by the preset value dth to obtain the updated value th_next of the information on the historical write operation stream, that is, the threshold adjustment direction is: th_next = th_now - dth;

[0133] If P_now < P_pre, it indicates that the reuse ratio of the cache line has decreased. Then, it can be inferred that the previous adjustment direction for the information of the historical write operation stream is not feasible. At this time, if when clearing the information of the historical write operation stream recently, at least one value th_now in the information of the historical write operation stream is less than at least one value th_pre in the information of the historical write operation stream when clearing the information of the historical write operation stream last time, then at least one value th_now in the current information of the historical write operation stream can be accumulated with a preset value dth to obtain the updated value th_next of the information of the historical write operation stream, that is, the threshold adjustment direction is: th_next = th_now + dth.

[0134] Based on the principle of the trainer 235 introduced above, in some embodiments, the internal hardware circuit structure of the trainer 235 can refer to Figure 8 , in Figure 8 , the logic gate devices included in the trainer 235 can be: a numerical comparator K, a two-input AND gate L, a flip-flop M, a selector N, a numerical calculator O, and a flip-flop P.

[0135] Exemplarily, taking the instruction for the clearer 234 to output and clear the historical information as the binary number "1" as an example:

[0136] When the "1" output by the clearer 234 is input to the two-input AND gate L, if P_now < P_pre and the numerical comparator K outputs "1", then the two-input AND gate L outputs "1", that is, a rising edge is input to the CLK pin of the flip-flop P. When the CLK pin of the flip-flop detects a rising edge signal, the value of the D pin of the flip-flop P is imported to the Q pin and output to the selector N. Since the D pin of the flip-flop P is connected to the reverse of the previous adjustment direction, that is, a reverse adjustment signal is output. Then, when the D pin of the flip-flop P receives the reverse adjustment signal, the Q pin outputs the reverse adjustment signal to the selector N. The selector N selects an adjustment value that is the reverse of the adjustment value of the previous adjustment direction (for example, +dth was selected last time, and -dth is selected this time), and outputs it to the numerical calculator O. The numerical calculator Q adds the adjustment value selected this time (+dth or -dth) to the basis of the information of the historical write operation stream adjusted last time, and outputs the information th_next of the historical write operation stream adjusted this time to the D pin of the flip-flop P. The D pin of the flip-flop P outputs the adjusted information th_next of the historical write operation stream ( Figure 8 the th1_L, th2_L, amax_L, and th_T in

[0137] wherein, in Figure 8 In the figure, th1L_init represents the manually set initial value of th1_L, th2L_init represents the manually set initial value of th2_L, amax_init represents the initial value of amax_L, which is the maximum number of cache lines that can be allocated to the SW sequence, and th_T_init represents the initial value of th_T.

[0138] Therefore, the present application can also adaptively adjust the parameter thresholds in the information of the historical write operation flow, so that the future behavior characteristics of the program can be predicted based on the historical characteristic information of the program behavior, which can solve the problem of being unable to adaptively select the allocation strategy according to needs.

[0139] It should be noted that the present application does not limit the critical value for comparing the size of numerical values, that is, the case where the numerical values ​​are equal. That is, the case where the numerical values ​​are equal can be greater than or less than. The embodiments of the present application are only described by way of example.

[0140] Thus, the write allocation processing device provided by the embodiments of the present application determines whether to allocate a new target write operation stream to the cache each time a new target write operation stream arrives based on the information about the historical write operation streams at that time. Because different target write operation streams arrive at different times and have different information about their historical write operation streams, the allocation strategies they select will also be different, thereby achieving dynamic allocation strategy selection. Specifically, the device can dynamically analyze program behavior characteristics, determine program behavior characteristics in real time, and dynamically select an allocation strategy, thus resolving the problem that static allocation mechanisms cannot adapt to changes in program behavior.

[0141] Furthermore, the hardware module added to the cache in this application is a dedicated hardware circuit, which can realize the information search of historical write operation flows, allocation strategy decisions, and information updates of historical write operation flows. The parameter thresholds used for allocation strategy decisions can be automatically trained and optimized by the hardware circuit after the initial manual setting. That is, the dynamic selection of allocation strategies is automatically completed by the hardware without the need for software personnel to add instructions.

[0142] In addition, the allocation strategy of the present application adaptively determines whether to write to the cache based on the reuse information and average length and other information in the historical information, and writes the target write operation flow with high reuse and small sequence length to the cache. Moreover, the information of the historical write operation flow is allocated according to the SW source, operation address and data value indicated by the index, so that it can accurately match the reuse information and average length and other information corresponding to the currently received target write operation flow.

[0143] Using the cache memory provided by the embodiment of the present application, the embodiment of the present application also provides a write allocation processing method, such as Figure 9 As shown, the method includes:

[0144] 901. A target write operation stream is detected from received write operations, where addresses of multiple consecutive write operations included in the target write operation stream have regularity.

[0145] Step 901 may be implemented by the detector 231 in the cache memory. That is, when regularity is detected in the addresses of d consecutive write operations among the received write operations, a write operation stream consisting of m write operations starting from the d+1th write operation is used as the target write operation stream, where d and m are both positive integers greater than 1.

[0146] The specific implementation of step 901 can refer to the description of the detector 231 in the above device embodiment.

[0147] 902. Determine whether to allocate a cache line for a target write operation flow based on information of at least one historical write operation flow, where the at least one historical write operation flow is used to indicate a write operation flow before the target write operation flow.

[0148] The information of the historical write operation flow can refer to the introduction in the above embodiment. For example, the information of the historical write operation flow includes the average length of at least one historical write operation flow and the reuse information of at least one historical write operation flow. In some embodiments, the content of the information of the historical write operation flow can be seen in Table 1.

[0149] In some embodiments, step 902 may be implemented by determining whether to allocate a cache line to the target write operation stream based on the average length of at least one historical write operation stream, reuse information of at least one historical write operation stream, and a randomly extracted probability value. For a specific implementation, see the description of register 232 and arbiter 233 in the above embodiment.

[0150] In some embodiments, the method and steps of the present application may further include:

[0151] 903. When the time during which no write operation flow is detected exceeds a time threshold, clear information of at least one historical write operation flow.

[0152] The specific implementation of step 903 can refer to the introduction of the clearer 234 in the above embodiment.

[0153] 904. The device updates the current historical write operation stream information based on the value of the reuse information in the historical write operation stream information when the historical write operation stream information was most recently cleared, and the value of the reuse information in the historical write operation stream information when the historical write operation stream information was most recently cleared.

[0154] The specific implementation of step 904 can refer to the introduction of the trainer 235 in the above embodiment.

[0155] Therefore, the beneficial effects achieved by the method embodiments of the present application can refer to the beneficial effects of the above-mentioned embodiments on the cache memory, and will not be repeated here. In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0156] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0157] In addition, each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of a software functional unit. The above content is only a specific implementation method of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered within the protection scope of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A cache memory, characterized in that: include: a detector, configured to detect a target write operation stream from the received write operations, wherein addresses of a plurality of consecutive write operations contained in the target write operation stream have regularity; a register for storing information about at least one historical write operation stream, the at least one historical write operation stream being used to indicate a write operation stream preceding the target write operation stream, the information about the at least one historical write operation stream comprising an average length of the at least one historical write operation stream and reuse information of the at least one historical write operation stream, the average length of the at least one historical write operation stream being an average value of lengths of the at least one historical write operation stream, and the reuse information of the at least one historical write operation stream being a proportion of cache lines allocated to the at least one historical write operation stream that are reused; An arbiter is configured to determine whether to allocate a cache line to the target write operation flow according to an average length of the at least one historical write operation flow and reuse information of the at least one historical write operation flow.

2. The cache memory according to claim 1, wherein: The detector is specifically used for: When regularity is detected in the addresses of d consecutive write operations received, a write operation stream consisting of m write operations starting from the d+1th write operation is used as the target write operation stream, where d and m are both positive integers greater than 1.

3. The cache memory according to claim 1, wherein: The arbitrator includes a random probability generator and a calculator; The random probability generator is used to randomly generate probability values; The calculator is configured to determine whether to allocate a cache line to the target write operation flow according to an average length of the at least one historical write operation flow, reuse information of the at least one historical write operation flow, and the probability value.

4. The cache memory according to claim 3, wherein: The calculator is specifically used for: If the average length of the at least one historical write operation flow is less than a length threshold, and the probability value is less than reuse information of the historical write operation flow, it is determined to allocate a cache line for the target write operation flow.

5. The cache memory according to claim 3, wherein: The calculator is specifically used for: If the average length of the at least one historical write operation flow is less than a length threshold, and the probability value is greater than or equal to the reuse information of the historical write operation flow, it is determined not to allocate a cache line for the target write operation flow. The cache memory according to claim 3 , wherein: The calculator is specifically used for: If the average length of the at least one historical write operation stream is greater than a length threshold, it is determined not to allocate a cache line for the target write operation stream.

7. The cache memory according to any one of claims 1 to 6, characterized in that: The cache memory also includes a cleaner; The clearer is configured to instruct the register to clear the information of the at least one historical write operation flow when the time for which the detector does not detect the write operation flow exceeds a time threshold.

8. The cache memory according to any one of claims 1 to 6, characterized in that: The regularity of the addresses of the multiple write operations included in the target write operation stream means that the addresses of the multiple write operations increase or decrease.

9. A method for allocating write operations, characterized in that: include: detecting a target write operation stream from the received write operations, wherein addresses of a plurality of consecutive write operations included in the target write operation stream have regularity; Whether to allocate a cache line to the target write operation stream is determined based on the average length of at least one historical write operation stream and the reuse information of the at least one historical write operation stream, the at least one historical write operation stream is used to indicate the write operation stream before the target write operation stream, the information of the at least one historical write operation stream includes the average length of the at least one historical write operation stream and the reuse information of the at least one historical write operation stream, the average length of the at least one historical write operation stream is the average value of the lengths of the at least one historical write operation stream, and the reuse information of the at least one historical write operation stream is the proportion of cache lines that are reused in the cache lines allocated to the at least one historical write operation stream.

10. The method according to claim 9, characterized in that The detecting a target write operation stream from the received write operation includes: When regularity is detected in the addresses of d consecutive write operations received, a write operation stream consisting of m write operations starting from the d+1th write operation is used as the target write operation stream, where d and m are both positive integers greater than 1.

11. The method according to claim 9, characterized in that The determining whether to allocate a cache line to the target write operation flow according to the average length of the at least one historical write operation flow and the reuse information of the at least one historical write operation flow comprises: Randomly generate probability values; Determining whether to allocate a cache line to the target write operation flow is performed according to an average length of the at least one historical write operation flow, reuse information of the at least one historical write operation flow, and the probability value.

12. The method according to claim 11, characterized in that The determining whether to allocate a cache line to the target write operation flow according to the average length of the at least one historical write operation flow, the reuse information of the at least one historical write operation flow, and the probability value comprises: If the average length of the at least one historical write operation flow is less than a length threshold, and the probability value is less than reuse information of the historical write operation flow, it is determined to allocate a cache line for the target write operation flow.

13. The method according to claim 11, characterized in that The determining whether to allocate a cache line to the target write operation flow according to the average length of the at least one historical write operation flow, the reuse information of the at least one historical write operation flow, and the probability value comprises: If the average length of the at least one historical write operation flow is less than a length threshold, and the probability value is greater than or equal to the reuse information of the historical write operation flow, it is determined not to allocate a cache line for the target write operation flow.

14. The method according to claim 11, characterized in that The determining whether to allocate a cache line to the target write operation flow according to the average length of the at least one historical write operation flow, the reuse information of the at least one historical write operation flow, and the probability value comprises: If the average length of the at least one historical write operation stream is greater than a length threshold, it is determined not to allocate a cache line for the target write operation stream.

15. The method according to any one of claims 9 to 14, characterized in that: The method further comprises: When the time during which no write operation flow is detected exceeds a time threshold, information of the at least one historical write operation flow is cleared.

16. The method according to any one of claims 9 to 14, characterized in that: The regularity of the addresses of the multiple write operations included in the target write operation stream means that the addresses of the multiple write operations increase or decrease.

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