Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present application provides a semiconductor structure and a manufacturing method thereof. In the semiconductor structure, an in-situ insulating layer is formed on a heterojunction. The in-situ insulating layer has a groove, and a transition layer is provided in the groove and on the in-situ insulating layer. A p-type semiconductor layer is formed in a gate region on the transition layer. The transition layer facilitates the formation of the p-type semiconductor layer outside the groove during the process. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be relatively small, thereby increasing the threshold voltage. In addition, due to the provision of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of two-dimensional electron gas can be increased, the control ability of the gate over the channel can be improved, and the working current can be enhanced.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] As a typical representative of the third-generation semiconductor materials, wide-bandgap semiconductor material group-III nitrides have excellent characteristics such as a large bandgap, high voltage resistance, high temperature resistance, high electron saturation velocity and drift velocity, and are easy to form high-quality heterostructures, making them very suitable for manufacturing high-temperature, high-frequency, and high-power electronic devices.

[0003] For example, due to strong spontaneous polarization and piezoelectric polarization in the AlGaN / GaN heterojunction, a high-concentration two-dimensional electron gas (2DEG) exists at the AlGaN / GaN interface, which is widely used in semiconductor structures such as high electron mobility transistors (HEMTs).

[0004] Enhancement-mode devices have very wide applications in the field of power electronics due to their normally-off characteristics. There are many ways to implement enhancement-mode devices. For example, a p-type semiconductor is set at the gate to deplete the two-dimensional electron gas. Summary of the Invention

[0005] However, the inventors of this application found that: for the enhancement-mode device realized by setting a p-type semiconductor at the gate, the threshold voltage is small, and this method requires etching the p-type semiconductor outside the gate region, but etching inevitably brings etching loss.

[0006] To solve the above problems, on the one hand, the present invention provides a semiconductor structure, including:

[0007] A semiconductor substrate, a heterojunction, and an in-situ insulating layer distributed from bottom to top;

[0008] A groove penetrating the in-situ insulating layer; a transition layer located in the groove and on the in-situ insulating layer;

[0009] A p-type semiconductor layer in the gate region located on the transition layer, and the p-type semiconductor layer does not fill the groove.

[0010] Optionally, the semiconductor structure further includes: a gate located on the p-type semiconductor layer; and a source and a drain located on both sides of the gate.

[0011] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0012] Optionally, the material of the in-situ insulating layer includes at least one of SiN and SiAlN; and / or the material of the transition layer includes at least one of AlN, SiAlN, and AlGaN.

[0013] Optionally, the non-gate region on the transition layer also has the p-type semiconductor layer.

[0014] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top, and the source and drain are in contact with the channel layer or the barrier layer.

[0015] On the other hand, the present invention provides a method for manufacturing a semiconductor structure, including:

[0016] Providing a semiconductor substrate and forming a heterojunction on the semiconductor substrate;

[0017] Forming an in-situ insulating layer on the heterojunction;

[0018] Forming a groove penetrating the in-situ insulating layer;

[0019] Forming a transition layer and a p-type semiconductor layer in the groove and on the in-situ insulating layer, and the p-type semiconductor layer does not fill the groove.

[0020] Optionally, it further includes: forming a gate on the p-type semiconductor layer in the gate region; forming a source and a drain on both sides of the gate.

[0021] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top.

[0022] Optionally, the material of the in-situ insulating layer includes at least one of SiN and SiAlN; and / or the material of the transition layer includes at least one of AlN, SiAlN, and AlGaN.

[0023] Optionally, the p-type semiconductor layer is also patterned, and the p-type semiconductor layer in the gate region is retained.

[0024] Optionally, the heterojunction includes a channel layer and a barrier layer from bottom to top, and the source and drain are in contact with the channel layer or the barrier layer.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1) In the semiconductor structure of the present invention, an in-situ insulating layer is formed on the heterojunction. There are grooves in the in-situ insulating layer, and a transition layer is provided in the grooves and on the in-situ insulating layer. A p-type semiconductor layer is formed in the gate region on the transition layer. The transition layer facilitates the formation of the p-type semiconductor layer outside the grooves during the process. The in-situ insulating layer and the transition layer can reduce the gate leakage current formed by the channel leakage to the gate in the device. Therefore, the thickness of the barrier layer in the heterojunction can be relatively small, thereby increasing the threshold voltage. In addition, due to the setting of the in-situ insulating layer, the sheet resistance can be reduced, the concentration of the two-dimensional electron gas can be increased, the control ability of the gate over the channel can be improved, and the working current can be enhanced.

[0027] The setting of the transition layer can, on the one hand, avoid the selective growth of the p-type semiconductor on the in-situ insulating layer, thereby improving the quality of the p-type semiconductor layer. On the other hand, it can also prevent the diffusion of atoms (such as Si atoms) in the in-situ insulating layer into the p-type semiconductor layer and affecting the p-type semiconductor layer.

[0028] 2) In an alternative solution, the heterojunction includes a channel layer and a barrier layer from bottom to top. Specifically, a) The channel layer and the barrier layer can each have one layer; or b) The channel layer and the barrier layer can each have multiple layers and are alternately distributed; or c) One channel layer and two or more barrier layers to meet different functional requirements.

[0029] 3) In an alternative solution, the heterojunction includes a GaN-based material. The GaN-based material can include any one or a combination of GaN, AlGaN, and AlInGaN. The semiconductor structure of the present invention has strong compatibility with existing HEMT devices.

[0030] 4) In an alternative solution, the p-type semiconductor layer includes a GaN-based material. The material of the transition layer includes at least one of AlN, SiAlN, and AlGaN. The GaN-based material can include any one or a combination of GaN, AlGaN, and AlInGaN. The transition layer is formed by an in-situ growth process, which can improve the quality of the subsequent p-type semiconductor layer.

[0031] 5) In an alternative solution, the non-gate region on the transition layer also has a p-type semiconductor layer. In other words, the p-type semiconductor layer on the transition layer can be patterned, and only the p-type semiconductor layer in the gate region is retained, consuming the excess two-dimensional electron gas under the gate. Due to the presence of the in-situ insulating layer and the transition layer, the p-type semiconductor channel in the non-gate region can also be unpatterned, and the p-type semiconductor layers in the gate region and the non-gate region are both retained in the semiconductor structure.

[0032] 6) In an alternative solution, the source and drain are in contact with the channel layer or the barrier layer to meet the requirements of different semiconductor structures. Description of the Drawings

[0033] Figure 1It is a schematic structural diagram of the semiconductor structure according to the first embodiment of the present invention;

[0034] Figure 2 It is a flowchart of the manufacturing method of the semiconductor structure according to the first embodiment of the present invention;

[0035] Figures 3 to 5 It is Figure 2 The schematic diagram of the intermediate structure corresponding to the process in

[0036] Figure 6 It is a schematic structural diagram of the semiconductor structure according to the second embodiment of the present invention;

[0037] Figure 7 It is a schematic structural diagram of the semiconductor structure according to the third embodiment of the present invention;

[0038] Figure 8 It is a flowchart of the manufacturing method of the semiconductor structure according to the third embodiment of the present invention;

[0039] Figure 9 It is a schematic structural diagram of the semiconductor structure according to the fourth embodiment of the present invention;

[0040] Figure 10 It is a flowchart of the manufacturing method of the semiconductor structure according to the fourth embodiment of the present invention.

[0041] For the convenience of understanding the present invention, all the reference numerals appearing in the present invention are listed below:

[0042] Semiconductor structures 1, 2, 3, 4 Semiconductor substrate 10

[0043] Heterojunction 11 In-situ insulating layer 12

[0044] Groove 13 Transition layer 14

[0045] p-type semiconductor layer 15a Gate 15b

[0046] Source 16 Drain 17

[0047] Channel layer 11a Barrier layer 11b Detailed implementation manners

[0048] To make the above objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0049] Figure 1 It is a schematic structural diagram of the semiconductor structure according to the first embodiment of the present invention.

[0050] Referring to Figure 1 As shown, the semiconductor structure 1 includes:

[0051] A semiconductor substrate 10, a heterojunction 11, and an in-situ insulating layer 12 distributed from bottom to top;

[0052] A groove 13 penetrating the in-situ insulating layer 12; A transition layer 14 located within the groove 13 and on the in-situ insulating layer 12;

[0053] A p-type semiconductor layer 15a and a gate 15b of a gate region located on the transition layer 14, and a source 16 and a drain 17 located on both sides of the gate 15b.

[0054] The semiconductor substrate 10 can be sapphire, silicon carbide, silicon, GaN, or diamond.

[0055] The heterojunction 11 can include a channel layer 11a and a barrier layer 11b from bottom to top. A two-dimensional electron gas can be formed at the interface between the channel layer 11a and the barrier layer 11b. In an alternative embodiment, the channel layer 11a is an intrinsic GaN layer and the barrier layer 11b is an n-type AlGaN layer. In other alternative embodiments, the combination of the channel layer 11a and the barrier layer 11b can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN, or InN / InAlN. In addition, in addition to Figure 1 The shown channel layer 11a and barrier layer 11b each have one layer; The channel layer 11a and the barrier layer 11b can also each have multiple layers and be alternately distributed; Or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0056] There can also be a nucleation layer and a buffer layer (not shown) between the heterojunction 11 and the semiconductor substrate 10. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The nucleation layer can relieve the lattice mismatch and thermal mismatch problems between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10. The buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.

[0057] The in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process. One of the functions of the in-situ insulating layer 12 is to electrically insulate the gate 15b outside the groove 13 from the barrier layer 11b. In a HEMT structure, the in-situ insulating layer 12 can also suppress the current collapse effect.

[0058] In an alternative embodiment, the in-situ insulating layer 12 is a single-layer structure, and the material of the single-layer structure includes: one or more mixtures of SiN, SiAlN. In another alternative embodiment, the in-situ insulating layer 12 is a laminated structure, and the laminated structure may include, from bottom to top: an SiN layer and an SiAlN layer, an SiAlN layer and an SiN layer, or an SiN layer, an SiAlN layer, and an SiN layer, etc.

[0059] The transition layer 14 can be formed by an in-situ growth process. In an alternative embodiment, the transition layer 14 is a single-layer structure, and the material of the single-layer structure may include: one or more mixtures of AlN, SiAlN, AlGaN. In another alternative embodiment, the transition layer 14 is a laminated structure, and the laminated structure may include at least two of an AlN layer, an SiAlN layer, and an AlGaN layer. The transition layer 14 made of the above materials can solve the problem that the p-type GaN-based material cannot grow on the in-situ insulating layer 12, and thus a p-type semiconductor layer 15a can be formed outside the groove 13.

[0060] The p-type semiconductor layer 15a can be a GaN-based material, such as at least one of AlN, GaN, AlGaN, AlInGaN, and the p-type doping ions therein can be magnesium ions to deplete the two-dimensional electron gas below the gate region to form an enhancement-mode device.

[0061] Figure 1 In, the source electrode 16 and the drain electrode 17 are in contact with the barrier layer 11b, and an ohmic contact is formed therebetween; an ohmic contact is also formed between the gate electrode 15b and the p-type semiconductor layer 15a. The materials of the source electrode 16, the drain electrode 17, and the gate electrode 15b can be existing conductive materials such as metals and doped polysilicon.

[0062] In the above semiconductor structure 1, the in-situ insulating layer 12 and the transition layer 14 reduce the gate leakage current formed by the channel leakage to the gate electrode 15b. Therefore, the thickness of the barrier layer 11b in the heterojunction 11 can be smaller, thereby reducing the threshold voltage; in addition, due to the setting of the in-situ insulating layer 12, the sheet resistance can be reduced, the concentration of the two-dimensional electron gas can be increased, thereby improving the control ability of the gate electrode over the channel and increasing the operating current.

[0063] The setting of the transition layer 14 can, on the one hand, avoid the selective growth of the p-type semiconductor layer 15a on the in-situ insulating layer 12, thereby improving the quality of the p-type semiconductor layer; on the other hand, it can also prevent atoms (such as Si atoms) in the in-situ insulating layer 12 from diffusing into the p-type semiconductor layer and affecting the p-type semiconductor layer.

[0064] To verify the technical effects of the present invention, taking the thickness of the barrier layer 11b as 5 nm as an example, 5 nm Al 0.25GaN Barrier Layer / GaN Channel Layer Semiconductor Structure and 5nm In-situ SiN Layer / 5nm Al 0.25 When comparing with the GaN barrier layer / GaN channel layer semiconductor structure, it is found that: the sheet resistance (surface resistance) between the source electrode 16 and the drain electrode 17 can be reduced from 2300Ω / □ to 325Ω / □, and the two-dimensional electron gas concentration in the heterojunction 11 can be increased from 2.4E12 / cm 2 to 1.03E13 / cm 2 .

[0065] In addition, in the existing HEMT structure of the AlGaN barrier layer / GaN channel layer, the thickness of the barrier layer 11b needs to be 15nm - 25nm to ensure the generation of a two-dimensional electron gas with sufficient concentration. In this application, when the thickness range of the barrier layer 11b is 1nm - 15nm, a two-dimensional electron gas with sufficient concentration can be generated; preferably, the thickness of the barrier layer 11b can be controlled below 10nm.

[0066] Figure 2 is a flowchart of the manufacturing method of the semiconductor structure of the first embodiment of the present invention; Figures 3 to 5 is Figure 2 the schematic diagram of the intermediate structure corresponding to the process in

[0067] First, referring to Figure 2 the steps S1 in Figure 3 and as shown in

[0068] a semiconductor substrate 10 is provided, and a heterojunction 11 is formed on the semiconductor substrate 10. The semiconductor substrate 10 can be sapphire, silicon carbide, silicon, GaN or diamond.

[0069] The heterojunction 11 can include a channel layer 11a and a barrier layer 11b from bottom to top. In an alternative, the channel layer 11a is an intrinsic GaN layer and the barrier layer 11b is an n-type AlGaN layer. In other alternatives, the combination of the channel layer 11a and the barrier layer 11b can also be GaN / AlN, GaN / InN, GaN / InAlGaN, GaAs / AlGaAs, GaN / InAlN or InN / InAlN. The formation process of the channel layer 11a and the barrier layer 11b can include: atomic layer deposition (ALD), or chemical vapor deposition (CVD), or molecular beam epitaxy (MBE), or plasma enhanced chemical vapor deposition (PECVD), or low pressure chemical vapor deposition (LPCVD), or metal-organic chemical vapor deposition (MOCVD), or a combination thereof.

[0070] In addition to Figure 1 the channel layer 11a and the barrier layer 11b shown each having one layer; the channel layer 11a and the barrier layer 11b can also each have multiple layers and be alternately distributed; or one channel layer 11a and two or more barrier layers 11b to form a multi-barrier structure.

[0071] Before forming the heterojunction 11 on the semiconductor substrate 10, a nucleation layer and a buffer layer (not shown) can be sequentially formed first. The material of the nucleation layer can be, for example, AlN, AlGaN, etc., and the material of the buffer layer can include at least one of AlN, GaN, AlGaN, and AlInGaN. The formation method of the buffer layer can be the same as that of the heterojunction 11. The nucleation layer can relieve the lattice mismatch and thermal mismatch problems between the epitaxially grown semiconductor layer, such as the channel layer 11a in the heterojunction 11 and the semiconductor substrate 10, and the buffer layer can reduce the dislocation density and defect density of the epitaxially grown semiconductor layer and improve the crystal quality.

[0072] Test Figure 3 the sheet resistance (surface resistance) of the shown example structure, which is 2300 Ω / □.

[0073] Next, referring to Figure 2 step S2 in Figure 4 as shown, an in-situ insulating layer 12 is formed on the heterojunction 11.

[0074] The in-situ insulating layer 12 is an insulating layer formed by an in-situ growth process. In one alternative, the in-situ insulating layer 12 is a single-layer structure, and the materials of this single-layer structure include: one or a mixture of more of SiN and SiAlN. In another alternative, the in-situ insulating layer 12 is a laminated structure, and this laminated structure may include, from bottom to top: an SiN layer and an SiAlN layer, an SiAlN layer and an SiN layer, or an SiN layer, an SiAlN layer, and an SiN layer, etc.

[0075] After that, referring to Figure 2 the steps S3 in Figure 4 as shown, a groove 13 penetrating the in-situ insulating layer 12 is formed.

[0076] The groove 13 can be formed by dry etching or wet etching. Specifically, a patterned mask layer is first formed on the in-situ insulating layer 12. The mask layer can be a photoresist layer, and is patterned by a process of first exposure and then development. The dry etching gas can be CF4, C3F8, etc., and the wet etching solution can be hot phosphoric acid.

[0077] Test Figure 4 the sheet resistance (surface resistance) of the shown example structure, which is 325 Ω / sq.

[0078] Then, referring to Figure 2 the steps S4 in Figure 5 as shown, a transition layer 14 and a p-type semiconductor layer 15a are sequentially formed in the groove 13 and on the in-situ insulating layer 12; referring to Figure 1 as shown, the p-type semiconductor layer 15a is patterned, and the p-type semiconductor layer 15a in the gate region is retained; a gate 15b is formed on the p-type semiconductor layer 15a in the gate region; source electrodes 16 and drain electrodes 17 are formed on both sides of the gate 15b.

[0079] The transition layer 14 can be formed by an in-situ growth process. In one alternative, the transition layer 14 is a single-layer structure, and the materials of this single-layer structure may include: one or a mixture of more of AlN, SiAlN, and AlGaN. In another alternative, the transition layer 14 is a laminated structure, and this laminated structure may include at least two of an AlN layer, an SiAlN layer, and an AlGaN layer.

[0080] The p-type semiconductor layer 15a includes a GaN-based material, such as at least one of GaN, AlGaN, and AlInGaN, and the p-type doping ions therein can be magnesium ions. The formation process of the p-type semiconductor layer 15a can refer to the formation processes of the channel layer 11a and the barrier layer 11b.

[0081] The patterned p-type semiconductor layer 15a can be achieved by dry etching or wet etching. Compared with the solution of patterning the p-type semiconductor layer 15a directly formed on the barrier layer 11b, the in-situ insulating layer 12 and the transition layer 14 can prevent over-etching in the patterning process from damaging the barrier layer 11b.

[0082] The source electrode 16, the drain electrode 17, and the gate electrode 15b can be made of existing conductive materials such as metal and doped polysilicon, and are formed by physical vapor deposition or chemical vapor deposition correspondingly.

[0083] Figure 6 It is a schematic structural diagram of the semiconductor structure of the second embodiment of the present invention.

[0084] Refer to Figure 6 and Figure 1 As shown, the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, and the only difference is that the source electrode 16 and the drain electrode 17 are in contact with the channel layer 11a.

[0085] Ohmic contacts are formed between the source electrode 16 and the channel layer 11a, and between the drain electrode 17 and the channel layer 11a.

[0086] Correspondingly, the manufacturing method of the semiconductor structure 2 of the second embodiment is substantially the same as that of the semiconductor structure 1 of the first embodiment, and the only difference is that in step S4, when forming the source electrode 16 and the drain electrode 17 on both sides of the gate electrode 15b, the p-type semiconductor layer 15a, the transition layer 14, the in-situ insulating layer 12, and the barrier layer 11b in the source region and the drain region are removed to expose the channel layer 11a.

[0087] Figure 7 It is a schematic structural diagram of the semiconductor structure of the third embodiment of the present invention. Figure 8 It is a flowchart of the manufacturing method of the semiconductor structure of the third embodiment of the present invention.

[0088] Refer to Figure 7 and Figure 1 and Figure 6 As shown, the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structures 1 and 2 of the first and second embodiments, and the only difference is that on the transition layer 14, the non-gate region outside the gate region also has a p-type semiconductor layer 15a.

[0089] Correspondingly, refer to Figure 8 and Figure 2As shown, the manufacturing method of the semiconductor structure 3 in the third embodiment is substantially the same as that of the semiconductor structures 1 and 2 in the first and second embodiments, with the only difference being that: in step S4', the step of patterning the p-type semiconductor layer 15a is omitted. In other words, step S4' includes: sequentially forming a transition layer 14 and a p-type semiconductor layer 15a in the groove 13 and on the in-situ insulating layer 12; forming a gate 15b on the p-type semiconductor layer 15a in the gate region; and forming a source 16 and a drain 17 on both sides of the gate 15b.

[0090] Figure 9 FIG. is a schematic structural diagram of a semiconductor structure according to a fourth embodiment of the present invention. Figure 10 FIG. is a flowchart of a manufacturing method of a semiconductor structure according to a fourth embodiment of the present invention. Refer to Figure 9 and Figure 1 As shown, the semiconductor structure 4 in the fourth embodiment is substantially the same as the semiconductor structure 1 in the first embodiment, with the only difference being that: the semiconductor structure 4 is an intermediate semiconductor structure, and the gate 15b, the source 16, and the drain 17 are not fabricated.

[0091] Correspondingly, refer to Figure 10 and Figure 2 As shown, the manufacturing method of the semiconductor structure 4 in the fourth embodiment is substantially the same as that of the semiconductor structure 1 in the first embodiment, with the only difference being that: in step S4'', the steps of fabricating the gate 15b, the source 16, and the drain 17 are omitted, and the p-type semiconductor layer 15a does not fill the groove 13.

[0092] The semiconductor structure 4 can also be produced and sold as a semi-finished product.

[0093] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Including: A semiconductor substrate (10), a heterojunction (11), and an in-situ insulating layer (12) distributed from bottom to top; A groove (13) penetrating through the in-situ insulating layer (12); A transition layer (14) located in the groove (13) and on the in-situ insulating layer (12); A p-type semiconductor layer (15a) of a gate region located on the transition layer (14), and the p-type semiconductor layer (15a) does not fill the groove (13); Wherein, the material of the in-situ insulating layer (12) includes at least one of SiN and SiAlN; and / or the material of the transition layer (14) includes at least one of AlN and AlGaN; and / or the p-type semiconductor layer (15a) is at least one of AlN, GaN, AlGaN, and AlInGaN; Wherein, both the in-situ insulating layer (12) and the transition layer (14) are formed by an in-situ growth process; Wherein, the transition layer (14) completely covers the upper surface of the in-situ insulating layer (12), and the transition layer (14) is arranged to avoid selective growth of the p-type semiconductor layer (15a) on the in-situ insulating layer (12) and prevent atoms in the in-situ insulating layer (12) from diffusing into the p-type semiconductor layer (15a).

2. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: A gate (15b) located on the p-type semiconductor layer (15a); And a source electrode (16) and a drain electrode (17) located on both sides of the gate (15b).

3. The semiconductor structure according to claim 1 or 2, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

4. The semiconductor structure according to claim 1 or 2, characterized in that, The non-gate region on the transition layer (14) also has the p-type semiconductor layer (15a).

5. The semiconductor structure according to claim 2, wherein The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top, and the source electrode (16) and the drain electrode (17) are in contact with the channel layer (11a) or the barrier layer (11b).

6. A manufacturing method of a semiconductor structure, characterized in that, Including: Providing a semiconductor substrate (10) and forming a heterojunction (11) on the semiconductor substrate (10); Forming an in-situ insulating layer (12) on the heterojunction (11); Forming a groove (13) penetrating through the in-situ insulating layer (12); Forming a transition layer (14) and a p-type semiconductor layer (15a) in the groove (13) and on the in-situ insulating layer (12), and the p-type semiconductor layer (15a) does not fill the groove (13); Wherein, the material of the in-situ insulating layer (12) includes at least one of SiN and SiAlN; and / or the material of the transition layer (14) includes at least one of AlN and AlGaN; and / or the p-type semiconductor layer (15a) is at least one of AlN, GaN, AlGaN, and AlInGaN; Wherein, both the in-situ insulating layer (12) and the transition layer (14) are formed by an in-situ growth process; Wherein, the transition layer (14) completely covers the upper surface of the in-situ insulating layer (12), and the transition layer (14) is configured to avoid selective growth of the p-type semiconductor layer (15a) on the in-situ insulating layer (12) and prevent atoms in the in-situ insulating layer (12) from diffusing into the p-type semiconductor layer (15a).

7. The method for fabricating a semiconductor structure according to claim 6, wherein Further included are: forming a gate (15b) on the p-type semiconductor layer (15a) in the gate region; forming a source electrode (16) and a drain electrode (17) on both sides of the gate (15b).

8. The method for fabricating a semiconductor structure according to claim 6 or 7, wherein The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein, The p-type semiconductor layer (15a) is also patterned, and the p-type semiconductor layer (15a) in the gate region is retained.

10. The manufacturing method of the semiconductor structure according to claim 7, characterized in that, The heterojunction (11) includes a channel layer (11a) and a barrier layer (11b) from bottom to top, and the source electrode (16) and the drain electrode (17) are in contact with the channel layer (11a) or the barrier layer (11b).

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