A gallium oxide MODFET device with p-SnO hybrid gate and a preparation method thereof

Abstract

The application discloses a gallium oxide MODFET device with a p-SnO hybrid gate and a preparation method thereof, which comprises buffer, interval, doping and barrier layers on a substrate, forms source-drain regions, source-drain electrodes, a p-SnO layer, a gate dielectric, a first passivation layer, a gate electrode, a floating field plate, a second passivation layer, a dielectric layer and a source field plate and the like. A p-n junction and a MIS structure are deposited in a gate recess, a three-dimensional gate control is realized by fully surrounding the gate electrode, strong depletion of the p-n junction is realized, a high-quality interface of the MIS structure is combined, high threshold voltage is obtained, low gate leakage current and high reliability are maintained. A composite field plate of an integrated discrete floating field plate and a high-k dielectric recess and a source field plate is adopted, on the one hand, a capacitive coupling effect of the floating field plate is used to realize a stepwise and smooth lateral electric field and hardly add gate-drain capacitance, and low Miller capacitance is maintained; on the other hand, high-k dielectric is introduced in a high electric field area near a drain electrode, and redistribution of a longitudinal electric field is realized; and the two kinds of field plates are cooperated to realize three-dimensional modulation of an internal electric field of the device, increase a breakdown voltage and maintain a relatively fast switching speed.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a gallium oxide MODFET device with a p-SnO mixed gate and its fabrication method. Background Technology

[0002] With the ever-increasing demands for efficiency, power density, and operating temperature in power electronic systems, the performance development of traditional silicon-based materials has reached its physical limits due to the inherent limitations of their physical properties. Third-generation semiconductor materials, represented by silicon carbide (SiC) and gallium nitride (GaN), have gradually become commercialized and have demonstrated superior performance in medium- and high-voltage applications. Currently, the fourth-generation ultra-wide bandgap semiconductor, gallium oxide (β-Ga2O3), boasts a bandgap (~4.9 eV) far exceeding that of SiC (~3.2 eV) and GaN (~3.4 eV), a critical breakdown electric field as high as 8 MV / cm, and a Baliga figure of merit (3444) that is 10 times that of SiC and more than 4 times that of GaN, demonstrating enormous application potential in next-generation high-voltage, high-current power devices. However, gallium oxide suffers from low mobility. This can be addressed by using δ-modulation doping to form a high-density two-dimensional electron gas (2DEG) at the heterojunction interface, constituting a modulation-doped field-effect transistor (MODFET) to significantly improve channel mobility.

[0003] Despite its significant material advantages, the commercialization of gallium oxide MODFETs is still constrained by two interconnected core bottlenecks: First, achieving high-performance, high-reliability enhancement-mode operation is extremely difficult. Due to the presence of high-density 2DEG, the devices are typically depletion-mode, conducting without a gate voltage and requiring a negative gate voltage to turn off. This leads to high system safety risks, complex gate drive circuits, and increased system power consumption. Enhancement-mode devices, on the other hand, are in the off-mode without a gate voltage, offering higher system safety and reliability. The gate drive design is simpler, significantly reducing switching losses in the off-mode, making them more valuable for research and application. Existing technologies, such as grooved gates, introduce additional lattice damage, resulting in larger gate leakage currents and unstable threshold voltages. Fluorine ion implantation suffers from drift and diffusion of implanted ions under electric field and temperature stress, leading to poor long-term threshold voltage stability. Commonly used p-GaN has limited threshold voltage regulation due to the low activation energy of Mg, while p-type oxides, such as NiO and CuO, have low threshold voltages due to shallow valence band levels, failing to meet the requirements of higher threshold voltages for safer operation in practical applications.

[0004] Second, the actual breakdown voltage of the device is far lower than the theoretical value of the material. Although gallium oxide theoretically has an extremely high critical breakdown electric field, in actual devices, the electric field will be highly concentrated at the gate edge, especially on the drain side, forming a peak electric field, causing the device to break down prematurely. Common single-field plates have limited ability to modulate the electric field and cannot fully utilize the high breakdown field strength advantage of gallium oxide.

[0005] Therefore, it is necessary to explore a solution that can achieve enhanced operation with high threshold voltage and high reliability while also obtaining high breakdown voltage. Summary of the Invention

[0006] In view of the above problems, this application provides a gallium oxide MODFET device with a p-SnO hybrid gate and its fabrication method, so as to synergistically solve the comprehensive problems of low threshold voltage, difficulty in balancing gate control capability and breakdown voltage, and insufficient reliability in existing enhancement-mode technologies.

[0007] In a first aspect, this application provides a gallium oxide MODFET device with a p-SnO mixed gate, comprising: a buffer layer, a spacer layer, a delta-doped layer and a barrier layer sequentially stacked on a substrate; The barrier layer, the delta-doped layer, the spacer layer, and the buffer layer of a certain thickness are respectively provided with source and drain regions on both sides, and the source and drain regions are heavily doped n-type gallium oxide layers; the source and drain regions are respectively provided with source and drain electrodes; The barrier layer has a gate groove running through the front and back in the middle, and a p-SnO layer is provided on the gate groove near the source region side; a gate dielectric is provided on the top surface of the p-SnO layer, the remaining gate groove, and between the two. A first passivation layer is deposited on the device surface, excluding the source, drain, gate grooves, and the portion of the barrier layer region to their left. A fully enclosed gate is provided on the p-SnO layer and the gate dielectric surface. A plurality of electrically isolated discrete gate floating field plates with the same spacing and thickness are deposited on the first passivation layer between the drain and the gate. A second passivation layer is deposited on the first passivation layer, the gate, and the gate floating field plates. A dielectric groove is provided on the upper surface of the second passivation layer near the drain side, and a high-k dielectric layer is filled in the dielectric groove. A source field plate is deposited on the source, the high-k dielectric layer, and between them.

[0008] In some embodiments, the thickness of the buffer layer extending into the source and drain regions is 20-40 nm; the depth of the gate trench needs to retain a barrier layer thickness of 2-5 nm; the p-SnO layer occupies 40%-60% of the surface area of ​​the gate trench; 3-5 gate floating field plates are provided; the source field plate is covered with a high-k dielectric layer and extends outwards by a small portion.

[0009] The etching depth of a buffer layer of a certain thickness needs to be greater than the depth of the 2D electron gas channel. The 2DEG is mainly located near the upper surface of the buffer layer (at the interface with the spacer layer). This depth range ensures sufficient groove depth to epitaxially form high-quality source and drain regions to form good ohmic contacts. Etching too deeply increases the process difficulty and time, and produces more etching damage.

[0010] The thickness of the barrier layer in the gate trench is sufficient to ensure that the built-in electric field of pn formed by p-SnO can effectively deplete the channel and maintain the heterojunction interface quality without destroying the interface that generates 2DEG.

[0011] The role of p-SnO is to increase the threshold voltage, while the MIS region maintains dynamic characteristics and conduction capability. If the p-SnO ratio is too low, the pn junction depletion effect may be too weak, making it impossible to achieve a sufficiently high threshold voltage. If the ratio is too high, it will reduce the proportion of the MIS region, resulting in a decrease in gate control capability and an increase in on-resistance.

[0012] The gate floating field plate does not contact the gate metal. A second passivation layer separates it horizontally, while vertically, the gate floating field plate lies above the first passivation layer, acting as an insulating medium to physically isolate the floating field plate from the channel, with no DC path between them. Increasing the number of gate floating field plates allows for finer division of the electric field peaks; however, the further the field plate is from the gate, the weaker the capacitive coupling with the channel, resulting in a poorer modulation effect. Furthermore, an excessive number of field plates increases photolithographic complexity and chip area. For a specific gate-drain pitch, increasing the number of field plates after the electric field has been sufficiently modulated has little effect.

[0013] The starting position of the source field plate: Starting from the source, it extends across the gate region from the surface of the second passivation layer to the edge of the high-k dielectric trench, completely covering the entire high-k dielectric trench and extending 1~3 μm. This extended field plate, combined with the conventional passivation layer, can further shift the electric field towards the drain side to achieve a smoother transition.

[0014] In some embodiments, the gate dielectric within the gate recess is 5–10 nm below the upper surface of the barrier layer. This provides sufficient space for the gate dielectric to fully surround the barrier, thereby enabling three-dimensional contact and encapsulation from the top and sidewalls.

[0015] In some embodiments, the gate dielectric thickness deposited on the surface of the p-SnO layer and within the gate trench is 5-15 nm. The gate dielectric isolates the p-SnO layer from the overlying gate metal, reducing gate leakage and forming a good interface with the p-SnO layer to suppress interface states. The gate dielectric thickness deposited on the surface of the p-SnO layer and within the gate trench is consistent, and the growth is completed in a single process.

[0016] The function of the first passivation layer is to act as an insulating protective layer, covering all exposed surfaces to suppress surface states and provide electrical isolation. The upper surface of the first passivation layer must be a continuous plane located at the highest position of the current device.

[0017] In some embodiments, the substrate is a high-resistivity or semi-insulating β-Ga₂O₃, and its doping element can be one of Mg, Fe, Zn, P, etc.; the doping concentration is 5 × 10⁻⁶. 15 ~5×10 18 cm -3 The substrate thickness is 250~550 μm.

[0018] In some embodiments, the buffer layer is unintentionally doped β-Ga2O3; the thickness of the buffer layer is 100~500nm.

[0019] Unintentional doping refers to the process of epitaxial growth of materials (such as MOCVD, MBE) in which no specific dopant (such as Si, Fe, etc.) is actively and intentionally introduced. However, due to reasons such as the purity of raw materials, background impurities in the reaction chamber, trace impurities in the carrier gas or precursor, a low concentration of impurity atoms is inevitably introduced, which has a certain impact on the electrical properties of the material.

[0020] In some embodiments, the spacer layer is unintentionally doped β-(AlGa)₂O₃ with an Al composition of 0.15 to 0.3; the thickness of the spacer layer is 1 to 5 nm.

[0021] β-(AlGa)₂O₃ is a material formed by mixing gallium oxide and aluminum oxide in different proportions, specifically in the form of β-(AlGa)₂O₃. x Ga 1-x The alloy is β-Ga₂O₃, where x represents the Al component. When x = 0, the material is pure β-Ga₂O₃; when x = 1, the material is pure Al₂O₃. This means that in this alloy material, the proportion of aluminum atoms to the total number of metal atoms (aluminum + gallium) is between 15% and 30%.

[0022] In some embodiments, the δ-doped layer is an n-type doped β-(AlGa)₂O₃, and the doping element can be either Si or Ge, with a doping concentration of 1 × 10⁻⁶. 19 ~5×10 19 cm -3 The Al component accounts for 0.15~0.3% of Al and Ga; the thickness of the δ-doped layer is 1~2 nm.

[0023] In some embodiments, the barrier layer is unintentionally doped β-(AlGa)2O3, with the Al component accounting for 0.15 to 0.3% of the total Al and Ga content; the thickness of the barrier layer is 18 to 25 nm.

[0024] In some embodiments, the heavily doped n-type gallium oxide layer is heavily doped n-type β-Ga₂O₃, and the doping element is one of Si, Sn, and Ge, with a doping concentration of 1 × 10⁻⁶. 20 ~5×10 20 cm -3 The thickness of the heavily doped n-type gallium oxide layer is 50~100nm; the source and drain electrodes can be independently selected from one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Ti / Au. In some embodiments, the thickness of the p-SnO layer is 50~100 nm; the concentration of the p-SnO layer is 5×10⁻⁶. 17 ~3×10 18 cm -3 .

[0025] The concentration of the p-SnO layer refers to the concentration of effective, freely movable holes or acceptors in p-SnO. Specifically, it refers to the number of holes per unit volume of p-SnO that can participate in electrical conduction under thermal equilibrium conditions.

[0026] In some embodiments, the first passivation layer and the second passivation layer are independently selected from Si3N4 and SiO2, and have a thickness of 100~400 nm.

[0027] In some embodiments, the gate dielectric can be one or more of Al2O3, HfO2, and ZrO2, with a thickness of 5-15 nm; the gate electrode is one of Ni / Au, Pt / Au, and TiN; the gate floating field plate is one of Ni / Au, Pt / Au, and TiN; the high-k dielectric layer is one or more of BaTiO3, SrTiO3, TiO2, and ZrO2; and the source field plate is one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Ti / Au.

[0028] Secondly, this application provides a method for fabricating a gallium oxide MODFET device with a p-SnO hybrid gate, comprising the following steps: S1. A buffer layer, a spacer layer, a delta-doped layer, and a barrier layer are epitaxially grown sequentially on the substrate; S2. Etching is performed on both sides of the barrier layer, forming a first groove on the left side of the barrier layer and a second groove on the right side of the barrier layer. The etching depth penetrates the barrier layer, the δ-doped layer, the spacer layer, and a buffer layer of a certain thickness. Then, heavily doped n-type gallium oxide is epitaxially grown outside the first groove to form the source region, and heavily doped n-type gallium oxide is epitaxially grown outside the second groove to form the drain region. Next, metal is deposited above the source region to form the source electrode, and metal is deposited above the drain region to form the drain electrode. The electrodes are then rapidly annealed in a nitrogen atmosphere to form an ohmic contact. S3. In the middle region of the barrier layer between the source and drain regions, a portion of the thickness is etched to form a gate groove, the depth of which is less than the total thickness of the barrier layer. S4. Selectively deposit a p-SnO layer in the gate trench, depositing only the region of the gate trench near the source region, while leaving the rest of the gate trench exposed; S5. Deposit a gate dielectric layer on the upper surface of the p-SnO layer and the remaining exposed gate recess region; S6. A first passivation layer is deposited on the surface of device S5. The source, drain, gate trench, and part of the barrier layer region on the left are exposed by photolithography and etching. Gate metal is photolithographically etched and deposited in the exposed gate trench and part of the barrier layer region on the left to form a gate that fully surrounds the p-SnO and gate dielectric structure. At the same time, a series of electrically isolated gate floating field plates are deposited on the first passivation layer on the right side of the gate with the same spacing and thickness by photolithography. S7. Deposit a second passivation layer on the surface other than the source and drain. Form a dielectric groove in the area above the second passivation layer near the drain by photolithography and etching. Deposit a high-k dielectric layer in the dielectric groove to completely fill the groove. S8. Photolithography and metal deposition are performed between the source electrode and the high-k dielectric layer to form a source field plate. The source field plate covers the dielectric groove where the dielectric layer is located and extends outward by a small portion.

[0029] In some embodiments, the growth methods for the buffer layer, spacer layer, delta-doped layer, barrier layer, and heavily doped n-type gallium oxide layer can be one of MOCVD, MBE, and Mist-CVD.

[0030] The beneficial effects of this application are: 1) A pn ​​junction with a local groove is formed, and p-SnO has a deep valence band level, which can form a strong built-in electric field with the two-dimensional electron gas channel. The channel is depleted from the side and top at zero gate voltage, which can achieve a higher threshold voltage. A groove MIS (metal-insulator-semiconductor) structure is formed on the other side of the gate groove region to form a high-quality dielectric layer / semiconductor interface, which can effectively induce and accumulate electrons in the device in the turn-on state, and has better gate control capability and long-term reliability.

[0031] 2) A fully enclosed gate can maximize the gate control capability: The gate metal not only covers the top of the hybrid gate, but also wraps around the two sidewalls, electrically connecting the pn junction region and the MIS region, ensuring that gate control is applied more evenly throughout the channel.

[0032] 3) Discrete floating field plates reduce Miller capacitance while increasing breakdown voltage: Since there is no direct metal contact between the field plate and the gate, and they are in a floating state, their contribution to the gate-drain capacitance is minimized, thus reducing Miller capacitance. This improves switching speed and reduces switching losses. Each floating field plate can form a coupling capacitor with the channel below. Under the high voltage of the off-state, the floating field plate can induce charge, redistributing the electric field lines below it. This disperses the single high electric field peak concentrated at the gate edge into multiple secondary electric field peaks, increasing breakdown voltage and further improving device reliability.

[0033] 4) The integrated high-k dielectric trench and source field plate structure improves the longitudinal electric field distribution and enables broader electric field modulation: By etching a trench near the high-electric-field region of the drain and completely filling it with a high-k dielectric layer, a source field plate is deposited and extends to cover the right side of the trench. At the interface between the high-k dielectric and the low-k passivation layer, the internal electric field of the high-k dielectric is significantly suppressed to maintain the continuity of the electric displacement vector. When the high-k dielectric trench is located in the region where the peak electric field is located, it can absorb and make the electric field more uniformly distributed, thereby effectively suppressing the electric field concentration phenomenon on the semiconductor surface. At the same time, the electric field is extended to the drain side through the source field plate, achieving broader electric field modulation.

[0034] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0035] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a schematic diagram of the structure of a gallium oxide MODFET device with a p-SnO hybrid gate according to the present invention; Figure 2 This is a schematic diagram of the epitaxial structure formed on a substrate in the device manufacturing method of the present invention, comprising a buffer layer, a spacer layer, a delta-doped layer, and a barrier layer. Figure 3 for Figure 2 A schematic diagram of the structure forming the first and second grooves based on the existing structure; Figure 4 for Figure 3 Based on this, a schematic diagram of the source region, drain region, source electrode, and drain electrode structure is formed; Figure 5 for Figure 4 A schematic diagram of the structure in which the gate groove is formed on the basis; Figure 6 for Figure 5 A schematic diagram of a structure in which a p-SnO layer is formed on the basis; Figure 7 for Figure 6 A schematic diagram of the structure in which the gate dielectric layer is formed on the basis; Figure 8 for Figure 7 A schematic diagram of the structure on which the first passivation layer is formed; Figure 9 for Figure 8 A schematic diagram of the structure on which the gate is formed; Figure 10 for Figure 9 A schematic diagram of the structure forming the gate floating field plate based on the foundation; Figure 11 for Figure 10 A schematic diagram of the structure on which a second passivation layer is formed; Figure 12 for Figure 11 A schematic diagram of a high-k dielectric layer formed on the basis.

[0036] The reference numerals in the detailed embodiments are as follows: 1-Substrate; 2-Buffer layer; 3-Spacer layer; 4-δ-Doped layer; 5-Barrier layer; 6-Source region; 7-Drain region; 8-Source; 9-Drain; 10-p-SnO layer; 11-Gate dielectric; 12-First passivation layer; 13-Gate; 14-Gate floating field plate; 15-Second passivation layer; 16-High-k dielectric layer; 17-Source field plate. Detailed Implementation

[0037] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0038] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0039] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0040] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0041] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0042] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0043] In the description of the embodiments of this application, the technical terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.

[0044] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0045] According to some embodiments of this application, refer to Figure 1-12 This application provides a gallium oxide MODFET device with a p-SnO hybrid gate, comprising: a buffer layer 2, a spacer layer 3, a delta-doped layer 4, and a barrier layer 5 sequentially stacked on a substrate 1; The barrier layer 5, the δ-doped layer 4, the spacer layer 3, and the buffer layer 2 of a certain thickness are respectively provided with a source region 6 and a drain region 7 on both sides. The source region 6 and the drain region 7 are heavily doped n-type gallium oxide layers. The source region 6 and the drain region 7 are respectively provided with a source electrode 8 and a drain electrode 9. The barrier layer 5 has a gate groove running through the front and back in the middle, and a p-SnO layer 10 is provided on the side of the gate groove near the source region 6; a gate dielectric 11 is provided on the top surface of the p-SnO layer 10, the remaining gate groove, and between the two. A first passivation layer 12 is deposited on the device surface, excluding the source 8, drain 9, gate groove, and the left portion of the barrier layer 5. A fully enclosed gate 13 is provided on the surface of the p-SnO layer 10 and the gate dielectric 11. A plurality of electrically isolated discrete gate floating field plates 14 with the same spacing and thickness are deposited on the first passivation layer 12 between the drain 9 and the gate 13. A second passivation layer 15 is deposited on the first passivation layer 12, the gate 13, and the gate floating field plates 14. A dielectric groove is provided on the upper surface of the second passivation layer 15 near the drain 9. A high-k dielectric layer 16 is filled in the dielectric groove. A source field plate 17 is deposited on the source 8, the high-k dielectric layer 16, and between them.

[0046] All structural layers of the device are arranged through the front and back.

[0047] Discrete emphasizes that the field plates are spatially independent; while electrical isolation emphasizes that there is no electrical contact between the field plates or between the field plates and other electrodes. One is a spatial description, and the other is an electrical description. The two are not equivalent. Combining electrical isolation and discreteness can indicate that these field plates are both spatially discrete and electrically isolated from each other.

[0048] In some embodiments, the thickness of the buffer layer 2 extending into the source region 6 and drain region 7 is 20-40 nm; the depth of the gate trench needs to retain the thickness of the barrier layer 5 by 2-5 nm; the p-SnO layer 10 occupies 40%-60% of the surface area of ​​the gate trench; 3-5 gate floating field plates 14 are provided; the source field plate 17 covers the high-k dielectric layer 16 and extends outward by a small portion.

[0049] The etching depth of the buffer layer 2, which has a certain thickness, is greater than the depth of the two-dimensional electron gas channel. The 2DEG is mainly located near the upper surface of the buffer layer 2 (at the interface with the spacer layer 3). This depth range ensures sufficient groove depth to epitaxially form high-quality source region 6 and drain region 7 to form good ohmic contact. Etching too deeply will increase the process difficulty and time, and produce more etching damage.

[0050] The barrier layer 5 is retained in the gate groove. The barrier layer 5 is retained to a sufficient thickness to ensure that the pn built-in electric field formed by p-SnO can effectively deplete the channel and maintain the heterojunction interface quality without destroying the interface that generates 2DEG.

[0051] The role of p-SnO is to increase the threshold voltage, while the MIS region maintains dynamic characteristics and conduction capability. If the p-SnO ratio is too low, the pn junction depletion effect may be too weak, making it impossible to achieve a sufficiently high threshold voltage. If the ratio is too high, it will reduce the proportion of the MIS region, resulting in a decrease in gate I3 control capability and an increase in on-resistance.

[0052] The gate floating field plate 14 is not in metal contact with the gate 13. A second passivation layer 15 separates them in the horizontal direction. In the vertical direction, the gate floating field plate 14 is located above the first passivation layer 12, serving as an insulating medium to physically isolate the floating field plate from the channel, with no DC path between them. Increasing the number of gate floating field plates 14 can finely divide the electric field peaks, but the capacitance coupling between the field plate and the channel weakens as the field plate is farther from the gate 13, resulting in a worse modulation effect. Furthermore, an excessive number of field plates increases photolithography complexity and chip area. For a specific gate-drain pitch, increasing the number of field plates after the electric field has been sufficiently modulated has little effect.

[0053] The starting position of the source field plate 17: Starting from the source 8, it extends from the surface of the second passivation layer 15 across the gate 13 region, reaching the edge of the high-k dielectric trench, and needs to completely cover the entire high-k dielectric trench, extending 1~3 μm. This extended field plate, combined with the conventional passivation layer, can further push the electric field towards the drain 9 side to achieve a smoother transition.

[0054] The gate dielectric 11 within the gate recess is 5-10 nm below the upper surface of the barrier layer 5. This provides sufficient space for the gate dielectric 11 to fully surround the barrier layer 5, thereby enabling three-dimensional contact and encapsulation from the top and sidewalls.

[0055] The thickness of the gate dielectric 11 deposited on the surface of the p-SnO layer 10 and in the gate trench is 5~15 nm. The gate dielectric 11 isolates the gate dielectric 10 from the metal gate 13 above it, thereby reducing gate leakage. It also forms a good interface with the p-SnO layer 10 to suppress interface states. The thickness of the gate dielectric 11 deposited on the surface of the p-SnO layer 10 and in the gate trench is consistent, and the growth is completed in a single process.

[0056] The function of the first passivation layer 12 is to act as an insulating protective layer, covering all exposed surfaces to suppress surface states and provide electrical isolation. The upper surface of the first passivation layer 12 must be a continuous plane located at the highest position of the current device.

[0057] In some embodiments, the substrate 1 is a high-resistivity or semi-insulating β-Ga₂O₃, and its doping element can be one of Mg, Fe, Zn, P, etc.; the doping concentration is 5 × 10⁻⁶. 15 ~5×10 18 cm -3 The thickness of the substrate 1 is 250~550 μm.

[0058] A high-resistivity or semi-insulating substrate 1 can prevent vertical leakage, effectively reduce leakage current and improve the off-state leakage performance of the device.

[0059] In some embodiments, the buffer layer 2 is unintentionally doped with β-Ga2O3; the thickness of the buffer layer 2 is 100~500 nm.

[0060] The function of buffer layer 2 is to form a "triangular potential well" at the upper interface to gather electrons to form a two-dimensional electron gas and provide a channel for electron transport, while reducing the leakage current of the device.

[0061] In some embodiments, the spacer layer 3 is unintentionally doped β-(AlGa)2O3, and the Al component accounts for 0.15~0.3% of Al and Ga; the thickness of the spacer layer 3 is 1~5 nm.

[0062] Spacer layer 3 can suppress disordered scattering of the alloy and improve electron mobility. If spacer layer 3 is too thin, the δ-doped layer 4 is too close to the interface of the two-dimensional electron gas, which increases the scattering of charge carriers and reduces mobility; if spacer layer 3 is too thick, the influence of δ-doped layer 4 on the two-dimensional electron gas interface is reduced, and the increase in electron density and mobility is not significant.

[0063] In some embodiments, the δ-doped layer 4 is an n-type doped β-(AlGa)₂O₃, and the doping element can be either Si or Ge, with a doping concentration of 1 × 10⁻⁶. 19 ~5×10 19 cm -3 The Al component accounts for 0.15~0.3% of Al and Ga; the thickness of the δ-doped layer 4 is 1~2 nm.

[0064] A thicker δ-doped layer 4 can increase the 2DEG density and mobility; however, a thinner δ-doped layer 4 will increase parasitic capacitance, affecting the device's switching speed and frequency response.

[0065] In some embodiments, the barrier layer 5 is unintentionally doped β-(AlGa)2O3, and the Al component accounts for 0.15~0.3% of Al and Ga; the thickness of the barrier layer 5 is 18~25 nm.

[0066] Increasing the thickness of barrier layer 5 can improve the 2DEG density, but the 2DEG density tends to saturate after a certain thickness; an excessively thick barrier layer 5 will increase the parasitic capacitance of the device and affect the high-frequency characteristics.

[0067] In some embodiments, the heavily doped n-type gallium oxide layer is heavily doped n-type β-Ga₂O₃, and the doping element is one of Si, Sn, and Ge, with a doping concentration of 1 × 10⁻⁶. 20 ~5×10 20 cm -3 The thickness of the heavily doped n-type gallium oxide layer is 50~100nm; the source 8 and drain 9 are independently selected from one of Ti / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Au, etc. Heavily doped n-type gallium oxide layers help achieve good ohmic contacts and reduce the difficulty of fabrication. The thickness of the heavily doped n-type gallium oxide layer should be greater than the sum of the thicknesses of spacer layer 3, δ-doped layer 4, and barrier layer 5 to reduce the leakage current of the channel. If the heavily doped n-type gallium oxide layer is too thick, it will increase the distance from the source 8 and drain 9 to the channel, reducing the modulation effect of the source 8 and drain 9 on the channel.

[0068] In some embodiments, the thickness of the p-SnO layer 10 is 50~100 nm; the concentration of the p-SnO layer 10 is 5×10⁻⁶. 17 ~3×10 18 cm -3 .

[0069] The p-SnO layer thickness of 10 ensures that the depletion region of the pn junction can effectively penetrate and deplete the two-dimensional electron gas in the channel, thereby achieving a higher threshold voltage. If the p-SnO thickness is too small, sufficient channel depletion cannot be achieved, resulting in poor modulation of the threshold voltage and a low threshold voltage. If the thickness is too large, it will increase the physical distance between the gate 13 and the channel, thereby weakening the gate 13's control over the channel, while also increasing cost and process complexity.

[0070] In some embodiments, the first passivation layer 12 and the second passivation layer 15 are independently selected from Si3N4 and SiO2, and have a thickness of 100~400 nm.

[0071] In some embodiments, the gate dielectric 11 can be one or more of Al2O3, HfO2, and ZrO2, and the thickness can be 5~15 nm; the gate electrode 13 is one of Ni / Au, Pt / Au, and TiN; the gate floating field plate 14 is one of Ni / Au, Pt / Au, and TiN; the high-k dielectric layer 16 is one or more of BaTiO3, SrTiO3, TiO2, and ZrO2; and the source field plate 17 is one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Ti / Au.

[0072] The function of gate dielectric 11 is to reduce the leakage current of gate 13, increase the breakdown voltage of gate 13, and at the same time reduce the voltage division of p-SnO layer 10 to further increase the threshold voltage.

[0073] The integrated high-k dielectric 16 and source field plate 17 (a composite field plate structure composed of high-k dielectric 16 and source field plate 17) can gradually increase the surface potential from gate 13 to drain 9, thereby increasing the area of ​​the depletion region and being able to withstand a larger drain voltage, thereby increasing the breakdown voltage.

[0074] Secondly, this application provides a method for fabricating a gallium oxide MODFET device with a p-SnO hybrid gate, comprising the following steps: S1. A buffer layer 2, a spacer layer 3, a δ-doped layer 4 and a barrier layer 5 are epitaxially grown sequentially on substrate 1; S2. Etching is performed on both sides of the barrier layer 5, forming a first groove on the left side of the barrier layer 5 and a second groove on the right side of the barrier layer 5. The etching depth penetrates the barrier layer 5, the δ-doped layer 4, the spacer layer 3, and a buffer layer 2 of a certain thickness. Then, heavily doped n-type gallium oxide is epitaxially grown outside the first groove to form the source region 6, and heavily doped n-type gallium oxide is epitaxially grown outside the second groove to form the drain region 7. Next, metal is deposited above the source region 6 to form the source electrode 8, and metal is deposited above the drain region 7 to form the drain electrode 9. The ohmic contact is formed by rapid annealing in a nitrogen atmosphere. S3. In the middle region of the barrier layer 5 between the source region 6 and the drain region 7, a portion of the thickness is etched to form a gate groove, the depth of which is less than the total thickness of the barrier layer 5. S4. Selective deposition is performed in the gate trench, depositing the p-SnO layer 10 only in the region of the gate trench near the source region 6, while the remaining region of the gate trench remains exposed; S5. Deposit a gate dielectric 11 on the upper surface of the p-SnO layer 10 and the remaining exposed gate recess region; S6. A first passivation layer 12 is deposited on the surface of device S5. The source 8, drain 9, gate groove and the left part of the barrier layer 5 region are exposed by photolithography and etching. Gate 13 metal is photolithographically etched and deposited in the exposed gate groove and the left part of the barrier layer 5 region to form a gate structure that fully surrounds the p-SnO layer 10 and the gate dielectric 11 (or the first passivation layer 12 is deposited on the device surface except for the source 8, drain 9, gate groove and the left part of the barrier layer 5 region. Gate 13 metal is photolithographically etched and deposited in the exposed gate groove and the left part of the barrier layer 5 region to form a gate structure that fully surrounds the p-SnO layer 10 and the gate dielectric 11); at the same time, a series of electrically isolated gate floating field plates 14 are deposited above the first passivation layer 12 on the right side of the gate 13 with the same spacing and thickness by photolithography. S7. A second passivation layer 15 is deposited on the surface other than the source electrode 8 and the drain electrode 9. A dielectric groove is formed in the area above the second passivation layer 15 near the drain electrode 9 by photolithography and etching. A high-k dielectric layer 16 is deposited in the dielectric groove to completely fill the groove. S8. Photolithography and metal deposition are performed between the source electrode 8 and the high-k dielectric layer 16 to form a source field plate 17. The source field plate 17 covers the dielectric groove where the dielectric layer is located and extends outward by a small portion.

[0075] In some embodiments, the growth methods of the buffer layer 2, spacer layer 3, δ-doped layer 4, barrier layer 5, and heavily doped n-type gallium oxide layer can be one of MOCVD, MBE, and Mist-CVD.

[0076] According to some embodiments of this application, see Figure 1-12 This application provides a method for fabricating a gallium oxide MODFET device with a p-SnO hybrid gate, comprising the following steps: 1) A β-Ga₂O₃ buffer layer 2, a β-(AlGa)₂O₃ spacer layer 3, a δ-doped layer 4, and a β-(AlGa)₂O₃ barrier layer 5 are sequentially deposited on a semi-insulating β-Ga₂O₃ substrate 1 using metal-organic chemical vapor deposition (MOCVD). Here, the thickness of the semi-insulating β-Ga₂O₃ substrate 1 is 550 μm, the thickness of the β-Ga₂O₃ buffer layer 2 is 300 nm, the thickness of the β-(AlGa)₂O₃ spacer layer 3 is 3 nm, the thickness of the δ-doped layer 4 is 1 nm, and the thickness of the β-(AlGa)₂O₃ barrier layer 5 is 20 nm. Figure 2 As shown. The doping concentration of the δ-doped layer 4 is 5 × 10⁻⁶. 19 cm -3 The aluminum composition of spacer layer 3, δ-doped layer 4, and barrier layer 5 is 0.18.

[0077] 2) Plasma-enhanced chemical vapor deposition (PECVD) was used to grow 300 nm SiO2 as a mask. Photolithography defined the source region 6 and drain region 7 windows. BOE solution was used to remove the SiO2 above the source region 6 and drain region 7. Simultaneously, Cl2 / BCl3 dry etching was used to etch the β-(AlGa)2O3 barrier layer 5, the δ-doped layer 4, the β-(AlGa)2O3 spacer layer 3, and a β-Ga2O3 buffer layer 2 of a certain thickness to expose the channel region. The total etching depth was 50 nm. Figure 3 As shown.

[0078] 3) 70 nm heavily doped n-type β-Ga₂O₃ was epitaxially grown in the etched area using MOCVD to form source region 6 and drain region 7. Then, the SiO₂ mask was removed by immersion in hydrofluoric acid for 30 min. Ti / Au (50 / 50 nm) was sequentially deposited using electron beam evaporation to cover source region 6 and drain region 7, and then rapidly thermally annealed at 475 °C in a nitrogen atmosphere for 1 min to form the ohmic contacts for source electrode 8 and drain electrode 9. Figure 4 As shown.

[0079] 4) A SiO2 mask is deposited and patterned again on the surface of barrier layer 5, and the gate trench region is defined by photolithography. This region is located between the source 8 and the drain 9. A portion of the β-(AlGa)2O3 barrier layer 5 is etched using Cl2 / BCl3 dry etching to form the gate trench, with an etching depth of approximately 15 nm. Figure 5 As shown.

[0080] 5) A PECVD deposition of approximately 300 nm SiO2 was used as a mask. The mask layer was then photolithographically etched and etched to expose approximately half of the gate trench area (near the source 8 side). A 70 nm p-SnO layer was selectively deposited in the exposed gate trench area using magnetron sputtering, with a hole concentration of approximately 2 × 10⁻⁶. 18 cm -3 This forms a recessed pn junction. Next, the surface SiO2 mask and the p-SnO layer 10 covering it are removed by immersion in hydrofluoric acid for 30 minutes, leaving the p-SnO layer 10 only on a specific side of the gate recess, while the other side remains exposed, forming a hybrid gate structure, such as... Figure 6 As shown.

[0081] 6) Using SiO2 as a mask, photolithography and etching are performed to expose the area where the gate trench is located. A 5 nm layer of Al2O3 is deposited using ALD as the gate dielectric 11, covering the p-SnO and the other half of the exposed gate trench, as shown below. Figure 7 As shown.

[0082] 7) Using SiO2 as a mask, photolithography and etching are performed to expose the device surface except for the area to the left of the gate trench, the gate trench region, the source 8, and the drain 9. A 100 nm Si3N4 layer is deposited using PECVD as the first passivation layer 12. Figure 8 As shown.

[0083] 8) Photolithography is used to define the region where gate 13 is located (including the gate groove and its outward extension to the left). A Ni / Au metal (50 / 100 nm) is deposited to form a fully enclosed gate, ensuring that the gate 13 metal is in direct contact with the p-SnO on the left side, thus providing lateral control of gate 13. Figure 9 As shown. Simultaneously, above the first passivation layer 12 between the gate 13 and the drain 9, and at a certain distance from the gate 13, a series of Ni / Au metals with the same spacing and thickness (50 / 100 nm) are photolithographically lithographically deposited to form discrete gate floating field plates 14. Each field plate is approximately 1 μm wide and 1 μm apart, and there are three such field plates. These field plates are not electrically connected to the gate 13 below, as shown. Figure 10 As shown.

[0084] 9) Using SiO2 as a mask, photolithography and etching are performed to expose the device surface except for the source electrode 8 and drain electrode 9. PECVD is used to deposit 400 nm Si3N4 as the second passivation layer 15. Figure 11 As shown.

[0085] 10) Selectively photolithographically etch a dielectric trench with a depth of 200 nm and a width of 3 μm in the region near the drain 9 of the second passivation layer 15. Simultaneously, an ALD deposition of a 200 nm high-k dielectric layer 16 BaTiO3 is used to fill the etched dielectric trench to form a dielectric field plate. For example... Figure 12 As shown. Next, a Ti / Au (100 / 100 nm) metal layer is photolithographically etched and deposited to form a source field plate 17, which is electrically connected to the source 8. This source field plate 17 extends from the source 8 region along the upper surface of the second passivation layer 15 to the right side of the dielectric field plate. As... Figure 1 As shown.

[0086] The device prepared by the method of this application has the following technical characteristics: By combining a recessed pn junction, a recessed MIS, and a fully enclosed gate structure, a hybrid gate is constructed within the gate recess by selective deposition, where a local recessed pn junction and a local recessed MIS structure coexist. Three-dimensional gate control is then performed using a fully enclosed gate 13 metal to form the hybrid gate. The depletion effect of the pn junction is used to achieve a higher threshold voltage, while the MIS structure is combined to achieve a combination of strong depletion of the pn junction and a high-quality interface of the MIS structure. This reduces gate 13 leakage current, enhances gate 13 control capability, and achieves a high threshold voltage while maintaining low gate 13 leakage current and high reliability.

[0087] The discrete gate floating field plate 14 has no electrical connection with the gate 13, which minimizes the Miller capacitance. Based on the capacitive coupling effect, the floating field plate can rearrange the electric field distribution below it, dispersing the concentrated electric field peak into multiple secondary peaks, forming a stepped transverse electric field distribution.

[0088] The high-k dielectric 16 is combined with the source field plate 17: A groove is etched and filled with the high-k dielectric layer 16 in the high-electric-field region near the drain 9, while the source field plate 17 is deposited simultaneously. This structure is based on the dielectric constant abrupt change effect. To maintain a continuous electric displacement vector at the interface between the high-k dielectric and the low-k passivation layer, the internal electric field of the high-k dielectric is significantly suppressed, thereby homogenizing the longitudinal electric field to alleviate the electric field concentration effect. The source field plate 17 further extends the electric field towards the drain 9, achieving more extensive electric field modulation.

[0089] By combining the discrete gate floating field plate 14 with a composite structure consisting of a high-k dielectric 16 and a source field plate 17, a step-like smoothing of the lateral electric field is achieved through the capacitive coupling effect of the gate floating field plate 14, with almost no gate-drain capacitance, maintaining a low Miller capacitance. Simultaneously, a high-k dielectric is introduced into the high-field region near the drain 9 to redistribute the longitudinal electric field. Through the synergistic effect of these two field plates, three-dimensional electric field modulation of the internal electric field of the device is achieved, increasing the breakdown voltage while maintaining a fast switching speed.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application, and they should all be covered within the scope of the claims and specification of this application. In particular, as long as there is no structural conflict, the various technical features mentioned in the embodiments can be combined in any way. This application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims

1. A gallium oxide MODFET device with a p-SnO hybrid gate, characterized in that, include: A buffer layer, a spacer layer, a delta-doped layer, and a barrier layer are sequentially stacked on the substrate. The barrier layer, the delta-doped layer, the spacer layer, and the buffer layer of a certain thickness are respectively provided with source and drain regions on both sides, and the source and drain regions are heavily doped n-type gallium oxide layers; the source and drain regions are respectively provided with source and drain electrodes; The barrier layer has a gate groove running through the front and back in the middle, and a p-SnO layer is provided on the gate groove near the source region side; a gate dielectric is provided on the top surface of the p-SnO layer, the remaining gate groove, and between the two. A first passivation layer is deposited on the device surface, excluding the source, drain, gate recess and the left-side portion of the barrier layer region; a fully enclosed gate is provided on the p-SnO layer and the gate dielectric surface; a plurality of discrete gate floating field plates with the same spacing and thickness are deposited on the first passivation layer between the drain and the gate. A second passivation layer is deposited on the first passivation layer, the gate, and the gate floating field plate; a dielectric groove is provided on the upper surface of the second passivation layer near the drain side, and a high-k dielectric layer is filled in the dielectric groove; a source field plate is deposited on the source, the high-k dielectric layer, and between the two.

2. The device as claimed in claim 1, characterized in that, The thickness of the buffer layer extending into the source and drain regions is 20-40 nm; the depth of the gate trench needs to retain a barrier layer thickness of 2-5 nm; the p-SnO layer occupies 40%-60% of the surface area of ​​the gate trench; there are 3-5 gate floating field plates; the source field plate is covered with a high-k dielectric layer and extends outwards by a small portion.

3. The device as claimed in claim 1, characterized in that, The substrate is a high-resistivity or semi-insulating β-Ga₂O₃, and its doping element can be one of Mg, Fe, Zn, P, etc.; the doping concentration is 5 × 10⁻⁶. 15 ~5×10 18 cm -3 The substrate thickness is 250~550 μm.

4. The device as claimed in claim 1, characterized in that, The buffer layer is unintentionally doped β-Ga₂O₃, and the thickness of the buffer layer is 100~500 nm; the spacer layer is unintentionally doped β-(AlGa)₂O₃, the Al component accounts for 0.15~0.3% of Al and Ga, and the thickness of the spacer layer is 1~5 nm.

5. The device as claimed in claim 1, characterized in that, The δ-doped layer is an n-type doped β-(AlGa)₂O₃, and the doping element can be either Si or Ge, with a doping concentration of 1 × 10⁻⁶. 19 ~5×10 19 cm -3 The Al component accounts for 0.15~0.3% of Al and Ga, and the thickness of the δ-doped layer is 1~2 nm; the barrier layer is unintentionally doped β-(AlGa)2O3, the Al component accounts for 0.15~0.3% of Al and Ga, and the thickness of the barrier layer is 18~25 nm.

6. The device as claimed in claim 1, characterized in that, The heavily doped n-type gallium oxide layer is a heavily doped n-type β-Ga₂O₃, with the doping element being one of Si, Sn, or Ge, and the doping concentration being 1 × 10⁻⁶. 20 ~5×10 20 cm -3 The thickness of the heavily doped n-type gallium oxide layer is 50~100 nm; the source and drain can be one of Ti / Au, Ti / Al / Ni / Au, Ti / Al / Ti / Au, etc.

7. The device as claimed in claim 1, characterized in that, The thickness of the p-SnO layer is 50~100 nm; the concentration of the p-SnO layer is 5×10⁻⁶. 17 ~3×10 18 cm -3 .

8. The device as claimed in claim 1, characterized in that, The first passivation layer and the second passivation layer are independently selected from Si3N4 and SiO2, and the thickness is 100~400 nm.

9. The device as claimed in claim 1, characterized in that, The gate dielectric can be one or more of Al2O3, HfO2, and ZrO2, and the thickness can be 5~15 nm; the gate electrode is one of Ni / Au, Pt / Au, and TiN; the gate floating field plate is one of Ni / Au, Pt / Au, and TiN; the high-k dielectric layer is one or more of BaTiO3, SrTiO3, TiO2, and ZrO2; and the source field plate is one of Ti / Au, Ti / Al / Ni / Au, and Ti / Al / Ti / Au.

10. A method for fabricating a gallium oxide MODFET device with a p-SnO hybrid gate, characterized in that, Includes the following steps: S1. A buffer layer, a spacer layer, a delta-doped layer, and a barrier layer are epitaxially grown sequentially on the substrate; S2. Etching is performed on both sides of the barrier layer, forming a first groove on the left side of the barrier layer and a second groove on the right side of the barrier layer. The etching depth penetrates the barrier layer, the δ-doped layer, the spacer layer, and a buffer layer of a certain thickness. Then, heavily doped n-type gallium oxide is epitaxially grown outside the first groove to form the source region, and heavily doped n-type gallium oxide is epitaxially grown outside the second groove to form the drain region. Next, metal is deposited above the source region to form the source electrode, and metal is deposited above the drain region to form the drain electrode. The electrodes are then rapidly annealed in a nitrogen atmosphere to form an ohmic contact. S3. In the middle region of the barrier layer between the source and drain regions, a portion of the thickness is etched to form a gate trench, the depth of which is less than the total thickness of the barrier layer. S4. Selectively deposit a p-SnO layer in the gate trench, depositing only the region of the gate trench near the source region, while leaving the rest of the gate trench exposed; S5. Deposit a gate dielectric layer on the upper surface of the p-SnO layer and the remaining exposed gate recess region; S6. Deposit a first passivation layer on the device surface, excluding the source, drain, gate trench, and the portion of the barrier layer region to its left. Photolithographically etch and deposit gate metal in the exposed gate trench and the portion of the barrier layer region to its left to form a gate that fully surrounds the p-SnO and gate dielectric structure; simultaneously, photolithographically deposit a series of electrically isolated gate floating field plates above the first passivation layer on the right side of the gate with the same spacing and thickness; S7. Deposit a second passivation layer on the surface other than the source and drain. Form a dielectric groove in the area above the second passivation layer near the drain by photolithography and etching. Deposit a high-k dielectric layer in the dielectric groove to completely fill the groove. S8. Photolithography and metal deposition are performed between the source electrode and the high-k dielectric layer to form a source field plate. The source field plate covers the dielectric groove where the dielectric layer is located and extends outward by a small portion.

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