Gate drive circuit

Abstract

A gate drive circuit is provided which uses a simpler circuit and suppresses an increase in cost, and which includes a higher-speed switching circuit. The gate drive circuit drives a semiconductor switch based on a control signal, and includes: an input terminal; a high-side switch connected to a positive-side power supply; a low-side switch connected to a negative-side power supply; a first differentiation circuit connected to the positive-side power supply, which differentiates the control signal and supplies it to the high-side switch; a second differentiation circuit connected to the negative-side power supply, which differentiates the control signal and supplies it to the low-side switch; an output terminal which outputs a signal to be driven; a first impedance circuit connected between the high-side switch and the output terminal; and a second impedance circuit connected between the high-side switch and the output terminal.

Description

TECHNICAL FIELD

[0001] The present application relates to a gate drive circuit for driving a power switch such as an Insulated Gate Bipolar Transistor (IGBT) or a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). BACKGROUND

[0002] With the recent demand for energy saving, solar power generation or wind power generation is gradually becoming important in terms of energy supply. A gate drive circuit for driving a large power switch used in such a power machine is used.

[0003] Such a large power switch needs to be turned on / off at high speed (with accuracy of the order of nanoseconds (nsec)). That is, regarding the switching frequency of the power machine, there is a tendency to promote high frequency from the viewpoint of achieving light weight, space saving, low price, and the like. The power switch used in such a situation also needs to be switched at high speed.

[0004] Regarding the power switch, an IGBT or a SiC-MOSFET, GaN, or the like semiconductor is used. These IGBTs and the like semiconductors have a large input capacitance at the drive terminal (gate terminal). The gate circuit of a large power switch is generally capacitive, and the larger the power capacity, the larger the capacitance.

[0005] Therefore, at the initial stage of driving the power switch, a large current flows. Therefore, driving such a high-speed switch as the power switch requires the ability to switch a large current at high speed. From the recent demand for energy saving, further lightening of the device is sought, and further high speed is required. As a result, for a drive circuit for a high-speed switching power switch, the ability to supply a large current instantaneously is further required.

[0006] On the other hand, the control circuit of the power machine cannot directly supply such a large current to the large power switch. Therefore, between the control circuit and the large power switch, a gate drive circuit that performs current amplification or voltage amplification at high speed is generally required. The present application aims to provide a gate drive circuit that can achieve faster switching as a switching circuit for such a gate drive circuit.

[0007] Prior art

[0008] For example, Patent Literature 1 (Japanese Patent Laid-Open No. 03-286619) described later discloses a gate drive circuit that drives a semiconductor including an insulated gate. In particular, a structure is disclosed in which a check valve type switch is provided midway through a wire that supplies charge from a power supply to a gate, and an inductive element is provided between the check valve type switch and the gate. It is considered that resonance is produced between the gate capacitance and the inductance of the inductive element using this structure, and thus high-speed switching can be achieved.

[0009] Patent Literature 2 (Japanese Patent Laid-Open No. 04-176209) described later discloses a structure in which charge for turning on (ON) operation of a metal-oxide-semiconductor (MOS) transistor is supplied via a diode. It is considered that a MOSFET (metal-oxide-semiconductor field-effect transistor) that temporarily performs ON operation continues to perform ON operation, and thus high-speed switching can be performed.

[0010] Patent Literature 3 (Japanese Patent Laid-Open No. 2017-17995) described later discloses a wireless power supply device that includes a high-frequency circuit using a Metal Insulator Semiconductor Effect Field Transistors (MISFET) and a resonance circuit connected to the high-frequency circuit. It is considered that high-speed switching is possible by the resonance circuit, and a wireless power supply device with excellent performance can be provided.

[0011] Prior Art Documents

[0012] Patent Literature

[0013] Patent Literature 1: Japanese Patent Laid-Open No. 03-286619

[0014] Patent Literature 2: Japanese Patent Laid-Open No. 04-176209

[0015] Patent Literature 3: Japanese Patent Laid-Open No. 2017-17995 SUMMARY

[0016] PROBLEMS TO BE SOLVED BY THE INVENTION

[0017] In the case of amplifying a signal from a control circuit at high speed, a circuit structure is used in which Figure 10 such a circuit structure. As Figure 10As shown, the switching circuit 10 is configured with a high-side switch 11 provided on the positive side of the power supply and a low-side switch 12 provided on the negative side of the power supply. Further, an input terminal 13 that inputs a control signal from a control circuit not shown is connected to the high-side switch 11 and the low-side switch 12. Thus, a circuit is configured in which the high-side switch 11 and the low-side switch 12 are driven by the control signal (or "ON / OFF signal") from the control circuit.

[0018] Figure 10 Further, an output terminal 14 that outputs an output signal for driving the IGBT 15 is connected to the high-side switch 11 and the low-side switch 12. Further, a P-AMP 16 for power amplification is provided between the output terminal 14 and the IGBT 15 (see Figure 10 ).

[0019] However, if the control signal from the control circuit is directly connected to the high-side switch 11 and the low-side switch 12, when the ON / OFF signal from the control circuit changes from L to H or from H to L, there are sometimes periods in which both switches (the high-side switch 11 and the low-side switch 12) become in the ON state at the same time.

[0020] The reason for this is that, as shown in Figure 11 , when the state of the control signal from the control circuit is changed, there is always a period in which the potential passes through the intermediate potential between Vdc (the positive side of the power supply) and Vee (the negative side of the power supply). During this period, the voltage of the control signal is an input voltage (referred to as an ON action voltage) that causes both the high-side switch 11 and the low-side switch 12 to perform the ON action. As a result, during this period, both switches perform the ON action at the same time.

[0021] Figure 11 A graph showing the state of the ON / OFF action of the high-side switch 11 and the low-side switch 12 when the control signal is changed. Figure 11 In the graph, the horizontal axis shows the passage of time, and the vertical axis shows the signals.

[0022] For example, if the threshold voltage for the ON / OFF switching of the high-side switch 11 is set to VHg and the threshold voltage for the low-side switch 12 is set to VLg, during the period in which the output voltage of the control circuit changes from VLg to (Vdc - VHg), both switches become in the ON action state. That is, Figure 11 As shown in the period from time t1 to t2, both the high-side switch 11 and the low-side switch 12 become in the ON action state, and thus a through current is generated from Vdc to Vee.

[0023] Method using a level shift circuit

[0024] One method to prevent this through-current is to use a level shifting circuit. An example of a circuit using a level shifting circuit is shown below. Figure 12A A level shifting circuit is a circuit that shifts the DC level of the signal from the high-side switch 11 in the direction of voltage increase by a certain value. By using this level shifting circuit, the voltage can be eliminated. Figure 11 The period during which both switches simultaneously turn on, as shown in the diagram.

[0025] Figure 12A In, with Figure 10 Compared to the previous diagram, the aspect with the level shifting circuit 20 is different. That is, Figure 12A If the switching circuit 10a is related to Figure 10 Compared to the switching circuit 10, the level shifting circuit 20 is different. Furthermore, Figure 12A The diagram shows a control circuit 21 that applies control signals to the input terminal 13.

[0026] Figure 12B The diagram shows a timeline depicting the level shifting process performed by the level shifting circuit 20. Figure 12B In the time graph, the horizontal axis represents the passage of time, and the vertical axis shows the status of the output signal of the level shifting circuit 20 applied to the high-side switch 11 and the status of the output signal (control signal) of the control circuit 21 applied to the low-side switch 12.

[0027] like Figure 12B As shown, in this example, the output signal (control signal) of control circuit 21 is a 10Vp-p signal that swings between GND level and 10V. In contrast, the output signal of level shifting circuit 21 is shifted by a shift voltage, resulting in a 10Vp-p signal that swings between the positive side voltage (Vdc) and Vdc-10V. This level shifting results in the high-side switch 11 entering the OFF operation earlier, and conversely, entering the ON operation later.

[0028] The result is, as Figure 12B As shown, after the high-side switch 11 is in the OFF state, a predetermined dead time is elapsed before the low-side switch 12 enters the ON state. Conversely, after the low-side switch 12 is in the OFF state, a predetermined dead time is elapsed before the high-side switch 11 enters the ON state.

[0029] so, Figure 12A and Figure 12BIn the example shown, by using a level shifting circuit, the timing of the ON / OFF operation of the high-side switch 11 is staggered, thus allowing for a dead time when both switches are in the OFF state. Therefore, through-current can be prevented.

[0030] Method using dead time

[0031] Furthermore, as another method to prevent through-current, there is a method of pre-setting a dead time for the control signal itself. An illustration of the method for creating the dead time is shown in [illustration missing]. Figure 13A , Figure 13B .

[0032] Figure 13A The circuit diagram illustrates the use of the described method. Figure 10 The switching circuit 10 is different. Figure 13A The switch circuit 10b shown includes two types of input terminals. That is, as shown... Figure 13A As shown, the switching circuit 10b includes two types of input terminals: an input terminal 13a for supplying control signals to the internal high-side switch 11 and an input terminal 13b for supplying control signals to the low-side switch 12.

[0033] In addition, the control circuit 21a outputs two control signals: an ON / OFF signal for the high-side switch 11 (control signal IN1 for the high-side switch) and an ON / OFF signal for the low-side switch 12 (control signal IN2 for the low-side switch). These two control signals are supplied to each switch to drive the two switches.

[0034] Furthermore, by pre-setting a dead time between the high-side switch control signal IN1 and the low-side switch control signal IN2, the period for each switch to perform an ON operation is set to be slightly shorter than the period for performing an OFF operation. As a result, the period during which both switches simultaneously perform ON operations can be eliminated. A timing diagram illustrating this timing will be provided below. Figure 13B .

[0035] Figure 13B The diagram shows the status of each signal when the control circuit 21 outputs two control signals with dead time. Figure 13B In the time graph, the horizontal axis represents the passage of time, and the vertical axis shows the control signal IN1 for the high-side switch and the control signal IN2 for the low-side switch.

[0036] like Figure 13BAs shown, in this example, after the control circuit 21a changes the control signal IN1 of the high-side switch to a value that causes the high-side switch 11 to open (OFF), after a predetermined dead time, it changes the control signal IN2 of the low-side switch to a value that causes the low-side switch 12 to open (ON).

[0037] Furthermore, after the control circuit 21a changes the control signal IN2 of the low-side switch to a value that causes the low-side switch 12 to open (OFF), it then changes the control signal IN1 of the high-side switch to a value that causes the high-side switch 11 to open (ON) after a predetermined dead time.

[0038] In this manner, the high-side switch 11 and the low-side switch 12 alternately turn on (ON) with a specified dead time interval, the control circuit 21a controls and outputs the control signal IN1 for the high-side switch and the control signal IN2 for the low-side switch.

[0039] As a result, through current flowing between the high-side switch 11 and the low-side switch 12 can be prevented.

[0040] Each of these methods can prevent through current, but cannot avoid circuit complexity or increased circuit cost. This invention addresses this problem by providing a gate drive circuit that uses simpler circuitry, suppresses cost increases, and includes a faster switching circuit.

[0041] Technical means to solve the problem

[0042] (1) To solve the aforementioned problem, the present invention provides a gate driving circuit that drives a semiconductor switch based on a control signal, comprising: an input terminal for inputting the control signal; a high-side switch connected to a positive power supply; a low-side switch connected to a negative power supply; a first differentiating circuit connected to the input terminal and the positive power supply, differentiating the control signal and supplying it to the high-side switch; a second differentiating circuit connected to the input terminal and the negative power supply, differentiating the control signal and supplying it to the low-side switch; an output terminal for outputting a signal that drives the semiconductor switch; a first impedance circuit connected between the high-side switch and the output terminal, having an impedance of 0Ω or higher; and a second impedance circuit connected between the low-side switch and the output terminal, having an impedance of 0Ω or higher.

[0043] (2) Moreover, the present invention is the gate drive circuit described in (1), wherein the high-side switch includes a pnp transistor, the low-side switch includes an npn transistor, the first differentiating circuit supplies the differentiated control signal to the base of the pnp transistor, the second differentiating circuit supplies the differentiated control signal to the base of the npn transistor, the first impedance circuit is connected between the collector terminal of the pnp transistor and the output terminal, and the second impedance circuit is connected between the collector terminal of the npn transistor and the output terminal.

[0044] (3) Moreover, the gate drive circuit described in (1) or (2) of the present invention includes: a Zener diode connected between the collector terminal of the pnp transistor or the collector terminal of the npn transistor and the output terminal.

[0045] (4) Moreover, the present invention is a gate drive circuit described in any one of (1) to (3), and includes: a semiconductor switch connected between the input terminal of the high-side switch and the positive power supply, wherein the semiconductor switch is turned on by a predetermined inhibit signal to connect the input terminal of the high-side switch to the positive power supply, and is able to inhibit the output of high voltage to the output terminal independently of the control signal.

[0046] (5) Moreover, the present invention is a gate driving circuit that drives multiple semiconductor switches in parallel based on a control signal, comprising: an input terminal for inputting the control signal; a high-side switch connected to a positive power supply; a low-side switch connected to a negative power supply; a first differentiating circuit connected to the input terminal and the positive power supply, differentiating the control signal and supplying it to the high-side switch; a second differentiating circuit connected to the input terminal and the negative power supply, differentiating the control signal and supplying it to the low-side switch; an output terminal for outputting a signal that drives the semiconductor switches; a first impedance circuit connected between the high-side switch and the output terminal, having an impedance of 0Ω or higher; and a second impedance circuit connected between the low-side switch and the output terminal, having an impedance of 0Ω or higher.

[0047] The effects of the invention

[0048] According to the present invention, a switching circuit that prevents through-current is implemented using a simpler structure. Therefore, a gate drive circuit that uses the aforementioned switching circuit to prevent through-current and has a simpler structure can be provided. Attached Figure Description

[0049] Figure 1 This is a circuit diagram of the switching circuit using the differentiating circuit in Embodiment 1.

[0050] Figure 2 An explanatory diagram illustrating an example of the differentiating circuit in Embodiment 1.

[0051] Figure 3A To be Figure 1 The differentiating circuit is set as a specific circuit example circuit diagram.

[0052] Figure 3B This is a time diagram showing the status of the signal in the switching circuit using the differentiating circuit in Embodiment 1.

[0053] Figure 4 The graph is obtained by calculating the input voltage of the high-side switch using equation (1).

[0054] Figure 5 This is a circuit diagram of a switching circuit using bipolar transistors to construct both high-side and low-side switches.

[0055] Figure 6 This is a circuit diagram of a switching circuit that uses a Zener diode.

[0056] Figure 7 This is a circuit diagram of a switching circuit with a P-channel MOSFET between the input terminal of the high-side switch and Vdc.

[0057] Figure 8 This is a circuit diagram of a specific gate drive circuit that uses a switching circuit.

[0058] Figure 9 This is a circuit diagram of a specific gate drive circuit that uses a switching circuit.

[0059] Figure 10 This is a conventional circuit diagram that includes a switching circuit.

[0060] Figure 11 A graph showing changes in the control signal.

[0061] Figure 12A This is a circuit diagram of a switch circuit that previously used a level shifter.

[0062] Figure 12B This is a timeline showing the state of level shifting performed by a level shifting circuit in the past.

[0063] Figure 13A This is a switch circuit diagram for a control signal with a dead time, as previously used.

[0064] Figure 13B A time diagram showing the operation of a switching circuit that previously used a control signal with a dead time.

[0065] [Explanation of Symbols]

[0066] 10, 10a, 10b, 110, 110a, 110b, 110c, 110d, 110e: Switching circuits

[0067] 11, 111, 111a: High-side switch

[0068] 12, 112, 112a: Low-side switch

[0069] 13, 113: Input terminals

[0070] 14, 114, 114b: Output terminals

[0071] 15: IGBT

[0072] 16: P-AMP

[0073] 20: Shift circuit

[0074] 21, 131: Control circuit

[0075] 120, 121: Differentiating circuits

[0076] 140: P-channel MOSFET

[0077] 141: Disable signal input terminal

[0078] 142: Softoff-in terminal

[0079] 200, 200b: Gate drive circuit

[0080] C, C1, C2: Capacitors

[0081] D1: Zener diode

[0082] IN1: Control signal for high-side switch

[0083] IN2: Control signal for low-side switch

[0084] R, R1, R2, R10, R11, Ra, Rb, Rg: Resistors

[0085] Vdc: Positive power supply

[0086] Vee: Negative-side power supply

[0087] z1, z2: Impedance circuit Detailed Implementation

[0088] Hereinafter, suitable embodiments of the present invention will be described with reference to the accompanying drawings.

[0089] 1. Embodiment 1

[0090] This embodiment is a switching circuit for a gate drive circuit, which drives a power switch such as an IGBT or MOSFET. Figure 1 The diagram shows a gate drive circuit including a switching circuit 110. This gate drive circuit is a gate drive circuit that drives the gate of an IGBT 15. Here, the IGBT 15 corresponds to a suitable example of the semiconductor switch of the claim. Moreover, the gate drive circuit, with the switching circuit 110 as its main structure, may include other circuits. For example, it may also include a P-AMP 16 (see Figure 110). Figure 1 However, depending on the application, it may not be included. The switching circuit 110 of this embodiment 1 is characterized by connecting differentiating circuits 120 and 121 to the input terminals of the high-side switch 111 and the low-side switch 112. These differentiating circuits 120 and 121 produce the same effect as described below: during the rising period of the input signal (control signal), the level shifting circuit is inserted on the input side of the high-side switch 111 (shifting the voltage in the positive direction). Furthermore, it produces the same effect as described below: during the falling period of the input signal, a level shifting circuit is inserted on the input side of the low-side switch 112 (shifting the voltage in the negative direction).

[0091] Here, differentiating circuits 120 and 121 are set as Figure 2 The circuit networks shown in differential circuits 1 to 3, or circuit networks formed by connecting these circuit networks in parallel. Figure 2 Differential circuit 1 is a circuit consisting only of capacitor C. Figure 2 Differential circuit 2 is a parallel circuit of capacitor C and resistor R. Furthermore, Figure 2 Differential circuit 3 is a direct circuit of resistor Ra and capacitor C, and a parallel circuit of resistor Rb.

[0092] Here, if a parallel circuit of, for example, capacitor C and resistor R is used ( Figure 2 Differential circuit 2) is used as differentiating circuit 120, 121, then the Figure 1 Can Figure 3A That's how it's expressed.

[0093] also, Figure 1 The impedances Z1 and Z2 in Figure 3A The text is omitted. Furthermore, the differentiating circuit 120... Figure 3A It includes a parallel circuit of capacitor C1 and resistor R1, but shows resistor Rg as the input resistance of high-side switch 111. Furthermore, the differentiating circuit 121... Figure 3A It includes a parallel circuit of capacitor C2 and resistor R2, but resistor Rg is shown as the input resistance of low-side switch 112. Furthermore, Figure 3AThe control circuit 131 that outputs control signals is also shown. The control circuit 131 supplies control signals to the input terminal 113.

[0094] Figure 3A The gate drive circuit in the circuit uses the switching circuit 110 as the main structure, but it may or may not include P-AMP16.

[0095] Differentiating circuit 120 corresponds to a suitable example of the first differentiating circuit of claim 1. Differentiating circuit 121 corresponds to a suitable example of the second differentiating circuit of claim 2. This will be discussed later. Figure 3A , Figure 5 , Figure 6 The same applies to the middle.

[0096] Figure 3A In this case, consider the scenario where the control signal rises from the Vee potential to the Vdc potential. Let the absolute value of the slope of the voltage rise of the control signal at this time be k (V / sec).

[0097] Furthermore, the moment when the control signal begins to move from the Vee potential toward the Vdc potential is set to t = 0. If limited to the period when the control signal is in the rising process, the input terminal voltage vhg of the high-side switch 111 and the input terminal voltage vlg of the low-side switch 112 are represented by the following equations (1) and (2), respectively.

[0098] According to equation (1), the input terminal voltage of the high-side switch 111 at t = 0 becomes the value of the first term of equation (1). It can be seen that even if the control signal voltage rises from Vee, the starting point of the input voltage of the high-side switch 111 also begins from the voltage shown in the first term of equation (1). That is, by setting the differentiating circuit 120, the same effect as having a voltage shifting circuit can be achieved, preventing both the high-side switch 111 and the low-side switch 112 from being in an ON state.

[0099] The reason is that the differentiating circuit 120 is connected to the positive power supply Vdc. The control signal is differentiated with reference to the positive power supply Vdc, thus starting from the voltage shown in the first term of equation (1).

[0100] On the other hand, Equation (2) for the input terminal voltage of the low-side switch 112 does not contain such a term, and there is no initial voltage generated when the voltage of the control signal rises from Vee.

[0101] The reason is that the differentiating circuit 121 is connected to the negative power supply Vee. The control signal is differentiated for the negative power supply Vee, thus not generating the voltage shown in the first term of equation (1).

[0102] In this way, the same effect as when a voltage shifting circuit is inserted only for the high-side switch 111 can be obtained. That is, the same effect as when a voltage shifting circuit is inserted for the high-side switch 111 can be obtained. Figure 12A and Figure 12B The circuit shown has the same effect.

[0103] [Number 1]

[0104]

[0105] [Number 2]

[0106]

[0107] in,

[0108] [Number 3]

[0109]

[0110] Here, as an example, let the time constant τ1 = 200nsec. Figure 3A R1 = 27kΩ, Rg = 2.2kΩ, C1 = 100pF, Vdc = 15V, and Vee = -10V, with the control signal voltage rise rate set to k = 3V / nsec. If these values ​​are used to calculate the input voltage of the high-side switch 111 using equation (1), then the following can be plotted: Figure 4 The chart. Figure 4 In the graph, the horizontal axis represents time, and the vertical axis represents the drive voltage of the high-side switch 111. As described... Figure 4 The chart shows that the first term of equation (1) is... Figure 4 The voltage of the control signal of the high-side switch 111 is increased, as if there were a voltage shift circuit, represented by "shift voltage (first item)".

[0111] Next, consider the opposite scenario, namely... Figure 3A The control signal moves from Vdc toward Vee.

[0112] Figure 3A In this study, the case where the control signal moves from Vdc towards Vee is investigated. The instant when the control signal begins to move from Vdc towards Vee is set to t=0, and the study is limited to the period during which the control signal decreases. Therefore, the voltages at the input terminals of the high-side switch 111 and the low-side switch 112 are expressed by the following equations (4) and (5).

[0113] [Number 4]

[0114]

[0115] [Number 5]

[0116]

[0117] At this time, a voltage equivalent to voltage shift is generated for the input voltage of the low-side switch 112, but no voltage shift is generated for the input voltage of the high-side switch 111.

[0118] Furthermore, a time graph showing how the control signal obtained from the differentiating circuit changes is plotted on... Figure 3B . Figure 3B In the diagram, the horizontal axis represents time, and the vertical axis sequentially shows the signals at the input terminals of the high-side switch 111 and the low-side switch 112. That is, it depicts how the control signal changes due to the differentiating circuit.

[0119] Figure 3B In this process, the control signal rises from Vee to Vdc with a specified rise time (tr), and falls from Vdc back to Vee with a specified fall time (tf) (refer to...). Figure 3B Here, tr = Vdc / k and tf = Vdc / k.

[0120] Figure 3B The lower segment represents the signal at the input terminal of the low-side switch 112. Because it passes through a differentiating circuit, when compared with the control signal in the upper segment, it exhibits overshoot during the signal rise and undershoot during the signal fall. The portion of the signal value exceeding Vsh (threshold) constitutes the period during which the low-side switch 112 is turned on.

[0121] and, Figure 3B The signal at the input terminal of the high-side switch 111, in the middle section, exhibits overshoot during the signal rise and undershoot during the signal fall, similar to the low-side switch 112, due to the passing through a differentiating circuit. The portion of this signal from Vdc to Vsh (threshold) constitutes the period of the high-side switch 111's OFF operation. The portion from Vsh (threshold) to GND constitutes the period of the high-side switch 111's ON operation. These conditions are shown in... Figure 3B .

[0122] also, Figure 3BThe signal at the input terminal of the high-side switch 111 in the middle section is increased by the shift voltage shown in the first term of Equation (1). Due to the shift voltage, the waveform of the signal at the input terminal of the high-side switch 111 is lower than Vsh when it falls, and the timing of the high-side switch 111 switching to ON is delayed. Moreover, due to the shift voltage (first term of Equation (1), the waveform of the signal at the input terminal of the high-side switch 111 exceeds Vsh earlier when it rises, and the timing of the high-side switch 111 switching to OFF is advanced. As a result, a dead time can be formed between the signal appearing at the input terminal of the low-side switch 112 and the signal at the input terminal of the high-side switch 111, preventing the high-side switch 111 and the low-side switch 112 from switching to ON simultaneously.

[0123] Furthermore, the output signal of the high-side switch 111 is connected to the output terminal 114 via impedance z1 (see reference). Figure 1 Furthermore, the output signal of the low-side switch 112 is connected to the output terminal 114 via impedance z2 (see reference). Figure 1 Impedance circuits z1 and z2 can use specified resistance values, or they can be without resistance values. That is, either or both of impedance circuits z1 and z2 can be 0Ω (i.e., directly connected). However, in order to achieve output stabilization and smooth switching between the high-side switch 111 and the low-side switch 112, it is preferable to pre-insert an impedance circuit with a small value.

[0124] Impedance circuit z1 corresponds to a suitable example of the first impedance circuit of claim 2. Furthermore, impedance circuit z2 corresponds to a suitable example of the second impedance circuit of claim 3.

[0125] As explained above, according to Figure 3A and Figure 3B ( Figure 1 The circuit structure prevents the high-side switch 111 and the low-side switch 112 from being simultaneously ON when the control signal swings between Vee and Vdc, in both cases when the control signal rises (from Vee to Vdc) and falls (from Vdc to Vee).

[0126] 2. Embodiment 2 - example using bipolar transistor

[0127] Figure 5 The diagram below shows a circuit block diagram of a gate drive circuit, which includes a switching circuit 110 in which the high-side switch 111a uses a pnp transistor and the low-side switch 112a uses an npn transistor. Figure 5In this circuit, the gate drive circuit also uses the switching circuit 110 as the main structure, but it may also include other structures. For example, the gate drive circuit may include P-AMP16, or it may not.

[0128] In the case of using so-called bipolar transistors, the same principle applies as explained above. Figure 1 to Figure 3B The circuit shown achieves roughly the same effect. Moreover, for each switch of the high-side switch 111a, transistors are used instead of MOSFETs, which provides various advantages.

[0129] The following formulas relate to the case in Embodiment 2 where transistors are used in the high-side switch 111a and the low-side switch 112a. The base-emitter voltage when each transistor is turned on is set to VBE. When the transistor transitions from an off state to an on state, the base voltage up to just before it turns on is calculated. After the transistor turns on, the base-emitter voltage is limited to approximately 0.7V. Furthermore, when the transistor transitions from an on state to an off state, it is assumed that from the moment the control signal begins to change, the base-emitter impedance is high relative to the resistance value of resistor Rg.

[0130] Regarding the input signals of each switch when the control signal rises from Vee to Vdc, the formula representing the input signal of the high-side switch 111a is Equation (6), and the formula representing the input signal of the low-side switch 112a is Equation (7).

[0131] However, in the case of equation (7), if the base-emitter junction is conducting, the base-emitter voltage is clamped at approximately 0.7V.

[0132] [Number 6]

[0133]

[0134] [Number 7]

[0135]

[0136] The formulas for the control signal decreasing from Vdc to Vee are shown in equations (8) and (9) below. However, in the case of equation (8), if the base-emitter junction of the transistor is turned on, the base-emitter voltage is clamped at approximately 0.7V.

[0137] [Number 8]

[0138]

[0139] [Number 9]

[0140]

[0141] Here, when a MOSFET is used instead of a bipolar transistor for the high-side switch 111 or the low-side switch 112, a threshold voltage of the MOSFET's gate needs to be applied between the gate and source when transitioning from the OFF state to the ON state. By applying a voltage above the threshold between the gate and source, the MOSFET is turned ON and current flows. The current that can flow between the drain and source is almost independent of the gate-source voltage; if the gate-source voltage exceeds the threshold, current can flow.

[0142] On the other hand, if the transistor voltage exceeds approximately 0.6V, which serves as the base-emitter voltage, both base and collector currents flow, but the current is limited to hFE times the base current. Therefore, if the base current Ib is limited, even if the pnp transistor of the high-side switch 111a and the npn transistor of the low-side switch 112a are simultaneously turned on and become conductive, the flowing current (collector current) is limited to IC = hFE × Ib. If this is for a very short time, damage can sometimes be avoided. In contrast, when using MOSFETs to construct the high-side switch 111 and the low-side switch 112, the drain current is limited only by the on-resistance, which may result in a large current, making it impossible to allow the high-side switch 111 and the low-side switch 112 to be turned on simultaneously.

[0143] Furthermore, in the case of a MOSFET, the gate-source voltage has a maximum rating, and a voltage exceeding this maximum rating cannot be applied. Therefore, depending on the magnitude of the control signal voltage, a Zener diode for protection is sometimes required. In contrast, in the case of a transistor, the base-emitter voltage becomes approximately 0.6V when the transistor is ON, thus eliminating the need for such a Zener diode for protection.

[0144] Thus, the aspects that need to be considered are different when bipolar transistors are used for the high-side switch 111 and the low-side switch 112 versus when MOSFETs are used.

[0145] 3. Embodiment 3 - example using zener diode

[0146] Figure 6 This is a block diagram showing the case where a Zener diode D1 is inserted into the output circuit of the switching circuit 110a. In the gate drive circuit for driving power switches (such as IGBT 15), the switching circuit described in this embodiment and the output of the gate drive circuit using this switching circuit are designed to be diverse. Figure 6 The gate drive circuit in the circuit uses the switching circuit 110a as its main structure, but it may also include other structures. For example, the gate drive circuit may or may not include P-AMP16.

[0147] For example, the output sometimes requires a swing from Vdc to Vee, and sometimes a voltage range must be defined, such as Vdc to GND. In such cases, such as Figure 6 As shown, the swing of the output voltage can be adjusted by inserting a diode D1 between the transistor constituting the high-side switch 111a or the low-side switch 112a and the output terminal 114.

[0148] For example, to obtain an output in the range of Vdc to GND, simply make the Zener voltage of D1 equal to Vee, assuming that the output is taken from the collector of the pnp transistor constituting the high-side switch 111. Figure 5 That kind of connection will suffice.

[0149] Conversely, when an output that swings between Vee and GND is desired, the output can be obtained from the collector of the npn transistor that constitutes the low-side switch 112.

[0150] Especially this embodiment Figure 6 The Zener diode D1 used in the circuit shown can charge the equivalent capacitor connected in parallel with Zener diode D1 to the voltage of Zener diode D1 during the period when the low-side switch 112a is turned on. Therefore, even at the instant when the switch reverses and the high-side switch is turned on and the low-side switch 112a is turned off, the charge accumulated in the equivalent capacitor is maintained. As a result, according to this embodiment, there are also advantages such as: it is not necessary to charge the equivalent capacitor connected in parallel with Zener diode D1 at the instant of switching between the high-side and low-side switches, and a stable output voltage can be output instantaneously.

[0151] 4. Embodiment 4

[0152] Figure 7 This is a circuit block diagram of the gate drive circuit when a P-channel MOSFET 140 (hereinafter referred to as Q1) is inserted between the input terminal of the high-side switch 111 and Vdc. The source terminal of Q1 is connected to Vdc, and the drain terminal is connected to the input terminal of the high-side switch 111. Figure 7 The gate drive circuit in the circuit uses the switching circuit 110b as its main structure, but may also include other structures. For example, the gate drive circuit may include a snubber or inverter circuit using MOSFETs or the like connected between the output terminal 114 and the IGBT 15 that is being driven, or it may not include such a circuit.

[0153] The gate drive circuit includes a switching circuit 110b, which includes an inhibit signal input terminal 141 for inputting an inhibit signal IN2. The inhibit signal input terminal 141 is connected to the gate terminal of Q1 via a voltage divider circuit consisting of resistors R10 and R11.

[0154] When the inhibit signal IN2 is high, if a low signal is input to the control signal IN1, the output terminal 114 will output a high signal accordingly. If a high signal is input to the control signal IN1, the output terminal 114 will output a low signal accordingly.

[0155] On the other hand, when the disable signal IN2 is low, the output terminal 114 becomes low regardless of the value of the control signal IN1. Depending on the driving state of the IGBT 15 being driven, sometimes even if the control signal IN1 performs normal operation, the output terminal 114 must be forced to remain low. Therefore, in this case, Q1 is set to allow the input of a disable signal.

[0156] In addition, in this case, it is also thought to use an external circuit to force the output terminal 114 to low. However, since the output resistance of the output terminal 114 is low, forcing it to low will cause a large current to flow, and the high-side switch 111 of this circuit will become an overload state and malfunction.

[0157] Furthermore, it is also conceivable to insert, for example, a specified logic circuit into input terminal 113 to force the control signal itself to remain high. However, it can be argued that the unnecessary generation of the logic circuit, or the time delay of this logic circuit, does not yield preferred results.

[0158] Typically, this type of prohibited action is performed under abnormal conditions such as the IGBT15's state, and the delay time needs to be minimized. Therefore, actions that do not produce the aforementioned delay are... Figure 7 The circuit shown can be easily constructed to accept inhibit signals. Furthermore, according to... Figure 7 The circuit shown can be more easily configured to accept prohibition signals.

[0159] 5. Specific embodiments of the invention 5.1 Specific embodiment 1

[0161] An example of the circuit diagram of a specific gate drive circuit 200 is shown below. Figure 8 . Figure 8 The gate drive circuit shown includes a switching circuit 110c as its main structure; other circuits are not shown. However, as explained so far... Figure 1 , Figure 3A and Figure 5Thus, for example, a P-AMP could be included. A control signal is input to input terminal 113. The control signal oscillates between +15V of the positive power supply and -10V of the negative power supply. Moreover, the control signal is a rectangular wave with a frequency of approximately 10kHz.

[0162] Input terminal 113 and Figure 3A Similarly, two differentiating circuits 120 and 121 are connected. The output signal of differentiating circuit 120 is supplied to the base terminal of high-side switch 111 (e.g., a pnp transistor) (hereinafter referred to as Q1). The output signal of differentiating circuit 121 is supplied to the base terminal of low-side switch 112 (e.g., an npn transistor) (hereinafter referred to as Q2) (see reference). Figure 8 ).

[0163] Between the collector terminals of Q1 and Q2, a series circuit consisting of a Zener diode D1 and a resistor R5 is connected, and the output signal of the switching circuit 110c is output from both ends of this series circuit. These two output signals are output from the output terminal 114b via an inverter containing a P-channel MOSFET (referred to as Q3) and an N-channel MOSFET (referred to as Q4). Therefore, the output terminal 114b is essentially the output terminal of the switching circuit 110c. The output terminal 114b is connected to the gate terminal of the IGBT 15, which is being driven.

[0164] Furthermore, when the control signal changes from -10V to +15V, the voltage at the base terminal of Q1 produces a voltage equivalent to the voltage of the shift circuit, as shown in the first term of equation (1), and then rises proportionally to the increase in the control signal voltage to +15V. At this time, the voltage calculated by equation (1) appears at the base terminal of Q1. Thus, in the very early stage of the control voltage changing from -10V to +15V, the state changes from ON to OFF.

[0165] On the other hand, Q2 changes from an OFF state to an ON state as the control signal changes from -10V to +15V. When the control signal changes from +15V to -10V, the voltage at the base terminal of Q2, due to the action of the differentiating circuit 121 containing C2 and R2, generates a voltage equivalent to that of the shift circuit. Because of this generated voltage, in the very early stages of the control signal drop, the potential at the base terminal decreases, and Q2 performs an OFF operation.

[0166] Next, Q1 changes from an OFF state to an ON state due to the control signal voltage changing from +15V to -10V. When the control signal voltage is -10V, Figure 8Transistor Q4 is turned on, and transistor Q3 is turned off. Therefore, the output voltage at terminal 114b of the gate drive circuit 200 becomes low, and the gate drive circuit 200 draws charge from the gate-source of the IGBT 15 via R9 and Q4. As a result, the IGBT is turned off. The gate terminal of the IGBT 15 becomes approximately -10V, maintaining the off state. The gate-source voltage of Q3 can be ensured by the Zener diode D1, allowing for appropriate voltage application.

[0167] If the control voltage becomes +15V, Q3 will be ON and Q4 will be OFF. At this time, the gate drive circuit 200 flows current between the gate and source of IGBT 15 via R8 and Q3. The output voltage at output terminal 114b becomes high, setting the gate voltage of IGBT 15 to approximately +15V. As a result, IGBT 15 is ON. The gate voltage remains at +15V, maintaining the ON state. Similarly, regarding the gate-source voltage of Q4, the withstand voltage can be ensured by the Zener diode D1, and a voltage can be appropriately applied to the gate terminal of Q4. Thus, Figure 8 The gate drive circuit 200 shown can drive the IGBT15, which switches high power. The polarity of the control signal and the output signal are also matched, thus allowing for very efficient circuit configuration. 5.2 Specific embodiment 2

[0169] The circuit diagram of specific implementation method 2 is shown in Figure 9 . Figure 9 The gate drive circuit 200b is shown in the figure. Figure 9 In the circuit, the gate drive circuit 200b includes a switching circuit 110d comprising R1 to R7, C1, C2, D1, Q1, Q2, etc. This switching circuit 110d is the... Figure 5 A suitable example of a switching circuit with the structure shown in (and claim 3 of claim).

[0170] and, Figure 9 In the circuit 110e, which includes R11~R15, R20, C11, C12, C20, D11, Q11, Q12, etc., the switching circuit is as follows: Figure 6 (and claim 4) is a suitable example of the switching circuit with the structure shown. Furthermore, Q3, Q4, Q14, R6-R9, R16-R19 are equivalent to Figure 1 This is a suitable example of the internal circuit structure of the P-AMP (Power Amplifier) ​​16.

[0171] For input terminal 113, a control signal of approximately 10kHz rectangular wave is input for normal operation, and Softoff-in terminal 142 is in a high state during normal operation. In this state, when input terminal 113 is high, Q3 is turned on, and output terminal 114 outputs high. Moreover, when input terminal 113 is low, both Q4 and Q14 are turned on, and the output terminal is low due to being connected to a potential of -10V via R9 and R19. At this time, the gate charge of IGBT 15 is discharged due to the parallel resistance value of R9 and R19.

[0172] The discharge time constant becomes:

[0173] [Number 10]

[0174]

[0175] The time it takes for IGBT15 to transition from an ON (on) state to an OFF (off) state is affected by the aforementioned time constant. A larger τ results in a longer transition time, and a shorter τ results in a shorter transition time.

[0176] also, Figure 9 The example shown illustrates an example of R9 and R19 connected in parallel relative to the gate terminal of IGBT15, through which the time constant is calculated as in equation (10), but the two resistors can also be connected in series.

[0177] For example, Figure 9 Alternatively, the connection target of the R9 terminal, which is connected to the gate terminal of IGBT15, can be changed from the gate terminal of IGBT15 to the connection point of the drain terminal of R19 and Q14.

[0178] By configuring the circuit in this way, the time constant for the normal operation (of IGBT15) of the OFF state becomes the time constant based on R19. Furthermore, the time constant for receiving an inhibit signal can be set to the time constant based on R9. However, the resistance value of R9 is assumed to be sufficiently greater than the resistance value of R19.

[0179] The transition time of the IGBT15 from the ON (on) to the OFF (off) state needs to be appropriately selected. If the transition time is too long, the switching loss increases; if it is too short, the switching loss decreases, but a voltage surge due to parasitic inductance is generated. Furthermore, this voltage surge increases proportionally to the collector current. Therefore, by adjusting the transition time relative to the collector current, the optimal switching loss can be selected. Moreover, if the OFF operation is performed with the normal transition time during a short circuit, a surge voltage exceeding the collector-emitter withstand voltage of the IGBT15 is applied, leading to damage to the IGBT15.

[0180] This embodiment keeps Q11 in an OFF state by setting the Softoff-in terminal 142 low during a short circuit. In this state, the time constant for acquiring the gate charge of IGBT 15 can be expressed as τ = Cge × R9. As a result, the time constant τ increases, and the transition time of IGBT 15 from the ON to the OFF state also increases, reducing voltage surges. Consequently, damage to IGBT 15 can be avoided.

[0181] 6. Effects and other

[0182] As explained above, the switching circuit according to this embodiment and the gate drive circuit using this switching circuit achieve the following effects.

[0183] A differentiating circuit is provided at the input of the switching circuit, and the control signal passing through the differentiating circuit is supplied to the switching circuit (high-side switch, low-side switch). As a result, the same effect as voltage shifting of the control signal can be achieved. Therefore, a switching circuit that prevents through-current can be provided with a simple structure. Furthermore, a gate drive circuit with a simple structure can be provided using the aforementioned switching circuit.

[0184] Furthermore, bipolar transistors (PNP type, NPN type) can be used instead of MOSFETs as switching circuits (high-side switch, low-side switch). In this case, the base-emitter voltage is clamped to about 0.6V, so there is no need to set up a protection Zener diode as required by MOSFETs, thus allowing for a simpler structure.

[0185] Furthermore, regarding the switching circuit, although the same effect as voltage shifting the control signal can be achieved, the time until the gate voltage of the semiconductor switch is switched can be shortened by using a differentiating circuit. Therefore, if the switching circuit is applied to the parallel driving of multiple semiconductor switches, the deviation in the ON / OFF timing of the multiple semiconductor switches can be suppressed small and effectively.

[0186] Furthermore, a Zener diode or similar device can be used between the switching circuit (high-side switch, low-side switch) and the output terminal, allowing adjustments such as narrowing the output voltage range to be made solely using the voltage across the Zener diode. This also allows for adjustment of the output voltage swing range.

[0187] Furthermore, depending on the driving state of the IGBT or similar device being driven, the gate drive circuit may sometimes be forcibly stopped. If a switch is provided that connects the high-side input terminal to Vdc based on an inhibit signal, the gate drive circuit can be easily forcibly stopped using a simple structure. An example of a P-channel MOSFET has been described above as the switch used for connection, but any switch that operates via an inhibit signal can be used.

[0188] Furthermore, in this embodiment, the time constant for extracting charge from the IGBT, which is being driven, can be extended. As a result, surge voltage caused by parasitic inductance can be reduced, thus preventing IGBT damage.

[0189] Furthermore, if the time constant is too long, the switching loss increases; if it is too short, a voltage surge occurs as described above. The voltage surge increases proportionally to the collector current, therefore, by adjusting the time constant in relation to the collector current, a switching loss that matches the collector current can be selected.

[0190] Furthermore, the embodiments described above are merely examples of means of implementing the present invention, and should be appropriately modified or changed according to the structure of the device to which the present invention is applicable or various conditions. The present invention is not limited to the form of this embodiment. For example, in the embodiments described, IGBTs were mainly used as the power semiconductor switch to be driven, but other power semiconductor switches may also be applied. Moreover, the various differentiating circuits described above are suitable examples, and other circuits including the same function may also be used.

[0191] Industrial availability

[0192] This invention relates to a gate drive circuit for driving power switches such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

Claims

1. A gate driving circuit that drives a semiconductor switch based on a control signal, characterized in that, include: The input terminal is used to input the control signal; The high-side switch is connected to the positive-side power supply; The low-side switch is connected to the negative-side power supply; The first differentiating circuit is connected to the input terminal and the positive power supply. The second differentiating circuit is connected to the input terminal and the negative power supply. The first differentiating circuit and the second differentiating circuit differentiate the control signal according to the positive power supply and the negative power supply, respectively, and form a dead time between the signal at the input terminal of the high-side switch and the signal at the input terminal of the low-side switch. The output terminal outputs a signal to drive the semiconductor switch; A first impedance circuit, connected between the high-side switch and the output terminal, has an impedance of 0 Ω or higher; as well as The second impedance circuit, connected between the low-side switch and the output terminal, has an impedance of 0 Ω or higher.

2. The gate driving circuit according to claim 1, characterized in that, The high-side switch includes a PNP transistor. The low-side switch includes an npn transistor. The first differentiating circuit supplies the differentiated control signal to the base of the PNP transistor. The second differentiating circuit supplies the differentiated control signal to the base of the npn transistor. The first impedance circuit is connected between the collector terminal and the output terminal of the PNP transistor. The second impedance circuit is connected between the collector terminal of the npn transistor and the output terminal.

3. The gate driving circuit according to claim 2, characterized in that, include: A Zener diode is connected between the collector terminal of the pnp transistor or the collector terminal of the npn transistor and the output terminal.

4. The gate driving circuit according to claim 1 or 2, characterized in that, include: A semiconductor switch is connected between the input terminal of the high-side switch and the positive-side power supply. The semiconductor switch is activated by a predetermined disable signal, connecting the input terminal of the high-side switch to the positive-side power supply. It can prevent the output of high voltage to the output terminal independently of the control signal.

5. A gate driving circuit that drives multiple semiconductor switches in parallel based on a control signal, characterized in that, include: The input terminal is used to input the control signal; The high-side switch is connected to the positive-side power supply; The low-side switch is connected to the negative-side power supply; The first differentiating circuit is connected to the input terminal and the positive power supply. The second differentiating circuit is connected to the input terminal and the negative power supply. The first differentiating circuit and the second differentiating circuit differentiate the control signal according to the positive power supply and the negative power supply, respectively, and form a dead time between the signal at the input terminal of the high-side switch and the signal at the input terminal of the low-side switch. The output terminal outputs a signal to drive the semiconductor switch; A first impedance circuit, connected between the high-side switch and the output terminal, has an impedance of 0 Ω or higher; as well as The second impedance circuit, connected between the low-side switch and the output terminal, has an impedance of 0 Ω or higher.

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