Conditioning circuits, photodetectors, photodetection arrays, and optical systems

Abstract

A regulating circuit, a photodetector, a photodetection array, and an optical system. The regulating circuit is adapted to cooperate with the photodetector, and the photodetector is adapted to receive laser pulses to generate a first pulse combination. The regulating circuit includes: a regulating unit adapted to receive the first pulse combination and, within a preset time, only sample the arrival time of the first first pulse in the first pulse combination; W pulse ≤ the preset time ≤ 5W pulse , where W pulse is the pulse width of the laser pulse.

Description

Technical Field

[0001] The present invention relates to the field of electricity, and in particular to a regulating circuit, a photodetector, a photodetection array and an optical system. Background Art

[0002] Time-of-Flight (ToF) is currently the mainstream laser ranging technology. Its principle is to use a laser to actively project a light beam, which is reflected from the target surface and then received by a detector. By calculating the round-trip flight time t, the distance from the target to the ranging device can be calculated based on the speed of light c: z = ct / 2. Among them, d-ToF (direct time-of-flight) is a commonly used ToF technology, which directly measures the time difference between the transmission and reception of the light pulse. Due to laser safety restrictions and power consumption limitations, the pulse energy emitted by the laser is limited, but it must cover the entire field of view. When the light pulse is reflected back to the detector, the energy density is reduced by more than a trillion times. At the same time, ambient light acts as noise, interfering with the detector's signal detection and reconstruction. In this case, the signal-to-noise ratio obtained by the detector is insufficient to directly restore the analog signal of the pulse, resulting in significant errors in direct time-of-flight measurements. Therefore, the d-ToF method requires extremely sensitive light detectors to detect weak light signals.

[0003] A single-photon avalanche diode (SPAD) is an avalanche photodiode operating in Geiger mode. When the reverse bias voltage across the SPAD exceeds its avalanche breakdown voltage, the internal electric field becomes extremely strong, the photogenerated carriers acquire significant kinetic energy, and impact ionization causes a continuous avalanche multiplication effect. Consequently, a single photon can drive the avalanche photodiode to saturation photocurrent. SPADs have extremely high gain and sensitivity, making them commonly used for single-photon detection and offer significant advantages in laser ranging.

[0004] The core technology for d-ToF ranging using SPAD is time-correlated single photon counting (TCSPC). Its basic idea is to treat photons as random events and perform statistics after repeatedly measuring photons for multiple cycles. When the light signal is very weak and the detection frequency is very high, no photons may be detected in some cycles, while one photon may be detected in other cycles. The detection time of the photon is mapped to a certain time period. After a large number of repeated measurements, the number of photons in each time period is counted to obtain a frequency distribution histogram of photons changing with time. The histogram is then fitted to obtain the intensity change of the light signal. The point where the light signal intensity is highest is taken as the pulse peak, and the time corresponding to this point is taken as the pulse return time. The ToF time is obtained by subtracting the emission time from the pulse return time.

[0005] However, existing SPADs are manufactured using a CMOS process, which exhibits significant deviations under varying temperatures and process angles, causing SPAD parameters to deviate from their set values. This is particularly true when a single SPAD is triggered twice by a single received laser pulse, outputting two avalanche signals. This significantly increases the computational complexity of the signal readout circuit and system power consumption. Furthermore, if a large number of SPADs are retriggered by the falling edge of the laser pulse, the photon frequency corresponding to the falling edge of the pulse may be high on the histogram, potentially resulting in a double peak during fitting and misjudging the peak position and distance. Summary of the Invention

[0006] The problem solved by the present invention is that the existing photoelectric detectors are prone to performance parameter deviations.

[0007] To solve the above problem, the present invention provides a regulating circuit suitable for cooperating with a photodetector. The photodetector is suitable for receiving laser pulses to generate a first pulse combination, including: a regulating unit, suitable for receiving the first pulse combination, and sampling only the arrival time of the first first pulse in the first pulse combination within a preset time, W pulse ≤ the preset time ≤ 5W pulse , where W pulse is the pulse width of the laser pulse.

[0008] The present invention further provides a data processing chip, comprising: the above-mentioned regulating circuit, wherein the regulating circuit is suitable for cooperating with one or more photodetectors.

[0009] The present invention further provides a photoelectric detector suitable for cooperating with the above-mentioned regulating circuit. The photoelectric detector comprises: a photoelectric conversion unit suitable for generating the first pulse combination in response to the one laser pulse.

[0010] The present invention also provides a photodetection array, comprising: multiple rows and multiple columns; wherein each row and each column is respectively provided with multiple photodetection units, and each photodetection unit includes at least one of the above-mentioned photodetectors; the adjustment circuit, the adjustment circuit couples one or more photodetectors in a photodetection unit.

[0011] The present invention also provides an optical system, comprising: a light emitting module, comprising: a light emitting array, comprising multiple rows and multiple columns; wherein each row and each column is respectively provided with multiple light emitting units, and each light emitting unit includes at least one light emitter; the light emitting array also includes a light emitting array driving circuit, coupled to each light emitter, for emitting a detection laser beam; a light detection module, comprising the above-mentioned photoelectric detection array, for receiving the detection echo.

[0012] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0013] When a photodetector is triggered multiple times in response to a received laser pulse, it generates multiple first pulses. If subsequent distance determination is performed based on these multiple first pulses, the computational effort of the subsequent signal readout circuit will increase, potentially leading to misjudgments of distance. The adjustment unit provided by the present invention, however, generates a corresponding second pulse based on these multiple first pulses for subsequent processing. This allows precise control of the minimum time interval of the output signal, avoids misjudgments of pulses during subsequent processing, reduces the computational effort and power consumption of the subsequent signal readout circuit, and improves the accuracy of distance determination. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a schematic diagram of a SPAD quenching and reset circuit;

[0015] Figure 2 This is a schematic diagram of the detection effect of different dead times.

[0016] Figure 3 This is a schematic diagram of a SPAD array chip;

[0017] Figure 4 is a schematic diagram of a regulating circuit according to an embodiment of the present invention;

[0018] Figure 5 1 is a schematic diagram of signal waveforms related to the present invention;

[0019] Figure 6 This is a structural block diagram of the coordination between the regulating circuit and the photodetector of the present invention; Figure 7 is a schematic diagram of a regulating circuit according to another embodiment of the present invention;

[0020] Figure 8 is a schematic diagram of a regulating circuit according to another embodiment of the present invention;

[0021] Figure 9 Schematic diagram of a current output analog-to-digital converter according to the present invention;

[0022] Figure 10 This is a schematic diagram of the connection between the photoelectric detection unit and the data processing chip of the present invention;

[0023] Figure 11 It is a schematic structural diagram of the optical system of the present invention. DETAILED DESCRIPTION

[0024] To find the cause of the intensity compensation or distance judgment errors, the inventors conducted further research on photodetectors:

[0025] When a photon enters a SPAD, it triggers an avalanche. To ensure proper operation, a dedicated circuit controls the SPAD's reverse bias voltage to below the avalanche breakdown voltage, quenching the avalanche. The SPAD is then reset, restoring its reverse bias voltage to its initial state, above the avalanche breakdown voltage, to detect subsequent photons. The period between avalanche quenching and reset is when the SPAD cannot sense other photons, a period known as dead time.

[0026] For example, Figure 1 As shown, the SPAD quenching and reset circuit can include a passive quenching circuit, a SPAD, and a resistor Rs. The passive quenching circuit is a quenching resistor RL. Before a photon arrives, the SPAD is reverse biased at Vp and is in a state to be detected. Once a photon reaches the SPAD, it excites photogenerated carriers, which are guided to the avalanche multiplication region under the action of the internal electric field, triggering an avalanche. The instantaneous increase in avalanche current causes a large voltage drop across the quenching resistor RL, reducing the voltage across the SPAD to below the breakdown voltage, and the avalanche is quenched. Afterwards, the voltage Vp charges the SPAD, causing the SPAD to return to the state to be detected and continue detecting the next photon.

[0027] In laser ranging applications, using a single SPAD device as a pixel will introduce significant noise interference, making it difficult to distinguish noise factors such as dark counts and ambient light from the effective signal, resulting in relatively poor application performance. Therefore, multiple SPAD devices are usually used as a pixel, that is, multiple SPADs are connected in parallel to a readout circuit to read distance information. By judging under certain conditions, noise can be filtered out and the effective signal can be obtained more accurately. At the same time, multiple pixels are arranged in a certain array to form a planar array SPAD detector, which can increase the detector's photosensitive surface and thus increase the detectable field of view.

[0028] Combine Figure 1 and Figure 2, a is a laser pulse received by a photodetector (e.g., the echo laser pulse received by the photodetector after the transmitted pulse is reflected by the target object). Its typical full width at half maximum is several nanometers. The time difference between the start time of the rising edge and the end time of the falling edge of the laser pulse is defined as the pulse width of the laser pulse. After the transmitted pulse is reflected by the target object, Figure 2 The echo laser pulse shown in a is injected into the SPAD photosensitive surface, triggering the SPAD avalanche, and the output terminal Vout is output Figure 2 The avalanche signal shown in b. The time difference between the echo pulse and the transmitted pulse is determined based on the SPAD trigger time as the time of flight (TOF). By measuring the time of flight, the distance to the target object can be calculated. After outputting the detection signal b, the SPAD cannot be triggered again due to the dead time effect. The SPAD can avalanche again after avalanche and recovery. Within a detection window, that is, the total time of multiple repeated measurements of a certain field of view, the number of SPAD avalanches in each time period of each measurement is counted, and the results of multiple repeated measurements are superimposed to obtain a histogram of the number of photons changing with time. By fitting the histogram, the echo pulse waveform can be obtained. Among them, the time at the peak is the arrival time of the echo signal.

[0029] The dead time of SPAD is determined by the quenching and reset circuits integrated on the SPAD detector array, and there are large deviations under different temperatures and processes. The area of ​​the array SPAD is large, and the circuit lengths between the SPAD units and circuit elements such as the voltage source at different positions vary greatly, resulting in uneven dead time of SPADs at different positions. In particular, if the dead time of the SPAD is less than the pulse width of the received laser pulse, and the reset is completed before the end of the laser pulse and the detection state is restored, then the SPAD may be triggered once by the rising edge of the laser pulse and then triggered again by the falling edge of the pulse, and the output terminal Vout output Figure 2 c shows two avalanche signals. That is, one laser pulse received by the detector causes the SPAD to be triggered twice, which can easily cause the photon frequency corresponding to the falling edge of the pulse in the histogram to be too high, and the echo signal will be misjudged as Figure 2 The double peaks shown in d cause errors in ToF judgment and distance calculation.

[0030] In addition, if the dead time is too small, when the ambient light is strong, the SPAD will be triggered at a very high frequency, and the noise signal will be too strong, increasing the system's computing power and power consumption, and may even exceed the system's response speed, resulting in data loss.

[0031] In the front-illuminated SPAD array, Figure 3On the chip surface shown (perpendicular to the page, inward, indicating the direction of light incidence), front-end circuitry such as quenching and reset circuits are located around the SPAD's photosensitive surface, thus occupying a significant portion of the chip area. To improve the fill factor (SPAD photosensitive surface area divided by total chip area) and ensure detection efficiency, limited space is available for circuit fabrication. Therefore, integrating circuitry for regulating or controlling dead time within the SPAD detector array is highly challenging.

[0032] Based on the above research, the inventors propose a regulating circuit that can be used in conjunction with a photodetector. The photodetector is adapted to receive laser pulses and generate a first pulse combination.

[0033] The regulating circuit includes: a regulating unit adapted to receive the first pulse combination, and to sample only the arrival time of the first first pulse in the first pulse combination within a preset time, pulse ≤ the preset time ≤ 5W pulse , where W pulse is the pulse width of the laser pulse.

[0034] Specifically, the regulating unit is adapted to output a second pulse corresponding to the arrival time of the first first pulse in the first pulse combination, and the first sudden edge of the second pulse corresponds to the first sudden edge of the first first pulse.

[0035] When a laser pulse triggers the photodetector multiple times, multiple first pulses will be generated. If the subsequent data accumulation, histogram formation and distance judgment are performed based on multiple first pulses, erroneous results will be produced. However, the adjustment unit provided by the present invention only records and outputs the arrival time of the first first pulse within a preset time, and the preset time is not less than W pulse , that is, the pulse width of the laser pulse, which can avoid misjudgment of the pulse in subsequent processing, reduce system power consumption, and improve the accuracy of distance judgment.

[0036] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0037] This embodiment also provides a photodetector that cooperates with the regulation circuit. The photodetector includes a photoelectric conversion unit. The photoelectric conversion unit can generate a first pulse combination Pulse-1 in response to a laser pulse. The photoelectric conversion unit can be an avalanche diode. More specifically, the photoelectric conversion unit can be a SPAD(s).

[0038] Combine Figure 4 and Figure 5The following description uses the example of a photoelectric conversion unit using a SPAD (not shown) and a first pulse combination Pulse-1 comprising two first pulses. Specifically, the first pulse combination Pulse-1 includes a first first pulse p11 and a second first pulse p12. The first and second first pulses here refer to the relative timing of each other, with the first first pulse p11 being generated earlier than the second first pulse p12. Both p11 and p12 are designated as first pulses because both pulse signals are generated by the laser pulse being reflected by the target and received by the photodetector.

[0039] The regulation circuit includes an output signal providing unit 1 and a reset unit 2. The output signal providing unit 1 generates the second pulse Pulse-2 according to the reset pulse Pulse-r and the first first pulse p11. The reset unit 2 can generate the reset pulse Pulse-r according to the second pulse Pulse-2.

[0040] The output signal providing unit 1 generates the first sudden edge of the second pulse Pulse-2 based on the first sudden edge of the first first pulse p11, and generates the second sudden edge of the second pulse signal Pulse-2 based on the first sudden edge of the reset pulse Pulse-r. The first sudden edge of the first pulse p11 corresponds to the trigger time of the SPAD. The output signal providing unit 1 generates the first sudden edge of the second pulse Pulse-2 based on the first sudden edge of the first first pulse p11, and the first sudden edge of the second pulse Pulse-2 also corresponds to the trigger time of the SPAD.

[0041] The first pulse and the second pulse Pulse-2 can both be positive pulses, and the reset pulse Pulse-r can be a negative pulse. The first sudden edge of the first pulse is a rising edge, and the second sudden edge of the first pulse is a falling edge. The first sudden edge of the second pulse Pulse-2 is a rising edge, and the second sudden edge of the second pulse Pulse-2 is a falling edge. The first sudden edge of the reset pulse Pulse-r is a falling edge, and the second sudden edge of the reset pulse Pulse-r is a rising edge. The sudden edges of the above pulses can represent the arrival time or end time of the pulses. In other embodiments, other methods can also be used to represent them.

[0042] Figure 6 This is a structural block diagram of the coordination between the regulating circuit and the photodetector.

[0043] The input end of the regulation circuit is coupled to the output end of the SPAD, and is suitable for receiving the first pulse combination Pulse-1 generated by the SPAD; the output end of the regulation circuit is coupled to the signal readout circuit, and outputs pulse-2 to the signal readout circuit. The signal readout circuit obtains the first sudden edge of Pulse-2, that is, the SPAD trigger time, and stores data such as the SPAD trigger time and the number of triggered SPADs in each time period measured multiple times, and performs subsequent processing such as generating a histogram.

[0044] As an implementable embodiment, the output signal providing unit 1 may include a bistable circuit. A first input terminal of the bistable circuit is adapted to receive a first positive voltage VDD. A second input terminal of the bistable circuit is adapted to receive the first pulse combination Pulse-1. A reset terminal of the bistable circuit is adapted to receive the reset pulse Pulse-r. An output terminal of the bistable circuit is adapted to output the second pulse Pulse-2. The first positive voltage VDD may be a power supply voltage.

[0045] More specifically, the bistable circuit may be a D flip-flop. An input terminal D of the D flip-flop is adapted to receive a first positive voltage VDD. A clock signal terminal clk of the D flip-flop is adapted to receive the first pulse combination Pulse-1. A reset terminal rst of the D flip-flop is adapted to receive the reset pulse Pulse-r. An output terminal Q of the D flip-flop is adapted to output the second pulse Pulse-2.

[0046] Since the input terminal D of the D flip-flop receives the first positive voltage VDD, when the clock signal terminal clk of the D flip-flop receives the rising edge of the pulse signal, the output terminal Q of the D flip-flop starts to output a high level; when the reset terminal rst of the D flip-flop receives a reset pulse, the D flip-flop is reset, and the output terminal Q of the D flip-flop starts to output a low level; thus, the output terminal Q of the D flip-flop can generate a pulse signal.

[0047] Based on the above principles, after the SPAD is triggered, its output terminal outputs the first pulse combination, Pulse-1. When the clock signal terminal clk of the D flip-flop receives the rising edge of the first pulse p11, the output terminal Q of the D flip-flop begins to output a high level, generating the rising edge of the second pulse, Pulse-2. The output terminal Q of the D flip-flop then remains high until the reset terminal rst of the D flip-flop receives the falling edge of the reset pulse, Pulse-r. The D flip-flop begins to reset, and the output terminal Q of the D flip-flop begins to output a low level, generating the falling edge of the second pulse, Pulse-2. As a result, the output terminal Q of the D flip-flop outputs a complete second pulse, Pulse-2.

[0048] During the duration of the reset pulse Pulse-r (low-level duration), regardless of the level of the input signal at the clock signal terminal clk of the D flip-flop, such as the subsequent input of the second first pulse p12, it will not affect the D flip-flop's output terminal Q, which remains at a low level. Therefore, from the rising edge of the second pulse Pulse-2 to the end of reset, the D flip-flop only generates the second pulse Pulse-2 based on the first first pulse p11 and the reset pulse Pulse-r, and does not generate any additional pulse signals based on the second first pulse p12. Optionally, the time from the rising edge of the second pulse Pulse-2 to the end of reset is not less than the pulse width of the laser pulse, which can further ensure that the double peak phenomenon is avoided.

[0049] In the above process, the D flip-flop's inactive response to any input pulses during the reset phase is similar to the SPAD's outputting a trigger signal without sensing other photons during its dead time. Therefore, the adjustment unit of this embodiment can extend the SPAD's dead time, thereby preventing problems such as double peaks caused by the SPAD's dead time being less than the laser pulse width, and data loss due to insufficient back-end circuit processing speed. Furthermore, by setting the duration of the reset pulse Pulse-r, the SPAD's dead time can be adjusted, achieving dead time regulation.

[0050] In the case where the dead time determined by the adjustment circuit is not less than the pulse width of the laser pulse, the dead time cannot be increased indefinitely, otherwise the detection accuracy will be reduced, and it may even cause the adjustment unit to be unable to output the subsequent echo signal to trigger the avalanche signal generated by the SPAD, resulting in data loss and detection failure. In this embodiment, the preset time, that is, the time from the rising edge of the second pulse Pulse-2 to the end of the D flip-flop reset is ≤5W pulse On the one hand, it ensures that when the photodetector receives other echo laser pulses, the adjustment circuit can output the corresponding SPAD trigger time. On the other hand, when the ambient light is strong, the dead time is extended to ≥W pulse and ≤5W pulse , which can reduce the amount of data output by the regulation circuit to the signal readout circuit when the ambient light causes the SPAD to be frequently triggered and generate excessive noise signals, thereby reducing the system computational complexity without losing detection accuracy.

[0051] Specifically, the reset unit 2 generates the first sudden edge of the reset pulse Pulse-r according to the first sudden edge of the second pulse Pulse-2. The reset unit 2 may include: a control unit 21, a capacitive storage unit 22 and a reset signal providing unit 23.

[0052] The control unit 21 generates one of a charging signal and a discharging signal based on the first abrupt edge of the second pulse Pulse-2, and generates the other of the charging signal and the discharging signal based on the second abrupt edge of the second pulse Pulse-2. The capacitive storage unit 22 can charge and discharge its stored charge based on the charging signal and the discharging signal. The reset signal providing unit 23 can generate the reset pulse Pulse-r after the voltage of the capacitive storage unit 22 reaches a threshold voltage.

[0053] In a specific embodiment, the control unit 21 may include: a PMOS transistor P1, an NMOS transistor N1 and a resistor unit.

[0054] The source of the PMOS transistor P1 is adapted to be connected to a first positive voltage VDD. The gate of the PMOS transistor is connected to the gate of the NMOS transistor N1 and adapted to receive the second pulse Pulse-2. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor N1, the capacitive storage unit 22, and the reset signal providing unit 23. The source of the NMOS transistor N1 is connected to the resistor unit. The first positive voltage VDD may be a power supply voltage. The resistor unit may be a resistor R1 or a variable resistor.

[0055] The capacitive storage unit 22 may be a capacitor C1 , a first end of the capacitor C1 is connected to the drain of the PMOS transistor P1 , and a second end of the capacitor C1 is grounded or connected to another relatively low voltage level.

[0056] The reset signal providing unit 23 includes an even number of inverters connected in series, and the output end of the last inverter is suitable for outputting the reset pulse. Figure 3 A reset signal providing unit 23 is provided, which is composed of two inverters. The input of the first inverter is connected to the drain of the PMOS transistor P1, the output of the first inverter is connected to the input of the second inverter, and the output of the second inverter is suitable for generating the reset pulse Pulse-r.

[0057] Continue to refer Figure 5 When the D flip-flop begins outputting a high level based on the rising edge of the first pulse p11, the gate of NMOS transistor N1 is at a high level, and the gate-source voltage is greater than the turn-on voltage, turning on NMOS transistor N1 and turning off PMOS transistor P1. At this point, NMOS transistor N1, resistor R1, and capacitor C1 form a discharge path, and capacitor C1 begins to discharge. The voltage V1 across capacitor C1 gradually decreases, and the rate of decrease depends on the capacitance of capacitor C1 and the resistance of resistor R1.

[0058] When the voltage V1 on capacitor C1 drops below the inverter's flip-flop threshold, after passing through two inverters, the falling edge of the reset pulse Pulse-r is generated, maintaining the reset pulse Pulse-r at a low level. The low-level reset pulse Pulse-r is input to the clock signal terminal clk of the D-type flip-flop, causing the D-type flip-flop to enter a reset state. The output terminal Q of the D-type flip-flop then generates the falling edge of the second pulse Pulse-2. The output terminal Q of the D-type flip-flop then remains low. At this point, the gate of the PMOS transistor P1 is turned on by the low voltage, while the NMOS transistor N1 is turned off. The voltage V1 on capacitor C1 begins to rise. Due to the low equivalent resistance of the PMOS transistor P1, the voltage V1 on capacitor C1 quickly returns to a high level. After passing through two inverters, the rising edge of the low-level reset pulse Pulse-r is generated, thus terminating the reset pulse Pulse-r. After the reset pulse Pulse-r ends, the D-type flip-flop enters its operating state and resumes triggering.

[0059] The time difference between the rising edge of the D-type flip-flop output, Pulse-2, and the rising edge of the reset pulse, Pulse-r, is the discharge time τ for the capacitor to discharge from VDD to the inverter's flip-flop threshold, plus the delay Δt of the two inverter stages. The time difference between the rising and falling edges of the reset pulse, Pulse-r, is the delay Δt of the two inverter stages. Therefore, the time difference between the rising edge of the D-type flip-flop output, Pulse-2, and the falling edge of the reset pulse, Pulse-r, is τ + 2Δt, which is the minimum time interval between two adjacent second pulses output by the regulation circuit.

[0060] Compared to τ, the time of 2Δt can be ignored, and the minimum time interval between two adjacent second pulses output by the regulation circuit is approximately the discharge of the capacitor. In this embodiment, the flip threshold of the inverter is VDD / 2, and the time required for the corresponding capacitor to discharge from VDD to VDD / 2 is approximately 0.7RC, that is, τ=0.7RC, where R is the resistance value of the resistor unit and C is the capacitance value of the capacitive storage unit 22. The matching degree and process accuracy of resistors and capacitors are much higher than those of CMOS devices, so that the deadtime of the SPAD determined by the regulation circuit can be maintained at a stable value, enhancing the controllability of the deadtime and avoiding deadtime deviation caused by the process. Coupling each SPAD unit output end on the array SPAD chip to an adjustment circuit can also improve the deadtime consistency of SPAD units at different positions on the array SPAD chip. The values ​​of R and C can be obtained based on the deadtime calculation of the system design.

[0061] The resistance unit of another embodiment of the present application may include a variable resistor R2, such as Figure 7 shown.

[0062] When the resistance unit uses a variable resistor R2, when the capacitance value C of the capacitive storage unit is constant, the deadtime is determined by the resistance value of the variable resistor R2. When the resistance value of the variable resistor R2 is increased, the deadtime of the SPAD becomes longer, which can improve the effect of avoiding the double peak problem; when the resistance value of the variable resistor R2 is reduced, the deadtime of the SPAD is shortened. The capacitance value C is determined during the design and preparation of the adjustment circuit. After it is prepared into a circuit element, the capacitance value C can no longer be adjusted. However, the resistance value of the variable resistor R2 can still be adjusted according to actual needs during the use of the circuit, thereby changing the deadtime determined by the adjustment circuit.

[0063] In fact, when the dead time of the SPAD determined by the regulating circuit meets the requirement of being greater than the pulse width of the laser pulse, the smaller the dead time, the better, so as to ensure that the subsequent detection signal is not lost. However, when the ambient light is very strong, even if there is no echo laser pulse, the ambient light will still cause the SPAD to trigger frequently, and these trigger signals are all noise, which will increase the system data processing capacity and reduce the signal-to-noise ratio. Therefore, in this embodiment, by changing the variable resistor R2, the dead time can be increased to no more than 5W pulse During the detection process, the dead time can be flexibly adjusted according to the ambient light intensity, thereby reducing the signal output of the regulation circuit when the ambient light is too strong, which can not only reduce the system calculation amount and thus reduce power consumption, but also improve the signal-to-noise ratio.

[0064] like Figure 8 As shown, in another specific embodiment, the control unit 21 may include: a PMOS transistor P1, an NMOS transistor N1 and a current output analog-to-digital converter DAC.

[0065] The source of the PMOS transistor P1 is connected to a first positive voltage VDD, and the gate of the PMOS transistor is connected to the gate of the NMOS transistor N1 and is adapted to receive the second pulse Pulse-2. The drain of the PMOS transistor P1 is connected to the drain of the NMOS transistor, the capacitive storage unit 22, and the reset signal providing unit 23. The source of the NMOS transistor N1 is connected to the current-output analog-to-digital converter DAC.

[0066] Please refer to the equivalent diagram of the current output analog-to-digital converter DAC Figure 8 shown.

[0067] The current output analog-to-digital converter DAC includes: a reference branch and an output branch. The reference branch and the output branch are both composed of MOS transistors and switches. The reference branch includes MOS transistor Mr, and the output branch includes MOS transistors M1, M2, M3, and M4. For a given reference branch current Ir , the output current I0 and the reference branch current I r The relationship is:

[0068]

[0069] In formula 2, (W / L)0 represents the width and length parameters of the MOS tube in the reference branch, (W / L) r Indicates the width and length parameters of the MOS tube in the output branch.

[0070] According to actual needs, the MOS transistors M1, M2, M3, and M4 can be set to different width and length parameters. By closing the switch, switching between different MOS transistors can be achieved, and different output currents I0 can be obtained.

[0071] Similar to the previous embodiment, the time difference between the rising edge of the output pulse Pulse-2 and the falling edge of the reset pulse Pulse-r in this embodiment of the D flip-flop is τ + 2Δt, which is the minimum time interval between two adjacent second pulses output by the regulation circuit. In this embodiment, the inverter's flip-flop threshold is VDD / 2, and the time it takes for the capacitor to discharge to VDD / 2 is determined by the charge and discharge current, i.e., τ = (0.5VDD*C) / I, where I is the output current of the current-output analog-to-digital converter DAC and C is the capacitance of the capacitive storage unit 22.

[0072] When the voltage value of the first positive voltage VDD and the capacitance value of the capacitive storage unit 22 are constant, the dead time is determined by the output current value of the current-output analog-to-digital converter DAC. Therefore, by switching different MOS transistors in the current-output analog-to-digital converter DAC, different output currents can be obtained, thereby achieving switching between different dead time values.

[0073] The dead time is adjusted by using a current output analog-to-digital converter (DAC) to discharge the charge on the capacitive storage unit 22 through output current.

[0074] As can be seen from the above description, the regulation circuit provided in this embodiment can adjust the dead time of the SPAD. When the ambient light is too strong and the trigger frequency is too high, reducing the signal-to-noise ratio, it can effectively reduce the number of trigger events and avoid detection errors caused by insufficient system response speed. In a SPAD-based lidar system, the dead time of the SPAD is not less than the pulse width of the laser pulse, which can avoid phenomena such as double peaks in the detection results.

[0075] The embodiment of the present invention further provides a data processing chip suitable for a SPAD array. Figure 10 As shown, the SPAD array includes multiple rows and multiple columns, each row and each column is provided with multiple photodetection units, and each photodetection unit includes one or more SPADs. When a photodetection unit includes multiple SPADs, multiple SPADs can be connected to the same signal readout circuit and used as a pixel. In the application of tof measurement, the signal readout circuit usually includes a time to digital converter (TDC), which outputs the SPAD trigger time and the number of SPADs triggered simultaneously in the same time to the synchronization circuit for generating a histogram and subsequent ToF time determination.

[0076] The data processing chip provided by an embodiment of the present invention includes multiple regulation circuits, each coupled to one or more photodetectors in a photodetection unit. By adjusting the dead time of the SPADs, the regulation circuits can effectively control the pulse signals output by the photodetectors to subsequent circuits.

[0077] Figure 10 As an example, each photodetection unit 1000 includes four SPADs, namely SPAD1001A, SPAD1001B, SPAD1001C, and SPAD1001D. The output end of each SPAD is coupled to the input end of a regulation circuit (the clock signal end clk end of the D flip-flop). Specifically, the output end of SPAD1001A is coupled to the input end of the regulation circuit 1002A, the output end of SPAD1001B is coupled to the input end of the regulation circuit 1002B, the output end of SPAD1001C is coupled to the input end of the regulation circuit 1002C, and the output end of SPAD1001D is coupled to the input end of the regulation circuit 1002D. The four regulation circuit output ends (the output end Q of the D flip-flop) corresponding to the four SPADs in each photodetection unit 1000 are all coupled to the same signal readout circuit to output Pulse-2 to the TDC.

[0078] like Figure 11 As shown, the embodiment of the present invention further provides an optical system 110 .

[0079] Optical system 110 includes: a light emitting module 111, a light detection module 112, and a control module 113. The light emitting module 111 refers to the portion of the optical detection system used for laser emission (which may include circuits, devices, structures, etc.); the light detection module 112 refers to the portion of the optical detection system used for detecting the laser's return signal (which may include circuits, devices, structures, etc.).

[0080] The light emitting module 111 includes a light emitting array 1111, such as a vertical-cavity surface-emitting laser (VCSEL) array. The light emitting array 1111 includes multiple rows and multiple columns. Each row and column is provided with multiple light emitting units 11111, each light emitting unit 11111 including at least one light emitter. The light emitting array 1111 is also configured with a corresponding emission array driver circuit, coupled to each light emitter, for driving the light emitter to operate.

[0081] The light detection module 112 includes a photoelectric detection array 1121. The photoelectric detection array 1121 can be, for example, Figure 10 The photodetection array 1121 is configured to receive the optical echo signal after the detection beam reaches the target object 114. In addition, the optical detection module 112 may further include a signal readout circuit (not shown) for reading out the signal generated by the photodetection array 1121 and transmitting it to the control module 113.

[0082] In the optical detection system, an emitting lens group 1114 may be provided, located on the outgoing light path of the light emitting array 1111; in the optical detection system, a receiving lens group 1122 may be provided, and the photoelectric detection array 1121 may be located on the focal plane of the receiving lens group 1122.

[0083] The control module 113 is coupled to the light emitting array 1111 and the photodetection array 1121 ; it controls the light emitting array to emit detection beams in a certain order and power, and the corresponding photodetection array receives echo signals.

[0084] The light detection module 112 further includes a data processing chip 1123. The data processing chip 1123 includes a plurality of regulating circuits, each regulating circuit being coupled to a photodetector. The data processing chip of the embodiment of the present invention may be Figure 10 The data processing chip shown adjusts the trigger signal of each SPAD to avoid double peaks and improve the signal-to-noise ratio.

[0085] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A regulating circuit, adapted to cooperate with a photodetector, the photodetector comprising a SPAD, adapted to receive laser pulses to generate a first pulse combination, characterized in that: The regulating circuit is coupled to a SPAD, and the regulating circuit includes: The adjustment unit is adapted to receive the first pulse combination and output a second pulse within a preset time, wherein the second pulse corresponds to an arrival time of the first first pulse in the first pulse combination generated by the same coupled SPAD, W pulse ≤ the preset time ≤ 5W pulse , where W pulse is the pulse width of the laser pulse.

2. The regulating circuit according to claim 1, wherein: The first sudden edge of the second pulse corresponds to the first sudden edge of the first pulse.

3. The regulating circuit according to claim 2, wherein: The first pulse and the second pulse are both positive pulses, the first sudden edge of the second pulse is a rising edge, and the first sudden edge of the first pulse is a rising edge.

4. The regulating circuit according to claim 2, wherein: The adjustment unit includes: an output signal providing unit, adapted to generate the second pulse according to the reset pulse and the first first pulse; The reset unit is adapted to generate the reset pulse according to the second pulse.

5. The regulating circuit according to claim 4, wherein: The output signal providing unit is adapted to generate the first sudden edge of the second pulse according to the first sudden edge of the first pulse, and to generate the second sudden edge of the second pulse signal based on the first sudden edge of the reset pulse.

6. The regulating circuit according to claim 4, wherein: The reset pulse is a negative pulse, and the first sudden change edge of the reset pulse is a falling edge.

7. The regulating circuit according to claim 4, wherein: The total duration of the second pulse and the reset pulse is not less than W pulse .

8. The regulating circuit according to claim 4, wherein: The output signal providing unit includes: a bistable circuit; The first input terminal of the bistable circuit is adapted to receive a first positive voltage; The second input terminal of the bistable circuit is adapted to receive the first pulse combination; The reset terminal of the bistable circuit is suitable for receiving the reset pulse; The output terminal of the bistable circuit is suitable for outputting the second pulse.

9. The regulating circuit according to claim 4, wherein: The output signal providing unit includes: a D flip-flop; The input terminal of the D flip-flop is adapted to receive a first positive voltage; The clock signal terminal of the D flip-flop is adapted to receive the first pulse combination; The reset terminal of the D flip-flop is suitable for receiving the reset pulse; The output terminal of the D flip-flop is suitable for outputting the second pulse.

10. The regulating circuit according to claim 4, wherein: The reset unit includes: a control unit, adapted to generate one of a charging signal and a discharging signal according to a first sudden edge of the second pulse, and to generate the other of the charging signal and the discharging signal according to a second sudden edge of the second pulse; a capacitive storage unit, adapted to charge and discharge the charge stored in itself according to the charging signal and the discharging signal; The reset signal providing unit generates the reset pulse after the voltage of the capacitive storage unit reaches a threshold voltage.

11. The regulating circuit according to claim 4, wherein: The reset unit includes: a control unit, a capacitive storage unit and a reset signal providing unit; The control unit includes: a PMOS transistor, an NMOS transistor, and a resistor unit; the source of the PMOS transistor is suitable for connecting to a first positive voltage, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and is suitable for receiving the second pulse, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, the capacitive storage unit, and the reset signal providing unit; the source of the NMOS transistor is connected to the resistor unit; The capacitive storage unit includes: a capacitor; The reset signal providing unit includes: an even number of inverters connected in series, and the output end of the last inverter is suitable for outputting the reset pulse.

12. The regulating circuit according to claim 11, wherein: The resistance unit includes a resistor or a variable resistor.

13. The regulating circuit according to claim 4, wherein: The reset unit includes: a control unit, a capacitive storage unit and a reset signal providing unit; The control unit includes: a PMOS transistor, an NMOS transistor, and a current output type analog-to-digital converter; the source of the PMOS transistor is suitable for connecting to a first positive voltage, the gate of the PMOS transistor is connected to the gate of the NMOS transistor and is suitable for receiving the second pulse, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, a capacitive storage unit, and a reset signal providing unit; the source of the NMOS transistor is connected to the current output type analog-to-digital converter; The capacitive storage unit includes: a capacitor; The reset signal providing unit includes: an even number of inverters connected in series, and the output end of the last inverter is suitable for outputting the reset pulse.

14. A data processing chip, characterized in that: include: The regulating circuit according to any one of claims 1 to 13, wherein the regulating circuit is adapted to cooperate with one or more photodetectors.

15. A photodetector, suitable for cooperating with the regulating circuit according to any one of claims 1 to 13, characterized in that: include: The photoelectric conversion unit is adapted to generate the first pulse combination in response to a laser pulse.

16. The photodetector according to claim 15, wherein The photoelectric conversion unit is an avalanche diode.

17. The photodetector according to claim 16, wherein The photoelectric conversion unit is a single-photon avalanche diode.

18. A photoelectric detection array, characterized in that: include: A plurality of rows and a plurality of columns; wherein each row and each column is provided with a plurality of photodetection units, each photodetection unit comprising at least one photodetector according to any one of claims 15 to 17; The regulating circuit according to any one of claims 1 to 13, wherein the regulating circuit is coupled to one or more photodetectors in a photodetection unit.

19. An optical system, characterized in that include: The light emitting module comprises: a light emitting array including a plurality of rows and a plurality of columns; wherein each row and each column is provided with a plurality of light emitting units, each light emitting unit including at least one light emitter; the light emitting array further comprises a light emitting array driving circuit coupled to each light emitter for emitting a detection laser beam; The optical detection module comprises: the photoelectric detection array according to claim 18, for receiving detection echoes.

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