Storage device and method of operating the same

Abstract

The present disclosure provides a storage device and an operating method thereof. The storage device includes a memory die, a storage controller processor, and a memory, the storage controller processor configured to control an operation of the memory die by scheduling a plurality of commands provided to the memory die, the plurality of commands corresponding to a command queue of the memory die, wherein the storage controller processor is configured to: receive the plurality of commands from a first tenant and a second tenant, respectively; schedule the plurality of commands in the command queue according to the first tenant and the second tenant providing the plurality of commands; and reschedule the plurality of commands according to an urgency of the plurality of commands and an operation performed in the memory die, and control the memory die to process the plurality of commands in an order different from an order in which the plurality of commands are received by the storage controller processor.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0172573, filed with the Korean Intellectual Property Office on December 10, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] One or more exemplary embodiments of the present invention relate to storage devices and methods of operating the same, and more specifically, to storage devices for scheduling commands received from a host and methods of operating the storage devices. Background Technology

[0004] A storage system consists of a host and storage devices. The host and storage devices are interconnected via various standard interfaces, such as Universal Flash Memory (UFS), Serial ATA (SATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), and embedded multimedia cards (eMMC). When storage systems are used in mobile devices, high-speed operation between the host and storage devices is crucial, and the storage devices need to efficiently process commands from the host. Summary of the Invention

[0005] The technical problems to be solved by at least some exemplary embodiments of the present invention include, for example, providing a storage device for efficiently processing commands from a host and a method of operating the storage device.

[0006] According to at least some exemplary embodiments of the present invention, a storage device includes a memory die, a storage controller processor, and a memory, the storage controller processor being configured to control operations performed on the memory die by scheduling a plurality of commands provided to the memory die, the memory storing a command queue corresponding to the memory die, wherein the storage controller processor is configured to: receive the plurality of commands from a first tenant and a second tenant, respectively; schedule the plurality of commands in the command queue according to the first tenant and the second tenant providing the plurality of commands; reschedule the plurality of commands according to the operations performed on the memory die and the urgency of the plurality of commands; and control the memory die to process the plurality of commands in an order different from the order in which the plurality of commands are received by the storage controller processor.

[0007] According to at least some exemplary embodiments of the present invention, a storage device includes a plurality of memory dies, a storage controller processor, and a memory, wherein the storage controller processor is configured to schedule a plurality of commands provided to the plurality of memory dies and control operations performed on the plurality of memory dies, the memory storing a plurality of command queues corresponding to the plurality of memory dies respectively, wherein the storage controller processor is further configured to: schedule the plurality of commands in the plurality of command queues according to a plurality of tenants configured to provide the plurality of commands respectively and the urgency of the plurality of commands, and reschedule the plurality of commands according to operations performed on the memory dies on which at least some of the plurality of commands have been provided.

[0008] According to at least some exemplary embodiments of the present invention, a method of operating a storage device including a storage controller processor and a plurality of memory dies is provided, the method comprising: receiving a plurality of commands from a plurality of tenants; scheduling the plurality of commands in a round-robin manner according to the plurality of tenants; scheduling the plurality of commands separately according to the urgency of the plurality of commands; and rescheduling the plurality of commands according to operations performed on memory dies in which at least some of the plurality of commands have been provided. Attached Figure Description

[0009] The above and other features and advantages of the exemplary embodiments of the inventive concept will become more apparent from the detailed description of these embodiments with reference to the accompanying drawings. The drawings are intended to depict exemplary embodiments of the inventive concept and should not be construed as limiting the scope of the claims. Unless explicitly stated otherwise, the drawings are not to be considered as drawn to scale.

[0010] Figure 1 This is a block diagram of a host-storage system according to at least one exemplary embodiment of the present invention;

[0011] Figure 2 This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention.

[0012] Figures 3A to 3C This is a diagram illustrating the scheduling operation of a storage device according to at least one exemplary embodiment of the present invention.

[0013] Figure 4 This is a diagram illustrating the scheduling operation of a storage device according to at least one exemplary embodiment of the present invention.

[0014] Figure 5 This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention.

[0015] Figure 6This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention.

[0016] Figure 7A This is a diagram illustrating command information about a memory die stored in a storage controller of a storage device, according to at least one exemplary embodiment of the present invention.

[0017] Figure 7B This is a diagram illustrating command information about a tenant stored in the storage controller of a storage device, according to at least one example embodiment of the present invention.

[0018] Figure 8A and Figure 8B This is a diagram illustrating the operation of a management command to retrieve a command input from a storage controller of a storage device, according to at least one exemplary embodiment of the present invention.

[0019] Figure 9 This is a diagram of a system that utilizes a storage device according to at least one exemplary embodiment of the present invention.

[0020] Figure 10 This is a block diagram of a memory system according to an embodiment;

[0021] Figure 11 This is a block diagram of a system according to at least one exemplary embodiment of the present invention;

[0022] Figure 12 This is a block diagram of a system according to at least one exemplary embodiment of the present invention;

[0023] Figure 13A and Figure 13B This is a block diagram illustrating an example of a system based on at least one exemplary embodiment of the concept of the present invention; and

[0024] Figure 14 This is a block diagram of a data center including a system according to at least one example embodiment of the concept of the present invention. Detailed Implementation

[0025] As is customary in the field of this invention, embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case of blocks, units, and / or modules implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and can optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing certain functions and processors performing other functions (e.g., one or more programmable microprocessors and associated circuitry). Furthermore, without departing from the scope of the inventive concept, each block, unit, and / or module of the embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the embodiments can be physically combined into more complex blocks, units, and / or modules.

[0026] Figure 1 This is a block diagram of a host-storage system according to at least one exemplary embodiment of the present invention.

[0027] The host-storage system 10 may include a host 100 and a storage device 200. Furthermore, the storage device 200 may include a storage controller 210 and non-volatile memory 220. Additionally, according to at least one exemplary embodiment of the present invention, the host 100 may include a host controller 110 and host memory 120. The host memory 120 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 200.

[0028] Storage device 200 may include a storage medium for storing data in response to a request from host 100. For example, storage device 200 may include at least one of solid-state drives (SSDs), embedded memory, and removable external memory. When storage device 200 is an SSD, it may be a device conforming to the Fast Non-Volatile Memory (NVMe) standard and the Compute Fast Link (CXL) standard. When storage device 200 is embedded memory or external memory, it may be a device conforming to the Universal Flash Memory (UFS) standard or the eMMC standard. Host 100 and storage device 200 may generate packets according to standard protocols applied to host 100 and storage device 200 respectively, and may send such packets.

[0029] The non-volatile memory 220 of storage device 200 may include memory dies 221 (or memory chips). For example, memory dies 221 may include first memory dies DIE1 to nth memory dies DIEn, and n may be a natural number and may be different numbers.

[0030] When the non-volatile memory 220 of storage device 200 includes flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may include different types of non-volatile memory. For example, storage device 200 may include magnetic RAM (MRAM), spin-transfer torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase-change RAM (PRAM), resistive RAM (RRAM), and other types of memory.

[0031] In an example embodiment, the host controller 110 and the host memory 120 may be separate semiconductor chips. Alternatively, in an example embodiment, the host controller 110 and the host memory 120 may be integrated into the same semiconductor chip.

[0032] For example, host controller 110 may be any module included in the application processor, and the application processor may be implemented as a system-on-a-chip (SoC). Furthermore, host memory 120 may be embedded memory included in the application processor, or non-volatile memory or memory module external to the application processor. Host controller 110 may be or include processing circuitry, such as hardware including logic circuitry; a hardware / software combination executing software; or a combination of both. For example, processing circuitry may more specifically include, but is not limited to, one or more of the following: central processing unit (CPU), processor core, arithmetic logic unit (ALU), digital signal processor, microcomputer, field-programmable gate array (FPGA), programmable logic unit, microprocessor, application-specific integrated circuit (ASIC), etc. The processing circuitry of host controller 110 may be configured to perform and / or control any operations described in this specification performed by the host controller or its components via hardware and / or software (e.g., firmware). In this specification, host controller 110 may also be referred to as host controller circuitry 110.

[0033] For example, different tenants (e.g., first tenant T1 and second tenant T2) can be executed by host controller 110. Each tenant can be an entity that can be executed by a host (e.g., host 100) and can issue data access commands (e.g., read and / or write commands). Examples of tenants include, but are not limited to, processes, programs, program instances, and virtual machines. Each of first tenant T1 and second tenant T2 can access storage device 200 to store or read data. For example, storage device 200 can distinguish first tenant T1 and second tenant T2 based on the physical / virtual functionality of an interface (e.g., Fast Peripheral Component Interconnect (PCIe)), a first commit queue SQ1 / second commit queue SQ2, namespaces, NVMe sets, streams, etc. Alternatively, for example, host 100 can change the identifiers (IDs) that respectively indicate first tenant T1 and second tenant T2, as well as the Quality of Service (QoS) configurations for first tenant T1 and second tenant T2, and storage device 200 can distinguish first tenant T1 and second tenant T2 from each other based on the IDs and QoS configurations.

[0034] Figure 1 This illustrates two distinct tenants executed by host controller 110, but host storage system 10 is not limited to this. At least three tenants can be executed by host controller 110. Furthermore, with... Figure 1 The diagrams differ, and the first tenant T1 and the second tenant T2 can be tenants executed by different hosts. For example, each host can have different QoS configuration values, and the storage device 200 can distinguish the first tenant T1 and the second tenant T2 by using the QoS configuration values.

[0035] In an example embodiment, storage device 200 may receive information from host 100 regarding the IDs and priorities assigned to tenants. Storage controller 210 may allocate resources for user-requested tasks based on the priority of each tenant. Alternatively, in an example embodiment, storage device 200 may allocate resources for user-requested tasks, taking into account factors such as the bandwidth required by each tenant, the allowed latency for each tenant, and the size of the memory region allocated to support each tenant.

[0036] The storage controller 210 may include a host interface 211, a memory interface 212, and a storage controller processor 213. Furthermore, the storage controller 210 may also include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, a scheduler 217, and a command queue 218. According to at least some exemplary embodiments of the present invention, the storage controller processor 213 may be or include: hardware containing logic circuitry; a hardware / software combination executing software; or a combination thereof. For example, the storage controller processor may more specifically include, but is not limited to, one or more of the following: a central processing unit (CPU), a processor core, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The storage controller processor 213 may be configured to perform and / or control any operations described in the specification performed by the storage controller processor, storage controller, storage device, or elements thereof (e.g., storage controller 210 and / or non-volatile memory 220 of storage device 200, and / or host interface 211, memory interface 212, flash translation layer (FTL) 214, packet manager 215, buffer memory 216, scheduler 217, and / or command queue 218 of storage controller 210) via hardware and / or software (e.g., firmware). For example, in at least one exemplary embodiment of the invention, the storage controller processor 213 is a central processing unit (CPU).

[0037] The storage controller 210 may also include memory. At least one of the FTL 214, the group manager 215, and the scheduler 217 may be implemented as software or firmware and may be loaded onto the memory of the storage controller 210 to operate under the control of the storage controller processor 213. The command queue 218 may be stored in the memory of the storage controller 210 and may be controlled by the storage controller processor 213.

[0038] According to at least some exemplary embodiments of the present invention, the memory can be used as operational memory, buffer memory, cache memory, etc., for example, the memory can be implemented as DRAM, SRAM, PRAM, or flash memory. For example, the memory controller 210 may also include working memory loaded with FTL 214, and when the memory controller processor 213 executes the FTL, it can control data write and read operations on the non-volatile memory. However, the memory controller 210 of the storage device 200 is not limited thereto, and each component of the memory controller 210 can be implemented as hardware, software, or firmware.

[0039] Host interface 211 can receive packets from host 100 and send packets to host 100. Packets sent from host 100 to host interface 211 may include commands, addresses, data, etc., to be written to non-volatile memory 220, and packets sent from host interface 211 to host 100 may include responses to commands, data read from non-volatile memory 220, etc. Memory interface 212 can send data to non-volatile memory 220 to non-volatile memory 220 or receive data read from non-volatile memory 220. Memory interface 212 may be implemented in accordance with standard protocols such as Toggle or ONFI.

[0040] FTL 214 can perform various functions such as address mapping, wear leveling, and garbage collection. Address mapping can be the process of switching a logical address received from the host to a physical address used to actually store data in non-volatile memory 220. Wear leveling is a technique to prevent excessive degradation of any block by ensuring that blocks in non-volatile memory 220 are used evenly. For example, wear leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection is a technique to ensure available capacity in non-volatile memory 220 by copying valid data from existing blocks to new blocks and erasing existing blocks.

[0041] The packet manager 215 can generate packets according to the protocol of the interface negotiated with the host 100, or parse various information from packets received from the host 100. For example, the packet manager 215 can obtain commands from packets received from the host 100.

[0042] Buffer memory 216 can temporarily store data to be written to or read from non-volatile memory 220. Buffer memory 216 can be included in memory controller 210 or can be external to memory controller 210.

[0043] Scheduler 217 can schedule the processing order of commands received from host 100. Scheduler 217 can schedule commands according to the type of memory die corresponding to each command (e.g., normal or urgent) and store them in command queue 218. Commands received from host 100 can be temporarily buffered in command queue 218.

[0044] In an example embodiment, command queue 218 may include first command queues CQ1 through nth command queues CQn. Each of the first command queues CQ1 through nth command queues CQn may be a command queue dedicated to a specific memory die in the memory die 221 included in the non-volatile memory 220. For example, the first command queue CQ1 may be dedicated to the first memory die DIE1, the second command queue CQ2 may be dedicated to the second memory die DIE2, and the nth command queue CQn may be dedicated to the nth memory die DIEn. Command queue 218 may be implemented as a register, but one or more embodiments are not limited thereto.

[0045] Figure 1 As shown, the number n of the first command queues CQ1 to the nth command queue CQn is the same as the number n of the first memory dies DIE1 to the nth memory dies DIEn. However, in the storage device 200, the number of the first command queues CQ1 to the nth command queue CQn may be different from the number of the first memory dies DIE1 to the nth memory dies DIEn, and the number of the first command queues CQ1 to the nth command queue CQn and the number of the first memory dies DIE1 to the nth memory dies DIEn may vary. Furthermore, in the example embodiment, one command queue may be dedicated to multiple memory dies, and multiple command queues may be dedicated to one memory die. For example, the first command queue CQ1 and the second command queue CQ2 may both be dedicated to the first memory die DIE1, or in the example embodiment, the first command queue CQ1 may be dedicated to both the first memory die DIE1 and the second memory die DIE2.

[0046] The storage controller 210 may also include an error correction code (ECC) engine. The ECC engine can perform error detection and error correction on read data read from the non-volatile memory 220. More specifically, the ECC engine can generate parity bits for the data to be written to the non-volatile memory 220, and the generated parity bits can be stored in the non-volatile memory 220 along with the written data. When reading data from the non-volatile memory 220, the ECC engine can correct errors in the read data by using the parity bits read from the non-volatile memory 220 along with the read data, and can output the error-corrected read data.

[0047] Storage device 200 can manage commands sent from different first tenants T1 and second tenants T2 according to the urgency of the commands (e.g., the priority of processing the commands), and can schedule the commands. Therefore, commands received from first tenant T1 and second tenant T2 can be processed equally, and urgent commands can be prioritized. Thus, head-of-line (HOL) blocking problems where commands remain congested even when some memory dies 221 included in non-volatile memory 220 are not active can be prevented. Figure 2 This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention.

[0048] Reference Figure 1 and Figure 2 In operation S100, the storage controller 210 of the storage device 200 can receive commands from tenants. For example, the storage controller 210 can receive commands from the first tenant T1 and the second tenant T2, respectively.

[0049] When a command is received, the memory controller 210 can also receive a logical address along with the command. The memory controller 210 can translate the logical address corresponding to the command into a physical address. Based on the translated physical address, a memory die can be selected from the memory die 221 to process the command accordingly.

[0050] Furthermore, when a command is received, the storage controller 210 can categorize the command according to its urgency (i.e., the priority of processing the command). For example, these commands can be divided into urgent commands and normal commands, respectively. However, the storage controller 210 is not limited to this and can divide the commands into three or more groups according to their urgency.

[0051] In operation S200, the storage controller 210 can schedule commands in a round-robin manner based on the tenant. For example, the storage controller 210 can schedule commands sent from the first tenant T1 and the second tenant T2 in a round-robin manner, so that the first tenant T1 and the second tenant T2 can access the memory die 221 equally. The storage controller 210 can schedule a first command received from the first tenant T1, and then schedule a second command received from the second tenant T2. After scheduling the second command received from the second tenant T2, the storage controller 210 can schedule commands received from another tenant instead of the second tenant T2.

[0052] In operation S300, the storage controller 210 can schedule commands based on their urgency. The storage controller 210 can schedule urgent commands so that they are processed in the storage device 200 before normal commands. When the storage device 200 receives a command, it can receive information about the urgency of that command as information about the command.

[0053] Storage device 200 can prioritize urgent commands by scheduling them according to their urgency, and can prevent urgent commands from being left unprocessed due to normal commands preceding them in the command queue. In other words, it can prevent HOL blocking problems.

[0054] In operation S400, the memory controller 210 can reschedule commands based on the operations performed on the memory die. In an example embodiment, when an urgent read command is scheduled and queued in a first command queue CQ1 corresponding to the first memory die DIE1, while a normal programming operation based on a normal programming command is being performed on a specific memory die (e.g., the first memory die DIE1), the memory controller 210 can reschedule commands to prioritize the urgent read command. The memory controller 210 can suspend the normal programming operation already being performed on the first memory die DIE1 by sending the urgent read command to the first memory die DIE1, thereby prioritizing the execution of the urgent read operation based on the urgent read command. When the urgent read operation is completed, the suspended normal programming operation can be resumed on the first memory die DIE1.

[0055] In this embodiment, before executing operation S400, the memory controller 210 may perform an operation that determines whether the address of a normal programming command being processed in a specific memory die is the same as the address of an urgent read command, and may execute operation S400 based on the determination result. For example, when a normal programming operation based on a normal programming command is performed in a specific memory die, and when the address of a queued urgent read command is the same as the address of a normal programming command, the memory controller 210 may reschedule the command to prioritize the urgent read command; when the address of a queued urgent read command is different from the address of a normal programming command, the memory controller 210 may not reschedule the command to prioritize the urgent read command. However, the memory controller 210 is not limited to this; the memory controller 210 may reschedule the command to prioritize the urgent read command regardless of whether the address of a queued urgent read command is the same as the address of a normal programming command.

[0056] Storage device 200 can perform a rescheduling operation to change the processing order of urgent commands, so that urgent commands can be processed preferentially in the memory dies where the urgent commands were scheduled. Therefore, the problem caused by urgent read commands not being processed due to preceding program commands can be solved, and the QoS of read operations can be improved.

[0057] Operations S200 to S400 can be performed by the scheduler 217 of the storage controller 210. Figure 2 The diagram shows that operation S300 is performed after operation S200, but the operation of storage device 200 is not limited to this. Operation S200 can be performed after operation S300, or operations S200 and S300 can be performed in parallel.

[0058] Figures 3A to 3C This is a diagram illustrating the scheduling operation of a storage device according to at least one exemplary embodiment of the present invention, and it illustrates... Figure 2 Operations S200 and S300. Figure 4 This is a diagram illustrating the scheduling operation of a storage device according to at least one exemplary embodiment of the present invention, and shows... Figure 2 Operation S400. Figures 3A to 3C The time for sequentially executed scheduling operations is shown.

[0059] Reference Figure 3A Tenant T1 can manage the first commit queue SQ1, and tenant T2 can manage the second commit queue SQ2. Each of the first commit queue SQ1 and the second commit queue SQ2 can be a queue where various types of events, including commands from host 100, are arranged for processing. The commands stored in the first commit queue SQ1 and the second commit queue SQ2 can be controlled by the host controller (e.g., ...). Figure 1 The host controller 110) acquires the data and thus sends it to the storage device 200. For example, each of the first commit queue SQ1 and the second commit queue SQ2 can be generated in the host memory of the host 100 (e.g., ...). Figure 1 The first commit queue SQ1 and the second commit queue SQ2 can be implemented as circular queues, but are not limited thereto.

[0060] Commands stored in the first submission queue SQ1 and the second submission queue SQ2 may include the address of the command to be processed, the urgency of the command, and information about the command type. For example, the first submission queue SQ1 may store a first command as an urgent programming command to be processed in the first memory die DIE1, and then a third command as an urgent programming command to be processed in the first memory die DIE1. Furthermore, for example, the second submission queue SQ2 may store a second command as an urgent read command to be processed in the first memory die DIE1, a fourth command as a normal programming command to be processed in the first memory die DIE1, and a fifth command as a normal read command to be processed in the second memory die DIE2. For example, in the storage device 200, urgent commands may be set to be processed before normal commands. However, in... Figure 3A The commands stored in the first commit queue SQ1 and the second commit queue SQ2 are merely examples and are not limited to these. Commands with different characteristics can be stored in the first commit queue SQ1 and the second commit queue SQ2, and commands can be divided into three or more types according to their urgency.

[0061] Storage device 200 can receive commands from host 100, manage commands according to the corresponding tenant, manage commands according to the corresponding memory die, and manage commands according to the urgency of the commands.

[0062] Storage device 200 may include command queues corresponding to memory dies. The memory dies 221 included in non-volatile memory 220 may include a first memory die DIE1 and a second memory die DIE2, and command queue 218 may include a first command queue CQ1 and a second command queue CQ2. According to at least some exemplary embodiments of the present invention, the first command queue CQ1 may be a command queue dedicated to the first memory die DIE1, and the second command queue CQ2 may be a command queue dedicated to the second memory die DIE2.

[0063] In the first command queue CQ1, commands can be categorized and stored according to their urgency. For example, the first command queue CQ1 may include a first emergency command queue UCQ1 storing urgent commands and a first normal command queue NCQ1 storing normal commands. In an example embodiment, commands stored in the first emergency command queue UCQ1 may be processed in the first memory die DIE1 before commands stored in the first normal command queue NCQ1.

[0064] In an example embodiment, the storage controller of storage device 200 can provide the first memory die DIE1 with an emergency command queue (UCQ1) containing as many emergency commands as there are according to a first threshold, and then provide the first memory die DIE1 with normal commands queued in a first normal command queue (NCQ1). According to at least some example embodiments of the invention, the first threshold can be set to prevent persistent delays in processing normal commands due to emergency commands, and can be preset or vary depending on the state of the first memory die DIE1.

[0065] Commands can be categorized according to their urgency and stored in a second command queue CQ2. For example, the second command queue CQ2 may include a second emergency command queue UCQ2 storing urgent commands and a second normal command queue NCQ2 storing normal commands. Commands stored in the second emergency command queue UCQ2 may be processed in the second memory die DIE2 before commands stored in the second normal command queue NCQ2.

[0066] In an example embodiment, the storage controller of storage device 200 can provide the second memory die DIE2 with an emergency command queue (UCQ2) containing as many emergency commands as there are queued according to a second threshold, and then provide the second memory die DIE2 with normal commands queued in a second normal command queue (NCQ2). According to at least some example embodiments of the invention, the second threshold can be set to prevent persistent delays in processing normal commands due to emergency commands, and can be preset or vary depending on the state of the second memory die DIE2. The first threshold and the second threshold can be the same as or different from each other.

[0067] Storage device 200 can schedule commands based on their urgency, thus prioritizing urgent commands. This prevents urgent commands from being left unprocessed due to normal commands preceding them in the command queue. In other words, it prevents HOL (Household Rank) blocking problems.

[0068] The storage controller of storage device 200 can schedule commands sent from the first tenant T1 and the second tenant T2 in a round-robin manner so that the first tenant T1 and the second tenant T2 can access the memory die 221 equally.

[0069] Storage device 200 can store a first command from a first tenant T1 in a first emergency command queue UCQ1 of a first command queue CQ1, and then store a second command from a second tenant T2 in a first emergency command queue UCQ1 of a first queue CQ1. Figure 3AThe diagram illustrates command scheduling operations based on first tenant T1 and second tenant T2, but one or more embodiments are not limited thereto. When a third tenant accesses storage device 200, a first command from first tenant T1 and a second command from second tenant T2 can be stored in a first command queue CQ1, and then commands from the third tenant can be stored.

[0070] Reference Figure 3B The storage device 200 can store a third command from the first tenant T1 in the first emergency command queue UCQ1 of the first command queue CQ1. That is, the first command, the second command, and the third command can be stored and scheduled sequentially in the first emergency command queue UCQ1 of the first command queue CQ1. Then, the storage device 200 can store a fourth command from the second tenant T2 in the first normal command queue NCQ1 of the first command queue CQ1.

[0071] That is, although the storage controller of storage device 200 receives the second command from the second tenant T2 after sequentially receiving the first command and the third command from the first tenant T1, storage device 200 can store the first command from the first tenant T1 in the first urgent command queue UCQ1 of the first command queue CQ1, store the second command from the second tenant T2 in the first urgent command queue UCQ1 of the first command queue CQ1, and then store the third command from the first tenant T1 in the first urgent command queue UCQ1 of the first command queue CQ1. Therefore, the storage controller of storage device 200 can schedule commands so that the first tenant T1 and the second tenant T2 can access the memory die 221 equally, respectively.

[0072] Reference Figure 3C Storage device 200 can store the fifth command received from the second tenant T2 in the normal command queue of the second command queue CQ2.

[0073] When an urgent read command is queued in the command queue corresponding to a specific memory die, and a normal programming operation based on a normal programming command is being executed on the memory die, the storage device 200 can send an urgent read command to the memory die to prioritize commands with relatively high urgency. Therefore, operations already being performed on the aforementioned memory die can be paused, and an urgent read operation can be performed based on the urgent read command. However, as in Figure 3C In the first emergency command queue UCQ1 of the first command queue CQ1 shown, when the first command is scheduled before the second command, the first command, which is an emergency programming command, must be sent to the first memory die DIE1 before the second command, which is an emergency read command. Therefore, the normal programming operation performed in the first memory die DIE1 is not suspended.

[0074] Reference Figure 3C and Figure 4 When an urgent read command is scheduled after an urgent programming command in an urgent command queue (e.g., the first urgent command queue UCQ1) included in command queue 218, the storage controller of storage device 200 can reorder the commands so that the urgent read command is processed first in the urgent command queue. When an urgent read command is set to be processed first in the urgent command queue, and while an operation according to the current normal programming command is being performed on the memory die, the storage controller can send the urgent read command even if the operation according to the normal programming command has not been completed on the memory die. When an urgent read command is received while an operation according to the current normal programming command is being performed on the memory die, the operation can be set to pause on the memory die.

[0075] For example, such as Figure 3C As shown, normal programming operations are performed in the first memory die DIE1, and when commands are scheduled in a polling manner, the first command and the subsequent second command (i.e., the read command) can be queued in the first urgent command queue UCQ1 of the first command queue CQ1. Therefore, as Figure 4 As shown, storage device 200 can change the order of the first command and the second command, thereby performing a rescheduling so that the second command is processed before the first command. Since the next command to be processed in the first memory die DIE1 is the second command as an emergency read command, the second command can be sent to the first memory die DIE1, and normal programming operations in the first memory die DIE1 can be suspended. The first memory die DIE1 can then read data according to the second command. After the emergency read operation is performed, the suspended normal programming operations can be resumed in the first memory die DIE1.

[0076] Storage device 200 can perform a rescheduling operation to change the processing order of urgent read commands, so that the urgent read command is preferentially processed in the first memory die DIE1 on which it is scheduled. Changing the processing order of urgent read commands can include changing the position of the urgent read commands according to the processing order. The position of the urgent read commands according to the processing order can also be referred to as the processing order position of the urgent read commands. For example, in Figures 3A to 3C and Figure 4In the example shown, in the processing order of the first emergency command queue UCQ1 of command queue CQ1, the processing order of the emergency read command DIE1-URGENT-READ(2) changes from second to first, and in the processing order of the first emergency command queue UCQ1 of command queue CQ1, the processing order of the emergency programming command DIE1-URGENT-PROGRAM(1) changes from first to second. Therefore, the problem caused by the failure to process the emergency read command due to preceding program commands can be solved, and the QoS of the read operation can be improved.

[0077] Figure 5 This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention, and shows... Figure 1 An example of operation S400. Operation S400 may include operations S10 to S50.

[0078] Figure 5 Operations can be performed in the first command queue to the nth command queue (e.g., first memory die DIE1 to nth memory die DIEn) respectively, corresponding to the first memory die to the nth memory die (e.g., first memory die DIE1 to nth memory die DIEn). Figure 1 The operations are executed in the first command queue CQ1 to the nth command queue CQn. For example, the storage device can perform the operations described below with respect to the first command queue CQ1 and the first memory die DIE1, perform the operations described below with respect to the second command queue CQ2 and the second memory die DIE2 in parallel, and perform the operations described below with respect to the nth command queue CQn and the nth memory die DIEn in parallel.

[0079] Reference Figure 5 In operation S10, the storage controller of the storage device can determine whether a command recently sent to a specific memory die is a normal programming command. For example, the storage controller can store information about commands sent to non-volatile storage devices. The storage controller can determine which command was most recently sent based on this information.

[0080] In operation S20, the memory controller can determine whether the first command queued in the command queue corresponding to a specific memory die is an urgent read command. In operation S30, the memory controller can determine whether an urgent read command is queued in the command queue corresponding to a specific memory die. That is, the memory controller can determine in operation S20 whether the command scheduled first among those scheduled to be processed on the specific memory die is an urgent read command, and can determine in operation S30 whether the urgent read command is included among the commands scheduled to be processed on the specific memory die.

[0081] When it is determined in operation S10 that the command recently sent to a specific memory die is not a normal programming command, or when it is determined in operation S20 that the first command in the command queue corresponding to the specific memory die is an urgent read command, or when it is determined in operation S30 that an urgent read command is not queued in the command queue corresponding to the specific memory die, the memory controller may execute operation S50. In operation S50, the memory controller may send the first command from the commands queued in the command queue to the memory die corresponding to the command queue. According to at least some exemplary embodiments of the present invention, when it is determined that the operation already performed on the memory die has been completed, the memory controller may send the first command to the memory die, or the memory controller may send the first command to the memory die even though the operation already performed on the memory die has not been completed. After the performed operation is completed, the operation of processing the first command can be performed on the memory die.

[0082] Conversely, when it is determined in operation S10 that the command most recently sent to a specific memory die is a normal programming command, when it is determined in operation S20 that the first command in the command queue corresponding to the specific memory die is not an urgent read command, and when it is determined in operation S30 that an urgent read command is queued in the command queue corresponding to the specific memory die, the memory controller can execute operation S40. In operation S40, the memory controller can change the urgent read command queued in the command queue to be processed first, and according to the changed processing order, the memory controller can send the urgent read command to the specific memory die. When the command processing order is changed, the processing order of other commands can also be shifted (push) one by one. On the specific memory die, the normally executed programming operation can be paused, and an urgent read operation based on the received urgent read command can be executed.

[0083] In an example embodiment, before executing operation S40, the storage controller can determine whether a programming command with the same address as the urgent read command is queued before the urgent read command, and can execute operation S40 based on the determination result. For example, when a programming command with the same address as the urgent read command is queued before the urgent read command, the storage controller can maintain the processing order of the urgent read commands; however, when a programming command with the same address as the urgent read command is not queued before the urgent read command, the storage controller can change the processing order of the urgent read commands. However, the storage controller is not limited to this. The storage controller can execute operation S40 without determining whether a programming command with the same address as the urgent read command is queued before the urgent read command.

[0084] Figure 6 This is a flowchart illustrating the operation of a storage device according to at least one exemplary embodiment of the present invention, and shows... Figure 5 Here is an example of operation S40. Operation S40 may include operations S41 to S43.

[0085] Figure 6 Operations can be performed in the first command queue to the nth command queue (e.g., first memory die DIE1 to nth memory die DIEn) respectively, corresponding to the first memory die to the nth memory die (e.g., first memory die DIE1 to nth memory die DIEn). Figure 1 The operations are executed in the first command queue CQ1 to the nth command queue CQn. For example, the storage device can perform the operations described below with respect to the first command queue CQ1 and the first memory die DIE1, perform the operations described below with respect to the second command queue CQ2 and the second memory die DIE2 in parallel, and perform the operations described below with respect to the nth command queue CQn and the nth memory die DIEn in parallel.

[0086] Reference Figure 6 In operation S41, the storage controller of the storage device can determine whether the number of times the processing order of commands has been changed in a specific urgent command queue has reached a reference value. For example, as Figure 4 As shown, when the order of the first command and the second command is changed in the first emergency command queue UCQ1 of the first command queue CQ1, the number of times the order is changed is counted, and the count value can be stored in the storage controller of the storage device 200. The storage controller can compare the count value with a reference value and determine whether the count value has reached the reference value. According to at least some exemplary embodiments of the present invention, the reference value can be preset in the storage controller, or it can be a value that changes according to the state of the first memory die DIE1. Furthermore, the reference value can be set the same for the first command queue CQ1 to the nth command queue CQn, or it can be different.

[0087] In operation S43, when the number of times the processing order has been changed does not reach the reference value, that is, when the number of times the processing order has been changed is less than the reference value, the storage controller can change the urgent read command queued in the command queue to be processed first, and can update the number of times the processing order has been changed. The value obtained by counting the number of times the processing order has been changed can be updated.

[0088] Conversely, when the number of times the processing order has been changed reaches a reference value, the storage controller may stop changing the processing order of commands queued in the command queue and may execute operation S50.

[0089] When the processing order of urgent read commands in the command queue is successively changed to first, another command that is scheduled to be processed first (e.g., as...) Figure 3CThe first command of an emergency programming order will continue to be moved backward and cannot be processed. Therefore, by limiting the number of times the processing order is changed to a reference value, excessive delays in processing emergency programming orders can be prevented.

[0090] Figure 7A This is a diagram illustrating command information about a memory die stored in the storage controller of a storage device, according to at least one exemplary embodiment of the present invention. Figure 7B This is a diagram illustrating command information about a tenant stored in the storage controller of a storage device, according to at least one example embodiment of the present invention.

[0091] Reference Figure 7A The memory controller may store a first table TA1 containing command information about each memory die. In an example embodiment, the first table TA1 may include a number of entries corresponding to the number of memory dies.

[0092] According to this embodiment, the storage controller of the storage device can limit the number of commands that can be processed in each memory die. The storage controller can manage a first table TA1 to provide tenants with equal opportunities to access specific memory dies and to schedule commands based on the urgency of commands in each memory die. The storage controller can use the first table TA1 to select memory dies from the memory dies that prioritize processing commands received from the host.

[0093] The first table TA1 may include: information about the die index indicating each memory die, and information about the turn indicating the next command to be processed in the corresponding memory die. For example, when performing an operation to process a current normal command in a memory die, the information about the turn can be set to process an urgent command. Or, for example, when processing an emergency command consecutively in a memory die with a number equal to or greater than a threshold, the information about the turn can be set to process normal commands.

[0094] The first table TA1 may also include: an urgent availability bit indicating whether there are urgent commands that must be processed in the memory die; a normal availability bit indicating whether there are normal commands that must be processed in the memory die; and an entry urgent command count indicating the number of urgent commands received corresponding to the memory die; an exit urgent command count indicating the number of urgent commands dequeued from the command queue corresponding to the memory die; an entry normal command count indicating the number of normal commands received corresponding to the memory die; and an exit normal command count indicating the number of normal commands dequeued from the command queue corresponding to the memory die. For example, when an urgent command corresponding to the memory die is received, the information regarding the urgent availability bit and the entry urgent command count can be updated, and when a scheduled urgent command is provided to the memory die, the information regarding the urgent availability bit and the exit urgent command count can be updated. Furthermore, for example, when a normal command corresponding to the memory die is received, the information regarding the normal availability bit and the entry normal command count can be updated, and when a scheduled normal command is provided to the memory die, the information regarding the normal availability bit and the exit normal command count can be updated. When the outgoing normal command count and the outgoing emergency command count exceed a preset value (e.g., the number of commands that can be processed all at once in the memory die), the memory controller can reset the emergency available bit and the normal available bit, so that commands corresponding to the memory die can be not scheduled.

[0095] Furthermore, the first table TA1 may include: information about a recently allocated command index, indicating the memory die to which a command was most recently allocated (i.e., scheduled); and information about the type of the recently allocated command, indicating the type of the recently allocated command. According to at least some exemplary embodiments of the invention, the type of command may vary depending on whether the command is a read command, a programming command, an urgent command, or a normal command. The memory controller may schedule commands based on the information about the recently allocated command index and the information about the type of the recently allocated command, where the command does not correspond to the memory die to which it was most recently allocated but to another memory die.

[0096] refer to Figure 7B The storage controller may store a second table TA2 that includes command information for each tenant. In an example embodiment, the second table TA2 may include as many entries as the product of the number of tenants and memory dies.

[0097] The storage controller of the storage device can manage a second table, TA2, to distribute commands received from each tenant equally among them in a round-robin fashion (rather than in the order they were received). The storage controller can use the second table, TA2, to determine which command from a tenant has been scheduled in the memory die.

[0098] The second table TA2 may include: information indicating the tenant index for each tenant; information indicating the die index for each memory die; and information indicating the most recently allocated tenant corresponding to the command most recently allocated to the corresponding memory die. The storage controller can schedule commands received from another tenant, not the one that sent the most recently allocated command, based on the information about the most recently allocated tenant, and the storage controller can update the information about the most recently allocated tenant when a new command is scheduled.

[0099] Table TA2 may also include information about a tenant's available emergency / normal command bitmap, which indicates whether emergency commands received from the tenant are queued in the command queue corresponding to the memory die, and whether normal commands received from the tenant are queued in the command queue corresponding to the memory die. The tenant's available emergency / normal command bitmap can indicate whether emergency and normal commands corresponding to the tenant and the memory die are scheduled.

[0100] Furthermore, the second table TA2 may include: information indicating that an insert tenant emergency command corresponding to an urgent command for a tenant and a memory die has been received; information indicating that an allocation tenant emergency command corresponding to an urgent command for a tenant and a memory die was recently allocated; information indicating that an insert tenant normal command corresponding to a normal command for a normal command for a tenant and a memory die has been received; and information indicating that a tenant normal command corresponding to a normal command for a normal command for a tenant and a memory die was recently allocated. Therefore, even if the storage device receives a command required from a specific tenant to the same memory die very early, the storage controller can prioritize scheduling commands received from other tenants by using the second table TA2.

[0101] Figure 8A and Figure 8B This is a diagram illustrating the operation of a management command to retrieve a command input from the storage controller of a storage device, according to at least one example embodiment of the present invention.

[0102] Reference Figure 8A and Figure 8BA third table, TA3, including information about each command, can be stored to manage commands sent to the storage device. In an example embodiment, the third table TA3 may include as many entries as the total number of commands that can be processed in the storage device. For example, all command queues in the storage device (e.g., Figure 1 The total queue depth of the command queue 218 is 1024, and the number of entries in the third table T3 can be 1024. The storage controller can use the third table TA3 to retrieve commands sent to the storage device, thus improving retrieval speed.

[0103] The third table TA3 may include at least one of the following: information about the index of a received command; information about a validity bit indicating whether the corresponding command is valid and the type of the corresponding command; information about a threshold related to the number of times the order of the corresponding commands has been changed; information about the tenant index corresponding to the corresponding command; information about the memory die index corresponding to the corresponding command; information about the next tenant command, which indicates a command from a tenant having a next index value corresponding to the tenant of the corresponding command; information about the previous tenant command, which indicates a command from a tenant having a previous index value corresponding to the tenant of the corresponding command; and information about the up tenant command, which indicates a command received after the corresponding command from the tenant corresponding to the corresponding command. The storage controller may use the third table TA3 to manage the commands received by the storage device in a linked list manner.

[0104] According to at least some exemplary embodiments of the present invention, information regarding a threshold related to the number of times the order of a corresponding command is changed can be set to prioritize other commands over the corresponding command in scheduling, and to limit the number of times the existing processing order of the corresponding command is moved backward. Therefore, delays in the processing time of specific commands that occur when the processing order of a specific command among the commands received by the storage device is continuously moved backward can be prevented.

[0105] Reference Figure 3C and Figure 8B Commands received by the storage device can be managed in a linked list manner. These commands can be organized into different linked lists based on the memory die and the type of command (e.g., emergency command or normal command).

[0106] For example, the first to fourth commands scheduled for processing in the first memory die can form an urgent command list and a normal command list, respectively. The first to third commands can form an urgent command list, and the fourth command can form a normal command list. According to at least some exemplary embodiments of the present invention, in the urgent command list, the first and third commands received from the same tenant (i.e., the first tenant) can be connected to each other in the vertical direction, i.e., connected by an upward pointer. In the urgent command list, the first command from the first tenant and the second command from the second tenant can be connected to each other in the forward / backward direction, i.e., connected by a preceding / following pointer.

[0107] Figure 9 This is a diagram of a system that utilizes a storage device according to at least one exemplary embodiment of the concept of the present invention.

[0108] Reference Figure 9 , Figure 9 The system 1000 can essentially be a mobile system, such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or Internet of Things (IoT) device. However, Figure 9 System 1000 is not limited to this. System 1000 can be, for example, a PC, a laptop computer, a server, a media player, or automotive equipment such as a navigation device.

[0109] Reference Figure 9 The system 1000 may include a main processor 1100, memories 1200A and 1200B, and storage devices 1300A and 1300B, and may also include one or more of the following: an optical input device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0110] The main processor 1100 can control all operations of the system 1000, and more specifically, control the operations of other components forming the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, an application processor, etc.

[0111] The main processor 1100 may include at least one CPU core 1110, and may also include a controller 1120 for controlling memories 1200A and 1200B and / or storage devices 1300A and 1300B. According to an embodiment, the main processor 1100 may also include an accelerator 1130, which is a dedicated circuit for high-speed data computation, such as artificial intelligence (AI) data computation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), a data processing unit (DPU), etc., and may be implemented as a chip physically separate from other components of the main processor 1100.

[0112] Memory 1200A and 1200B can be used as main memory devices of system 1000 and may include volatile memory, such as SRAM and / or DRAM. However, memory 1200A and 1200B may include non-volatile memory, such as PRAM and / or RRAM. Memory 1200A and 1200B may be integrated into the same package as main processor 1100.

[0113] Storage devices 1300A and 1300B can both operate as non-volatile storage devices that store data regardless of power supply, and can have a relatively larger capacity than storage devices 1200A and 1200B. Storage devices 1300A and 1300B may include controllers 1310A and 1310B, and flash memory 1320A and 1320B that stores data under the control of storage controllers 1310A and 1310B. Flash memory 1320A and 1320B may include NAND flash memory, but may also include other types of NVM, such as PRAM and / or RRAM.

[0114] Storage devices 1300A and 1300B can be physically separated from the main processor 1100 in system 1000, or storage devices 1300A and 1300B can be housed in the same package as the main processor 1100. Furthermore, storage devices 1300A and 1300B can both be, for example, SSDs or memory cards, and can therefore be detachably coupled to other components of system 1000 via an interface such as connection interface 1480 described below. Storage devices 1300A and 1300B can both be devices employing standard protocols such as UFS. Storage devices 1300A and 1300B can be implemented as references... Figures 1 to 8B The storage device 200.

[0115] The optical input device 1410 can capture still or moving images and can be a camera, video camera, webcam, etc.

[0116] User input device 1420 can receive various types of data input from the user in system 1000, and can be a touchpad, keypad, keyboard, mouse, microphone, etc.

[0117] Sensor 1430 can detect various physical quantities that can be obtained from outside the system 1000, and can convert the detected physical quantities into electrical signals. Sensor 1430 can be a temperature sensor, pressure sensor, lighting sensor, position sensor, acceleration sensor, biosensor, gyroscope, etc.

[0118] The communication device 1440 can receive signals from other devices outside the system 1000 and send signals to other devices outside the system 1000 according to different communication protocols. The communication device 1440 may include an antenna, transceiver, modem, etc.

[0119] The display 1450 and the speaker 1460 can be used as output devices to output visual and auditory information to the user of the system 1000, respectively.

[0120] The power supply device 1470 can appropriately convert power supplied from batteries embedded in the system and / or external power, and can supply power to each component of the system 1000.

[0121] The connection interface 1480 allows the system 1000 to connect to external devices connected to the system 1000 and exchange data with them. The connection interface 1480 can be implemented using various interface methods, such as Advanced Technology Connect (ATA), SATA, external SATA (e-SATA), SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB), Secure Digital (SD) card, MMC, eMMC, UFS, eUFS, and CF card interfaces.

[0122] Figure 10 This is a block diagram of a memory system according to an embodiment. (Refer to...) Figure 10 The memory system 2000 may include a memory device 2100 and a memory controller 2200. The memory system 2000 may support first channels CH1 to m-th channels CHm, and the memory device 2100 and the memory controller 2200 may be interconnected via channels CH1 to CHm. For example, the memory system 2000 may be implemented as a storage device such as an SSD, and the memory controller 2200 may correspond to... Figure 1 The storage controller 210, and the storage device 2100 can correspond to Figure 1 220 non-volatile memory.

[0123] Memory device 2100 may include NVM devices NVM11 to NVMmk. Each of NVM devices NVM11 to NVMmk may be connected to one of channels CH1 to CHm via a corresponding way. For example, NVM devices NVM11 to NVM1k may be connected to the first channel CH1 via ways W11 to W1k, and non-volatile memories NVM21 to NVM2k may be connected to the second channel CH2 via ways W21 to W2k. In an example embodiment, each of NVM devices NVM11 to NVMmk may reside in any memory cell operated according to a single command from memory controller 2200. For example, each of NVM devices NVM11 to NVMmk may be a memory chip or a memory die, but one or more embodiments are not limited thereto. For example, NVM devices NVM11 to NVMmk may correspond to first memory dies DIE1 to nth memory dies DIEn, respectively.

[0124] The memory controller 2200 can receive signals from / send signals to the memory device 2100 via channels CH1 to CHm. For example, the memory controller 2200 can send commands ICMD1 to ICMDm, addresses ADDR1 to ADDRm, and data DATA1 to DATAm to the memory device 2100 via channels CH1 to CHm, or it can receive data DATA1 to DATAm from the memory device 2100.

[0125] The memory controller 2200 can select one of the NVM devices connected to the corresponding channel via the channel, and can exchange signals with the selected NVM device. For example, the memory controller 2200 can select NVM device NVM11 connected to the first channel CH1 from NVM devices NVM11 to NVMmn. The memory controller 2200 can send command ICMD1, address ADDR1, and data DATA1 to the selected NVM device NVM11 via the first channel CH1, or can receive data DATA1 from the selected NVM device NVM11.

[0126] The memory controller 2200 can receive signals from and send signals to the memory device 2100 in parallel through different channels. For example, when sending command ICMD1 to the memory device 2100 through the first channel CH1, the memory controller 2200 can send command ICMD2 to the memory device 2100 through the second channel CH2. For example, when receiving data DATA1 from the memory device 2100 through the first channel CH1, the memory controller 2200 can receive data DATA2 from the memory device 2100 through the second channel CH2.

[0127] The memory controller 2200 can control all operations of the memory device 2100. The memory controller 2200 can control the NVM devices NVM11 to NVMmk connected to channels CH1 to CHm respectively by sending signals to channels CH1 to CHm. For example, the memory controller 2200 can control one NVM device selected from NVM11 to NVM1k by sending the command ICMD1 and the address ADDR1 to the first channel CH1.

[0128] NVM devices NVM11 to NVMmk can all operate under the control of memory controller 2200. For example, non-volatile memory device NVM11 can program data DATA1 according to the command ICMD1, address ADDR1, and data DATA1 provided to channel CH1. For example, non-volatile memory device NVM21 can read data DATA2 according to the command ICMD2 and address ADDR2 provided to the second channel CH2, and can send the read data DATA2 to memory controller 2200.

[0129] Figure 10 The diagram shows that memory device 2100 communicates with memory controller 2200 via m channels and includes n non-volatile memory devices corresponding to each channel. However, the number of channels and the number of non-volatile memory devices connected to a channel can vary.

[0130] Figure 11 This is a block diagram of a system 3000 according to at least one exemplary embodiment of the present invention.

[0131] System 3000 can be any computing system (or component included in a computing system), comprising a device 3100 and a host processor 3200 capable of communicating with each other. For example, system 3000 can be included in a fixed computing system such as a desktop computer, server, or kiosk, or a portable computing system such as a laptop computer, mobile phone, or wearable device. Furthermore, in some embodiments, system 3000 can be included in a system-on-a-chip (SoC) or system-in-package (SiP) in which the device 3100 and host processor 3200 are integrated into a single chip or package. Figure 11 As shown, system 3000 may include device 3100, host processor 3200, device-attached memory 3300, and host memory 3400. In some embodiments, device-attached memory 3300 may be omitted from system 3000.

[0132] Reference Figure 11Device 3100 and host processor 3200 can communicate with each other via link 3500, and can send messages and / or data to or receive messages and / or data from link 3500. At least some exemplary embodiments of the inventive concept will be described with reference to link 3500 based on a CXL specification supporting the CXL protocol. However, as a non-limiting example, device 3100 and host processor 3200 can communicate with each other using coherent interconnect technologies such as the Xbus protocol, NVLink protocol, Infinity Fabric protocol, Cache Coherent Interconnect for Accelerators (CCIX) protocol, and Coherent Accelerator Processor Interface (CAPI).

[0133] In some embodiments, link 3500 may support multiple protocols, and messages and / or data may be transmitted according to the protocols. For example, link 3500 may support the CXL protocol, which includes non-consistent protocols (e.g., CXL.io), consistent protocols (e.g., CXL.cache), and memory access protocols (or memory protocols) (e.g., CXL.mem). In some embodiments, as a non-limiting example, link 3500 may support protocols such as PCI, PCIe, USB, and SATA. In this specification, the protocols supported by link 3500 may be referred to as interconnect protocols.

[0134] Device 3100 can represent any device that provides functionality useful to host processor 3200, and in some embodiments, device 3100 can correspond to an accelerator conforming to the CXL specification. For example, software executing on host processor 3200 can offload at least a portion of computational and / or input / output (I / O) work to device 3100. In some embodiments, device 3100 may include at least one of the following: programmable components such as GPUs or NPUs, components providing fixed functionality (e.g., intellectual property (IP) cores), and reconfigurable components such as field-programmable gate arrays (FPGAs). Figure 11 As shown, device 3100 may include physical layer 3110, multiprotocol multiplexer (MUX) 3120, interface circuitry 3130 and accelerator circuitry 3140, and may communicate with device-attached memory 3300.

[0135] Accelerator circuit 3140 can perform useful functions provided by device 3100 to host processor 3200, and can be referred to as accelerator logic. For example... Figure 11As shown, when the device-attached memory 3300 is included in the system 3000, the accelerator circuit 3140 can communicate with the device-attached memory 3300, and can communicate with the device-attached memory 3300 based on a protocol independent of the link 3500 (i.e., a device-specific protocol). Furthermore, as... Figure 11 As shown, the accelerator circuit 3140 can communicate with the host processor 3200 via the interface circuit 3130 using multiple protocols.

[0136] Interface circuitry 3130 can determine one of the protocols based on messages and / or data from communication between accelerator circuitry 3140 and host processor 3200. Interface circuitry 3130 can be connected to at least one protocol queue included in multiprotocol multiplexer 3120 and can exchange messages and / or data with host processor 3200 through at least one protocol queue. In some embodiments, interface circuitry 3130 and multiprotocol multiplexer 3120 can be integrated into a single component. In some embodiments, multiprotocol multiplexer 3120 may include protocol queues corresponding to protocols supported by link 3500. Furthermore, in some embodiments, multiprotocol multiplexer 3120 can arbitrate communication according to different protocols and can provide selected communication to physical layer 3110. In some embodiments, physical layer 3110 can be connected to physical layer 3210 of host processor 3200 via a single interconnect, bus, trace, etc.

[0137] The host processor 3200 may be the main processor of the system 3000, such as a central processing unit (CPU), and in some embodiments, the host processor 3200 may correspond to a host processor (or host) conforming to the CXL specification. Figure 11 As shown, the host processor 3200 can be connected to the host memory 3400 and may include a physical layer 3210, a multiprotocol multiplexer 3220, an interface circuit 3230, a coherence / cache circuit 3240, a bus circuit 3250, at least one core 3260, and I / O devices 3270.

[0138] At least one core 3260 can execute instructions and can be connected to a coherent / cache circuit 3240. The coherent / cache circuit 3240 may include a cache hierarchy and may be referred to as coherent / cache logic. For example... Figure 11As shown, the coherent / cache circuitry 3240 can communicate with at least one core 3260 and interface circuitry 3230. For example, the coherent / cache circuitry 3240 can enable communication according to two or more protocols, including a consensus protocol and a memory access protocol. In some embodiments, the coherent / cache circuitry 3240 may include direct memory access (DMA) circuitry. I / O device 3270 can be used for communication with bus circuitry 3250. For example, bus circuitry 3250 may be PCIe logic, and I / O device 3270 may be a PCIe I / O device.

[0139] Interface circuitry 3230 enables communication between components of host processor 3200, such as communication between coherent / cached circuitry 3240 and bus circuitry 3250 and device 3100. In some embodiments, interface circuitry 3230 facilitates message and / or data communication between components of host processor 3200 and devices according to multiple protocols, such as non-coherent protocols, coherent protocols, and memory protocols. For example, interface circuitry 3230 may determine one protocol based on the messages and / or data communicated between components of host processor 3200 and device 3100.

[0140] The multiprotocol multiplexer 3220 may include at least one protocol queue. Interface circuitry 3230 may be connected to at least one protocol queue and may exchange messages and / or data with device 3100 through at least one protocol queue. In some embodiments, interface circuitry 3230 and multiprotocol multiplexer 3220 may be integrated into a single component. In some embodiments, multiprotocol multiplexer 3220 may include multiple protocol queues, each corresponding to a protocol supported by link 3500. Furthermore, in some embodiments, multiprotocol multiplexer 3220 may arbitrate communication according to different protocols and may provide selective communication to physical layer 3210.

[0141] Figures 1 to 8B The storage device can be composed of device 3100 and host processor 3200 or by... Figure 11 Access to various peripheral devices not shown in the diagram.

[0142] Figure 12 This is a block diagram of a system 4000 according to at least one exemplary embodiment of the present invention.

[0143] Reference Figure 12 System 4000 may include device 4100, host processor 4200, device memory 4300, and host memory 4400. In some embodiments, device memory 4300 may correspond to Figure 11 Device Additional Memory 3300.

[0144] For reference Figure 11The device 4100 and the host processor 4200 can communicate with each other according to multiple protocols. These protocols may include the memory protocol MEM, the coherent protocol COH, and the non-coherent protocol IO. In some embodiments, referring to the CXL specification 2.0, the memory protocol MEM, the coherent protocol COH, and the non-coherent protocol IO may correspond to CXL.mem, CXL.cache, and CXL.io, respectively. The non-coherent protocol IO may correspond to the PCIe transaction hierarchy and can be used for device discovery, interrupt management, register access settings, and signal error handling of the system 400.

[0145] When the host processor 4200 accesses the accelerator (e.g., Figure 11 The memory of the accelerator circuit 3140 Figure 11 When the device has attached memory (3300), the memory protocol MEM can be used. The memory protocol MEM can define transactions between the master and slave.

[0146] The master can represent the agent that triggers the request in the CXL.mem protocol. For example, in the case of a transaction for a MemRd command, the master can correspond to the host processor 4200 that triggered the MemRd command.

[0147] A slave can represent a proxy responsible for responding to requests triggered by the master in the CXL.mem protocol. For example, in the case of transactions used for MemRd commands, a slave can correspond to a storage device. A storage device can be... Figure 11 The host memory 3400 or the device-attached memory 3300.

[0148] The Memory Protocol (MEM) can define master-to-slave transactions and slave-to-master transactions. For example, referring to CXL specification 2.0, a master-to-slave transaction can be called a master-to-slave (M2S) transaction, and a slave-to-master transaction can be called a master-to-slave (S2M) transaction.

[0149] According to various embodiments, device 4100 may correspond to any of at least three types. When system 4000 does not include host memory 4400, device 4100 may correspond to Type 1 as defined in the CXL specification. In system 4000 including device 4100 of Type 1, the protocol may include only consistent protocol COH and inconsistent protocol IO. When device 4100 corresponds to Type 1, host processor 4200 can use device 4100 to cache data of host processor 4200 in device memory 4300. When device 4100 corresponds to Type 1, system 4000 may support device-to-host (D2H) cached coherent and host-to-device (H2D) snoop transactions.

[0150] When device 4100 operates as an accelerator (when device 4100 includes...) Figure 11 When the accelerator circuit 3140 is used, device 4100 may correspond to type 2 as defined in the CXL specification. In system 4000 including type 2 device 4100, the protocol may include all consistent protocol COH, non-consistent protocol IO, and memory protocol MEM. For example, host processor 4200 may retrieve device 4100 according to non-consistent protocol IO, access device memory 4300 corresponding to the retrieved device 4100 according to memory protocol MEM, and may allow device 4100 to use the host processor 4200's memory according to consistent protocol COH.

[0151] When device 4100 operates as a device for memory expansion, device 4100 may correspond to Type 3 as defined in the CXL specification. In system 4000 including Type 3 device 4100, the protocol may include a memory protocol MEM and a non-uniform protocol I / O. For example, host processor 4200 may identify and connect to device 4100 according to non-uniform protocol I / O, and may access the memory pool of device 4100 according to memory protocol MEM. Device 4100 may communicate with device memory 4300 and may include a memory controller 4110 for accessing device memory 4300. In some embodiments, with Figure 12 Unlike the illustration, the memory controller 4110 can be external to the device 4100 or integrated with the device memory 4300. Furthermore, the host processor 4200 can communicate with the host memory 4400 and may include a memory controller 4210 for accessing the host memory 4400. In some embodiments, with Figure 12 The diagrams differ, but the memory controller 4210 can be external to the host processor 4200 or integrated with the host memory 4400.

[0152] According to various embodiments, the device memory 4300 can be implemented as various types of memory, such as storage class memory (SCM).

[0153] SCM can possess the characteristics of both non-volatile and volatile memory, and can be accessed in bytes. For example, SCM can include phase-change RAM (PCM), FeRAM, MRAM, RRAM, STT-MRAM, etc. In an example embodiment, Figures 1 to 8B Storage devices can be implemented as Figure 12 The device memory is 4300.

[0154] Figure 13A and Figure 13BThis is a block diagram of a system example based on at least one exemplary embodiment of the concept of the present invention.

[0155] In detail, Figure 13A and Figure 13B The block diagrams shown above illustrate systems 900a and 900b, each comprising multiple CPUs. The descriptions provided above will not be repeated below.

[0156] Reference Figure 13A System 900a may include a first CPU 11a and a second CPU 21a, as well as a first dual data rate (DDR) memory 12a and a second DDR memory 22a respectively connected to the first CPU 11a and the second CPU 21a. Based on processor interconnect technology, the first CPU 11a and the second CPU 21a can be interconnected with each other through interconnect system 30a. For example... Figure 13A As shown, interconnect system 30a can provide at least one consistent CPU-to-CPU link.

[0157] System 900a may include a first I / O device 13a and a first accelerator 14a communicating with a first CPU 11a, and may include a first device memory 15a connected to the first accelerator 14a. The first CPU 11a and the first I / O device 13a may communicate with each other via bus 16a, and the first CPU 11a and the first accelerator 14a may communicate with each other via bus 17a. Furthermore, system 900a may include a second I / O device 23a and a second accelerator 24a communicating with a second CPU 21a, and may include a second device memory 25a connected to the second accelerator 24a. The second CPU 21a and the second I / O device 23a may communicate with each other via bus 26a, and the second CPU 21a and the second accelerator 24a may communicate with each other via bus 27a.

[0158] Protocol-based communication can be performed via buses 16a, 17a, 26a, and 27a, and the protocol supports selective and parallel access operations as described above with reference to the accompanying drawings. Therefore, access latency to memory (e.g., first device memory 15a, second device memory 25a, first DDR memory 12a, and / or second DDR memory 22a) can be reduced, and the performance of system 900a can be improved.

[0159] Reference Figure 13B ,and Figure 13ASimilar to system 900a, system 900b may include a first CPU 11b and a second CPU 21b, a first DDR memory 12b and a second DDR memory 22b, a first I / O device 13b and a second I / O device 23b, and a first accelerator 14b and a second accelerator 24b, and may also include remote remote memory 40. The first CPU 11b and the second CPU 21b can communicate with each other through interconnect system 30b. The first CPU 11b can be connected to the first I / O device 13b and the first accelerator 14b through buses 16b and 17b, and the second CPU 21b can be connected to the second I / O device 23b and the second accelerator 24b through buses 26b and 27b.

[0160] The first CPU 11b and the second CPU 21b can be connected to the remote memory 40 via the first bus 18 and the second bus 28. The remote memory 40 can be used for memory expansion in the system 900b, and the first bus 18 and the second bus 28 can be used as memory expansion ports. In addition to buses 16b, 17b, 26b, and 27b, protocols corresponding to the first bus 18 and the second bus 28 can also support memory access operations, as described in the accompanying drawings. Therefore, the access latency of the remote memory 40 can be reduced, and the performance of the system 900b can be improved.

[0161] Figure 14 This is a block diagram of a data center including a system according to at least one example embodiment of the concept of the present invention.

[0162] Reference Figure 14 In some embodiments, the system described can be included in data center 1 as an application server and / or storage server. Furthermore, embodiments relating to the selective and parallel error correction operations of the memory controller applied to at least some exemplary embodiments of the inventive concept can be applied to the application server and / or storage server, respectively.

[0163] Reference Figure 14 Data Center 1 can collect various types of data and provide services; it can be called a data storage center. For example, Data Center 1 could be a system used for search engine and database operations, or a computing system used by companies such as banks or government agencies. Figure 14 As shown, data center 1 may include application servers 50_1 to 50_n and storage servers 60_1 to 60_m (where m and n are both integers greater than 1). The number of application servers 50_1 to 50_n (i.e., n) and the number of storage servers 60_1 to 60_m (i.e., m) may vary depending on the embodiment, and m and n may be different from each other.

[0164] Application servers 50_1 to 50_n may each include at least one of processors 51_1 to 51_n, memory 52_1 to 52_n, switches 53_1 to 53_n, network interface controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. Processors 52_1 to 51_n can control all operations of application servers 50_1 to 50_n and can access memory 52_1 to 52_n to execute instructions and / or data loaded on memory 52_1 to 52_n. As a non-limiting example, memory 52_1 to 52_n may each include dual data rate synchronous DRAM (DDR SDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), dual in-line memory module (DIMM), Optane DIMM, or non-volatile DIMM (NVMDIMM).

[0165] According to embodiments, the number of processors and the number of memories included in application servers 50_1 to 50_n can vary. In some embodiments, processors 51_1 to 51_n and memories 52_1 to 52_n can provide processor-memory pairs. In some embodiments, the number of processors 51_1 to 51_n can be different from the number of memories 52_1 to 52_n. Each of processors 51_1 to 51_n can include a single-core processor or a multi-core processor. In some embodiments, such as Figure 14 As shown by the dashed lines, storage devices 55_1 to 55_n can be omitted from application servers 50_1 to 50_n. According to embodiments, the number of storage devices 55_1 to 55_n included in application servers 50_1 to 50_n can be selected differently. Processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, NICs 54_1 to 54_n, and / or storage devices 55_1 to 55_n can communicate with each other via the links described with reference to the accompanying drawings.

[0166] Storage servers 60_1 to 60_m may include at least one of processors 61_1 to 61_m, memory 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_m, and storage devices 65_1 to 65_m. The operation of processors 61_1 to 61_m and memory 62_1 to 62_m may be similar to that of processors 51_1 to 51_n and memory 52_1 to 52_n of application servers 50_1 to 50_n. Storage devices 65_1 to 65_m may be as described in the attached diagram. Figures 1 to 8B The aforementioned storage device.

[0167] Application servers 50_1 to 50_n and storage servers 60_1 to 60_m can perform internal communication via network 70. In some embodiments, network 70 can be implemented using Fibre Channel (FC), Ethernet, etc. FC can be a medium for data transmission with relatively high speed and can be an optical switch providing high performance / high availability. Depending on the access method of network 70, storage servers 60_1 to 60_m can be configured as file storage, block storage, or object storage.

[0168] In some embodiments, network 70 may be a storage-only network such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to the FC protocol (FCP). Alternatively, the SAN may be an IP-SAN implemented using a TCP / IP network and according to SCSI over TCP / IP or Internet SCSI (iSCSI) protocols. In some embodiments, network 70 may be a general-purpose network such as a TCP / IP network. For example, network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), or NVMe over Fabrics (NVMe-oF).

[0169] The following text primarily describes application server 50_1 and storage server 60_1. The description of application server 50_1 can be applied to another application server (e.g., application server 50_n), and the description of storage server 60_1 can be applied to another storage server (e.g., storage server 60_m).

[0170] Application server 50_1 can store data requested by users or clients in one of storage servers 60_1 to 60_m via network 70. Furthermore, application server 50_1 can retrieve data requested by users or clients from one of storage servers 60_1 to 60_m via network 70. For example, application server 50_1 can be implemented as a web server, a database management system (DBMS), etc.

[0171] Application server 50_1 can access the memory 52_n and / or storage device 55_n included in another application server 50_n via network 70, and / or can access the memory 62_1 to 62_m and / or storage device 65_1 to 65_m included in storage servers 60_1 to 60_m via network 70. Therefore, application server 50_1 can perform various operations on data stored in application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. For example, application server 50_1 can execute instructions for moving or copying data between application servers 50_1 to 50_n and / or storage servers 60_1 to 60_m. According to at least some exemplary embodiments of the present invention, data can be moved directly or via memory 62_1 to 62_m from storage devices 65_1 to 65_m of storage servers 60_1 to 60_m to memory 52_1 to 52_n of application servers 50_1 to 50_n. In some embodiments, the data moved over network 70 may be encrypted for security or privacy purposes.

[0172] In storage server 60_1, interface IF can provide physical connections between processor 61_1 and controller CTRL, as well as physical connections between NIC 64_1 and controller CTRL. For example, interface IF can be implemented using a direct-attached storage (DAS) method that directly accesses storage device 65_1 via a dedicated cable. Furthermore, interface IF can be implemented using various interface methods, such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE1394, USB, SD card, MMC, eMMC, UFS, eUFS, and CF card interfaces.

[0173] In storage server 60_1, switch 63_1 can selectively connect processor 61_1 and storage device 65_1 according to the control of processor 61_1, or selectively connect NIC 64_1 to storage device 65_1.

[0174] In some embodiments, NIC 64_1 may include a network interface card, network adapter, etc. NIC 64_1 can connect to network 70 via a wired interface, wireless interface, Bluetooth interface, optical interface, etc. NIC 64_1 may include internal memory, DSP, host bus interface, etc., and can be connected to processor 61_1, switch 63_1, etc., via the host bus interface. In some embodiments, NIC 64_1 may be integrated with at least one of processor 61_1, switch 63_1, and storage device 65_1.

[0175] In application servers 50_1 to 50_n or storage servers 60_1 to 60_m, processors 51_1 to 51_n and 61_1 to 61_m can send commands to storage devices 55_1 to 55_n and 65_1 to 65_m or memories 52_1 to 52_n and 62_1 to 62_m to program or read data. According to at least some example embodiments of the present invention, the data may be data that has been corrected for errors by an ECC engine. The data may be data that has undergone Data Bus Inversion (DBI) or Data Masking (DM) and may include Cyclic Redundancy Check (CRC) information. For privacy protection, the data may be encrypted.

[0176] Storage devices 55_1 to 55_n and 65_1 to 65_m can send control signals and command / address signals to the non-volatile memory device NVM (e.g., a NAND flash memory device) in response to read commands received from processors 51_1 to 51_n and 61_1 to 61_m. Therefore, when reading data from the non-volatile memory device NVM, a read enable signal is input as a data output control signal and used to output data to the DQ bus. A data strobe signal can be generated using the read enable signal. Command and address signals can be latched based on the rising or falling edge of the write enable signal.

[0177] The controller CTRL can control all operations of storage device 65_1. In embodiments, the controller CTRL may include static random access memory (SRAM). The controller CTRL can write data to the non-volatile storage device NVM in response to a write command, or read data from the non-volatile storage device NVM in response to a read command. For example, write and / or read commands may be generated in response to requests provided from a host (e.g., processor 61_1 in storage server 60_1, processor 61_m in another storage server 60_m, or processors 51_1 to 51_n in application servers 50_1 to 50_n). The buffer BUF can temporarily store (buffer) data to be written to or read from the non-volatile storage device NVM. In some embodiments, the buffer BUF may include DRAM. Furthermore, the buffer BUF may store metadata, and the metadata may represent user data or data generated by the controller CTRL for managing the non-volatile storage device NVM. Storage device 65_1 may include a security element (SE) for security or privacy.

[0178] Exemplary embodiments of the inventive concept have been described thus, and it will be apparent that they can be varied in many ways. These variations should not be considered as a departure from the intended spirit and scope of the exemplary embodiments of the inventive concept, and it will be apparent to those skilled in the art that all such modifications are intended to be included within the scope of the appended claims.

Claims

1. A storage device, the storage device comprising: Memory die; A storage controller processor configured to control operations performed on the memory die by scheduling multiple commands provided to the memory die; as well as The memory stores command queues corresponding to the memory die. The storage controller processor is configured as follows: The plurality of commands are received from a first tenant and a second tenant, respectively, wherein the first tenant and the second tenant are entities that can be executed by the host and can issue data access commands; Based on the first tenant and the second tenant providing the plurality of commands, schedule the plurality of commands in the command queue; and The multiple commands are rescheduled based on the operations performed on the memory die and the urgency of the multiple commands, and the memory die is controlled to process the multiple commands in an order different from the order in which the multiple commands are received by the memory controller processor, wherein the urgency of the multiple commands is assigned to the multiple commands by respective corresponding tenants in the first tenant or the second tenant.

2. The storage device according to claim 1, in, The storage controller processor is further configured to classify each of the plurality of commands into a normal command or an urgent command based on the urgency of the commands, wherein the urgent command is a command with a higher priority than the normal command. The command queue includes an emergency command queue and a normal command queue. Emergency commands are queued in the emergency command queue, and normal commands are queued in the normal command queue.

3. The storage device according to claim 2, wherein, The memory controller processor is also configured to reschedule the plurality of commands while performing a normal read operation based on a normal read command on the memory die.

4. The storage device according to claim 2, wherein, The storage controller processor is further configured to: The multiple commands are rescheduled by changing the processing order of the emergency read command to first. The emergency read command whose processing order position has been changed is sent to the memory die.

5. The storage device according to claim 4, wherein, The memory controller processor is also configured to suspend operations being performed on the memory die in response to receiving the emergency read command.

6. The storage device according to claim 1, wherein, The storage controller processor is further configured to: Receive a first command and a second command from the first tenant, and receive a third command from the second tenant; as well as The first command to be processed in the memory die is scheduled to be processed into the third command in the following order: The first command, the third command, and the second command.

7. The storage device according to claim 6, wherein, The storage controller processor is configured to receive the third command from the second tenant after sequentially receiving the first command and the second command from the first tenant.

8. A storage device, the storage device comprising: Multiple memory dies; A storage controller processor configured to schedule multiple commands provided to the plurality of memory dies and control operations performed on the plurality of memory dies; as well as The memory stores multiple command queues, each corresponding to one of the multiple memory dies. The storage controller processor is further configured to: The multiple commands are scheduled in multiple command queues based on multiple tenants configured to provide the multiple commands respectively and the urgency of the multiple commands, wherein the urgency of the multiple commands is assigned to the multiple commands by respective corresponding tenants among the multiple tenants, wherein the multiple tenants are entities that can be executed by the host and can issue data access commands, and The multiple commands are rescheduled based on the operations performed on the memory die in which at least some of the multiple commands are provided.

9. The storage device according to claim 8, wherein, The storage controller processor is further configured to classify each of the plurality of commands into a normal command or an emergency command based on the urgency of the plurality of commands, wherein the emergency command is a command with a higher priority than the normal command.

10. The storage device according to claim 9, wherein, Each of the plurality of command queues includes an emergency command queue and a normal command queue, wherein the emergency commands are queued in the emergency command queue and the normal commands are queued in the normal command queue.

11. The storage device according to claim 9, wherein, The memory controller processor is further configured to reschedule the plurality of commands while performing a normal read operation based on a normal read command in a memory die provided with at least some of the plurality of commands.

12. The storage device according to claim 9, wherein, The storage controller processor is further configured to: The multiple commands are rescheduled by changing the processing order of the emergency read command to first. The emergency read command whose processing order position has been changed is sent to the corresponding memory die among the plurality of memory dies.

13. The storage device according to claim 12, wherein, The storage controller processor is also configured to: In response to receiving the emergency read command, the operation being performed on the corresponding memory die is suspended, and Process the received emergency read command.

14. A method of operating a storage device, the storage device comprising a storage controller processor and a plurality of memory dies, the method comprising: Receive multiple commands from multiple tenants, wherein the multiple tenants are entities that can be executed by the host and can issue data access commands; The multiple commands are scheduled in a round-robin manner based on the multiple tenants; The multiple commands are scheduled according to their urgency, wherein the urgency of the multiple commands is assigned to each command by a corresponding tenant among the multiple tenants; and The multiple commands are rescheduled based on the operations performed on the memory die in which at least some of the multiple commands are provided.

15. The operating method according to claim 14, wherein, The receipt of multiple commands includes: Each of the plurality of commands is classified as a normal command or an emergency command based on its urgency, wherein the emergency command is a command with a higher priority than the normal command.

16. The operating method according to claim 15, wherein, The rescheduling of the plurality of commands includes: While performing normal programming operations according to normal programming commands in a memory die provided with at least some of the plurality of commands, the plurality of commands are rescheduled.

17. The operating method according to claim 15, wherein, The rescheduling of the plurality of commands includes: Change the processing order of the emergency read command among the multiple commands.

18. The operating method according to claim 17, wherein, The method of changing the processing order of the emergency read command among the multiple commands includes: The processing order of the emergency read command is changed to first, and the emergency read command is sent to the corresponding memory die.

19. The operating method according to claim 18, further comprising: After the emergency read command is sent to the corresponding memory die, the operation being performed on the corresponding memory die is paused, and the operation according to the emergency read command is performed on the corresponding memory die.

20. The operating method according to claim 17, wherein, The method of changing the processing order of the emergency read command among the multiple commands includes: If the number of times the processing order position of the emergency read command has been changed is less than a reference value, the processing order position of the emergency read command is changed to first and the number is updated.

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